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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018 Intel Corporation
4 */
5
6#include "intel_combo_phy.h"
7#include "intel_display_types.h"
8
9#define for_each_combo_phy(__dev_priv, __phy) \
10 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
11 for_each_if(intel_phy_is_combo(__dev_priv, __phy))
12
13#define for_each_combo_phy_reverse(__dev_priv, __phy) \
14 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
15 for_each_if(intel_phy_is_combo(__dev_priv, __phy))
16
17enum {
18 PROCMON_0_85V_DOT_0,
19 PROCMON_0_95V_DOT_0,
20 PROCMON_0_95V_DOT_1,
21 PROCMON_1_05V_DOT_0,
22 PROCMON_1_05V_DOT_1,
23};
24
25static const struct cnl_procmon {
26 u32 dw1, dw9, dw10;
27} cnl_procmon_values[] = {
28 [PROCMON_0_85V_DOT_0] =
29 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
30 [PROCMON_0_95V_DOT_0] =
31 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
32 [PROCMON_0_95V_DOT_1] =
33 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
34 [PROCMON_1_05V_DOT_0] =
35 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
36 [PROCMON_1_05V_DOT_1] =
37 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
38};
39
40/*
41 * CNL has just one set of registers, while gen11 has a set for each combo PHY.
42 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
43 * call the ICL macros even though the function has CNL on its name.
44 */
45static const struct cnl_procmon *
46cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
47{
48 const struct cnl_procmon *procmon;
49 u32 val;
50
51 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
52 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
53 default:
54 MISSING_CASE(val);
55 fallthrough;
56 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
57 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
58 break;
59 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
60 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
61 break;
62 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
63 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
64 break;
65 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
66 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
67 break;
68 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
69 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
70 break;
71 }
72
73 return procmon;
74}
75
76static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
77 enum phy phy)
78{
79 const struct cnl_procmon *procmon;
80 u32 val;
81
82 procmon = cnl_get_procmon_ref_values(dev_priv, phy);
83
84 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
85 val &= ~((0xff << 16) | 0xff);
86 val |= procmon->dw1;
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val);
88
89 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);
90 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
91}
92
93static bool check_phy_reg(struct drm_i915_private *dev_priv,
94 enum phy phy, i915_reg_t reg, u32 mask,
95 u32 expected_val)
96{
97 u32 val = intel_de_read(dev_priv, reg);
98
99 if ((val & mask) != expected_val) {
100 drm_dbg(&dev_priv->drm,
101 "Combo PHY %c reg %08x state mismatch: "
102 "current %08x mask %08x expected %08x\n",
103 phy_name(phy),
104 reg.reg, val, mask, expected_val);
105 return false;
106 }
107
108 return true;
109}
110
111static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
112 enum phy phy)
113{
114 const struct cnl_procmon *procmon;
115 bool ret;
116
117 procmon = cnl_get_procmon_ref_values(dev_priv, phy);
118
119 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
120 (0xff << 16) | 0xff, procmon->dw1);
121 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
122 -1U, procmon->dw9);
123 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
124 -1U, procmon->dw10);
125
126 return ret;
127}
128
129static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
130{
131 return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
132 (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT);
133}
134
135static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
136{
137 enum phy phy = PHY_A;
138 bool ret;
139
140 if (!cnl_combo_phy_enabled(dev_priv))
141 return false;
142
143 ret = cnl_verify_procmon_ref_values(dev_priv, phy);
144
145 ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
146 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
147
148 return ret;
149}
150
151static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
152{
153 u32 val;
154
155 val = intel_de_read(dev_priv, CHICKEN_MISC_2);
156 val &= ~CNL_COMP_PWR_DOWN;
157 intel_de_write(dev_priv, CHICKEN_MISC_2, val);
158
159 /* Dummy PORT_A to get the correct CNL register from the ICL macro */
160 cnl_set_procmon_ref_values(dev_priv, PHY_A);
161
162 val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0);
163 val |= COMP_INIT;
164 intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val);
165
166 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
167 val |= CL_POWER_DOWN_ENABLE;
168 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
169}
170
171static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
172{
173 u32 val;
174
175 if (!cnl_combo_phy_verify_state(dev_priv))
176 drm_warn(&dev_priv->drm,
177 "Combo PHY HW state changed unexpectedly.\n");
178
179 val = intel_de_read(dev_priv, CHICKEN_MISC_2);
180 val |= CNL_COMP_PWR_DOWN;
181 intel_de_write(dev_priv, CHICKEN_MISC_2, val);
182}
183
184static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
185{
186 /*
187 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
188 * PHY-B and may not even have instances of the register for the
189 * other combo PHY's.
190 */
191 if (IS_ELKHARTLAKE(i915) ||
192 IS_ROCKETLAKE(i915))
193 return phy < PHY_C;
194
195 return true;
196}
197
198static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
199 enum phy phy)
200{
201 /* The PHY C added by EHL has no PHY_MISC register */
202 if (!has_phy_misc(dev_priv, phy))
203 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
204 else
205 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
206 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
207 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
208}
209
210static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
211{
212 bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A);
213 bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D);
214 bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
215
216 /*
217 * VBT's 'dvo port' field for child devices references the DDI, not
218 * the PHY. So if combo PHY A is wired up to drive an external
219 * display, we should see a child device present on PORT_D and
220 * nothing on PORT_A and no DSI.
221 */
222 if (ddi_d_present && !ddi_a_present && !dsi_present)
223 return true;
224
225 /*
226 * If we encounter a VBT that claims to have an external display on
227 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message
228 * in the log and let the internal display win.
229 */
230 if (ddi_d_present)
231 drm_err(&i915->drm,
232 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n");
233
234 return false;
235}
236
237static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
238{
239 /*
240 * Certain PHYs are connected to compensation resistors and act
241 * as masters to other PHYs.
242 *
243 * ICL,TGL:
244 * A(master) -> B(slave), C(slave)
245 * RKL:
246 * A(master) -> B(slave)
247 * C(master) -> D(slave)
248 *
249 * We must set the IREFGEN bit for any PHY acting as a master
250 * to another PHY.
251 */
252 if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
253 return true;
254
255 return phy == PHY_A;
256}
257
258static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
259 enum phy phy)
260{
261 bool ret = true;
262 u32 expected_val = 0;
263
264 if (!icl_combo_phy_enabled(dev_priv, phy))
265 return false;
266
267 if (INTEL_GEN(dev_priv) >= 12) {
268 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy),
269 ICL_PORT_TX_DW8_ODCC_CLK_SEL |
270 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
271 ICL_PORT_TX_DW8_ODCC_CLK_SEL |
272 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
273
274 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy),
275 DCC_MODE_SELECT_MASK,
276 DCC_MODE_SELECT_CONTINUOSLY);
277 }
278
279 ret &= cnl_verify_procmon_ref_values(dev_priv, phy);
280
281 if (phy_is_master(dev_priv, phy)) {
282 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
283 IREFGEN, IREFGEN);
284
285 if (IS_ELKHARTLAKE(dev_priv)) {
286 if (ehl_vbt_ddi_d_present(dev_priv))
287 expected_val = ICL_PHY_MISC_MUX_DDID;
288
289 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),
290 ICL_PHY_MISC_MUX_DDID,
291 expected_val);
292 }
293 }
294
295 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
296 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
297
298 return ret;
299}
300
301void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
302 enum phy phy, bool is_dsi,
303 int lane_count, bool lane_reversal)
304{
305 u8 lane_mask;
306 u32 val;
307
308 if (is_dsi) {
309 drm_WARN_ON(&dev_priv->drm, lane_reversal);
310
311 switch (lane_count) {
312 case 1:
313 lane_mask = PWR_DOWN_LN_3_1_0;
314 break;
315 case 2:
316 lane_mask = PWR_DOWN_LN_3_1;
317 break;
318 case 3:
319 lane_mask = PWR_DOWN_LN_3;
320 break;
321 default:
322 MISSING_CASE(lane_count);
323 fallthrough;
324 case 4:
325 lane_mask = PWR_UP_ALL_LANES;
326 break;
327 }
328 } else {
329 switch (lane_count) {
330 case 1:
331 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :
332 PWR_DOWN_LN_3_2_1;
333 break;
334 case 2:
335 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :
336 PWR_DOWN_LN_3_2;
337 break;
338 default:
339 MISSING_CASE(lane_count);
340 fallthrough;
341 case 4:
342 lane_mask = PWR_UP_ALL_LANES;
343 break;
344 }
345 }
346
347 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));
348 val &= ~PWR_DOWN_LN_MASK;
349 val |= lane_mask << PWR_DOWN_LN_SHIFT;
350 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
351}
352
353static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
354{
355 enum phy phy;
356
357 for_each_combo_phy(dev_priv, phy) {
358 u32 val;
359
360 if (icl_combo_phy_verify_state(dev_priv, phy)) {
361 drm_dbg(&dev_priv->drm,
362 "Combo PHY %c already enabled, won't reprogram it.\n",
363 phy_name(phy));
364 continue;
365 }
366
367 if (!has_phy_misc(dev_priv, phy))
368 goto skip_phy_misc;
369
370 /*
371 * EHL's combo PHY A can be hooked up to either an external
372 * display (via DDI-D) or an internal display (via DDI-A or
373 * the DSI DPHY). This is a motherboard design decision that
374 * can't be changed on the fly, so initialize the PHY's mux
375 * based on whether our VBT indicates the presence of any
376 * "internal" child devices.
377 */
378 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
379 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) {
380 val &= ~ICL_PHY_MISC_MUX_DDID;
381
382 if (ehl_vbt_ddi_d_present(dev_priv))
383 val |= ICL_PHY_MISC_MUX_DDID;
384 }
385
386 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
387 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
388
389skip_phy_misc:
390 if (INTEL_GEN(dev_priv) >= 12) {
391 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
392 val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
393 val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
394 val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
395 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
396
397 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
398 val &= ~DCC_MODE_SELECT_MASK;
399 val |= DCC_MODE_SELECT_CONTINUOSLY;
400 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
401 }
402
403 cnl_set_procmon_ref_values(dev_priv, phy);
404
405 if (phy_is_master(dev_priv, phy)) {
406 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
407 val |= IREFGEN;
408 intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);
409 }
410
411 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
412 val |= COMP_INIT;
413 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
414
415 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
416 val |= CL_POWER_DOWN_ENABLE;
417 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
418 }
419}
420
421static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
422{
423 enum phy phy;
424
425 for_each_combo_phy_reverse(dev_priv, phy) {
426 u32 val;
427
428 if (phy == PHY_A &&
429 !icl_combo_phy_verify_state(dev_priv, phy))
430 drm_warn(&dev_priv->drm,
431 "Combo PHY %c HW state changed unexpectedly\n",
432 phy_name(phy));
433
434 if (!has_phy_misc(dev_priv, phy))
435 goto skip_phy_misc;
436
437 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
438 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
439 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
440
441skip_phy_misc:
442 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
443 val &= ~COMP_INIT;
444 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
445 }
446}
447
448void intel_combo_phy_init(struct drm_i915_private *i915)
449{
450 if (INTEL_GEN(i915) >= 11)
451 icl_combo_phys_init(i915);
452 else if (IS_CANNONLAKE(i915))
453 cnl_combo_phys_init(i915);
454}
455
456void intel_combo_phy_uninit(struct drm_i915_private *i915)
457{
458 if (INTEL_GEN(i915) >= 11)
459 icl_combo_phys_uninit(i915);
460 else if (IS_CANNONLAKE(i915))
461 cnl_combo_phys_uninit(i915);
462}