Loading...
1/*
2 * Copyright © 2006-2011 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 */
20
21#include <linux/i2c.h>
22
23#include <drm/drmP.h>
24#include <drm/drm_plane_helper.h>
25#include "framebuffer.h"
26#include "psb_drv.h"
27#include "psb_intel_drv.h"
28#include "psb_intel_reg.h"
29#include "gma_display.h"
30#include "power.h"
31
32#define INTEL_LIMIT_I9XX_SDVO_DAC 0
33#define INTEL_LIMIT_I9XX_LVDS 1
34
35static const struct gma_limit_t psb_intel_limits[] = {
36 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
37 .dot = {.min = 20000, .max = 400000},
38 .vco = {.min = 1400000, .max = 2800000},
39 .n = {.min = 1, .max = 6},
40 .m = {.min = 70, .max = 120},
41 .m1 = {.min = 8, .max = 18},
42 .m2 = {.min = 3, .max = 7},
43 .p = {.min = 5, .max = 80},
44 .p1 = {.min = 1, .max = 8},
45 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
46 .find_pll = gma_find_best_pll,
47 },
48 { /* INTEL_LIMIT_I9XX_LVDS */
49 .dot = {.min = 20000, .max = 400000},
50 .vco = {.min = 1400000, .max = 2800000},
51 .n = {.min = 1, .max = 6},
52 .m = {.min = 70, .max = 120},
53 .m1 = {.min = 8, .max = 18},
54 .m2 = {.min = 3, .max = 7},
55 .p = {.min = 7, .max = 98},
56 .p1 = {.min = 1, .max = 8},
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
59 */
60 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
61 .find_pll = gma_find_best_pll,
62 },
63};
64
65static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
66 int refclk)
67{
68 const struct gma_limit_t *limit;
69
70 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
71 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
72 else
73 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
74 return limit;
75}
76
77static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
78{
79 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
80 clock->p = clock->p1 * clock->p2;
81 clock->vco = refclk * clock->m / (clock->n + 2);
82 clock->dot = clock->vco / clock->p;
83}
84
85/**
86 * Return the pipe currently connected to the panel fitter,
87 * or -1 if the panel fitter is not present or not in use
88 */
89static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
90{
91 u32 pfit_control;
92
93 pfit_control = REG_READ(PFIT_CONTROL);
94
95 /* See if the panel fitter is in use */
96 if ((pfit_control & PFIT_ENABLE) == 0)
97 return -1;
98 /* Must be on PIPE 1 for PSB */
99 return 1;
100}
101
102static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
103 struct drm_display_mode *mode,
104 struct drm_display_mode *adjusted_mode,
105 int x, int y,
106 struct drm_framebuffer *old_fb)
107{
108 struct drm_device *dev = crtc->dev;
109 struct drm_psb_private *dev_priv = dev->dev_private;
110 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
111 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
112 int pipe = gma_crtc->pipe;
113 const struct psb_offset *map = &dev_priv->regmap[pipe];
114 int refclk;
115 struct gma_clock_t clock;
116 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
117 bool ok, is_sdvo = false;
118 bool is_lvds = false, is_tv = false;
119 struct drm_mode_config *mode_config = &dev->mode_config;
120 struct drm_connector *connector;
121 const struct gma_limit_t *limit;
122
123 /* No scan out no play */
124 if (crtc->primary->fb == NULL) {
125 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
126 return 0;
127 }
128
129 list_for_each_entry(connector, &mode_config->connector_list, head) {
130 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
131
132 if (!connector->encoder
133 || connector->encoder->crtc != crtc)
134 continue;
135
136 switch (gma_encoder->type) {
137 case INTEL_OUTPUT_LVDS:
138 is_lvds = true;
139 break;
140 case INTEL_OUTPUT_SDVO:
141 is_sdvo = true;
142 break;
143 case INTEL_OUTPUT_TVOUT:
144 is_tv = true;
145 break;
146 }
147 }
148
149 refclk = 96000;
150
151 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
152
153 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
154 &clock);
155 if (!ok) {
156 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
157 adjusted_mode->clock, clock.dot);
158 return 0;
159 }
160
161 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
162
163 dpll = DPLL_VGA_MODE_DIS;
164 if (is_lvds) {
165 dpll |= DPLLB_MODE_LVDS;
166 dpll |= DPLL_DVO_HIGH_SPEED;
167 } else
168 dpll |= DPLLB_MODE_DAC_SERIAL;
169 if (is_sdvo) {
170 int sdvo_pixel_multiply =
171 adjusted_mode->clock / mode->clock;
172 dpll |= DPLL_DVO_HIGH_SPEED;
173 dpll |=
174 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
175 }
176
177 /* compute bitmask from p1 value */
178 dpll |= (1 << (clock.p1 - 1)) << 16;
179 switch (clock.p2) {
180 case 5:
181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
182 break;
183 case 7:
184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
185 break;
186 case 10:
187 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
188 break;
189 case 14:
190 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
191 break;
192 }
193
194 if (is_tv) {
195 /* XXX: just matching BIOS for now */
196/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
197 dpll |= 3;
198 }
199 dpll |= PLL_REF_INPUT_DREFCLK;
200
201 /* setup pipeconf */
202 pipeconf = REG_READ(map->conf);
203
204 /* Set up the display plane register */
205 dspcntr = DISPPLANE_GAMMA_ENABLE;
206
207 if (pipe == 0)
208 dspcntr |= DISPPLANE_SEL_PIPE_A;
209 else
210 dspcntr |= DISPPLANE_SEL_PIPE_B;
211
212 dspcntr |= DISPLAY_PLANE_ENABLE;
213 pipeconf |= PIPEACONF_ENABLE;
214 dpll |= DPLL_VCO_ENABLE;
215
216
217 /* Disable the panel fitter if it was on our pipe */
218 if (psb_intel_panel_fitter_pipe(dev) == pipe)
219 REG_WRITE(PFIT_CONTROL, 0);
220
221 drm_mode_debug_printmodeline(mode);
222
223 if (dpll & DPLL_VCO_ENABLE) {
224 REG_WRITE(map->fp0, fp);
225 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
226 REG_READ(map->dpll);
227 udelay(150);
228 }
229
230 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
231 * This is an exception to the general rule that mode_set doesn't turn
232 * things on.
233 */
234 if (is_lvds) {
235 u32 lvds = REG_READ(LVDS);
236
237 lvds &= ~LVDS_PIPEB_SELECT;
238 if (pipe == 1)
239 lvds |= LVDS_PIPEB_SELECT;
240
241 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
242 /* Set the B0-B3 data pairs corresponding to
243 * whether we're going to
244 * set the DPLLs for dual-channel mode or not.
245 */
246 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
247 if (clock.p2 == 7)
248 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
249
250 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
251 * appropriately here, but we need to look more
252 * thoroughly into how panels behave in the two modes.
253 */
254
255 REG_WRITE(LVDS, lvds);
256 REG_READ(LVDS);
257 }
258
259 REG_WRITE(map->fp0, fp);
260 REG_WRITE(map->dpll, dpll);
261 REG_READ(map->dpll);
262 /* Wait for the clocks to stabilize. */
263 udelay(150);
264
265 /* write it again -- the BIOS does, after all */
266 REG_WRITE(map->dpll, dpll);
267
268 REG_READ(map->dpll);
269 /* Wait for the clocks to stabilize. */
270 udelay(150);
271
272 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
273 ((adjusted_mode->crtc_htotal - 1) << 16));
274 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
275 ((adjusted_mode->crtc_hblank_end - 1) << 16));
276 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
277 ((adjusted_mode->crtc_hsync_end - 1) << 16));
278 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
279 ((adjusted_mode->crtc_vtotal - 1) << 16));
280 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
281 ((adjusted_mode->crtc_vblank_end - 1) << 16));
282 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
283 ((adjusted_mode->crtc_vsync_end - 1) << 16));
284 /* pipesrc and dspsize control the size that is scaled from,
285 * which should always be the user's requested size.
286 */
287 REG_WRITE(map->size,
288 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
289 REG_WRITE(map->pos, 0);
290 REG_WRITE(map->src,
291 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
292 REG_WRITE(map->conf, pipeconf);
293 REG_READ(map->conf);
294
295 gma_wait_for_vblank(dev);
296
297 REG_WRITE(map->cntr, dspcntr);
298
299 /* Flush the plane changes */
300 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
301
302 gma_wait_for_vblank(dev);
303
304 return 0;
305}
306
307/* Returns the clock of the currently programmed mode of the given pipe. */
308static int psb_intel_crtc_clock_get(struct drm_device *dev,
309 struct drm_crtc *crtc)
310{
311 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
312 struct drm_psb_private *dev_priv = dev->dev_private;
313 int pipe = gma_crtc->pipe;
314 const struct psb_offset *map = &dev_priv->regmap[pipe];
315 u32 dpll;
316 u32 fp;
317 struct gma_clock_t clock;
318 bool is_lvds;
319 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
320
321 if (gma_power_begin(dev, false)) {
322 dpll = REG_READ(map->dpll);
323 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
324 fp = REG_READ(map->fp0);
325 else
326 fp = REG_READ(map->fp1);
327 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
328 gma_power_end(dev);
329 } else {
330 dpll = p->dpll;
331
332 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
333 fp = p->fp0;
334 else
335 fp = p->fp1;
336
337 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
338 LVDS_PORT_EN);
339 }
340
341 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
342 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
343 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
344
345 if (is_lvds) {
346 clock.p1 =
347 ffs((dpll &
348 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
349 DPLL_FPA01_P1_POST_DIV_SHIFT);
350 clock.p2 = 14;
351
352 if ((dpll & PLL_REF_INPUT_MASK) ==
353 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
354 /* XXX: might not be 66MHz */
355 psb_intel_clock(66000, &clock);
356 } else
357 psb_intel_clock(48000, &clock);
358 } else {
359 if (dpll & PLL_P1_DIVIDE_BY_TWO)
360 clock.p1 = 2;
361 else {
362 clock.p1 =
363 ((dpll &
364 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
365 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
366 }
367 if (dpll & PLL_P2_DIVIDE_BY_4)
368 clock.p2 = 4;
369 else
370 clock.p2 = 2;
371
372 psb_intel_clock(48000, &clock);
373 }
374
375 /* XXX: It would be nice to validate the clocks, but we can't reuse
376 * i830PllIsValid() because it relies on the xf86_config connector
377 * configuration being accurate, which it isn't necessarily.
378 */
379
380 return clock.dot;
381}
382
383/** Returns the currently programmed mode of the given pipe. */
384struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
385 struct drm_crtc *crtc)
386{
387 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
388 int pipe = gma_crtc->pipe;
389 struct drm_display_mode *mode;
390 int htot;
391 int hsync;
392 int vtot;
393 int vsync;
394 struct drm_psb_private *dev_priv = dev->dev_private;
395 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
396 const struct psb_offset *map = &dev_priv->regmap[pipe];
397
398 if (gma_power_begin(dev, false)) {
399 htot = REG_READ(map->htotal);
400 hsync = REG_READ(map->hsync);
401 vtot = REG_READ(map->vtotal);
402 vsync = REG_READ(map->vsync);
403 gma_power_end(dev);
404 } else {
405 htot = p->htotal;
406 hsync = p->hsync;
407 vtot = p->vtotal;
408 vsync = p->vsync;
409 }
410
411 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
412 if (!mode)
413 return NULL;
414
415 mode->clock = psb_intel_crtc_clock_get(dev, crtc);
416 mode->hdisplay = (htot & 0xffff) + 1;
417 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
418 mode->hsync_start = (hsync & 0xffff) + 1;
419 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
420 mode->vdisplay = (vtot & 0xffff) + 1;
421 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
422 mode->vsync_start = (vsync & 0xffff) + 1;
423 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
424
425 drm_mode_set_name(mode);
426 drm_mode_set_crtcinfo(mode, 0);
427
428 return mode;
429}
430
431const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
432 .dpms = gma_crtc_dpms,
433 .mode_set = psb_intel_crtc_mode_set,
434 .mode_set_base = gma_pipe_set_base,
435 .prepare = gma_crtc_prepare,
436 .commit = gma_crtc_commit,
437 .disable = gma_crtc_disable,
438};
439
440const struct drm_crtc_funcs psb_intel_crtc_funcs = {
441 .cursor_set = gma_crtc_cursor_set,
442 .cursor_move = gma_crtc_cursor_move,
443 .gamma_set = gma_crtc_gamma_set,
444 .set_config = gma_crtc_set_config,
445 .destroy = gma_crtc_destroy,
446};
447
448const struct gma_clock_funcs psb_clock_funcs = {
449 .clock = psb_intel_clock,
450 .limit = psb_intel_limit,
451 .pll_is_valid = gma_pll_is_valid,
452};
453
454/*
455 * Set the default value of cursor control and base register
456 * to zero. This is a workaround for h/w defect on Oaktrail
457 */
458static void psb_intel_cursor_init(struct drm_device *dev,
459 struct gma_crtc *gma_crtc)
460{
461 struct drm_psb_private *dev_priv = dev->dev_private;
462 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
463 u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
464 struct gtt_range *cursor_gt;
465
466 if (dev_priv->ops->cursor_needs_phys) {
467 /* Allocate 4 pages of stolen mem for a hardware cursor. That
468 * is enough for the 64 x 64 ARGB cursors we support.
469 */
470 cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1,
471 PAGE_SIZE);
472 if (!cursor_gt) {
473 gma_crtc->cursor_gt = NULL;
474 goto out;
475 }
476 gma_crtc->cursor_gt = cursor_gt;
477 gma_crtc->cursor_addr = dev_priv->stolen_base +
478 cursor_gt->offset;
479 } else {
480 gma_crtc->cursor_gt = NULL;
481 }
482
483out:
484 REG_WRITE(control[gma_crtc->pipe], 0);
485 REG_WRITE(base[gma_crtc->pipe], 0);
486}
487
488void psb_intel_crtc_init(struct drm_device *dev, int pipe,
489 struct psb_intel_mode_device *mode_dev)
490{
491 struct drm_psb_private *dev_priv = dev->dev_private;
492 struct gma_crtc *gma_crtc;
493 int i;
494 uint16_t *r_base, *g_base, *b_base;
495
496 /* We allocate a extra array of drm_connector pointers
497 * for fbdev after the crtc */
498 gma_crtc = kzalloc(sizeof(struct gma_crtc) +
499 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
500 GFP_KERNEL);
501 if (gma_crtc == NULL)
502 return;
503
504 gma_crtc->crtc_state =
505 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
506 if (!gma_crtc->crtc_state) {
507 dev_err(dev->dev, "Crtc state error: No memory\n");
508 kfree(gma_crtc);
509 return;
510 }
511
512 /* Set the CRTC operations from the chip specific data */
513 drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs);
514
515 /* Set the CRTC clock functions from chip specific data */
516 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
517
518 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
519 gma_crtc->pipe = pipe;
520 gma_crtc->plane = pipe;
521
522 r_base = gma_crtc->base.gamma_store;
523 g_base = r_base + 256;
524 b_base = g_base + 256;
525 for (i = 0; i < 256; i++) {
526 gma_crtc->lut_r[i] = i;
527 gma_crtc->lut_g[i] = i;
528 gma_crtc->lut_b[i] = i;
529 r_base[i] = i << 8;
530 g_base[i] = i << 8;
531 b_base[i] = i << 8;
532
533 gma_crtc->lut_adj[i] = 0;
534 }
535
536 gma_crtc->mode_dev = mode_dev;
537 gma_crtc->cursor_addr = 0;
538
539 drm_crtc_helper_add(&gma_crtc->base,
540 dev_priv->ops->crtc_helper);
541
542 /* Setup the array of drm_connector pointer array */
543 gma_crtc->mode_set.crtc = &gma_crtc->base;
544 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
545 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
546 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
547 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
548 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
549 gma_crtc->mode_set.num_connectors = 0;
550 psb_intel_cursor_init(dev, gma_crtc);
551
552 /* Set to true so that the pipe is forced off on initial config. */
553 gma_crtc->active = true;
554}
555
556struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
557{
558 struct drm_crtc *crtc = NULL;
559
560 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
561 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
562 if (gma_crtc->pipe == pipe)
563 break;
564 }
565 return crtc;
566}
567
568int gma_connector_clones(struct drm_device *dev, int type_mask)
569{
570 int index_mask = 0;
571 struct drm_connector *connector;
572 int entry = 0;
573
574 list_for_each_entry(connector, &dev->mode_config.connector_list,
575 head) {
576 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
577 if (type_mask & (1 << gma_encoder->type))
578 index_mask |= (1 << entry);
579 entry++;
580 }
581 return index_mask;
582}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright © 2006-2011 Intel Corporation
4 *
5 * Authors:
6 * Eric Anholt <eric@anholt.net>
7 */
8
9#include <linux/delay.h>
10#include <linux/i2c.h>
11
12#include <drm/drm_plane_helper.h>
13
14#include "framebuffer.h"
15#include "gma_display.h"
16#include "power.h"
17#include "psb_drv.h"
18#include "psb_intel_drv.h"
19#include "psb_intel_reg.h"
20
21#define INTEL_LIMIT_I9XX_SDVO_DAC 0
22#define INTEL_LIMIT_I9XX_LVDS 1
23
24static const struct gma_limit_t psb_intel_limits[] = {
25 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
26 .dot = {.min = 20000, .max = 400000},
27 .vco = {.min = 1400000, .max = 2800000},
28 .n = {.min = 1, .max = 6},
29 .m = {.min = 70, .max = 120},
30 .m1 = {.min = 8, .max = 18},
31 .m2 = {.min = 3, .max = 7},
32 .p = {.min = 5, .max = 80},
33 .p1 = {.min = 1, .max = 8},
34 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
35 .find_pll = gma_find_best_pll,
36 },
37 { /* INTEL_LIMIT_I9XX_LVDS */
38 .dot = {.min = 20000, .max = 400000},
39 .vco = {.min = 1400000, .max = 2800000},
40 .n = {.min = 1, .max = 6},
41 .m = {.min = 70, .max = 120},
42 .m1 = {.min = 8, .max = 18},
43 .m2 = {.min = 3, .max = 7},
44 .p = {.min = 7, .max = 98},
45 .p1 = {.min = 1, .max = 8},
46 /* The single-channel range is 25-112Mhz, and dual-channel
47 * is 80-224Mhz. Prefer single channel as much as possible.
48 */
49 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
50 .find_pll = gma_find_best_pll,
51 },
52};
53
54static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
55 int refclk)
56{
57 const struct gma_limit_t *limit;
58
59 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
60 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
61 else
62 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
63 return limit;
64}
65
66static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
67{
68 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
69 clock->p = clock->p1 * clock->p2;
70 clock->vco = refclk * clock->m / (clock->n + 2);
71 clock->dot = clock->vco / clock->p;
72}
73
74/**
75 * Return the pipe currently connected to the panel fitter,
76 * or -1 if the panel fitter is not present or not in use
77 */
78static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
79{
80 u32 pfit_control;
81
82 pfit_control = REG_READ(PFIT_CONTROL);
83
84 /* See if the panel fitter is in use */
85 if ((pfit_control & PFIT_ENABLE) == 0)
86 return -1;
87 /* Must be on PIPE 1 for PSB */
88 return 1;
89}
90
91static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
92 struct drm_display_mode *mode,
93 struct drm_display_mode *adjusted_mode,
94 int x, int y,
95 struct drm_framebuffer *old_fb)
96{
97 struct drm_device *dev = crtc->dev;
98 struct drm_psb_private *dev_priv = dev->dev_private;
99 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
100 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
101 int pipe = gma_crtc->pipe;
102 const struct psb_offset *map = &dev_priv->regmap[pipe];
103 int refclk;
104 struct gma_clock_t clock;
105 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
106 bool ok, is_sdvo = false;
107 bool is_lvds = false, is_tv = false;
108 struct drm_mode_config *mode_config = &dev->mode_config;
109 struct drm_connector *connector;
110 const struct gma_limit_t *limit;
111
112 /* No scan out no play */
113 if (crtc->primary->fb == NULL) {
114 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
115 return 0;
116 }
117
118 list_for_each_entry(connector, &mode_config->connector_list, head) {
119 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
120
121 if (!connector->encoder
122 || connector->encoder->crtc != crtc)
123 continue;
124
125 switch (gma_encoder->type) {
126 case INTEL_OUTPUT_LVDS:
127 is_lvds = true;
128 break;
129 case INTEL_OUTPUT_SDVO:
130 is_sdvo = true;
131 break;
132 case INTEL_OUTPUT_TVOUT:
133 is_tv = true;
134 break;
135 }
136 }
137
138 refclk = 96000;
139
140 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
141
142 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
143 &clock);
144 if (!ok) {
145 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
146 adjusted_mode->clock, clock.dot);
147 return 0;
148 }
149
150 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
151
152 dpll = DPLL_VGA_MODE_DIS;
153 if (is_lvds) {
154 dpll |= DPLLB_MODE_LVDS;
155 dpll |= DPLL_DVO_HIGH_SPEED;
156 } else
157 dpll |= DPLLB_MODE_DAC_SERIAL;
158 if (is_sdvo) {
159 int sdvo_pixel_multiply =
160 adjusted_mode->clock / mode->clock;
161 dpll |= DPLL_DVO_HIGH_SPEED;
162 dpll |=
163 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
164 }
165
166 /* compute bitmask from p1 value */
167 dpll |= (1 << (clock.p1 - 1)) << 16;
168 switch (clock.p2) {
169 case 5:
170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
171 break;
172 case 7:
173 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
174 break;
175 case 10:
176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
177 break;
178 case 14:
179 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
180 break;
181 }
182
183 if (is_tv) {
184 /* XXX: just matching BIOS for now */
185/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
186 dpll |= 3;
187 }
188 dpll |= PLL_REF_INPUT_DREFCLK;
189
190 /* setup pipeconf */
191 pipeconf = REG_READ(map->conf);
192
193 /* Set up the display plane register */
194 dspcntr = DISPPLANE_GAMMA_ENABLE;
195
196 if (pipe == 0)
197 dspcntr |= DISPPLANE_SEL_PIPE_A;
198 else
199 dspcntr |= DISPPLANE_SEL_PIPE_B;
200
201 dspcntr |= DISPLAY_PLANE_ENABLE;
202 pipeconf |= PIPEACONF_ENABLE;
203 dpll |= DPLL_VCO_ENABLE;
204
205
206 /* Disable the panel fitter if it was on our pipe */
207 if (psb_intel_panel_fitter_pipe(dev) == pipe)
208 REG_WRITE(PFIT_CONTROL, 0);
209
210 drm_mode_debug_printmodeline(mode);
211
212 if (dpll & DPLL_VCO_ENABLE) {
213 REG_WRITE(map->fp0, fp);
214 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
215 REG_READ(map->dpll);
216 udelay(150);
217 }
218
219 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
220 * This is an exception to the general rule that mode_set doesn't turn
221 * things on.
222 */
223 if (is_lvds) {
224 u32 lvds = REG_READ(LVDS);
225
226 lvds &= ~LVDS_PIPEB_SELECT;
227 if (pipe == 1)
228 lvds |= LVDS_PIPEB_SELECT;
229
230 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
231 /* Set the B0-B3 data pairs corresponding to
232 * whether we're going to
233 * set the DPLLs for dual-channel mode or not.
234 */
235 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
236 if (clock.p2 == 7)
237 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
238
239 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
240 * appropriately here, but we need to look more
241 * thoroughly into how panels behave in the two modes.
242 */
243
244 REG_WRITE(LVDS, lvds);
245 REG_READ(LVDS);
246 }
247
248 REG_WRITE(map->fp0, fp);
249 REG_WRITE(map->dpll, dpll);
250 REG_READ(map->dpll);
251 /* Wait for the clocks to stabilize. */
252 udelay(150);
253
254 /* write it again -- the BIOS does, after all */
255 REG_WRITE(map->dpll, dpll);
256
257 REG_READ(map->dpll);
258 /* Wait for the clocks to stabilize. */
259 udelay(150);
260
261 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
262 ((adjusted_mode->crtc_htotal - 1) << 16));
263 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
264 ((adjusted_mode->crtc_hblank_end - 1) << 16));
265 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
266 ((adjusted_mode->crtc_hsync_end - 1) << 16));
267 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
268 ((adjusted_mode->crtc_vtotal - 1) << 16));
269 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
270 ((adjusted_mode->crtc_vblank_end - 1) << 16));
271 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
272 ((adjusted_mode->crtc_vsync_end - 1) << 16));
273 /* pipesrc and dspsize control the size that is scaled from,
274 * which should always be the user's requested size.
275 */
276 REG_WRITE(map->size,
277 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
278 REG_WRITE(map->pos, 0);
279 REG_WRITE(map->src,
280 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
281 REG_WRITE(map->conf, pipeconf);
282 REG_READ(map->conf);
283
284 gma_wait_for_vblank(dev);
285
286 REG_WRITE(map->cntr, dspcntr);
287
288 /* Flush the plane changes */
289 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
290
291 gma_wait_for_vblank(dev);
292
293 return 0;
294}
295
296/* Returns the clock of the currently programmed mode of the given pipe. */
297static int psb_intel_crtc_clock_get(struct drm_device *dev,
298 struct drm_crtc *crtc)
299{
300 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
301 struct drm_psb_private *dev_priv = dev->dev_private;
302 int pipe = gma_crtc->pipe;
303 const struct psb_offset *map = &dev_priv->regmap[pipe];
304 u32 dpll;
305 u32 fp;
306 struct gma_clock_t clock;
307 bool is_lvds;
308 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
309
310 if (gma_power_begin(dev, false)) {
311 dpll = REG_READ(map->dpll);
312 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
313 fp = REG_READ(map->fp0);
314 else
315 fp = REG_READ(map->fp1);
316 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
317 gma_power_end(dev);
318 } else {
319 dpll = p->dpll;
320
321 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
322 fp = p->fp0;
323 else
324 fp = p->fp1;
325
326 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
327 LVDS_PORT_EN);
328 }
329
330 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
331 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
332 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
333
334 if (is_lvds) {
335 clock.p1 =
336 ffs((dpll &
337 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
338 DPLL_FPA01_P1_POST_DIV_SHIFT);
339 clock.p2 = 14;
340
341 if ((dpll & PLL_REF_INPUT_MASK) ==
342 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
343 /* XXX: might not be 66MHz */
344 psb_intel_clock(66000, &clock);
345 } else
346 psb_intel_clock(48000, &clock);
347 } else {
348 if (dpll & PLL_P1_DIVIDE_BY_TWO)
349 clock.p1 = 2;
350 else {
351 clock.p1 =
352 ((dpll &
353 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
354 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
355 }
356 if (dpll & PLL_P2_DIVIDE_BY_4)
357 clock.p2 = 4;
358 else
359 clock.p2 = 2;
360
361 psb_intel_clock(48000, &clock);
362 }
363
364 /* XXX: It would be nice to validate the clocks, but we can't reuse
365 * i830PllIsValid() because it relies on the xf86_config connector
366 * configuration being accurate, which it isn't necessarily.
367 */
368
369 return clock.dot;
370}
371
372/** Returns the currently programmed mode of the given pipe. */
373struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
374 struct drm_crtc *crtc)
375{
376 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
377 int pipe = gma_crtc->pipe;
378 struct drm_display_mode *mode;
379 int htot;
380 int hsync;
381 int vtot;
382 int vsync;
383 struct drm_psb_private *dev_priv = dev->dev_private;
384 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
385 const struct psb_offset *map = &dev_priv->regmap[pipe];
386
387 if (gma_power_begin(dev, false)) {
388 htot = REG_READ(map->htotal);
389 hsync = REG_READ(map->hsync);
390 vtot = REG_READ(map->vtotal);
391 vsync = REG_READ(map->vsync);
392 gma_power_end(dev);
393 } else {
394 htot = p->htotal;
395 hsync = p->hsync;
396 vtot = p->vtotal;
397 vsync = p->vsync;
398 }
399
400 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
401 if (!mode)
402 return NULL;
403
404 mode->clock = psb_intel_crtc_clock_get(dev, crtc);
405 mode->hdisplay = (htot & 0xffff) + 1;
406 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
407 mode->hsync_start = (hsync & 0xffff) + 1;
408 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
409 mode->vdisplay = (vtot & 0xffff) + 1;
410 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
411 mode->vsync_start = (vsync & 0xffff) + 1;
412 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
413
414 drm_mode_set_name(mode);
415 drm_mode_set_crtcinfo(mode, 0);
416
417 return mode;
418}
419
420const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
421 .dpms = gma_crtc_dpms,
422 .mode_set = psb_intel_crtc_mode_set,
423 .mode_set_base = gma_pipe_set_base,
424 .prepare = gma_crtc_prepare,
425 .commit = gma_crtc_commit,
426 .disable = gma_crtc_disable,
427};
428
429const struct drm_crtc_funcs psb_intel_crtc_funcs = {
430 .cursor_set = gma_crtc_cursor_set,
431 .cursor_move = gma_crtc_cursor_move,
432 .gamma_set = gma_crtc_gamma_set,
433 .set_config = gma_crtc_set_config,
434 .destroy = gma_crtc_destroy,
435 .page_flip = gma_crtc_page_flip,
436 .enable_vblank = psb_enable_vblank,
437 .disable_vblank = psb_disable_vblank,
438 .get_vblank_counter = psb_get_vblank_counter,
439};
440
441const struct gma_clock_funcs psb_clock_funcs = {
442 .clock = psb_intel_clock,
443 .limit = psb_intel_limit,
444 .pll_is_valid = gma_pll_is_valid,
445};
446
447/*
448 * Set the default value of cursor control and base register
449 * to zero. This is a workaround for h/w defect on Oaktrail
450 */
451static void psb_intel_cursor_init(struct drm_device *dev,
452 struct gma_crtc *gma_crtc)
453{
454 struct drm_psb_private *dev_priv = dev->dev_private;
455 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
456 u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
457 struct gtt_range *cursor_gt;
458
459 if (dev_priv->ops->cursor_needs_phys) {
460 /* Allocate 4 pages of stolen mem for a hardware cursor. That
461 * is enough for the 64 x 64 ARGB cursors we support.
462 */
463 cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1,
464 PAGE_SIZE);
465 if (!cursor_gt) {
466 gma_crtc->cursor_gt = NULL;
467 goto out;
468 }
469 gma_crtc->cursor_gt = cursor_gt;
470 gma_crtc->cursor_addr = dev_priv->stolen_base +
471 cursor_gt->offset;
472 } else {
473 gma_crtc->cursor_gt = NULL;
474 }
475
476out:
477 REG_WRITE(control[gma_crtc->pipe], 0);
478 REG_WRITE(base[gma_crtc->pipe], 0);
479}
480
481void psb_intel_crtc_init(struct drm_device *dev, int pipe,
482 struct psb_intel_mode_device *mode_dev)
483{
484 struct drm_psb_private *dev_priv = dev->dev_private;
485 struct gma_crtc *gma_crtc;
486 int i;
487
488 /* We allocate a extra array of drm_connector pointers
489 * for fbdev after the crtc */
490 gma_crtc = kzalloc(sizeof(struct gma_crtc) +
491 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
492 GFP_KERNEL);
493 if (gma_crtc == NULL)
494 return;
495
496 gma_crtc->crtc_state =
497 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
498 if (!gma_crtc->crtc_state) {
499 dev_err(dev->dev, "Crtc state error: No memory\n");
500 kfree(gma_crtc);
501 return;
502 }
503
504 /* Set the CRTC operations from the chip specific data */
505 drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs);
506
507 /* Set the CRTC clock functions from chip specific data */
508 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
509
510 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
511 gma_crtc->pipe = pipe;
512 gma_crtc->plane = pipe;
513
514 for (i = 0; i < 256; i++)
515 gma_crtc->lut_adj[i] = 0;
516
517 gma_crtc->mode_dev = mode_dev;
518 gma_crtc->cursor_addr = 0;
519
520 drm_crtc_helper_add(&gma_crtc->base,
521 dev_priv->ops->crtc_helper);
522
523 /* Setup the array of drm_connector pointer array */
524 gma_crtc->mode_set.crtc = &gma_crtc->base;
525 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
526 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
527 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
528 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
529 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
530 gma_crtc->mode_set.num_connectors = 0;
531 psb_intel_cursor_init(dev, gma_crtc);
532
533 /* Set to true so that the pipe is forced off on initial config. */
534 gma_crtc->active = true;
535}
536
537struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
538{
539 struct drm_crtc *crtc = NULL;
540
541 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
542 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
543 if (gma_crtc->pipe == pipe)
544 break;
545 }
546 return crtc;
547}
548
549int gma_connector_clones(struct drm_device *dev, int type_mask)
550{
551 int index_mask = 0;
552 struct drm_connector *connector;
553 int entry = 0;
554
555 list_for_each_entry(connector, &dev->mode_config.connector_list,
556 head) {
557 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
558 if (type_mask & (1 << gma_encoder->type))
559 index_mask |= (1 << entry);
560 entry++;
561 }
562 return index_mask;
563}