1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "../dmub_srv.h"
 27#include "dmub_reg.h"
 28#include "dmub_dcn20.h"
 29
 30#include "sienna_cichlid_ip_offset.h"
 31#include "dcn/dcn_3_0_0_offset.h"
 32#include "dcn/dcn_3_0_0_sh_mask.h"
 33
 34#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
 35#define CTX dmub
 36#define REGS dmub->regs
 37
 38/* Registers. */
 39
 40const struct dmub_srv_common_regs dmub_srv_dcn30_regs = {
 41#define DMUB_SR(reg) REG_OFFSET(reg),
 42	{ DMUB_COMMON_REGS() },
 43#undef DMUB_SR
 44
 45#define DMUB_SF(reg, field) FD_MASK(reg, field),
 46	{ DMUB_COMMON_FIELDS() },
 47#undef DMUB_SF
 48
 49#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
 50	{ DMUB_COMMON_FIELDS() },
 51#undef DMUB_SF
 52};
 53
 54/* Shared functions. */
 55
 56static void dmub_dcn30_get_fb_base_offset(struct dmub_srv *dmub,
 57					  uint64_t *fb_base,
 58					  uint64_t *fb_offset)
 59{
 60	uint32_t tmp;
 61
 62	if (dmub->fb_base || dmub->fb_offset) {
 63		*fb_base = dmub->fb_base;
 64		*fb_offset = dmub->fb_offset;
 65		return;
 66	}
 67
 68	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
 69	*fb_base = (uint64_t)tmp << 24;
 70
 71	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
 72	*fb_offset = (uint64_t)tmp << 24;
 73}
 74
 75static inline void dmub_dcn30_translate_addr(const union dmub_addr *addr_in,
 76					     uint64_t fb_base,
 77					     uint64_t fb_offset,
 78					     union dmub_addr *addr_out)
 79{
 80	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
 81}
 82
 83void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,
 84			      const struct dmub_window *cw0,
 85			      const struct dmub_window *cw1)
 86{
 87	union dmub_addr offset;
 88	uint64_t fb_base, fb_offset;
 89
 90	dmub_dcn30_get_fb_base_offset(dmub, &fb_base, &fb_offset);
 91
 92	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
 93
 94	/* MEM_CTNL read/write space doesn't exist. */
 95
 96	dmub_dcn30_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
 97
 98	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
 99	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
100	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
101	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
102		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
103		  DMCUB_REGION3_CW0_ENABLE, 1);
104
105	dmub_dcn30_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
106
107	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
108	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
109	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
110	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
111		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
112		  DMCUB_REGION3_CW1_ENABLE, 1);
113
114	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
115		     0x20);
116}
117
118void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
119			      const struct dmub_window *cw2,
120			      const struct dmub_window *cw3,
121			      const struct dmub_window *cw4,
122			      const struct dmub_window *cw5,
123			      const struct dmub_window *cw6)
124{
125	union dmub_addr offset;
126
127	/* sienna_cichlid  has hardwired virtual addressing for CW2-CW7 */
128
129	offset = cw2->offset;
130
131	if (cw2->region.base != cw2->region.top) {
132		REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
133		REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
134		REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
135		REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
136			  DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
137			  DMCUB_REGION3_CW2_ENABLE, 1);
138	} else {
139		REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
140		REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
141		REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
142		REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
143	}
144
145	offset = cw3->offset;
146
147	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
148	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
149	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
150	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
151		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
152		  DMCUB_REGION3_CW3_ENABLE, 1);
153
154	offset = cw4->offset;
155
156	/* New firmware can support CW4. */
157	if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10)) {
158		REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
159		REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
160		REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
161		REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
162			  DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
163			  DMCUB_REGION3_CW4_ENABLE, 1);
164	} else {
165		REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
166		REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
167		REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
168			  DMCUB_REGION4_TOP_ADDRESS,
169			  cw4->region.top - cw4->region.base - 1,
170			  DMCUB_REGION4_ENABLE, 1);
171	}
172
173	offset = cw5->offset;
174
175	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
176	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
177	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
178	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
179		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
180		  DMCUB_REGION3_CW5_ENABLE, 1);
181
182	offset = cw6->offset;
183
184	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
185	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
186	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
187	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
188		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
189		  DMCUB_REGION3_CW6_ENABLE, 1);
190}
191
192bool dmub_dcn30_is_auto_load_done(struct dmub_srv *dmub)
193{
194	return (REG_READ(DMCUB_SCRATCH0) > 0);
195}