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1/*
2 * Copyright 2012-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __FSL_SAI_H
10#define __FSL_SAI_H
11
12#include <sound/dmaengine_pcm.h>
13
14#define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
15 SNDRV_PCM_FMTBIT_S20_3LE |\
16 SNDRV_PCM_FMTBIT_S24_LE |\
17 SNDRV_PCM_FMTBIT_S32_LE)
18
19/* SAI Register Map Register */
20#define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */
21#define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */
22#define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */
23#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */
24#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */
25#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */
26#define FSL_SAI_TDR 0x20 /* SAI Transmit Data */
27#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */
28#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
29#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */
30#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */
31#define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */
32#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */
33#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */
34#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */
35#define FSL_SAI_RDR 0xa0 /* SAI Receive Data */
36#define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */
37#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
38
39#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
40#define FSL_SAI_xCR1(tx) (tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1)
41#define FSL_SAI_xCR2(tx) (tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2)
42#define FSL_SAI_xCR3(tx) (tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3)
43#define FSL_SAI_xCR4(tx) (tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4)
44#define FSL_SAI_xCR5(tx) (tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5)
45#define FSL_SAI_xDR(tx) (tx ? FSL_SAI_TDR : FSL_SAI_RDR)
46#define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR)
47#define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
48
49/* SAI Transmit/Receive Control Register */
50#define FSL_SAI_CSR_TERE BIT(31)
51#define FSL_SAI_CSR_FR BIT(25)
52#define FSL_SAI_CSR_SR BIT(24)
53#define FSL_SAI_CSR_xF_SHIFT 16
54#define FSL_SAI_CSR_xF_W_SHIFT 18
55#define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT)
56#define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT)
57#define FSL_SAI_CSR_WSF BIT(20)
58#define FSL_SAI_CSR_SEF BIT(19)
59#define FSL_SAI_CSR_FEF BIT(18)
60#define FSL_SAI_CSR_FWF BIT(17)
61#define FSL_SAI_CSR_FRF BIT(16)
62#define FSL_SAI_CSR_xIE_SHIFT 8
63#define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT)
64#define FSL_SAI_CSR_WSIE BIT(12)
65#define FSL_SAI_CSR_SEIE BIT(11)
66#define FSL_SAI_CSR_FEIE BIT(10)
67#define FSL_SAI_CSR_FWIE BIT(9)
68#define FSL_SAI_CSR_FRIE BIT(8)
69#define FSL_SAI_CSR_FRDE BIT(0)
70
71/* SAI Transmit and Receive Configuration 1 Register */
72#define FSL_SAI_CR1_RFW_MASK 0x1f
73
74/* SAI Transmit and Receive Configuration 2 Register */
75#define FSL_SAI_CR2_SYNC BIT(30)
76#define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
77#define FSL_SAI_CR2_MSEL_BUS 0
78#define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
79#define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
80#define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
81#define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
82#define FSL_SAI_CR2_BCP BIT(25)
83#define FSL_SAI_CR2_BCD_MSTR BIT(24)
84#define FSL_SAI_CR2_DIV_MASK 0xff
85
86/* SAI Transmit and Receive Configuration 3 Register */
87#define FSL_SAI_CR3_TRCE BIT(16)
88#define FSL_SAI_CR3_WDFL(x) (x)
89#define FSL_SAI_CR3_WDFL_MASK 0x1f
90
91/* SAI Transmit and Receive Configuration 4 Register */
92#define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
93#define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
94#define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
95#define FSL_SAI_CR4_SYWD_MASK (0x1f << 8)
96#define FSL_SAI_CR4_MF BIT(4)
97#define FSL_SAI_CR4_FSE BIT(3)
98#define FSL_SAI_CR4_FSP BIT(1)
99#define FSL_SAI_CR4_FSD_MSTR BIT(0)
100
101/* SAI Transmit and Receive Configuration 5 Register */
102#define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24)
103#define FSL_SAI_CR5_WNW_MASK (0x1f << 24)
104#define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16)
105#define FSL_SAI_CR5_W0W_MASK (0x1f << 16)
106#define FSL_SAI_CR5_FBT(x) ((x) << 8)
107#define FSL_SAI_CR5_FBT_MASK (0x1f << 8)
108
109/* SAI type */
110#define FSL_SAI_DMA BIT(0)
111#define FSL_SAI_USE_AC97 BIT(1)
112#define FSL_SAI_NET BIT(2)
113#define FSL_SAI_TRA_SYN BIT(3)
114#define FSL_SAI_REC_SYN BIT(4)
115#define FSL_SAI_USE_I2S_SLAVE BIT(5)
116
117#define FSL_FMT_TRANSMITTER 0
118#define FSL_FMT_RECEIVER 1
119
120/* SAI clock sources */
121#define FSL_SAI_CLK_BUS 0
122#define FSL_SAI_CLK_MAST1 1
123#define FSL_SAI_CLK_MAST2 2
124#define FSL_SAI_CLK_MAST3 3
125
126#define FSL_SAI_MCLK_MAX 4
127
128/* SAI data transfer numbers per DMA request */
129#define FSL_SAI_MAXBURST_TX 6
130#define FSL_SAI_MAXBURST_RX 6
131
132struct fsl_sai {
133 struct platform_device *pdev;
134 struct regmap *regmap;
135 struct clk *bus_clk;
136 struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
137
138 bool is_slave_mode;
139 bool is_lsb_first;
140 bool is_dsp_mode;
141 bool sai_on_imx;
142 bool synchronous[2];
143
144 unsigned int mclk_id[2];
145 unsigned int mclk_streams;
146 unsigned int slots;
147 unsigned int slot_width;
148
149 struct snd_dmaengine_dai_dma_data dma_params_rx;
150 struct snd_dmaengine_dai_dma_data dma_params_tx;
151};
152
153#define TX 1
154#define RX 0
155
156#endif /* __FSL_SAI_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
4 */
5
6#ifndef __FSL_SAI_H
7#define __FSL_SAI_H
8
9#include <sound/dmaengine_pcm.h>
10
11#define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
12 SNDRV_PCM_FMTBIT_S20_3LE |\
13 SNDRV_PCM_FMTBIT_S24_LE |\
14 SNDRV_PCM_FMTBIT_S32_LE)
15
16/* SAI Register Map Register */
17#define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */
18#define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */
19#define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */
20#define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */
21#define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */
22#define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */
23#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
24#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
25#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
26#define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */
27#define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */
28#define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */
29#define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */
30#define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */
31#define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */
32#define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */
33#define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */
34#define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */
35#define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */
36#define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */
37#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
38#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
39#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
40#define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
41#define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
42#define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
43#define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
44#define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
45#define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
46#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
47#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
48#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
49#define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */
50#define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */
51#define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */
52#define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */
53#define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */
54#define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */
55#define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */
56#define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */
57#define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */
58#define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */
59#define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */
60#define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */
61#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
62#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
63
64#define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs))
65#define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs))
66#define FSL_SAI_xCR2(tx, ofs) (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs))
67#define FSL_SAI_xCR3(tx, ofs) (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs))
68#define FSL_SAI_xCR4(tx, ofs) (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs))
69#define FSL_SAI_xCR5(tx, ofs) (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs))
70#define FSL_SAI_xDR(tx, ofs) (tx ? FSL_SAI_TDR(ofs) : FSL_SAI_RDR(ofs))
71#define FSL_SAI_xFR(tx, ofs) (tx ? FSL_SAI_TFR(ofs) : FSL_SAI_RFR(ofs))
72#define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
73
74/* SAI Transmit/Receive Control Register */
75#define FSL_SAI_CSR_TERE BIT(31)
76#define FSL_SAI_CSR_FR BIT(25)
77#define FSL_SAI_CSR_SR BIT(24)
78#define FSL_SAI_CSR_xF_SHIFT 16
79#define FSL_SAI_CSR_xF_W_SHIFT 18
80#define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT)
81#define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT)
82#define FSL_SAI_CSR_WSF BIT(20)
83#define FSL_SAI_CSR_SEF BIT(19)
84#define FSL_SAI_CSR_FEF BIT(18)
85#define FSL_SAI_CSR_FWF BIT(17)
86#define FSL_SAI_CSR_FRF BIT(16)
87#define FSL_SAI_CSR_xIE_SHIFT 8
88#define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT)
89#define FSL_SAI_CSR_WSIE BIT(12)
90#define FSL_SAI_CSR_SEIE BIT(11)
91#define FSL_SAI_CSR_FEIE BIT(10)
92#define FSL_SAI_CSR_FWIE BIT(9)
93#define FSL_SAI_CSR_FRIE BIT(8)
94#define FSL_SAI_CSR_FRDE BIT(0)
95
96/* SAI Transmit and Receive Configuration 1 Register */
97#define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1)
98
99/* SAI Transmit and Receive Configuration 2 Register */
100#define FSL_SAI_CR2_SYNC BIT(30)
101#define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
102#define FSL_SAI_CR2_MSEL_BUS 0
103#define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
104#define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
105#define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
106#define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
107#define FSL_SAI_CR2_BCP BIT(25)
108#define FSL_SAI_CR2_BCD_MSTR BIT(24)
109#define FSL_SAI_CR2_DIV_MASK 0xff
110
111/* SAI Transmit and Receive Configuration 3 Register */
112#define FSL_SAI_CR3_TRCE BIT(16)
113#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)
114#define FSL_SAI_CR3_WDFL(x) (x)
115#define FSL_SAI_CR3_WDFL_MASK 0x1f
116
117/* SAI Transmit and Receive Configuration 4 Register */
118#define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
119#define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
120#define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
121#define FSL_SAI_CR4_SYWD_MASK (0x1f << 8)
122#define FSL_SAI_CR4_MF BIT(4)
123#define FSL_SAI_CR4_FSE BIT(3)
124#define FSL_SAI_CR4_FSP BIT(1)
125#define FSL_SAI_CR4_FSD_MSTR BIT(0)
126
127/* SAI Transmit and Receive Configuration 5 Register */
128#define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24)
129#define FSL_SAI_CR5_WNW_MASK (0x1f << 24)
130#define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16)
131#define FSL_SAI_CR5_W0W_MASK (0x1f << 16)
132#define FSL_SAI_CR5_FBT(x) ((x) << 8)
133#define FSL_SAI_CR5_FBT_MASK (0x1f << 8)
134
135/* SAI type */
136#define FSL_SAI_DMA BIT(0)
137#define FSL_SAI_USE_AC97 BIT(1)
138#define FSL_SAI_NET BIT(2)
139#define FSL_SAI_TRA_SYN BIT(3)
140#define FSL_SAI_REC_SYN BIT(4)
141#define FSL_SAI_USE_I2S_SLAVE BIT(5)
142
143#define FSL_FMT_TRANSMITTER 0
144#define FSL_FMT_RECEIVER 1
145
146/* SAI clock sources */
147#define FSL_SAI_CLK_BUS 0
148#define FSL_SAI_CLK_MAST1 1
149#define FSL_SAI_CLK_MAST2 2
150#define FSL_SAI_CLK_MAST3 3
151
152#define FSL_SAI_MCLK_MAX 4
153
154/* SAI data transfer numbers per DMA request */
155#define FSL_SAI_MAXBURST_TX 6
156#define FSL_SAI_MAXBURST_RX 6
157
158struct fsl_sai_soc_data {
159 bool use_imx_pcm;
160 bool use_edma;
161 unsigned int fifo_depth;
162 unsigned int reg_offset;
163};
164
165struct fsl_sai {
166 struct platform_device *pdev;
167 struct regmap *regmap;
168 struct clk *bus_clk;
169 struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
170
171 bool is_slave_mode;
172 bool is_lsb_first;
173 bool is_dsp_mode;
174 bool synchronous[2];
175
176 unsigned int mclk_id[2];
177 unsigned int mclk_streams;
178 unsigned int slots;
179 unsigned int slot_width;
180 unsigned int bclk_ratio;
181
182 const struct fsl_sai_soc_data *soc_data;
183 struct snd_dmaengine_dai_dma_data dma_params_rx;
184 struct snd_dmaengine_dai_dma_data dma_params_tx;
185};
186
187#define TX 1
188#define RX 0
189
190#endif /* __FSL_SAI_H */