1/* SPDX-License-Identifier: GPL-2.0+ */
  2/*
  3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
  4 * synchronization devices.
  5 *
  6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
  7 */
  8#ifndef PTP_IDTCLOCKMATRIX_H
  9#define PTP_IDTCLOCKMATRIX_H
 10
 11#include <linux/ktime.h>
 12
 13#include "idt8a340_reg.h"
 14
 15#define FW_FILENAME	"idtcm.bin"
 16#define MAX_TOD		(4)
 17#define MAX_PLL		(8)
 18
 19#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
 20
 21#define TOD_MASK_ADDR		(0xFFA5)
 22#define DEFAULT_TOD_MASK	(0x04)
 23
 24#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
 25#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
 26
 27#define TOD0_PTP_PLL_ADDR		(0xFFA8)
 28#define TOD1_PTP_PLL_ADDR		(0xFFA9)
 29#define TOD2_PTP_PLL_ADDR		(0xFFAA)
 30#define TOD3_PTP_PLL_ADDR		(0xFFAB)
 31
 32#define TOD0_OUT_ALIGN_MASK_ADDR	(0xFFB0)
 33#define TOD1_OUT_ALIGN_MASK_ADDR	(0xFFB2)
 34#define TOD2_OUT_ALIGN_MASK_ADDR	(0xFFB4)
 35#define TOD3_OUT_ALIGN_MASK_ADDR	(0xFFB6)
 36
 37#define DEFAULT_OUTPUT_MASK_PLL0	(0x003)
 38#define DEFAULT_OUTPUT_MASK_PLL1	(0x00c)
 39#define DEFAULT_OUTPUT_MASK_PLL2	(0x030)
 40#define DEFAULT_OUTPUT_MASK_PLL3	(0x0c0)
 41
 42#define DEFAULT_TOD0_PTP_PLL		(0)
 43#define DEFAULT_TOD1_PTP_PLL		(1)
 44#define DEFAULT_TOD2_PTP_PLL		(2)
 45#define DEFAULT_TOD3_PTP_PLL		(3)
 46
 47#define POST_SM_RESET_DELAY_MS		(3000)
 48#define PHASE_PULL_IN_THRESHOLD_NS	(150000)
 49#define PHASE_PULL_IN_THRESHOLD_NS_V487	(15000)
 50#define TOD_WRITE_OVERHEAD_COUNT_MAX	(2)
 51#define TOD_BYTE_COUNT			(11)
 52#define WR_PHASE_SETUP_MS		(5000)
 53
 54#define OUTPUT_MODULE_FROM_INDEX(index)	(OUTPUT_0 + (index) * 0x10)
 55
 56#define PEROUT_ENABLE_OUTPUT_MASK		(0xdeadbeef)
 57
 58#define IDTCM_MAX_WRITE_COUNT			(512)
 59
 60/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
 61enum pll_mode {
 62	PLL_MODE_MIN = 0,
 63	PLL_MODE_NORMAL = PLL_MODE_MIN,
 64	PLL_MODE_WRITE_PHASE = 1,
 65	PLL_MODE_WRITE_FREQUENCY = 2,
 66	PLL_MODE_GPIO_INC_DEC = 3,
 67	PLL_MODE_SYNTHESIS = 4,
 68	PLL_MODE_PHASE_MEASUREMENT = 5,
 69	PLL_MODE_DISABLED = 6,
 70	PLL_MODE_MAX = PLL_MODE_DISABLED,
 71};
 72
 73enum hw_tod_write_trig_sel {
 74	HW_TOD_WR_TRIG_SEL_MIN = 0,
 75	HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
 76	HW_TOD_WR_TRIG_SEL_RESERVED = 1,
 77	HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
 78	HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
 79	HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
 80	HW_TOD_WR_TRIG_SEL_GPIO = 5,
 81	HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
 82	WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
 83};
 84
 85/* 4.8.7 only */
 86enum scsr_tod_write_trig_sel {
 87	SCSR_TOD_WR_TRIG_SEL_DISABLE = 0,
 88	SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1,
 89	SCSR_TOD_WR_TRIG_SEL_REFCLK = 2,
 90	SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3,
 91	SCSR_TOD_WR_TRIG_SEL_TODPPS = 4,
 92	SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5,
 93	SCSR_TOD_WR_TRIG_SEL_GPIO = 6,
 94	SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO,
 95};
 96
 97/* 4.8.7 only */
 98enum scsr_tod_write_type_sel {
 99	SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0,
100	SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1,
101	SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2,
102	SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
103};
104
105struct idtcm;
106
107struct idtcm_channel {
108	struct ptp_clock_info	caps;
109	struct ptp_clock	*ptp_clock;
110	struct idtcm		*idtcm;
111	u16			dpll_phase;
112	u16			dpll_freq;
113	u16			dpll_n;
114	u16			dpll_ctrl_n;
115	u16			dpll_phase_pull_in;
116	u16			tod_read_primary;
117	u16			tod_write;
118	u16			tod_n;
119	u16			hw_dpll_n;
120	enum pll_mode		pll_mode;
121	u8			pll;
122	u16			output_mask;
123	int			write_phase_ready;
124};
125
126struct idtcm {
127	struct idtcm_channel	channel[MAX_TOD];
128	struct i2c_client	*client;
129	u8			page_offset;
130	u8			tod_mask;
131	char			version[16];
132
133	/* Overhead calculation for adjtime */
134	u8			calculate_overhead_flag;
135	s64			tod_write_overhead_ns;
136	ktime_t			start_time;
137
138	/* Protects I2C read/modify/write registers from concurrent access */
139	struct mutex		reg_lock;
140};
141
142struct idtcm_fwrc {
143	u8 hiaddr;
144	u8 loaddr;
145	u8 value;
146	u8 reserved;
147} __packed;
148
149#endif /* PTP_IDTCLOCKMATRIX_H */