1/*
   2 * wm8994-regmap.c  --  Register map data for WM8994 series devices
   3 *
   4 * Copyright 2011 Wolfson Microelectronics PLC.
   5 *
   6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7 *
   8 *  This program is free software; you can redistribute  it and/or modify it
   9 *  under  the terms of  the GNU General  Public License as published by the
  10 *  Free Software Foundation;  either version 2 of the  License, or (at your
  11 *  option) any later version.
  12 *
  13 */
  14
  15#include <linux/mfd/wm8994/core.h>
  16#include <linux/mfd/wm8994/registers.h>
  17#include <linux/regmap.h>
  18#include <linux/device.h>
  19
  20#include "wm8994.h"
  21
  22static const struct reg_default wm1811_defaults[] = {
  23	{ 0x0001, 0x0000 },    /* R1    - Power Management (1) */
  24	{ 0x0002, 0x6000 },    /* R2    - Power Management (2) */
  25	{ 0x0003, 0x0000 },    /* R3    - Power Management (3) */
  26	{ 0x0004, 0x0000 },    /* R4    - Power Management (4) */
  27	{ 0x0005, 0x0000 },    /* R5    - Power Management (5) */
  28	{ 0x0006, 0x0000 },    /* R6    - Power Management (6) */
  29	{ 0x0015, 0x0000 },    /* R21   - Input Mixer (1) */
  30	{ 0x0018, 0x008B },    /* R24   - Left Line Input 1&2 Volume */
  31	{ 0x0019, 0x008B },    /* R25   - Left Line Input 3&4 Volume */
  32	{ 0x001A, 0x008B },    /* R26   - Right Line Input 1&2 Volume */
  33	{ 0x001B, 0x008B },    /* R27   - Right Line Input 3&4 Volume */
  34	{ 0x001C, 0x006D },    /* R28   - Left Output Volume */
  35	{ 0x001D, 0x006D },    /* R29   - Right Output Volume */
  36	{ 0x001E, 0x0066 },    /* R30   - Line Outputs Volume */
  37	{ 0x001F, 0x0020 },    /* R31   - HPOUT2 Volume */
  38	{ 0x0020, 0x0079 },    /* R32   - Left OPGA Volume */
  39	{ 0x0021, 0x0079 },    /* R33   - Right OPGA Volume */
  40	{ 0x0022, 0x0003 },    /* R34   - SPKMIXL Attenuation */
  41	{ 0x0023, 0x0003 },    /* R35   - SPKMIXR Attenuation */
  42	{ 0x0024, 0x0011 },    /* R36   - SPKOUT Mixers */
  43	{ 0x0025, 0x0140 },    /* R37   - ClassD */
  44	{ 0x0026, 0x0079 },    /* R38   - Speaker Volume Left */
  45	{ 0x0027, 0x0079 },    /* R39   - Speaker Volume Right */
  46	{ 0x0028, 0x0000 },    /* R40   - Input Mixer (2) */
  47	{ 0x0029, 0x0000 },    /* R41   - Input Mixer (3) */
  48	{ 0x002A, 0x0000 },    /* R42   - Input Mixer (4) */
  49	{ 0x002B, 0x0000 },    /* R43   - Input Mixer (5) */
  50	{ 0x002C, 0x0000 },    /* R44   - Input Mixer (6) */
  51	{ 0x002D, 0x0000 },    /* R45   - Output Mixer (1) */
  52	{ 0x002E, 0x0000 },    /* R46   - Output Mixer (2) */
  53	{ 0x002F, 0x0000 },    /* R47   - Output Mixer (3) */
  54	{ 0x0030, 0x0000 },    /* R48   - Output Mixer (4) */
  55	{ 0x0031, 0x0000 },    /* R49   - Output Mixer (5) */
  56	{ 0x0032, 0x0000 },    /* R50   - Output Mixer (6) */
  57	{ 0x0033, 0x0000 },    /* R51   - HPOUT2 Mixer */
  58	{ 0x0034, 0x0000 },    /* R52   - Line Mixer (1) */
  59	{ 0x0035, 0x0000 },    /* R53   - Line Mixer (2) */
  60	{ 0x0036, 0x0000 },    /* R54   - Speaker Mixer */
  61	{ 0x0037, 0x0000 },    /* R55   - Additional Control */
  62	{ 0x0038, 0x0000 },    /* R56   - AntiPOP (1) */
  63	{ 0x0039, 0x0000 },    /* R57   - AntiPOP (2) */
  64	{ 0x003B, 0x000D },    /* R59   - LDO 1 */
  65	{ 0x003C, 0x0003 },    /* R60   - LDO 2 */
  66	{ 0x003D, 0x0039 },    /* R61   - MICBIAS1 */
  67	{ 0x003E, 0x0039 },    /* R62   - MICBIAS2 */
  68	{ 0x004C, 0x1F25 },    /* R76   - Charge Pump (1) */
  69	{ 0x004D, 0xAB19 },    /* R77   - Charge Pump (2) */
  70	{ 0x0051, 0x0004 },    /* R81   - Class W (1) */
  71	{ 0x0055, 0x054A },    /* R85   - DC Servo (2) */
  72	{ 0x0059, 0x0000 },    /* R89   - DC Servo (4) */
  73	{ 0x0060, 0x0000 },    /* R96   - Analogue HP (1) */
  74	{ 0x00C5, 0x0000 },    /* R197  - Class D Test (5) */
  75	{ 0x00D0, 0x7600 },    /* R208  - Mic Detect 1 */
  76	{ 0x00D1, 0x007F },    /* R209  - Mic Detect 2 */
  77	{ 0x0101, 0x8004 },    /* R257  - Control Interface */
  78	{ 0x0200, 0x0000 },    /* R512  - AIF1 Clocking (1) */
  79	{ 0x0201, 0x0000 },    /* R513  - AIF1 Clocking (2) */
  80	{ 0x0204, 0x0000 },    /* R516  - AIF2 Clocking (1) */
  81	{ 0x0205, 0x0000 },    /* R517  - AIF2 Clocking (2) */
  82	{ 0x0208, 0x0000 },    /* R520  - Clocking (1) */
  83	{ 0x0209, 0x0000 },    /* R521  - Clocking (2) */
  84	{ 0x0210, 0x0083 },    /* R528  - AIF1 Rate */
  85	{ 0x0211, 0x0083 },    /* R529  - AIF2 Rate */
  86	{ 0x0220, 0x0000 },    /* R544  - FLL1 Control (1) */
  87	{ 0x0221, 0x0000 },    /* R545  - FLL1 Control (2) */
  88	{ 0x0222, 0x0000 },    /* R546  - FLL1 Control (3) */
  89	{ 0x0223, 0x0000 },    /* R547  - FLL1 Control (4) */
  90	{ 0x0224, 0x0C80 },    /* R548  - FLL1 Control (5) */
  91	{ 0x0226, 0x0000 },    /* R550  - FLL1 EFS 1 */
  92	{ 0x0227, 0x0006 },    /* R551  - FLL1 EFS 2 */
  93	{ 0x0240, 0x0000 },    /* R576  - FLL2Control (1) */
  94	{ 0x0241, 0x0000 },    /* R577  - FLL2Control (2) */
  95	{ 0x0242, 0x0000 },    /* R578  - FLL2Control (3) */
  96	{ 0x0243, 0x0000 },    /* R579  - FLL2 Control (4) */
  97	{ 0x0244, 0x0C80 },    /* R580  - FLL2Control (5) */
  98	{ 0x0246, 0x0000 },    /* R582  - FLL2 EFS 1 */
  99	{ 0x0247, 0x0006 },    /* R583  - FLL2 EFS 2 */
 100	{ 0x0300, 0x4050 },    /* R768  - AIF1 Control (1) */
 101	{ 0x0301, 0x4000 },    /* R769  - AIF1 Control (2) */
 102	{ 0x0302, 0x0000 },    /* R770  - AIF1 Master/Slave */
 103	{ 0x0303, 0x0040 },    /* R771  - AIF1 BCLK */
 104	{ 0x0304, 0x0040 },    /* R772  - AIF1ADC LRCLK */
 105	{ 0x0305, 0x0040 },    /* R773  - AIF1DAC LRCLK */
 106	{ 0x0306, 0x0004 },    /* R774  - AIF1DAC Data */
 107	{ 0x0307, 0x0100 },    /* R775  - AIF1ADC Data */
 108	{ 0x0310, 0x4050 },    /* R784  - AIF2 Control (1) */
 109	{ 0x0311, 0x4000 },    /* R785  - AIF2 Control (2) */
 110	{ 0x0312, 0x0000 },    /* R786  - AIF2 Master/Slave */
 111	{ 0x0313, 0x0040 },    /* R787  - AIF2 BCLK */
 112	{ 0x0314, 0x0040 },    /* R788  - AIF2ADC LRCLK */
 113	{ 0x0315, 0x0040 },    /* R789  - AIF2DAC LRCLK */
 114	{ 0x0316, 0x0000 },    /* R790  - AIF2DAC Data */
 115	{ 0x0317, 0x0000 },    /* R791  - AIF2ADC Data */
 116	{ 0x0318, 0x0003 },    /* R792  - AIF2TX Control */
 117	{ 0x0320, 0x0040 },    /* R800  - AIF3 Control (1) */
 118	{ 0x0321, 0x0000 },    /* R801  - AIF3 Control (2) */
 119	{ 0x0322, 0x0000 },    /* R802  - AIF3DAC Data */
 120	{ 0x0323, 0x0000 },    /* R803  - AIF3ADC Data */
 121	{ 0x0400, 0x00C0 },    /* R1024 - AIF1 ADC1 Left Volume */
 122	{ 0x0401, 0x00C0 },    /* R1025 - AIF1 ADC1 Right Volume */
 123	{ 0x0402, 0x00C0 },    /* R1026 - AIF1 DAC1 Left Volume */
 124	{ 0x0403, 0x00C0 },    /* R1027 - AIF1 DAC1 Right Volume */
 125	{ 0x0410, 0x0000 },    /* R1040 - AIF1 ADC1 Filters */
 126	{ 0x0411, 0x0000 },    /* R1041 - AIF1 ADC2 Filters */
 127	{ 0x0420, 0x0200 },    /* R1056 - AIF1 DAC1 Filters (1) */
 128	{ 0x0421, 0x0010 },    /* R1057 - AIF1 DAC1 Filters (2) */
 129	{ 0x0422, 0x0200 },    /* R1058 - AIF1 DAC2 Filters (1) */
 130	{ 0x0423, 0x0010 },    /* R1059 - AIF1 DAC2 Filters (2) */
 131	{ 0x0430, 0x0068 },    /* R1072 - AIF1 DAC1 Noise Gate */
 132	{ 0x0431, 0x0068 },    /* R1073 - AIF1 DAC2 Noise Gate */
 133	{ 0x0440, 0x0098 },    /* R1088 - AIF1 DRC1 (1) */
 134	{ 0x0441, 0x0845 },    /* R1089 - AIF1 DRC1 (2) */
 135	{ 0x0442, 0x0000 },    /* R1090 - AIF1 DRC1 (3) */
 136	{ 0x0443, 0x0000 },    /* R1091 - AIF1 DRC1 (4) */
 137	{ 0x0444, 0x0000 },    /* R1092 - AIF1 DRC1 (5) */
 138	{ 0x0450, 0x0098 },    /* R1104 - AIF1 DRC2 (1) */
 139	{ 0x0451, 0x0845 },    /* R1105 - AIF1 DRC2 (2) */
 140	{ 0x0452, 0x0000 },    /* R1106 - AIF1 DRC2 (3) */
 141	{ 0x0453, 0x0000 },    /* R1107 - AIF1 DRC2 (4) */
 142	{ 0x0454, 0x0000 },    /* R1108 - AIF1 DRC2 (5) */
 143	{ 0x0480, 0x6318 },    /* R1152 - AIF1 DAC1 EQ Gains (1) */
 144	{ 0x0481, 0x6300 },    /* R1153 - AIF1 DAC1 EQ Gains (2) */
 145	{ 0x0482, 0x0FCA },    /* R1154 - AIF1 DAC1 EQ Band 1 A */
 146	{ 0x0483, 0x0400 },    /* R1155 - AIF1 DAC1 EQ Band 1 B */
 147	{ 0x0484, 0x00D8 },    /* R1156 - AIF1 DAC1 EQ Band 1 PG */
 148	{ 0x0485, 0x1EB5 },    /* R1157 - AIF1 DAC1 EQ Band 2 A */
 149	{ 0x0486, 0xF145 },    /* R1158 - AIF1 DAC1 EQ Band 2 B */
 150	{ 0x0487, 0x0B75 },    /* R1159 - AIF1 DAC1 EQ Band 2 C */
 151	{ 0x0488, 0x01C5 },    /* R1160 - AIF1 DAC1 EQ Band 2 PG */
 152	{ 0x0489, 0x1C58 },    /* R1161 - AIF1 DAC1 EQ Band 3 A */
 153	{ 0x048A, 0xF373 },    /* R1162 - AIF1 DAC1 EQ Band 3 B */
 154	{ 0x048B, 0x0A54 },    /* R1163 - AIF1 DAC1 EQ Band 3 C */
 155	{ 0x048C, 0x0558 },    /* R1164 - AIF1 DAC1 EQ Band 3 PG */
 156	{ 0x048D, 0x168E },    /* R1165 - AIF1 DAC1 EQ Band 4 A */
 157	{ 0x048E, 0xF829 },    /* R1166 - AIF1 DAC1 EQ Band 4 B */
 158	{ 0x048F, 0x07AD },    /* R1167 - AIF1 DAC1 EQ Band 4 C */
 159	{ 0x0490, 0x1103 },    /* R1168 - AIF1 DAC1 EQ Band 4 PG */
 160	{ 0x0491, 0x0564 },    /* R1169 - AIF1 DAC1 EQ Band 5 A */
 161	{ 0x0492, 0x0559 },    /* R1170 - AIF1 DAC1 EQ Band 5 B */
 162	{ 0x0493, 0x4000 },    /* R1171 - AIF1 DAC1 EQ Band 5 PG */
 163	{ 0x0494, 0x0000 },    /* R1172 - AIF1 DAC1 EQ Band 1 C */
 164	{ 0x04A0, 0x6318 },    /* R1184 - AIF1 DAC2 EQ Gains (1) */
 165	{ 0x04A1, 0x6300 },    /* R1185 - AIF1 DAC2 EQ Gains (2) */
 166	{ 0x04A2, 0x0FCA },    /* R1186 - AIF1 DAC2 EQ Band 1 A */
 167	{ 0x04A3, 0x0400 },    /* R1187 - AIF1 DAC2 EQ Band 1 B */
 168	{ 0x04A4, 0x00D8 },    /* R1188 - AIF1 DAC2 EQ Band 1 PG */
 169	{ 0x04A5, 0x1EB5 },    /* R1189 - AIF1 DAC2 EQ Band 2 A */
 170	{ 0x04A6, 0xF145 },    /* R1190 - AIF1 DAC2 EQ Band 2 B */
 171	{ 0x04A7, 0x0B75 },    /* R1191 - AIF1 DAC2 EQ Band 2 C */
 172	{ 0x04A8, 0x01C5 },    /* R1192 - AIF1 DAC2 EQ Band 2 PG */
 173	{ 0x04A9, 0x1C58 },    /* R1193 - AIF1 DAC2 EQ Band 3 A */
 174	{ 0x04AA, 0xF373 },    /* R1194 - AIF1 DAC2 EQ Band 3 B */
 175	{ 0x04AB, 0x0A54 },    /* R1195 - AIF1 DAC2 EQ Band 3 C */
 176	{ 0x04AC, 0x0558 },    /* R1196 - AIF1 DAC2 EQ Band 3 PG */
 177	{ 0x04AD, 0x168E },    /* R1197 - AIF1 DAC2 EQ Band 4 A */
 178	{ 0x04AE, 0xF829 },    /* R1198 - AIF1 DAC2 EQ Band 4 B */
 179	{ 0x04AF, 0x07AD },    /* R1199 - AIF1 DAC2 EQ Band 4 C */
 180	{ 0x04B0, 0x1103 },    /* R1200 - AIF1 DAC2 EQ Band 4 PG */
 181	{ 0x04B1, 0x0564 },    /* R1201 - AIF1 DAC2 EQ Band 5 A */
 182	{ 0x04B2, 0x0559 },    /* R1202 - AIF1 DAC2 EQ Band 5 B */
 183	{ 0x04B3, 0x4000 },    /* R1203 - AIF1 DAC2 EQ Band 5 PG */
 184	{ 0x04B4, 0x0000 },    /* R1204 - AIF1 DAC2 EQ Band 1 C */
 185	{ 0x0500, 0x00C0 },    /* R1280 - AIF2 ADC Left Volume */
 186	{ 0x0501, 0x00C0 },    /* R1281 - AIF2 ADC Right Volume */
 187	{ 0x0502, 0x00C0 },    /* R1282 - AIF2 DAC Left Volume */
 188	{ 0x0503, 0x00C0 },    /* R1283 - AIF2 DAC Right Volume */
 189	{ 0x0510, 0x0000 },    /* R1296 - AIF2 ADC Filters */
 190	{ 0x0520, 0x0200 },    /* R1312 - AIF2 DAC Filters (1) */
 191	{ 0x0521, 0x0010 },    /* R1313 - AIF2 DAC Filters (2) */
 192	{ 0x0530, 0x0068 },    /* R1328 - AIF2 DAC Noise Gate */
 193	{ 0x0540, 0x0098 },    /* R1344 - AIF2 DRC (1) */
 194	{ 0x0541, 0x0845 },    /* R1345 - AIF2 DRC (2) */
 195	{ 0x0542, 0x0000 },    /* R1346 - AIF2 DRC (3) */
 196	{ 0x0543, 0x0000 },    /* R1347 - AIF2 DRC (4) */
 197	{ 0x0544, 0x0000 },    /* R1348 - AIF2 DRC (5) */
 198	{ 0x0580, 0x6318 },    /* R1408 - AIF2 EQ Gains (1) */
 199	{ 0x0581, 0x6300 },    /* R1409 - AIF2 EQ Gains (2) */
 200	{ 0x0582, 0x0FCA },    /* R1410 - AIF2 EQ Band 1 A */
 201	{ 0x0583, 0x0400 },    /* R1411 - AIF2 EQ Band 1 B */
 202	{ 0x0584, 0x00D8 },    /* R1412 - AIF2 EQ Band 1 PG */
 203	{ 0x0585, 0x1EB5 },    /* R1413 - AIF2 EQ Band 2 A */
 204	{ 0x0586, 0xF145 },    /* R1414 - AIF2 EQ Band 2 B */
 205	{ 0x0587, 0x0B75 },    /* R1415 - AIF2 EQ Band 2 C */
 206	{ 0x0588, 0x01C5 },    /* R1416 - AIF2 EQ Band 2 PG */
 207	{ 0x0589, 0x1C58 },    /* R1417 - AIF2 EQ Band 3 A */
 208	{ 0x058A, 0xF373 },    /* R1418 - AIF2 EQ Band 3 B */
 209	{ 0x058B, 0x0A54 },    /* R1419 - AIF2 EQ Band 3 C */
 210	{ 0x058C, 0x0558 },    /* R1420 - AIF2 EQ Band 3 PG */
 211	{ 0x058D, 0x168E },    /* R1421 - AIF2 EQ Band 4 A */
 212	{ 0x058E, 0xF829 },    /* R1422 - AIF2 EQ Band 4 B */
 213	{ 0x058F, 0x07AD },    /* R1423 - AIF2 EQ Band 4 C */
 214	{ 0x0590, 0x1103 },    /* R1424 - AIF2 EQ Band 4 PG */
 215	{ 0x0591, 0x0564 },    /* R1425 - AIF2 EQ Band 5 A */
 216	{ 0x0592, 0x0559 },    /* R1426 - AIF2 EQ Band 5 B */
 217	{ 0x0593, 0x4000 },    /* R1427 - AIF2 EQ Band 5 PG */
 218	{ 0x0594, 0x0000 },    /* R1428 - AIF2 EQ Band 1 C */
 219	{ 0x0600, 0x0000 },    /* R1536 - DAC1 Mixer Volumes */
 220	{ 0x0601, 0x0000 },    /* R1537 - DAC1 Left Mixer Routing */
 221	{ 0x0602, 0x0000 },    /* R1538 - DAC1 Right Mixer Routing */
 222	{ 0x0603, 0x0000 },    /* R1539 - AIF2ADC Mixer Volumes */
 223	{ 0x0604, 0x0000 },    /* R1540 - AIF2ADC Left Mixer Routing */
 224	{ 0x0605, 0x0000 },    /* R1541 - AIF2ADC Right Mixer Routing */
 225	{ 0x0606, 0x0000 },    /* R1542 - AIF1 ADC1 Left Mixer Routing */
 226	{ 0x0607, 0x0000 },    /* R1543 - AIF1 ADC1 Right Mixer Routing */
 227	{ 0x0608, 0x0000 },    /* R1544 - AIF1 ADC2 Left Mixer Routing */
 228	{ 0x0609, 0x0000 },    /* R1545 - AIF1 ADC2 Right Mixer Routing */
 229	{ 0x0610, 0x02C0 },    /* R1552 - DAC1 Left Volume */
 230	{ 0x0611, 0x02C0 },    /* R1553 - DAC1 Right Volume */
 231	{ 0x0612, 0x02C0 },    /* R1554 - AIF2TX Left Volume */
 232	{ 0x0613, 0x02C0 },    /* R1555 - AIF2TX Right Volume */
 233	{ 0x0614, 0x0000 },    /* R1556 - DAC Softmute */
 234	{ 0x0620, 0x0002 },    /* R1568 - Oversampling */
 235	{ 0x0621, 0x0000 },    /* R1569 - Sidetone */
 236	{ 0x0700, 0x8100 },    /* R1792 - GPIO 1 */
 237	{ 0x0701, 0xA101 },    /* R1793 - Pull Control (MCLK2) */
 238	{ 0x0702, 0xA101 },    /* R1794 - Pull Control (BCLK2) */
 239	{ 0x0703, 0xA101 },    /* R1795 - Pull Control (DACLRCLK2) */
 240	{ 0x0704, 0xA101 },    /* R1796 - Pull Control (DACDAT2) */
 241	{ 0x0707, 0xA101 },    /* R1799 - GPIO 8 */
 242	{ 0x0708, 0xA101 },    /* R1800 - GPIO 9 */
 243	{ 0x0709, 0xA101 },    /* R1801 - GPIO 10 */
 244	{ 0x070A, 0xA101 },    /* R1802 - GPIO 11 */
 245	{ 0x0720, 0x0000 },    /* R1824 - Pull Control (1) */
 246	{ 0x0721, 0x0156 },    /* R1825 - Pull Control (2) */
 247	{ 0x0732, 0x0000 },    /* R1842 - Interrupt Raw Status 2 */
 248	{ 0x0738, 0x07FF },    /* R1848 - Interrupt Status 1 Mask */
 249	{ 0x0739, 0xDFEF },    /* R1849 - Interrupt Status 2 Mask */
 250	{ 0x0740, 0x0000 },    /* R1856 - Interrupt Control */
 251	{ 0x0748, 0x003F },    /* R1864 - IRQ Debounce */
 252};
 253
 254static const struct reg_default wm8994_defaults[] = {
 255	{ 0x0001, 0x0000 },    /* R1     - Power Management (1) */ 
 256	{ 0x0002, 0x6000 },    /* R2     - Power Management (2) */ 
 257	{ 0x0003, 0x0000 },    /* R3     - Power Management (3) */ 
 258	{ 0x0004, 0x0000 },    /* R4     - Power Management (4) */ 
 259	{ 0x0005, 0x0000 },    /* R5     - Power Management (5) */ 
 260	{ 0x0006, 0x0000 },    /* R6     - Power Management (6) */ 
 261	{ 0x0015, 0x0000 },    /* R21    - Input Mixer (1) */ 
 262	{ 0x0018, 0x008B },    /* R24    - Left Line Input 1&2 Volume */ 
 263	{ 0x0019, 0x008B },    /* R25    - Left Line Input 3&4 Volume */ 
 264	{ 0x001A, 0x008B },    /* R26    - Right Line Input 1&2 Volume */ 
 265	{ 0x001B, 0x008B },    /* R27    - Right Line Input 3&4 Volume */ 
 266	{ 0x001C, 0x006D },    /* R28    - Left Output Volume */ 
 267	{ 0x001D, 0x006D },    /* R29    - Right Output Volume */ 
 268	{ 0x001E, 0x0066 },    /* R30    - Line Outputs Volume */ 
 269	{ 0x001F, 0x0020 },    /* R31    - HPOUT2 Volume */ 
 270	{ 0x0020, 0x0079 },    /* R32    - Left OPGA Volume */ 
 271	{ 0x0021, 0x0079 },    /* R33    - Right OPGA Volume */ 
 272	{ 0x0022, 0x0003 },    /* R34    - SPKMIXL Attenuation */ 
 273	{ 0x0023, 0x0003 },    /* R35    - SPKMIXR Attenuation */ 
 274	{ 0x0024, 0x0011 },    /* R36    - SPKOUT Mixers */ 
 275	{ 0x0025, 0x0140 },    /* R37    - ClassD */ 
 276	{ 0x0026, 0x0079 },    /* R38    - Speaker Volume Left */ 
 277	{ 0x0027, 0x0079 },    /* R39    - Speaker Volume Right */ 
 278	{ 0x0028, 0x0000 },    /* R40    - Input Mixer (2) */ 
 279	{ 0x0029, 0x0000 },    /* R41    - Input Mixer (3) */ 
 280	{ 0x002A, 0x0000 },    /* R42    - Input Mixer (4) */ 
 281	{ 0x002B, 0x0000 },    /* R43    - Input Mixer (5) */ 
 282	{ 0x002C, 0x0000 },    /* R44    - Input Mixer (6) */ 
 283	{ 0x002D, 0x0000 },    /* R45    - Output Mixer (1) */ 
 284	{ 0x002E, 0x0000 },    /* R46    - Output Mixer (2) */ 
 285	{ 0x002F, 0x0000 },    /* R47    - Output Mixer (3) */ 
 286	{ 0x0030, 0x0000 },    /* R48    - Output Mixer (4) */ 
 287	{ 0x0031, 0x0000 },    /* R49    - Output Mixer (5) */ 
 288	{ 0x0032, 0x0000 },    /* R50    - Output Mixer (6) */ 
 289	{ 0x0033, 0x0000 },    /* R51    - HPOUT2 Mixer */ 
 290	{ 0x0034, 0x0000 },    /* R52    - Line Mixer (1) */ 
 291	{ 0x0035, 0x0000 },    /* R53    - Line Mixer (2) */ 
 292	{ 0x0036, 0x0000 },    /* R54    - Speaker Mixer */ 
 293	{ 0x0037, 0x0000 },    /* R55    - Additional Control */ 
 294	{ 0x0038, 0x0000 },    /* R56    - AntiPOP (1) */ 
 295	{ 0x0039, 0x0000 },    /* R57    - AntiPOP (2) */ 
 296	{ 0x003A, 0x0000 },    /* R58    - MICBIAS */ 
 297	{ 0x003B, 0x000D },    /* R59    - LDO 1 */ 
 298	{ 0x003C, 0x0003 },    /* R60    - LDO 2 */ 
 299	{ 0x004C, 0x1F25 },    /* R76    - Charge Pump (1) */ 
 300	{ 0x0051, 0x0004 },    /* R81    - Class W (1) */ 
 301	{ 0x0055, 0x054A },    /* R85    - DC Servo (2) */ 
 302	{ 0x0057, 0x0000 },    /* R87    - DC Servo (4) */ 
 303	{ 0x0060, 0x0000 },    /* R96    - Analogue HP (1) */ 
 304	{ 0x0101, 0x8004 },    /* R257   - Control Interface */ 
 305	{ 0x0110, 0x0000 },    /* R272   - Write Sequencer Ctrl (1) */ 
 306	{ 0x0111, 0x0000 },    /* R273   - Write Sequencer Ctrl (2) */ 
 307	{ 0x0200, 0x0000 },    /* R512   - AIF1 Clocking (1) */ 
 308	{ 0x0201, 0x0000 },    /* R513   - AIF1 Clocking (2) */ 
 309	{ 0x0204, 0x0000 },    /* R516   - AIF2 Clocking (1) */ 
 310	{ 0x0205, 0x0000 },    /* R517   - AIF2 Clocking (2) */ 
 311	{ 0x0208, 0x0000 },    /* R520   - Clocking (1) */ 
 312	{ 0x0209, 0x0000 },    /* R521   - Clocking (2) */ 
 313	{ 0x0210, 0x0083 },    /* R528   - AIF1 Rate */ 
 314	{ 0x0211, 0x0083 },    /* R529   - AIF2 Rate */ 
 315	{ 0x0220, 0x0000 },    /* R544   - FLL1 Control (1) */ 
 316	{ 0x0221, 0x0000 },    /* R545   - FLL1 Control (2) */ 
 317	{ 0x0222, 0x0000 },    /* R546   - FLL1 Control (3) */ 
 318	{ 0x0223, 0x0000 },    /* R547   - FLL1 Control (4) */ 
 319	{ 0x0224, 0x0C80 },    /* R548   - FLL1 Control (5) */ 
 320	{ 0x0240, 0x0000 },    /* R576   - FLL2 Control (1) */ 
 321	{ 0x0241, 0x0000 },    /* R577   - FLL2 Control (2) */ 
 322	{ 0x0242, 0x0000 },    /* R578   - FLL2 Control (3) */ 
 323	{ 0x0243, 0x0000 },    /* R579   - FLL2 Control (4) */ 
 324	{ 0x0244, 0x0C80 },    /* R580   - FLL2 Control (5) */ 
 325	{ 0x0300, 0x4050 },    /* R768   - AIF1 Control (1) */ 
 326	{ 0x0301, 0x4000 },    /* R769   - AIF1 Control (2) */ 
 327	{ 0x0302, 0x0000 },    /* R770   - AIF1 Master/Slave */ 
 328	{ 0x0303, 0x0040 },    /* R771   - AIF1 BCLK */ 
 329	{ 0x0304, 0x0040 },    /* R772   - AIF1ADC LRCLK */ 
 330	{ 0x0305, 0x0040 },    /* R773   - AIF1DAC LRCLK */ 
 331	{ 0x0306, 0x0004 },    /* R774   - AIF1DAC Data */ 
 332	{ 0x0307, 0x0100 },    /* R775   - AIF1ADC Data */ 
 333	{ 0x0310, 0x4050 },    /* R784   - AIF2 Control (1) */ 
 334	{ 0x0311, 0x4000 },    /* R785   - AIF2 Control (2) */ 
 335	{ 0x0312, 0x0000 },    /* R786   - AIF2 Master/Slave */ 
 336	{ 0x0313, 0x0040 },    /* R787   - AIF2 BCLK */ 
 337	{ 0x0314, 0x0040 },    /* R788   - AIF2ADC LRCLK */ 
 338	{ 0x0315, 0x0040 },    /* R789   - AIF2DAC LRCLK */ 
 339	{ 0x0316, 0x0000 },    /* R790   - AIF2DAC Data */ 
 340	{ 0x0317, 0x0000 },    /* R791   - AIF2ADC Data */ 
 341	{ 0x0400, 0x00C0 },    /* R1024  - AIF1 ADC1 Left Volume */ 
 342	{ 0x0401, 0x00C0 },    /* R1025  - AIF1 ADC1 Right Volume */ 
 343	{ 0x0402, 0x00C0 },    /* R1026  - AIF1 DAC1 Left Volume */ 
 344	{ 0x0403, 0x00C0 },    /* R1027  - AIF1 DAC1 Right Volume */ 
 345	{ 0x0404, 0x00C0 },    /* R1028  - AIF1 ADC2 Left Volume */ 
 346	{ 0x0405, 0x00C0 },    /* R1029  - AIF1 ADC2 Right Volume */ 
 347	{ 0x0406, 0x00C0 },    /* R1030  - AIF1 DAC2 Left Volume */ 
 348	{ 0x0407, 0x00C0 },    /* R1031  - AIF1 DAC2 Right Volume */ 
 349	{ 0x0410, 0x0000 },    /* R1040  - AIF1 ADC1 Filters */ 
 350	{ 0x0411, 0x0000 },    /* R1041  - AIF1 ADC2 Filters */ 
 351	{ 0x0420, 0x0200 },    /* R1056  - AIF1 DAC1 Filters (1) */ 
 352	{ 0x0421, 0x0010 },    /* R1057  - AIF1 DAC1 Filters (2) */ 
 353	{ 0x0422, 0x0200 },    /* R1058  - AIF1 DAC2 Filters (1) */ 
 354	{ 0x0423, 0x0010 },    /* R1059  - AIF1 DAC2 Filters (2) */ 
 355	{ 0x0440, 0x0098 },    /* R1088  - AIF1 DRC1 (1) */ 
 356	{ 0x0441, 0x0845 },    /* R1089  - AIF1 DRC1 (2) */ 
 357	{ 0x0442, 0x0000 },    /* R1090  - AIF1 DRC1 (3) */ 
 358	{ 0x0443, 0x0000 },    /* R1091  - AIF1 DRC1 (4) */ 
 359	{ 0x0444, 0x0000 },    /* R1092  - AIF1 DRC1 (5) */ 
 360	{ 0x0450, 0x0098 },    /* R1104  - AIF1 DRC2 (1) */ 
 361	{ 0x0451, 0x0845 },    /* R1105  - AIF1 DRC2 (2) */ 
 362	{ 0x0452, 0x0000 },    /* R1106  - AIF1 DRC2 (3) */ 
 363	{ 0x0453, 0x0000 },    /* R1107  - AIF1 DRC2 (4) */ 
 364	{ 0x0454, 0x0000 },    /* R1108  - AIF1 DRC2 (5) */ 
 365	{ 0x0480, 0x6318 },    /* R1152  - AIF1 DAC1 EQ Gains (1) */ 
 366	{ 0x0481, 0x6300 },    /* R1153  - AIF1 DAC1 EQ Gains (2) */ 
 367	{ 0x0482, 0x0FCA },    /* R1154  - AIF1 DAC1 EQ Band 1 A */ 
 368	{ 0x0483, 0x0400 },    /* R1155  - AIF1 DAC1 EQ Band 1 B */ 
 369	{ 0x0484, 0x00D8 },    /* R1156  - AIF1 DAC1 EQ Band 1 PG */ 
 370	{ 0x0485, 0x1EB5 },    /* R1157  - AIF1 DAC1 EQ Band 2 A */ 
 371	{ 0x0486, 0xF145 },    /* R1158  - AIF1 DAC1 EQ Band 2 B */ 
 372	{ 0x0487, 0x0B75 },    /* R1159  - AIF1 DAC1 EQ Band 2 C */ 
 373	{ 0x0488, 0x01C5 },    /* R1160  - AIF1 DAC1 EQ Band 2 PG */ 
 374	{ 0x0489, 0x1C58 },    /* R1161  - AIF1 DAC1 EQ Band 3 A */ 
 375	{ 0x048A, 0xF373 },    /* R1162  - AIF1 DAC1 EQ Band 3 B */ 
 376	{ 0x048B, 0x0A54 },    /* R1163  - AIF1 DAC1 EQ Band 3 C */ 
 377	{ 0x048C, 0x0558 },    /* R1164  - AIF1 DAC1 EQ Band 3 PG */ 
 378	{ 0x048D, 0x168E },    /* R1165  - AIF1 DAC1 EQ Band 4 A */ 
 379	{ 0x048E, 0xF829 },    /* R1166  - AIF1 DAC1 EQ Band 4 B */ 
 380	{ 0x048F, 0x07AD },    /* R1167  - AIF1 DAC1 EQ Band 4 C */ 
 381	{ 0x0490, 0x1103 },    /* R1168  - AIF1 DAC1 EQ Band 4 PG */ 
 382	{ 0x0491, 0x0564 },    /* R1169  - AIF1 DAC1 EQ Band 5 A */ 
 383	{ 0x0492, 0x0559 },    /* R1170  - AIF1 DAC1 EQ Band 5 B */ 
 384	{ 0x0493, 0x4000 },    /* R1171  - AIF1 DAC1 EQ Band 5 PG */ 
 385	{ 0x04A0, 0x6318 },    /* R1184  - AIF1 DAC2 EQ Gains (1) */ 
 386	{ 0x04A1, 0x6300 },    /* R1185  - AIF1 DAC2 EQ Gains (2) */ 
 387	{ 0x04A2, 0x0FCA },    /* R1186  - AIF1 DAC2 EQ Band 1 A */ 
 388	{ 0x04A3, 0x0400 },    /* R1187  - AIF1 DAC2 EQ Band 1 B */ 
 389	{ 0x04A4, 0x00D8 },    /* R1188  - AIF1 DAC2 EQ Band 1 PG */ 
 390	{ 0x04A5, 0x1EB5 },    /* R1189  - AIF1 DAC2 EQ Band 2 A */ 
 391	{ 0x04A6, 0xF145 },    /* R1190  - AIF1 DAC2 EQ Band 2 B */ 
 392	{ 0x04A7, 0x0B75 },    /* R1191  - AIF1 DAC2 EQ Band 2 C */ 
 393	{ 0x04A8, 0x01C5 },    /* R1192  - AIF1 DAC2 EQ Band 2 PG */ 
 394	{ 0x04A9, 0x1C58 },    /* R1193  - AIF1 DAC2 EQ Band 3 A */ 
 395	{ 0x04AA, 0xF373 },    /* R1194  - AIF1 DAC2 EQ Band 3 B */ 
 396	{ 0x04AB, 0x0A54 },    /* R1195  - AIF1 DAC2 EQ Band 3 C */ 
 397	{ 0x04AC, 0x0558 },    /* R1196  - AIF1 DAC2 EQ Band 3 PG */ 
 398	{ 0x04AD, 0x168E },    /* R1197  - AIF1 DAC2 EQ Band 4 A */ 
 399	{ 0x04AE, 0xF829 },    /* R1198  - AIF1 DAC2 EQ Band 4 B */ 
 400	{ 0x04AF, 0x07AD },    /* R1199  - AIF1 DAC2 EQ Band 4 C */ 
 401	{ 0x04B0, 0x1103 },    /* R1200  - AIF1 DAC2 EQ Band 4 PG */ 
 402	{ 0x04B1, 0x0564 },    /* R1201  - AIF1 DAC2 EQ Band 5 A */ 
 403	{ 0x04B2, 0x0559 },    /* R1202  - AIF1 DAC2 EQ Band 5 B */ 
 404	{ 0x04B3, 0x4000 },    /* R1203  - AIF1 DAC2 EQ Band 5 PG */ 
 405	{ 0x0500, 0x00C0 },    /* R1280  - AIF2 ADC Left Volume */ 
 406	{ 0x0501, 0x00C0 },    /* R1281  - AIF2 ADC Right Volume */ 
 407	{ 0x0502, 0x00C0 },    /* R1282  - AIF2 DAC Left Volume */ 
 408	{ 0x0503, 0x00C0 },    /* R1283  - AIF2 DAC Right Volume */ 
 409	{ 0x0510, 0x0000 },    /* R1296  - AIF2 ADC Filters */ 
 410	{ 0x0520, 0x0200 },    /* R1312  - AIF2 DAC Filters (1) */ 
 411	{ 0x0521, 0x0010 },    /* R1313  - AIF2 DAC Filters (2) */ 
 412	{ 0x0540, 0x0098 },    /* R1344  - AIF2 DRC (1) */ 
 413	{ 0x0541, 0x0845 },    /* R1345  - AIF2 DRC (2) */ 
 414	{ 0x0542, 0x0000 },    /* R1346  - AIF2 DRC (3) */ 
 415	{ 0x0543, 0x0000 },    /* R1347  - AIF2 DRC (4) */ 
 416	{ 0x0544, 0x0000 },    /* R1348  - AIF2 DRC (5) */ 
 417	{ 0x0580, 0x6318 },    /* R1408  - AIF2 EQ Gains (1) */ 
 418	{ 0x0581, 0x6300 },    /* R1409  - AIF2 EQ Gains (2) */ 
 419	{ 0x0582, 0x0FCA },    /* R1410  - AIF2 EQ Band 1 A */ 
 420	{ 0x0583, 0x0400 },    /* R1411  - AIF2 EQ Band 1 B */ 
 421	{ 0x0584, 0x00D8 },    /* R1412  - AIF2 EQ Band 1 PG */ 
 422	{ 0x0585, 0x1EB5 },    /* R1413  - AIF2 EQ Band 2 A */ 
 423	{ 0x0586, 0xF145 },    /* R1414  - AIF2 EQ Band 2 B */ 
 424	{ 0x0587, 0x0B75 },    /* R1415  - AIF2 EQ Band 2 C */ 
 425	{ 0x0588, 0x01C5 },    /* R1416  - AIF2 EQ Band 2 PG */ 
 426	{ 0x0589, 0x1C58 },    /* R1417  - AIF2 EQ Band 3 A */ 
 427	{ 0x058A, 0xF373 },    /* R1418  - AIF2 EQ Band 3 B */ 
 428	{ 0x058B, 0x0A54 },    /* R1419  - AIF2 EQ Band 3 C */ 
 429	{ 0x058C, 0x0558 },    /* R1420  - AIF2 EQ Band 3 PG */ 
 430	{ 0x058D, 0x168E },    /* R1421  - AIF2 EQ Band 4 A */ 
 431	{ 0x058E, 0xF829 },    /* R1422  - AIF2 EQ Band 4 B */ 
 432	{ 0x058F, 0x07AD },    /* R1423  - AIF2 EQ Band 4 C */ 
 433	{ 0x0590, 0x1103 },    /* R1424  - AIF2 EQ Band 4 PG */ 
 434	{ 0x0591, 0x0564 },    /* R1425  - AIF2 EQ Band 5 A */ 
 435	{ 0x0592, 0x0559 },    /* R1426  - AIF2 EQ Band 5 B */ 
 436	{ 0x0593, 0x4000 },    /* R1427  - AIF2 EQ Band 5 PG */ 
 437	{ 0x0600, 0x0000 },    /* R1536  - DAC1 Mixer Volumes */ 
 438	{ 0x0601, 0x0000 },    /* R1537  - DAC1 Left Mixer Routing */ 
 439	{ 0x0602, 0x0000 },    /* R1538  - DAC1 Right Mixer Routing */ 
 440	{ 0x0603, 0x0000 },    /* R1539  - DAC2 Mixer Volumes */ 
 441	{ 0x0604, 0x0000 },    /* R1540  - DAC2 Left Mixer Routing */ 
 442	{ 0x0605, 0x0000 },    /* R1541  - DAC2 Right Mixer Routing */ 
 443	{ 0x0606, 0x0000 },    /* R1542  - AIF1 ADC1 Left Mixer Routing */ 
 444	{ 0x0607, 0x0000 },    /* R1543  - AIF1 ADC1 Right Mixer Routing */ 
 445	{ 0x0608, 0x0000 },    /* R1544  - AIF1 ADC2 Left Mixer Routing */ 
 446	{ 0x0609, 0x0000 },    /* R1545  - AIF1 ADC2 Right mixer Routing */ 
 447	{ 0x0610, 0x02C0 },    /* R1552  - DAC1 Left Volume */ 
 448	{ 0x0611, 0x02C0 },    /* R1553  - DAC1 Right Volume */ 
 449	{ 0x0612, 0x02C0 },    /* R1554  - DAC2 Left Volume */ 
 450	{ 0x0613, 0x02C0 },    /* R1555  - DAC2 Right Volume */ 
 451	{ 0x0614, 0x0000 },    /* R1556  - DAC Softmute */ 
 452	{ 0x0620, 0x0002 },    /* R1568  - Oversampling */ 
 453	{ 0x0621, 0x0000 },    /* R1569  - Sidetone */ 
 454	{ 0x0700, 0x8100 },    /* R1792  - GPIO 1 */ 
 455	{ 0x0701, 0xA101 },    /* R1793  - GPIO 2 */ 
 456	{ 0x0702, 0xA101 },    /* R1794  - GPIO 3 */ 
 457	{ 0x0703, 0xA101 },    /* R1795  - GPIO 4 */ 
 458	{ 0x0704, 0xA101 },    /* R1796  - GPIO 5 */ 
 459	{ 0x0705, 0xA101 },    /* R1797  - GPIO 6 */ 
 460	{ 0x0706, 0xA101 },    /* R1798  - GPIO 7 */ 
 461	{ 0x0707, 0xA101 },    /* R1799  - GPIO 8 */ 
 462	{ 0x0708, 0xA101 },    /* R1800  - GPIO 9 */ 
 463	{ 0x0709, 0xA101 },    /* R1801  - GPIO 10 */ 
 464	{ 0x070A, 0xA101 },    /* R1802  - GPIO 11 */ 
 465	{ 0x0720, 0x0000 },    /* R1824  - Pull Control (1) */ 
 466	{ 0x0721, 0x0156 },    /* R1825  - Pull Control (2) */ 
 467	{ 0x0738, 0x07FF },    /* R1848  - Interrupt Status 1 Mask */ 
 468	{ 0x0739, 0xFFFF },    /* R1849  - Interrupt Status 2 Mask */ 
 469	{ 0x0740, 0x0000 },    /* R1856  - Interrupt Control */ 
 470	{ 0x0748, 0x003F },    /* R1864  - IRQ Debounce */ 
 471};
 472
 473static const struct reg_default wm8958_defaults[] = {
 474	{ 0x0001, 0x0000 },    /* R1     - Power Management (1) */
 475	{ 0x0002, 0x6000 },    /* R2     - Power Management (2) */
 476	{ 0x0003, 0x0000 },    /* R3     - Power Management (3) */
 477	{ 0x0004, 0x0000 },    /* R4     - Power Management (4) */
 478	{ 0x0005, 0x0000 },    /* R5     - Power Management (5) */
 479	{ 0x0006, 0x0000 },    /* R6     - Power Management (6) */
 480	{ 0x0015, 0x0000 },    /* R21    - Input Mixer (1) */
 481	{ 0x0018, 0x008B },    /* R24    - Left Line Input 1&2 Volume */
 482	{ 0x0019, 0x008B },    /* R25    - Left Line Input 3&4 Volume */
 483	{ 0x001A, 0x008B },    /* R26    - Right Line Input 1&2 Volume */
 484	{ 0x001B, 0x008B },    /* R27    - Right Line Input 3&4 Volume */
 485	{ 0x001C, 0x006D },    /* R28    - Left Output Volume */
 486	{ 0x001D, 0x006D },    /* R29    - Right Output Volume */
 487	{ 0x001E, 0x0066 },    /* R30    - Line Outputs Volume */
 488	{ 0x001F, 0x0020 },    /* R31    - HPOUT2 Volume */
 489	{ 0x0020, 0x0079 },    /* R32    - Left OPGA Volume */
 490	{ 0x0021, 0x0079 },    /* R33    - Right OPGA Volume */
 491	{ 0x0022, 0x0003 },    /* R34    - SPKMIXL Attenuation */
 492	{ 0x0023, 0x0003 },    /* R35    - SPKMIXR Attenuation */
 493	{ 0x0024, 0x0011 },    /* R36    - SPKOUT Mixers */
 494	{ 0x0025, 0x0140 },    /* R37    - ClassD */
 495	{ 0x0026, 0x0079 },    /* R38    - Speaker Volume Left */
 496	{ 0x0027, 0x0079 },    /* R39    - Speaker Volume Right */
 497	{ 0x0028, 0x0000 },    /* R40    - Input Mixer (2) */
 498	{ 0x0029, 0x0000 },    /* R41    - Input Mixer (3) */
 499	{ 0x002A, 0x0000 },    /* R42    - Input Mixer (4) */
 500	{ 0x002B, 0x0000 },    /* R43    - Input Mixer (5) */
 501	{ 0x002C, 0x0000 },    /* R44    - Input Mixer (6) */
 502	{ 0x002D, 0x0000 },    /* R45    - Output Mixer (1) */
 503	{ 0x002E, 0x0000 },    /* R46    - Output Mixer (2) */
 504	{ 0x002F, 0x0000 },    /* R47    - Output Mixer (3) */
 505	{ 0x0030, 0x0000 },    /* R48    - Output Mixer (4) */
 506	{ 0x0031, 0x0000 },    /* R49    - Output Mixer (5) */
 507	{ 0x0032, 0x0000 },    /* R50    - Output Mixer (6) */
 508	{ 0x0033, 0x0000 },    /* R51    - HPOUT2 Mixer */
 509	{ 0x0034, 0x0000 },    /* R52    - Line Mixer (1) */
 510	{ 0x0035, 0x0000 },    /* R53    - Line Mixer (2) */
 511	{ 0x0036, 0x0000 },    /* R54    - Speaker Mixer */
 512	{ 0x0037, 0x0000 },    /* R55    - Additional Control */
 513	{ 0x0038, 0x0000 },    /* R56    - AntiPOP (1) */
 514	{ 0x0039, 0x0180 },    /* R57    - AntiPOP (2) */
 515	{ 0x003B, 0x000D },    /* R59    - LDO 1 */
 516	{ 0x003C, 0x0005 },    /* R60    - LDO 2 */
 517	{ 0x003D, 0x0039 },    /* R61    - MICBIAS1 */
 518	{ 0x003E, 0x0039 },    /* R62    - MICBIAS2 */
 519	{ 0x004C, 0x1F25 },    /* R76    - Charge Pump (1) */
 520	{ 0x004D, 0xAB19 },    /* R77    - Charge Pump (2) */
 521	{ 0x0051, 0x0004 },    /* R81    - Class W (1) */
 522	{ 0x0055, 0x054A },    /* R85    - DC Servo (2) */
 523	{ 0x0057, 0x0000 },    /* R87    - DC Servo (4) */
 524	{ 0x0060, 0x0000 },    /* R96    - Analogue HP (1) */
 525	{ 0x00C5, 0x0000 },    /* R197   - Class D Test (5) */
 526	{ 0x00D0, 0x5600 },    /* R208   - Mic Detect 1 */
 527	{ 0x00D1, 0x007F },    /* R209   - Mic Detect 2 */
 528	{ 0x0101, 0x8004 },    /* R257   - Control Interface */
 529	{ 0x0110, 0x0000 },    /* R272   - Write Sequencer Ctrl (1) */
 530	{ 0x0111, 0x0000 },    /* R273   - Write Sequencer Ctrl (2) */
 531	{ 0x0200, 0x0000 },    /* R512   - AIF1 Clocking (1) */
 532	{ 0x0201, 0x0000 },    /* R513   - AIF1 Clocking (2) */
 533	{ 0x0204, 0x0000 },    /* R516   - AIF2 Clocking (1) */
 534	{ 0x0205, 0x0000 },    /* R517   - AIF2 Clocking (2) */
 535	{ 0x0208, 0x0000 },    /* R520   - Clocking (1) */
 536	{ 0x0209, 0x0000 },    /* R521   - Clocking (2) */
 537	{ 0x0210, 0x0083 },    /* R528   - AIF1 Rate */
 538	{ 0x0211, 0x0083 },    /* R529   - AIF2 Rate */
 539	{ 0x0220, 0x0000 },    /* R544   - FLL1 Control (1) */
 540	{ 0x0221, 0x0000 },    /* R545   - FLL1 Control (2) */
 541	{ 0x0222, 0x0000 },    /* R546   - FLL1 Control (3) */
 542	{ 0x0223, 0x0000 },    /* R547   - FLL1 Control (4) */
 543	{ 0x0224, 0x0C80 },    /* R548   - FLL1 Control (5) */
 544	{ 0x0226, 0x0000 },    /* R550   - FLL1 EFS 1 */
 545	{ 0x0227, 0x0006 },    /* R551   - FLL1 EFS 2 */
 546	{ 0x0240, 0x0000 },    /* R576   - FLL2Control (1) */
 547	{ 0x0241, 0x0000 },    /* R577   - FLL2Control (2) */
 548	{ 0x0242, 0x0000 },    /* R578   - FLL2Control (3) */
 549	{ 0x0243, 0x0000 },    /* R579   - FLL2 Control (4) */
 550	{ 0x0244, 0x0C80 },    /* R580   - FLL2Control (5) */
 551	{ 0x0246, 0x0000 },    /* R582   - FLL2 EFS 1 */
 552	{ 0x0247, 0x0006 },    /* R583   - FLL2 EFS 2 */
 553	{ 0x0300, 0x4050 },    /* R768   - AIF1 Control (1) */
 554	{ 0x0301, 0x4000 },    /* R769   - AIF1 Control (2) */
 555	{ 0x0302, 0x0000 },    /* R770   - AIF1 Master/Slave */
 556	{ 0x0303, 0x0040 },    /* R771   - AIF1 BCLK */
 557	{ 0x0304, 0x0040 },    /* R772   - AIF1ADC LRCLK */
 558	{ 0x0305, 0x0040 },    /* R773   - AIF1DAC LRCLK */
 559	{ 0x0306, 0x0004 },    /* R774   - AIF1DAC Data */
 560	{ 0x0307, 0x0100 },    /* R775   - AIF1ADC Data */
 561	{ 0x0310, 0x4053 },    /* R784   - AIF2 Control (1) */
 562	{ 0x0311, 0x4000 },    /* R785   - AIF2 Control (2) */
 563	{ 0x0312, 0x0000 },    /* R786   - AIF2 Master/Slave */
 564	{ 0x0313, 0x0040 },    /* R787   - AIF2 BCLK */
 565	{ 0x0314, 0x0040 },    /* R788   - AIF2ADC LRCLK */
 566	{ 0x0315, 0x0040 },    /* R789   - AIF2DAC LRCLK */
 567	{ 0x0316, 0x0000 },    /* R790   - AIF2DAC Data */
 568	{ 0x0317, 0x0000 },    /* R791   - AIF2ADC Data */
 569	{ 0x0320, 0x0040 },    /* R800   - AIF3 Control (1) */
 570	{ 0x0321, 0x0000 },    /* R801   - AIF3 Control (2) */
 571	{ 0x0322, 0x0000 },    /* R802   - AIF3DAC Data */
 572	{ 0x0323, 0x0000 },    /* R803   - AIF3ADC Data */
 573	{ 0x0400, 0x00C0 },    /* R1024  - AIF1 ADC1 Left Volume */
 574	{ 0x0401, 0x00C0 },    /* R1025  - AIF1 ADC1 Right Volume */
 575	{ 0x0402, 0x00C0 },    /* R1026  - AIF1 DAC1 Left Volume */
 576	{ 0x0403, 0x00C0 },    /* R1027  - AIF1 DAC1 Right Volume */
 577	{ 0x0404, 0x00C0 },    /* R1028  - AIF1 ADC2 Left Volume */
 578	{ 0x0405, 0x00C0 },    /* R1029  - AIF1 ADC2 Right Volume */
 579	{ 0x0406, 0x00C0 },    /* R1030  - AIF1 DAC2 Left Volume */
 580	{ 0x0407, 0x00C0 },    /* R1031  - AIF1 DAC2 Right Volume */
 581	{ 0x0410, 0x0000 },    /* R1040  - AIF1 ADC1 Filters */
 582	{ 0x0411, 0x0000 },    /* R1041  - AIF1 ADC2 Filters */
 583	{ 0x0420, 0x0200 },    /* R1056  - AIF1 DAC1 Filters (1) */
 584	{ 0x0421, 0x0010 },    /* R1057  - AIF1 DAC1 Filters (2) */
 585	{ 0x0422, 0x0200 },    /* R1058  - AIF1 DAC2 Filters (1) */
 586	{ 0x0423, 0x0010 },    /* R1059  - AIF1 DAC2 Filters (2) */
 587	{ 0x0430, 0x0068 },    /* R1072  - AIF1 DAC1 Noise Gate */
 588	{ 0x0431, 0x0068 },    /* R1073  - AIF1 DAC2 Noise Gate */
 589	{ 0x0440, 0x0098 },    /* R1088  - AIF1 DRC1 (1) */
 590	{ 0x0441, 0x0845 },    /* R1089  - AIF1 DRC1 (2) */
 591	{ 0x0442, 0x0000 },    /* R1090  - AIF1 DRC1 (3) */
 592	{ 0x0443, 0x0000 },    /* R1091  - AIF1 DRC1 (4) */
 593	{ 0x0444, 0x0000 },    /* R1092  - AIF1 DRC1 (5) */
 594	{ 0x0450, 0x0098 },    /* R1104  - AIF1 DRC2 (1) */
 595	{ 0x0451, 0x0845 },    /* R1105  - AIF1 DRC2 (2) */
 596	{ 0x0452, 0x0000 },    /* R1106  - AIF1 DRC2 (3) */
 597	{ 0x0453, 0x0000 },    /* R1107  - AIF1 DRC2 (4) */
 598	{ 0x0454, 0x0000 },    /* R1108  - AIF1 DRC2 (5) */
 599	{ 0x0480, 0x6318 },    /* R1152  - AIF1 DAC1 EQ Gains (1) */
 600	{ 0x0481, 0x6300 },    /* R1153  - AIF1 DAC1 EQ Gains (2) */
 601	{ 0x0482, 0x0FCA },    /* R1154  - AIF1 DAC1 EQ Band 1 A */
 602	{ 0x0483, 0x0400 },    /* R1155  - AIF1 DAC1 EQ Band 1 B */
 603	{ 0x0484, 0x00D8 },    /* R1156  - AIF1 DAC1 EQ Band 1 PG */
 604	{ 0x0485, 0x1EB5 },    /* R1157  - AIF1 DAC1 EQ Band 2 A */
 605	{ 0x0486, 0xF145 },    /* R1158  - AIF1 DAC1 EQ Band 2 B */
 606	{ 0x0487, 0x0B75 },    /* R1159  - AIF1 DAC1 EQ Band 2 C */
 607	{ 0x0488, 0x01C5 },    /* R1160  - AIF1 DAC1 EQ Band 2 PG */
 608	{ 0x0489, 0x1C58 },    /* R1161  - AIF1 DAC1 EQ Band 3 A */
 609	{ 0x048A, 0xF373 },    /* R1162  - AIF1 DAC1 EQ Band 3 B */
 610	{ 0x048B, 0x0A54 },    /* R1163  - AIF1 DAC1 EQ Band 3 C */
 611	{ 0x048C, 0x0558 },    /* R1164  - AIF1 DAC1 EQ Band 3 PG */
 612	{ 0x048D, 0x168E },    /* R1165  - AIF1 DAC1 EQ Band 4 A */
 613	{ 0x048E, 0xF829 },    /* R1166  - AIF1 DAC1 EQ Band 4 B */
 614	{ 0x048F, 0x07AD },    /* R1167  - AIF1 DAC1 EQ Band 4 C */
 615	{ 0x0490, 0x1103 },    /* R1168  - AIF1 DAC1 EQ Band 4 PG */
 616	{ 0x0491, 0x0564 },    /* R1169  - AIF1 DAC1 EQ Band 5 A */
 617	{ 0x0492, 0x0559 },    /* R1170  - AIF1 DAC1 EQ Band 5 B */
 618	{ 0x0493, 0x4000 },    /* R1171  - AIF1 DAC1 EQ Band 5 PG */
 619	{ 0x0494, 0x0000 },    /* R1172  - AIF1 DAC1 EQ Band 1 C */
 620	{ 0x04A0, 0x6318 },    /* R1184  - AIF1 DAC2 EQ Gains (1) */
 621	{ 0x04A1, 0x6300 },    /* R1185  - AIF1 DAC2 EQ Gains (2) */
 622	{ 0x04A2, 0x0FCA },    /* R1186  - AIF1 DAC2 EQ Band 1 A */
 623	{ 0x04A3, 0x0400 },    /* R1187  - AIF1 DAC2 EQ Band 1 B */
 624	{ 0x04A4, 0x00D8 },    /* R1188  - AIF1 DAC2 EQ Band 1 PG */
 625	{ 0x04A5, 0x1EB5 },    /* R1189  - AIF1 DAC2 EQ Band 2 A */
 626	{ 0x04A6, 0xF145 },    /* R1190  - AIF1 DAC2 EQ Band 2 B */
 627	{ 0x04A7, 0x0B75 },    /* R1191  - AIF1 DAC2 EQ Band 2 C */
 628	{ 0x04A8, 0x01C5 },    /* R1192  - AIF1 DAC2 EQ Band 2 PG */
 629	{ 0x04A9, 0x1C58 },    /* R1193  - AIF1 DAC2 EQ Band 3 A */
 630	{ 0x04AA, 0xF373 },    /* R1194  - AIF1 DAC2 EQ Band 3 B */
 631	{ 0x04AB, 0x0A54 },    /* R1195  - AIF1 DAC2 EQ Band 3 C */
 632	{ 0x04AC, 0x0558 },    /* R1196  - AIF1 DAC2 EQ Band 3 PG */
 633	{ 0x04AD, 0x168E },    /* R1197  - AIF1 DAC2 EQ Band 4 A */
 634	{ 0x04AE, 0xF829 },    /* R1198  - AIF1 DAC2 EQ Band 4 B */
 635	{ 0x04AF, 0x07AD },    /* R1199  - AIF1 DAC2 EQ Band 4 C */
 636	{ 0x04B0, 0x1103 },    /* R1200  - AIF1 DAC2 EQ Band 4 PG */
 637	{ 0x04B1, 0x0564 },    /* R1201  - AIF1 DAC2 EQ Band 5 A */
 638	{ 0x04B2, 0x0559 },    /* R1202  - AIF1 DAC2 EQ Band 5 B */
 639	{ 0x04B3, 0x4000 },    /* R1203  - AIF1 DAC2 EQ Band 5 PG */
 640	{ 0x04B4, 0x0000 },    /* R1204  - AIF1 DAC2EQ Band 1 C */
 641	{ 0x0500, 0x00C0 },    /* R1280  - AIF2 ADC Left Volume */
 642	{ 0x0501, 0x00C0 },    /* R1281  - AIF2 ADC Right Volume */
 643	{ 0x0502, 0x00C0 },    /* R1282  - AIF2 DAC Left Volume */
 644	{ 0x0503, 0x00C0 },    /* R1283  - AIF2 DAC Right Volume */
 645	{ 0x0510, 0x0000 },    /* R1296  - AIF2 ADC Filters */
 646	{ 0x0520, 0x0200 },    /* R1312  - AIF2 DAC Filters (1) */
 647	{ 0x0521, 0x0010 },    /* R1313  - AIF2 DAC Filters (2) */
 648	{ 0x0530, 0x0068 },    /* R1328  - AIF2 DAC Noise Gate */
 649	{ 0x0540, 0x0098 },    /* R1344  - AIF2 DRC (1) */
 650	{ 0x0541, 0x0845 },    /* R1345  - AIF2 DRC (2) */
 651	{ 0x0542, 0x0000 },    /* R1346  - AIF2 DRC (3) */
 652	{ 0x0543, 0x0000 },    /* R1347  - AIF2 DRC (4) */
 653	{ 0x0544, 0x0000 },    /* R1348  - AIF2 DRC (5) */
 654	{ 0x0580, 0x6318 },    /* R1408  - AIF2 EQ Gains (1) */
 655	{ 0x0581, 0x6300 },    /* R1409  - AIF2 EQ Gains (2) */
 656	{ 0x0582, 0x0FCA },    /* R1410  - AIF2 EQ Band 1 A */
 657	{ 0x0583, 0x0400 },    /* R1411  - AIF2 EQ Band 1 B */
 658	{ 0x0584, 0x00D8 },    /* R1412  - AIF2 EQ Band 1 PG */
 659	{ 0x0585, 0x1EB5 },    /* R1413  - AIF2 EQ Band 2 A */
 660	{ 0x0586, 0xF145 },    /* R1414  - AIF2 EQ Band 2 B */
 661	{ 0x0587, 0x0B75 },    /* R1415  - AIF2 EQ Band 2 C */
 662	{ 0x0588, 0x01C5 },    /* R1416  - AIF2 EQ Band 2 PG */
 663	{ 0x0589, 0x1C58 },    /* R1417  - AIF2 EQ Band 3 A */
 664	{ 0x058A, 0xF373 },    /* R1418  - AIF2 EQ Band 3 B */
 665	{ 0x058B, 0x0A54 },    /* R1419  - AIF2 EQ Band 3 C */
 666	{ 0x058C, 0x0558 },    /* R1420  - AIF2 EQ Band 3 PG */
 667	{ 0x058D, 0x168E },    /* R1421  - AIF2 EQ Band 4 A */
 668	{ 0x058E, 0xF829 },    /* R1422  - AIF2 EQ Band 4 B */
 669	{ 0x058F, 0x07AD },    /* R1423  - AIF2 EQ Band 4 C */
 670	{ 0x0590, 0x1103 },    /* R1424  - AIF2 EQ Band 4 PG */
 671	{ 0x0591, 0x0564 },    /* R1425  - AIF2 EQ Band 5 A */
 672	{ 0x0592, 0x0559 },    /* R1426  - AIF2 EQ Band 5 B */
 673	{ 0x0593, 0x4000 },    /* R1427  - AIF2 EQ Band 5 PG */
 674	{ 0x0594, 0x0000 },    /* R1428  - AIF2 EQ Band 1 C */
 675	{ 0x0600, 0x0000 },    /* R1536  - DAC1 Mixer Volumes */
 676	{ 0x0601, 0x0000 },    /* R1537  - DAC1 Left Mixer Routing */
 677	{ 0x0602, 0x0000 },    /* R1538  - DAC1 Right Mixer Routing */
 678	{ 0x0603, 0x0000 },    /* R1539  - DAC2 Mixer Volumes */
 679	{ 0x0604, 0x0000 },    /* R1540  - DAC2 Left Mixer Routing */
 680	{ 0x0605, 0x0000 },    /* R1541  - DAC2 Right Mixer Routing */
 681	{ 0x0606, 0x0000 },    /* R1542  - AIF1 ADC1 Left Mixer Routing */
 682	{ 0x0607, 0x0000 },    /* R1543  - AIF1 ADC1 Right Mixer Routing */
 683	{ 0x0608, 0x0000 },    /* R1544  - AIF1 ADC2 Left Mixer Routing */
 684	{ 0x0609, 0x0000 },    /* R1545  - AIF1 ADC2 Right mixer Routing */
 685	{ 0x0610, 0x02C0 },    /* R1552  - DAC1 Left Volume */
 686	{ 0x0611, 0x02C0 },    /* R1553  - DAC1 Right Volume */
 687	{ 0x0612, 0x02C0 },    /* R1554  - DAC2 Left Volume */
 688	{ 0x0613, 0x02C0 },    /* R1555  - DAC2 Right Volume */
 689	{ 0x0614, 0x0000 },    /* R1556  - DAC Softmute */
 690	{ 0x0620, 0x0002 },    /* R1568  - Oversampling */
 691	{ 0x0621, 0x0000 },    /* R1569  - Sidetone */
 692	{ 0x0700, 0x8100 },    /* R1792  - GPIO 1 */
 693	{ 0x0701, 0xA101 },    /* R1793  - Pull Control (MCLK2) */
 694	{ 0x0702, 0xA101 },    /* R1794  - Pull Control (BCLK2) */
 695	{ 0x0703, 0xA101 },    /* R1795  - Pull Control (DACLRCLK2) */
 696	{ 0x0704, 0xA101 },    /* R1796  - Pull Control (DACDAT2) */
 697	{ 0x0705, 0xA101 },    /* R1797  - GPIO 6 */
 698	{ 0x0707, 0xA101 },    /* R1799  - GPIO 8 */
 699	{ 0x0708, 0xA101 },    /* R1800  - GPIO 9 */
 700	{ 0x0709, 0xA101 },    /* R1801  - GPIO 10 */
 701	{ 0x070A, 0xA101 },    /* R1802  - GPIO 11 */
 702	{ 0x0720, 0x0000 },    /* R1824  - Pull Control (1) */
 703	{ 0x0721, 0x0156 },    /* R1825  - Pull Control (2) */
 704	{ 0x0738, 0x07FF },    /* R1848  - Interrupt Status 1 Mask */
 705	{ 0x0739, 0xFFEF },    /* R1849  - Interrupt Status 2 Mask */
 706	{ 0x0740, 0x0000 },    /* R1856  - Interrupt Control */
 707	{ 0x0748, 0x003F },    /* R1864  - IRQ Debounce */
 708	{ 0x0900, 0x1C00 },    /* R2304  - DSP2_Program */
 709	{ 0x0901, 0x0000 },    /* R2305  - DSP2_Config */
 710	{ 0x0A0D, 0x0000 },    /* R2573  - DSP2_ExecControl */
 711	{ 0x2400, 0x003F },    /* R9216  - MBC Band 1 K (1) */
 712	{ 0x2401, 0x8BD8 },    /* R9217  - MBC Band 1 K (2) */
 713	{ 0x2402, 0x0032 },    /* R9218  - MBC Band 1 N1 (1) */
 714	{ 0x2403, 0xF52D },    /* R9219  - MBC Band 1 N1 (2) */
 715	{ 0x2404, 0x0065 },    /* R9220  - MBC Band 1 N2 (1) */
 716	{ 0x2405, 0xAC8C },    /* R9221  - MBC Band 1 N2 (2) */
 717	{ 0x2406, 0x006B },    /* R9222  - MBC Band 1 N3 (1) */
 718	{ 0x2407, 0xE087 },    /* R9223  - MBC Band 1 N3 (2) */
 719	{ 0x2408, 0x0072 },    /* R9224  - MBC Band 1 N4 (1) */
 720	{ 0x2409, 0x1483 },    /* R9225  - MBC Band 1 N4 (2) */
 721	{ 0x240A, 0x0072 },    /* R9226  - MBC Band 1 N5 (1) */
 722	{ 0x240B, 0x1483 },    /* R9227  - MBC Band 1 N5 (2) */
 723	{ 0x240C, 0x0043 },    /* R9228  - MBC Band 1 X1 (1) */
 724	{ 0x240D, 0x3525 },    /* R9229  - MBC Band 1 X1 (2) */
 725	{ 0x240E, 0x0006 },    /* R9230  - MBC Band 1 X2 (1) */
 726	{ 0x240F, 0x6A4A },    /* R9231  - MBC Band 1 X2 (2) */
 727	{ 0x2410, 0x0043 },    /* R9232  - MBC Band 1 X3 (1) */
 728	{ 0x2411, 0x6079 },    /* R9233  - MBC Band 1 X3 (2) */
 729	{ 0x2412, 0x000C },    /* R9234  - MBC Band 1 Attack (1) */
 730	{ 0x2413, 0xCCCD },    /* R9235  - MBC Band 1 Attack (2) */
 731	{ 0x2414, 0x0000 },    /* R9236  - MBC Band 1 Decay (1) */
 732	{ 0x2415, 0x0800 },    /* R9237  - MBC Band 1 Decay (2) */
 733	{ 0x2416, 0x003F },    /* R9238  - MBC Band 2 K (1) */
 734	{ 0x2417, 0x8BD8 },    /* R9239  - MBC Band 2 K (2) */
 735	{ 0x2418, 0x0032 },    /* R9240  - MBC Band 2 N1 (1) */
 736	{ 0x2419, 0xF52D },    /* R9241  - MBC Band 2 N1 (2) */
 737	{ 0x241A, 0x0065 },    /* R9242  - MBC Band 2 N2 (1) */
 738	{ 0x241B, 0xAC8C },    /* R9243  - MBC Band 2 N2 (2) */
 739	{ 0x241C, 0x006B },    /* R9244  - MBC Band 2 N3 (1) */
 740	{ 0x241D, 0xE087 },    /* R9245  - MBC Band 2 N3 (2) */
 741	{ 0x241E, 0x0072 },    /* R9246  - MBC Band 2 N4 (1) */
 742	{ 0x241F, 0x1483 },    /* R9247  - MBC Band 2 N4 (2) */
 743	{ 0x2420, 0x0072 },    /* R9248  - MBC Band 2 N5 (1) */
 744	{ 0x2421, 0x1483 },    /* R9249  - MBC Band 2 N5 (2) */
 745	{ 0x2422, 0x0043 },    /* R9250  - MBC Band 2 X1 (1) */
 746	{ 0x2423, 0x3525 },    /* R9251  - MBC Band 2 X1 (2) */
 747	{ 0x2424, 0x0006 },    /* R9252  - MBC Band 2 X2 (1) */
 748	{ 0x2425, 0x6A4A },    /* R9253  - MBC Band 2 X2 (2) */
 749	{ 0x2426, 0x0043 },    /* R9254  - MBC Band 2 X3 (1) */
 750	{ 0x2427, 0x6079 },    /* R9255  - MBC Band 2 X3 (2) */
 751	{ 0x2428, 0x000C },    /* R9256  - MBC Band 2 Attack (1) */
 752	{ 0x2429, 0xCCCD },    /* R9257  - MBC Band 2 Attack (2) */
 753	{ 0x242A, 0x0000 },    /* R9258  - MBC Band 2 Decay (1) */
 754	{ 0x242B, 0x0800 },    /* R9259  - MBC Band 2 Decay (2) */
 755	{ 0x242C, 0x005A },    /* R9260  - MBC_B2_PG2 (1) */
 756	{ 0x242D, 0x7EFA },    /* R9261  - MBC_B2_PG2 (2) */
 757	{ 0x242E, 0x005A },    /* R9262  - MBC_B1_PG2 (1) */
 758	{ 0x242F, 0x7EFA },    /* R9263  - MBC_B1_PG2 (2) */
 759	{ 0x2600, 0x00A7 },    /* R9728  - MBC Crossover (1) */
 760	{ 0x2601, 0x0D1C },    /* R9729  - MBC Crossover (2) */
 761	{ 0x2602, 0x0083 },    /* R9730  - MBC HPF (1) */
 762	{ 0x2603, 0x98AD },    /* R9731  - MBC HPF (2) */
 763	{ 0x2606, 0x0008 },    /* R9734  - MBC LPF (1) */
 764	{ 0x2607, 0xE7A2 },    /* R9735  - MBC LPF (2) */
 765	{ 0x260A, 0x0055 },    /* R9738  - MBC RMS Limit (1) */
 766	{ 0x260B, 0x8C4B },    /* R9739  - MBC RMS Limit (2) */
 767};
 768
 769static bool wm1811_readable_register(struct device *dev, unsigned int reg)
 770{
 771	switch (reg) {
 772	case WM8994_SOFTWARE_RESET:
 773	case WM8994_POWER_MANAGEMENT_1:
 774	case WM8994_POWER_MANAGEMENT_2:
 775	case WM8994_POWER_MANAGEMENT_3:
 776	case WM8994_POWER_MANAGEMENT_4:
 777	case WM8994_POWER_MANAGEMENT_5:
 778	case WM8994_POWER_MANAGEMENT_6:
 779	case WM8994_INPUT_MIXER_1:
 780	case WM8994_LEFT_LINE_INPUT_1_2_VOLUME:
 781	case WM8994_LEFT_LINE_INPUT_3_4_VOLUME:
 782	case WM8994_RIGHT_LINE_INPUT_1_2_VOLUME:
 783	case WM8994_RIGHT_LINE_INPUT_3_4_VOLUME:
 784	case WM8994_LEFT_OUTPUT_VOLUME:
 785	case WM8994_RIGHT_OUTPUT_VOLUME:
 786	case WM8994_LINE_OUTPUTS_VOLUME:
 787	case WM8994_HPOUT2_VOLUME:
 788	case WM8994_LEFT_OPGA_VOLUME:
 789	case WM8994_RIGHT_OPGA_VOLUME:
 790	case WM8994_SPKMIXL_ATTENUATION:
 791	case WM8994_SPKMIXR_ATTENUATION:
 792	case WM8994_SPKOUT_MIXERS:
 793	case WM8994_CLASSD:
 794	case WM8994_SPEAKER_VOLUME_LEFT:
 795	case WM8994_SPEAKER_VOLUME_RIGHT:
 796	case WM8994_INPUT_MIXER_2:
 797	case WM8994_INPUT_MIXER_3:
 798	case WM8994_INPUT_MIXER_4:
 799	case WM8994_INPUT_MIXER_5:
 800	case WM8994_INPUT_MIXER_6:
 801	case WM8994_OUTPUT_MIXER_1:
 802	case WM8994_OUTPUT_MIXER_2:
 803	case WM8994_OUTPUT_MIXER_3:
 804	case WM8994_OUTPUT_MIXER_4:
 805	case WM8994_OUTPUT_MIXER_5:
 806	case WM8994_OUTPUT_MIXER_6:
 807	case WM8994_HPOUT2_MIXER:
 808	case WM8994_LINE_MIXER_1:
 809	case WM8994_LINE_MIXER_2:
 810	case WM8994_SPEAKER_MIXER:
 811	case WM8994_ADDITIONAL_CONTROL:
 812	case WM8994_ANTIPOP_1:
 813	case WM8994_ANTIPOP_2:
 814	case WM8994_LDO_1:
 815	case WM8994_LDO_2:
 816	case WM8958_MICBIAS1:
 817	case WM8958_MICBIAS2:
 818	case WM8994_CHARGE_PUMP_1:
 819	case WM8958_CHARGE_PUMP_2:
 820	case WM8994_CLASS_W_1:
 821	case WM8994_DC_SERVO_1:
 822	case WM8994_DC_SERVO_2:
 823	case WM8994_DC_SERVO_READBACK:
 824	case WM8994_DC_SERVO_4:
 825	case WM8994_DC_SERVO_4E:
 826	case WM8994_ANALOGUE_HP_1:
 827	case WM8958_MIC_DETECT_1:
 828	case WM8958_MIC_DETECT_2:
 829	case WM8958_MIC_DETECT_3:
 830	case WM8994_CHIP_REVISION:
 831	case WM8994_CONTROL_INTERFACE:
 832	case WM8994_AIF1_CLOCKING_1:
 833	case WM8994_AIF1_CLOCKING_2:
 834	case WM8994_AIF2_CLOCKING_1:
 835	case WM8994_AIF2_CLOCKING_2:
 836	case WM8994_CLOCKING_1:
 837	case WM8994_CLOCKING_2:
 838	case WM8994_AIF1_RATE:
 839	case WM8994_AIF2_RATE:
 840	case WM8994_RATE_STATUS:
 841	case WM8994_FLL1_CONTROL_1:
 842	case WM8994_FLL1_CONTROL_2:
 843	case WM8994_FLL1_CONTROL_3:
 844	case WM8994_FLL1_CONTROL_4:
 845	case WM8994_FLL1_CONTROL_5:
 846	case WM8958_FLL1_EFS_1:
 847	case WM8958_FLL1_EFS_2:
 848	case WM8994_FLL2_CONTROL_1:
 849	case WM8994_FLL2_CONTROL_2:
 850	case WM8994_FLL2_CONTROL_3:
 851	case WM8994_FLL2_CONTROL_4:
 852	case WM8994_FLL2_CONTROL_5:
 853	case WM8958_FLL2_EFS_1:
 854	case WM8958_FLL2_EFS_2:
 855	case WM8994_AIF1_CONTROL_1:
 856	case WM8994_AIF1_CONTROL_2:
 857	case WM8994_AIF1_MASTER_SLAVE:
 858	case WM8994_AIF1_BCLK:
 859	case WM8994_AIF1ADC_LRCLK:
 860	case WM8994_AIF1DAC_LRCLK:
 861	case WM8994_AIF1DAC_DATA:
 862	case WM8994_AIF1ADC_DATA:
 863	case WM8994_AIF2_CONTROL_1:
 864	case WM8994_AIF2_CONTROL_2:
 865	case WM8994_AIF2_MASTER_SLAVE:
 866	case WM8994_AIF2_BCLK:
 867	case WM8994_AIF2ADC_LRCLK:
 868	case WM8994_AIF2DAC_LRCLK:
 869	case WM8994_AIF2DAC_DATA:
 870	case WM8994_AIF2ADC_DATA:
 871	case WM1811_AIF2TX_CONTROL:
 872	case WM8958_AIF3_CONTROL_1:
 873	case WM8958_AIF3_CONTROL_2:
 874	case WM8958_AIF3DAC_DATA:
 875	case WM8958_AIF3ADC_DATA:
 876	case WM8994_AIF1_ADC1_LEFT_VOLUME:
 877	case WM8994_AIF1_ADC1_RIGHT_VOLUME:
 878	case WM8994_AIF1_DAC1_LEFT_VOLUME:
 879	case WM8994_AIF1_DAC1_RIGHT_VOLUME:
 880	case WM8994_AIF1_ADC1_FILTERS:
 881	case WM8994_AIF1_ADC2_FILTERS:
 882	case WM8994_AIF1_DAC1_FILTERS_1:
 883	case WM8994_AIF1_DAC1_FILTERS_2:
 884	case WM8994_AIF1_DAC2_FILTERS_1:
 885	case WM8994_AIF1_DAC2_FILTERS_2:
 886	case WM8958_AIF1_DAC1_NOISE_GATE:
 887	case WM8958_AIF1_DAC2_NOISE_GATE:
 888	case WM8994_AIF1_DRC1_1:
 889	case WM8994_AIF1_DRC1_2:
 890	case WM8994_AIF1_DRC1_3:
 891	case WM8994_AIF1_DRC1_4:
 892	case WM8994_AIF1_DRC1_5:
 893	case WM8994_AIF1_DRC2_1:
 894	case WM8994_AIF1_DRC2_2:
 895	case WM8994_AIF1_DRC2_3:
 896	case WM8994_AIF1_DRC2_4:
 897	case WM8994_AIF1_DRC2_5:
 898	case WM8994_AIF1_DAC1_EQ_GAINS_1:
 899	case WM8994_AIF1_DAC1_EQ_GAINS_2:
 900	case WM8994_AIF1_DAC1_EQ_BAND_1_A:
 901	case WM8994_AIF1_DAC1_EQ_BAND_1_B:
 902	case WM8994_AIF1_DAC1_EQ_BAND_1_PG:
 903	case WM8994_AIF1_DAC1_EQ_BAND_2_A:
 904	case WM8994_AIF1_DAC1_EQ_BAND_2_B:
 905	case WM8994_AIF1_DAC1_EQ_BAND_2_C:
 906	case WM8994_AIF1_DAC1_EQ_BAND_2_PG:
 907	case WM8994_AIF1_DAC1_EQ_BAND_3_A:
 908	case WM8994_AIF1_DAC1_EQ_BAND_3_B:
 909	case WM8994_AIF1_DAC1_EQ_BAND_3_C:
 910	case WM8994_AIF1_DAC1_EQ_BAND_3_PG:
 911	case WM8994_AIF1_DAC1_EQ_BAND_4_A:
 912	case WM8994_AIF1_DAC1_EQ_BAND_4_B:
 913	case WM8994_AIF1_DAC1_EQ_BAND_4_C:
 914	case WM8994_AIF1_DAC1_EQ_BAND_4_PG:
 915	case WM8994_AIF1_DAC1_EQ_BAND_5_A:
 916	case WM8994_AIF1_DAC1_EQ_BAND_5_B:
 917	case WM8994_AIF1_DAC1_EQ_BAND_5_PG:
 918	case WM8994_AIF1_DAC1_EQ_BAND_1_C:
 919	case WM8994_AIF1_DAC2_EQ_GAINS_1:
 920	case WM8994_AIF1_DAC2_EQ_GAINS_2:
 921	case WM8994_AIF1_DAC2_EQ_BAND_1_A:
 922	case WM8994_AIF1_DAC2_EQ_BAND_1_B:
 923	case WM8994_AIF1_DAC2_EQ_BAND_1_PG:
 924	case WM8994_AIF1_DAC2_EQ_BAND_2_A:
 925	case WM8994_AIF1_DAC2_EQ_BAND_2_B:
 926	case WM8994_AIF1_DAC2_EQ_BAND_2_C:
 927	case WM8994_AIF1_DAC2_EQ_BAND_2_PG:
 928	case WM8994_AIF1_DAC2_EQ_BAND_3_A:
 929	case WM8994_AIF1_DAC2_EQ_BAND_3_B:
 930	case WM8994_AIF1_DAC2_EQ_BAND_3_C:
 931	case WM8994_AIF1_DAC2_EQ_BAND_3_PG:
 932	case WM8994_AIF1_DAC2_EQ_BAND_4_A:
 933	case WM8994_AIF1_DAC2_EQ_BAND_4_B:
 934	case WM8994_AIF1_DAC2_EQ_BAND_4_C:
 935	case WM8994_AIF1_DAC2_EQ_BAND_4_PG:
 936	case WM8994_AIF1_DAC2_EQ_BAND_5_A:
 937	case WM8994_AIF1_DAC2_EQ_BAND_5_B:
 938	case WM8994_AIF1_DAC2_EQ_BAND_5_PG:
 939	case WM8994_AIF1_DAC2_EQ_BAND_1_C:
 940	case WM8994_AIF2_ADC_LEFT_VOLUME:
 941	case WM8994_AIF2_ADC_RIGHT_VOLUME:
 942	case WM8994_AIF2_DAC_LEFT_VOLUME:
 943	case WM8994_AIF2_DAC_RIGHT_VOLUME:
 944	case WM8994_AIF2_ADC_FILTERS:
 945	case WM8994_AIF2_DAC_FILTERS_1:
 946	case WM8994_AIF2_DAC_FILTERS_2:
 947	case WM8958_AIF2_DAC_NOISE_GATE:
 948	case WM8994_AIF2_DRC_1:
 949	case WM8994_AIF2_DRC_2:
 950	case WM8994_AIF2_DRC_3:
 951	case WM8994_AIF2_DRC_4:
 952	case WM8994_AIF2_DRC_5:
 953	case WM8994_AIF2_EQ_GAINS_1:
 954	case WM8994_AIF2_EQ_GAINS_2:
 955	case WM8994_AIF2_EQ_BAND_1_A:
 956	case WM8994_AIF2_EQ_BAND_1_B:
 957	case WM8994_AIF2_EQ_BAND_1_PG:
 958	case WM8994_AIF2_EQ_BAND_2_A:
 959	case WM8994_AIF2_EQ_BAND_2_B:
 960	case WM8994_AIF2_EQ_BAND_2_C:
 961	case WM8994_AIF2_EQ_BAND_2_PG:
 962	case WM8994_AIF2_EQ_BAND_3_A:
 963	case WM8994_AIF2_EQ_BAND_3_B:
 964	case WM8994_AIF2_EQ_BAND_3_C:
 965	case WM8994_AIF2_EQ_BAND_3_PG:
 966	case WM8994_AIF2_EQ_BAND_4_A:
 967	case WM8994_AIF2_EQ_BAND_4_B:
 968	case WM8994_AIF2_EQ_BAND_4_C:
 969	case WM8994_AIF2_EQ_BAND_4_PG:
 970	case WM8994_AIF2_EQ_BAND_5_A:
 971	case WM8994_AIF2_EQ_BAND_5_B:
 972	case WM8994_AIF2_EQ_BAND_5_PG:
 973	case WM8994_AIF2_EQ_BAND_1_C:
 974	case WM8994_DAC1_MIXER_VOLUMES:
 975	case WM8994_DAC1_LEFT_MIXER_ROUTING:
 976	case WM8994_DAC1_RIGHT_MIXER_ROUTING:
 977	case WM8994_DAC2_MIXER_VOLUMES:
 978	case WM8994_DAC2_LEFT_MIXER_ROUTING:
 979	case WM8994_DAC2_RIGHT_MIXER_ROUTING:
 980	case WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING:
 981	case WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING:
 982	case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING:
 983	case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING:
 984	case WM8994_DAC1_LEFT_VOLUME:
 985	case WM8994_DAC1_RIGHT_VOLUME:
 986	case WM8994_DAC2_LEFT_VOLUME:
 987	case WM8994_DAC2_RIGHT_VOLUME:
 988	case WM8994_DAC_SOFTMUTE:
 989	case WM8994_OVERSAMPLING:
 990	case WM8994_SIDETONE:
 991	case WM8994_GPIO_1:
 992	case WM8994_GPIO_2:
 993	case WM8994_GPIO_3:
 994	case WM8994_GPIO_4:
 995	case WM8994_GPIO_5:
 996	case WM8994_GPIO_6:
 997	case WM8994_GPIO_8:
 998	case WM8994_GPIO_9:
 999	case WM8994_GPIO_10:
1000	case WM8994_GPIO_11:
1001	case WM8994_PULL_CONTROL_1:
1002	case WM8994_PULL_CONTROL_2:
1003	case WM8994_INTERRUPT_STATUS_1:
1004	case WM8994_INTERRUPT_STATUS_2:
1005	case WM8994_INTERRUPT_RAW_STATUS_2:
1006	case WM8994_INTERRUPT_STATUS_1_MASK:
1007	case WM8994_INTERRUPT_STATUS_2_MASK:
1008	case WM8994_INTERRUPT_CONTROL:
1009	case WM8994_IRQ_DEBOUNCE:
1010		return true;
1011	default:
1012		return false;
1013	}
1014}
1015
1016static bool wm8994_readable_register(struct device *dev, unsigned int reg)
1017{
1018	switch (reg) {
1019	case WM8994_DC_SERVO_READBACK:
1020	case WM8994_MICBIAS:
1021	case WM8994_WRITE_SEQUENCER_CTRL_1:
1022	case WM8994_WRITE_SEQUENCER_CTRL_2:
1023	case WM8994_AIF1_ADC2_LEFT_VOLUME:
1024	case WM8994_AIF1_ADC2_RIGHT_VOLUME:
1025	case WM8994_AIF1_DAC2_LEFT_VOLUME:
1026	case WM8994_AIF1_DAC2_RIGHT_VOLUME:
1027	case WM8994_AIF1_ADC2_FILTERS:
1028	case WM8994_AIF1_DAC2_FILTERS_1:
1029	case WM8994_AIF1_DAC2_FILTERS_2:
1030	case WM8958_AIF1_DAC2_NOISE_GATE:
1031	case WM8994_AIF1_DRC2_1:
1032	case WM8994_AIF1_DRC2_2:
1033	case WM8994_AIF1_DRC2_3:
1034	case WM8994_AIF1_DRC2_4:
1035	case WM8994_AIF1_DRC2_5:
1036	case WM8994_AIF1_DAC2_EQ_GAINS_1:
1037	case WM8994_AIF1_DAC2_EQ_GAINS_2:
1038	case WM8994_AIF1_DAC2_EQ_BAND_1_A:
1039	case WM8994_AIF1_DAC2_EQ_BAND_1_B:
1040	case WM8994_AIF1_DAC2_EQ_BAND_1_PG:
1041	case WM8994_AIF1_DAC2_EQ_BAND_2_A:
1042	case WM8994_AIF1_DAC2_EQ_BAND_2_B:
1043	case WM8994_AIF1_DAC2_EQ_BAND_2_C:
1044	case WM8994_AIF1_DAC2_EQ_BAND_2_PG:
1045	case WM8994_AIF1_DAC2_EQ_BAND_3_A:
1046	case WM8994_AIF1_DAC2_EQ_BAND_3_B:
1047	case WM8994_AIF1_DAC2_EQ_BAND_3_C:
1048	case WM8994_AIF1_DAC2_EQ_BAND_3_PG:
1049	case WM8994_AIF1_DAC2_EQ_BAND_4_A:
1050	case WM8994_AIF1_DAC2_EQ_BAND_4_B:
1051	case WM8994_AIF1_DAC2_EQ_BAND_4_C:
1052	case WM8994_AIF1_DAC2_EQ_BAND_4_PG:
1053	case WM8994_AIF1_DAC2_EQ_BAND_5_A:
1054	case WM8994_AIF1_DAC2_EQ_BAND_5_B:
1055	case WM8994_AIF1_DAC2_EQ_BAND_5_PG:
1056	case WM8994_AIF1_DAC2_EQ_BAND_1_C:
1057	case WM8994_DAC2_MIXER_VOLUMES:
1058	case WM8994_DAC2_LEFT_MIXER_ROUTING:
1059	case WM8994_DAC2_RIGHT_MIXER_ROUTING:
1060	case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING:
1061	case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING:
1062	case WM8994_DAC2_LEFT_VOLUME:
1063	case WM8994_DAC2_RIGHT_VOLUME:
1064		return true;
1065	default:
1066		return wm1811_readable_register(dev, reg);
1067	}
1068}
1069
1070static bool wm8958_readable_register(struct device *dev, unsigned int reg)
1071{
1072	switch (reg) {
1073	case WM8958_DSP2_PROGRAM:
1074	case WM8958_DSP2_CONFIG:
1075	case WM8958_DSP2_MAGICNUM:
1076	case WM8958_DSP2_RELEASEYEAR:
1077	case WM8958_DSP2_RELEASEMONTHDAY:
1078	case WM8958_DSP2_RELEASETIME:
1079	case WM8958_DSP2_VERMAJMIN:
1080	case WM8958_DSP2_VERBUILD:
1081	case WM8958_DSP2_TESTREG:
1082	case WM8958_DSP2_XORREG:
1083	case WM8958_DSP2_SHIFTMAXX:
1084	case WM8958_DSP2_SHIFTMAXY:
1085	case WM8958_DSP2_SHIFTMAXZ:
1086	case WM8958_DSP2_SHIFTMAXEXTLO:
1087	case WM8958_DSP2_AESSELECT:
1088	case WM8958_DSP2_EXECCONTROL:
1089	case WM8958_DSP2_SAMPLEBREAK:
1090	case WM8958_DSP2_COUNTBREAK:
1091	case WM8958_DSP2_INTSTATUS:
1092	case WM8958_DSP2_EVENTSTATUS:
1093	case WM8958_DSP2_INTMASK:
1094	case WM8958_DSP2_CONFIGDWIDTH:
1095	case WM8958_DSP2_CONFIGINSTR:
1096	case WM8958_DSP2_CONFIGDMEM:
1097	case WM8958_DSP2_CONFIGDELAYS:
1098	case WM8958_DSP2_CONFIGNUMIO:
1099	case WM8958_DSP2_CONFIGEXTDEPTH:
1100	case WM8958_DSP2_CONFIGMULTIPLIER:
1101	case WM8958_DSP2_CONFIGCTRLDWIDTH:
1102	case WM8958_DSP2_CONFIGPIPELINE:
1103	case WM8958_DSP2_SHIFTMAXEXTHI:
1104	case WM8958_DSP2_SWVERSIONREG:
1105	case WM8958_DSP2_CONFIGXMEM:
1106	case WM8958_DSP2_CONFIGYMEM:
1107	case WM8958_DSP2_CONFIGZMEM:
1108	case WM8958_FW_BUILD_1:
1109	case WM8958_FW_BUILD_0:
1110	case WM8958_FW_ID_1:
1111	case WM8958_FW_ID_0:
1112	case WM8958_FW_MAJOR_1:
1113	case WM8958_FW_MAJOR_0:
1114	case WM8958_FW_MINOR_1:
1115	case WM8958_FW_MINOR_0:
1116	case WM8958_FW_PATCH_1:
1117	case WM8958_FW_PATCH_0:
1118	case WM8958_MBC_BAND_1_K_1:
1119	case WM8958_MBC_BAND_1_K_2:
1120	case WM8958_MBC_BAND_1_N1_1:
1121	case WM8958_MBC_BAND_1_N1_2:
1122	case WM8958_MBC_BAND_1_N2_1:
1123	case WM8958_MBC_BAND_1_N2_2:
1124	case WM8958_MBC_BAND_1_N3_1:
1125	case WM8958_MBC_BAND_1_N3_2:
1126	case WM8958_MBC_BAND_1_N4_1:
1127	case WM8958_MBC_BAND_1_N4_2:
1128	case WM8958_MBC_BAND_1_N5_1:
1129	case WM8958_MBC_BAND_1_N5_2:
1130	case WM8958_MBC_BAND_1_X1_1:
1131	case WM8958_MBC_BAND_1_X1_2:
1132	case WM8958_MBC_BAND_1_X2_1:
1133	case WM8958_MBC_BAND_1_X2_2:
1134	case WM8958_MBC_BAND_1_X3_1:
1135	case WM8958_MBC_BAND_1_X3_2:
1136	case WM8958_MBC_BAND_1_ATTACK_1:
1137	case WM8958_MBC_BAND_1_ATTACK_2:
1138	case WM8958_MBC_BAND_1_DECAY_1:
1139	case WM8958_MBC_BAND_1_DECAY_2:
1140	case WM8958_MBC_BAND_2_K_1:
1141	case WM8958_MBC_BAND_2_K_2:
1142	case WM8958_MBC_BAND_2_N1_1:
1143	case WM8958_MBC_BAND_2_N1_2:
1144	case WM8958_MBC_BAND_2_N2_1:
1145	case WM8958_MBC_BAND_2_N2_2:
1146	case WM8958_MBC_BAND_2_N3_1:
1147	case WM8958_MBC_BAND_2_N3_2:
1148	case WM8958_MBC_BAND_2_N4_1:
1149	case WM8958_MBC_BAND_2_N4_2:
1150	case WM8958_MBC_BAND_2_N5_1:
1151	case WM8958_MBC_BAND_2_N5_2:
1152	case WM8958_MBC_BAND_2_X1_1:
1153	case WM8958_MBC_BAND_2_X1_2:
1154	case WM8958_MBC_BAND_2_X2_1:
1155	case WM8958_MBC_BAND_2_X2_2:
1156	case WM8958_MBC_BAND_2_X3_1:
1157	case WM8958_MBC_BAND_2_X3_2:
1158	case WM8958_MBC_BAND_2_ATTACK_1:
1159	case WM8958_MBC_BAND_2_ATTACK_2:
1160	case WM8958_MBC_BAND_2_DECAY_1:
1161	case WM8958_MBC_BAND_2_DECAY_2:
1162	case WM8958_MBC_B2_PG2_1:
1163	case WM8958_MBC_B2_PG2_2:
1164	case WM8958_MBC_B1_PG2_1:
1165	case WM8958_MBC_B1_PG2_2:
1166	case WM8958_MBC_CROSSOVER_1:
1167	case WM8958_MBC_CROSSOVER_2:
1168	case WM8958_MBC_HPF_1:
1169	case WM8958_MBC_HPF_2:
1170	case WM8958_MBC_LPF_1:
1171	case WM8958_MBC_LPF_2:
1172	case WM8958_MBC_RMS_LIMIT_1:
1173	case WM8958_MBC_RMS_LIMIT_2:
1174		return true;
1175	default:
1176		return wm8994_readable_register(dev, reg);
1177	}
1178}
1179
1180static bool wm8994_volatile_register(struct device *dev, unsigned int reg)
1181{
1182	switch (reg) {
1183	case WM8994_SOFTWARE_RESET:
1184	case WM8994_DC_SERVO_1:
1185	case WM8994_DC_SERVO_READBACK:
1186	case WM8994_RATE_STATUS:
1187	case WM8958_MIC_DETECT_3:
1188	case WM8994_DC_SERVO_4E:
1189	case WM8994_INTERRUPT_STATUS_1:
1190	case WM8994_INTERRUPT_STATUS_2:
1191		return true;
1192	default:
1193		return false;
1194	}
1195}
1196
1197static bool wm1811_volatile_register(struct device *dev, unsigned int reg)
1198{
1199	struct wm8994 *wm8994 = dev_get_drvdata(dev);
1200
1201	switch (reg) {
1202	case WM8994_GPIO_6:
1203		if (wm8994->cust_id > 1 || wm8994->revision > 1)
1204			return true;
1205		else
1206			return false;
1207	default:
1208		return wm8994_volatile_register(dev, reg);
1209	}
1210}
1211
1212static bool wm8958_volatile_register(struct device *dev, unsigned int reg)
1213{
1214	switch (reg) {
1215	case WM8958_DSP2_MAGICNUM:
1216	case WM8958_DSP2_RELEASEYEAR:
1217	case WM8958_DSP2_RELEASEMONTHDAY:
1218	case WM8958_DSP2_RELEASETIME:
1219	case WM8958_DSP2_VERMAJMIN:
1220	case WM8958_DSP2_VERBUILD:
1221	case WM8958_DSP2_EXECCONTROL:
1222	case WM8958_DSP2_SWVERSIONREG:
1223	case WM8958_DSP2_CONFIGXMEM:
1224	case WM8958_DSP2_CONFIGYMEM:
1225	case WM8958_DSP2_CONFIGZMEM:
1226	case WM8958_FW_BUILD_1:
1227	case WM8958_FW_BUILD_0:
1228	case WM8958_FW_ID_1:
1229	case WM8958_FW_ID_0:
1230	case WM8958_FW_MAJOR_1:
1231	case WM8958_FW_MAJOR_0:
1232	case WM8958_FW_MINOR_1:
1233	case WM8958_FW_MINOR_0:
1234	case WM8958_FW_PATCH_1:
1235	case WM8958_FW_PATCH_0:
1236		return true;
1237	default:
1238		return wm8994_volatile_register(dev, reg);
1239	}
1240}
1241
1242struct regmap_config wm1811_regmap_config = {
1243	.reg_bits = 16,
1244	.val_bits = 16,
1245
1246	.cache_type = REGCACHE_RBTREE,
1247
1248	.reg_defaults = wm1811_defaults,
1249	.num_reg_defaults = ARRAY_SIZE(wm1811_defaults),
1250
1251	.max_register = WM8994_MAX_REGISTER,
1252	.volatile_reg = wm1811_volatile_register,
1253	.readable_reg = wm1811_readable_register,
1254};
1255EXPORT_SYMBOL(wm1811_regmap_config);
1256
1257struct regmap_config wm8994_regmap_config = {
1258	.reg_bits = 16,
1259	.val_bits = 16,
1260
1261	.cache_type = REGCACHE_RBTREE,
1262
1263	.reg_defaults = wm8994_defaults,
1264	.num_reg_defaults = ARRAY_SIZE(wm8994_defaults),
1265
1266	.max_register = WM8994_MAX_REGISTER,
1267	.volatile_reg = wm8994_volatile_register,
1268	.readable_reg = wm8994_readable_register,
1269};
1270EXPORT_SYMBOL(wm8994_regmap_config);
1271
1272struct regmap_config wm8958_regmap_config = {
1273	.reg_bits = 16,
1274	.val_bits = 16,
1275
1276	.cache_type = REGCACHE_RBTREE,
1277
1278	.reg_defaults = wm8958_defaults,
1279	.num_reg_defaults = ARRAY_SIZE(wm8958_defaults),
1280
1281	.max_register = WM8994_MAX_REGISTER,
1282	.volatile_reg = wm8958_volatile_register,
1283	.readable_reg = wm8958_readable_register,
1284};
1285EXPORT_SYMBOL(wm8958_regmap_config);
1286
1287struct regmap_config wm8994_base_regmap_config = {
1288	.reg_bits = 16,
1289	.val_bits = 16,
1290};
1291EXPORT_SYMBOL(wm8994_base_regmap_config);