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1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "radeon.h"
26#include "radeon_asic.h"
27#include "sid.h"
28#include "r600_dpm.h"
29#include "si_dpm.h"
30#include "atom.h"
31#include <linux/math64.h>
32#include <linux/seq_file.h>
33
34#define MC_CG_ARB_FREQ_F0 0x0a
35#define MC_CG_ARB_FREQ_F1 0x0b
36#define MC_CG_ARB_FREQ_F2 0x0c
37#define MC_CG_ARB_FREQ_F3 0x0d
38
39#define SMC_RAM_END 0x20000
40
41#define SCLK_MIN_DEEPSLEEP_FREQ 1350
42
43static const struct si_cac_config_reg cac_weights_tahiti[] =
44{
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
105 { 0xFFFFFFFF }
106};
107
108static const struct si_cac_config_reg lcac_tahiti[] =
109{
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
196 { 0xFFFFFFFF }
197
198};
199
200static const struct si_cac_config_reg cac_override_tahiti[] =
201{
202 { 0xFFFFFFFF }
203};
204
205static const struct si_powertune_data powertune_data_tahiti =
206{
207 ((1 << 16) | 27027),
208 6,
209 0,
210 4,
211 95,
212 {
213 0UL,
214 0UL,
215 4521550UL,
216 309631529UL,
217 -1270850L,
218 4513710L,
219 40
220 },
221 595000000UL,
222 12,
223 {
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0,
231 0
232 },
233 true
234};
235
236static const struct si_dte_data dte_data_tahiti =
237{
238 { 1159409, 0, 0, 0, 0 },
239 { 777, 0, 0, 0, 0 },
240 2,
241 54000,
242 127000,
243 25,
244 2,
245 10,
246 13,
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
250 85,
251 false
252};
253
254static const struct si_dte_data dte_data_tahiti_le =
255{
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
258 0x5,
259 0xAFC8,
260 0x64,
261 0x32,
262 1,
263 0,
264 0x10,
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
268 85,
269 true
270};
271
272static const struct si_dte_data dte_data_tahiti_pro =
273{
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
276 5,
277 45000,
278 100,
279 0xA,
280 1,
281 0,
282 0x10,
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
286 90,
287 true
288};
289
290static const struct si_dte_data dte_data_new_zealand =
291{
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
294 0x5,
295 0xAFC8,
296 0x69,
297 0x32,
298 1,
299 0,
300 0x10,
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
304 85,
305 true
306};
307
308static const struct si_dte_data dte_data_aruba_pro =
309{
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
312 5,
313 45000,
314 100,
315 0xA,
316 1,
317 0,
318 0x10,
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
322 90,
323 true
324};
325
326static const struct si_dte_data dte_data_malta =
327{
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
330 5,
331 45000,
332 100,
333 0xA,
334 1,
335 0,
336 0x10,
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
340 90,
341 true
342};
343
344struct si_cac_config_reg cac_weights_pitcairn[] =
345{
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
406 { 0xFFFFFFFF }
407};
408
409static const struct si_cac_config_reg lcac_pitcairn[] =
410{
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498};
499
500static const struct si_cac_config_reg cac_override_pitcairn[] =
501{
502 { 0xFFFFFFFF }
503};
504
505static const struct si_powertune_data powertune_data_pitcairn =
506{
507 ((1 << 16) | 27027),
508 5,
509 0,
510 6,
511 100,
512 {
513 51600000UL,
514 1800000UL,
515 7194395UL,
516 309631529UL,
517 -1270850L,
518 4513710L,
519 100
520 },
521 117830498UL,
522 12,
523 {
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0,
531 0
532 },
533 true
534};
535
536static const struct si_dte_data dte_data_pitcairn =
537{
538 { 0, 0, 0, 0, 0 },
539 { 0, 0, 0, 0, 0 },
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 0,
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
550 0,
551 false
552};
553
554static const struct si_dte_data dte_data_curacao_xt =
555{
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
558 5,
559 45000,
560 100,
561 0xA,
562 1,
563 0,
564 0x10,
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
568 90,
569 true
570};
571
572static const struct si_dte_data dte_data_curacao_pro =
573{
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
576 5,
577 45000,
578 100,
579 0xA,
580 1,
581 0,
582 0x10,
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
586 90,
587 true
588};
589
590static const struct si_dte_data dte_data_neptune_xt =
591{
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
594 5,
595 45000,
596 100,
597 0xA,
598 1,
599 0,
600 0x10,
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
604 90,
605 true
606};
607
608static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
609{
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
670 { 0xFFFFFFFF }
671};
672
673static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
674{
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
735 { 0xFFFFFFFF }
736};
737
738static const struct si_cac_config_reg cac_weights_heathrow[] =
739{
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
800 { 0xFFFFFFFF }
801};
802
803static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
804{
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
865 { 0xFFFFFFFF }
866};
867
868static const struct si_cac_config_reg cac_weights_cape_verde[] =
869{
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
930 { 0xFFFFFFFF }
931};
932
933static const struct si_cac_config_reg lcac_cape_verde[] =
934{
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
989 { 0xFFFFFFFF }
990};
991
992static const struct si_cac_config_reg cac_override_cape_verde[] =
993{
994 { 0xFFFFFFFF }
995};
996
997static const struct si_powertune_data powertune_data_cape_verde =
998{
999 ((1 << 16) | 0x6993),
1000 5,
1001 0,
1002 7,
1003 105,
1004 {
1005 0UL,
1006 0UL,
1007 7194395UL,
1008 309631529UL,
1009 -1270850L,
1010 4513710L,
1011 100
1012 },
1013 117830498UL,
1014 12,
1015 {
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0,
1023 0
1024 },
1025 true
1026};
1027
1028static const struct si_dte_data dte_data_cape_verde =
1029{
1030 { 0, 0, 0, 0, 0 },
1031 { 0, 0, 0, 0, 0 },
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 0,
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042 0,
1043 false
1044};
1045
1046static const struct si_dte_data dte_data_venus_xtx =
1047{
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050 5,
1051 55000,
1052 0x69,
1053 0xA,
1054 1,
1055 0,
1056 0x3,
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060 90,
1061 true
1062};
1063
1064static const struct si_dte_data dte_data_venus_xt =
1065{
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068 5,
1069 55000,
1070 0x69,
1071 0xA,
1072 1,
1073 0,
1074 0x3,
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078 90,
1079 true
1080};
1081
1082static const struct si_dte_data dte_data_venus_pro =
1083{
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086 5,
1087 55000,
1088 0x69,
1089 0xA,
1090 1,
1091 0,
1092 0x3,
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096 90,
1097 true
1098};
1099
1100struct si_cac_config_reg cac_weights_oland[] =
1101{
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162 { 0xFFFFFFFF }
1163};
1164
1165static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166{
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227 { 0xFFFFFFFF }
1228};
1229
1230static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231{
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292 { 0xFFFFFFFF }
1293};
1294
1295static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296{
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357 { 0xFFFFFFFF }
1358};
1359
1360static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361{
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422 { 0xFFFFFFFF }
1423};
1424
1425static const struct si_cac_config_reg lcac_oland[] =
1426{
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469 { 0xFFFFFFFF }
1470};
1471
1472static const struct si_cac_config_reg lcac_mars_pro[] =
1473{
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516 { 0xFFFFFFFF }
1517};
1518
1519static const struct si_cac_config_reg cac_override_oland[] =
1520{
1521 { 0xFFFFFFFF }
1522};
1523
1524static const struct si_powertune_data powertune_data_oland =
1525{
1526 ((1 << 16) | 0x6993),
1527 5,
1528 0,
1529 7,
1530 105,
1531 {
1532 0UL,
1533 0UL,
1534 7194395UL,
1535 309631529UL,
1536 -1270850L,
1537 4513710L,
1538 100
1539 },
1540 117830498UL,
1541 12,
1542 {
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0,
1550 0
1551 },
1552 true
1553};
1554
1555static const struct si_powertune_data powertune_data_mars_pro =
1556{
1557 ((1 << 16) | 0x6993),
1558 5,
1559 0,
1560 7,
1561 105,
1562 {
1563 0UL,
1564 0UL,
1565 7194395UL,
1566 309631529UL,
1567 -1270850L,
1568 4513710L,
1569 100
1570 },
1571 117830498UL,
1572 12,
1573 {
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0,
1581 0
1582 },
1583 true
1584};
1585
1586static const struct si_dte_data dte_data_oland =
1587{
1588 { 0, 0, 0, 0, 0 },
1589 { 0, 0, 0, 0, 0 },
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 0,
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600 0,
1601 false
1602};
1603
1604static const struct si_dte_data dte_data_mars_pro =
1605{
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608 5,
1609 55000,
1610 105,
1611 0xA,
1612 1,
1613 0,
1614 0x10,
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618 90,
1619 true
1620};
1621
1622static const struct si_dte_data dte_data_sun_xt =
1623{
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626 5,
1627 55000,
1628 105,
1629 0xA,
1630 1,
1631 0,
1632 0x10,
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636 90,
1637 true
1638};
1639
1640
1641static const struct si_cac_config_reg cac_weights_hainan[] =
1642{
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703 { 0xFFFFFFFF }
1704};
1705
1706static const struct si_powertune_data powertune_data_hainan =
1707{
1708 ((1 << 16) | 0x6993),
1709 5,
1710 0,
1711 9,
1712 105,
1713 {
1714 0UL,
1715 0UL,
1716 7194395UL,
1717 309631529UL,
1718 -1270850L,
1719 4513710L,
1720 100
1721 },
1722 117830498UL,
1723 12,
1724 {
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0,
1732 0
1733 },
1734 true
1735};
1736
1737struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742extern int si_mc_load_microcode(struct radeon_device *rdev);
1743extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1744
1745static int si_populate_voltage_value(struct radeon_device *rdev,
1746 const struct atom_voltage_table *table,
1747 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748static int si_get_std_voltage_value(struct radeon_device *rdev,
1749 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750 u16 *std_voltage);
1751static int si_write_smc_soft_register(struct radeon_device *rdev,
1752 u16 reg_offset, u32 value);
1753static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754 struct rv7xx_pl *pl,
1755 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756static int si_calculate_sclk_params(struct radeon_device *rdev,
1757 u32 engine_clock,
1758 SISLANDS_SMC_SCLK_VALUE *sclk);
1759
1760static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762
1763static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764{
1765 struct si_power_info *pi = rdev->pm.dpm.priv;
1766
1767 return pi;
1768}
1769
1770static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771 u16 v, s32 t, u32 ileakage, u32 *leakage)
1772{
1773 s64 kt, kv, leakage_w, i_leakage, vddc;
1774 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775 s64 tmp;
1776
1777 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778 vddc = div64_s64(drm_int2fixp(v), 1000);
1779 temperature = div64_s64(drm_int2fixp(t), 1000);
1780
1781 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785 t_ref = drm_int2fixp(coeff->t_ref);
1786
1787 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791
1792 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793
1794 *leakage = drm_fixp2int(leakage_w * 1000);
1795}
1796
1797static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798 const struct ni_leakage_coeffients *coeff,
1799 u16 v,
1800 s32 t,
1801 u32 i_leakage,
1802 u32 *leakage)
1803{
1804 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805}
1806
1807static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808 const u32 fixed_kt, u16 v,
1809 u32 ileakage, u32 *leakage)
1810{
1811 s64 kt, kv, leakage_w, i_leakage, vddc;
1812
1813 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814 vddc = div64_s64(drm_int2fixp(v), 1000);
1815
1816 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819
1820 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821
1822 *leakage = drm_fixp2int(leakage_w * 1000);
1823}
1824
1825static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826 const struct ni_leakage_coeffients *coeff,
1827 const u32 fixed_kt,
1828 u16 v,
1829 u32 i_leakage,
1830 u32 *leakage)
1831{
1832 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833}
1834
1835
1836static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837 struct si_dte_data *dte_data)
1838{
1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841 u32 k = dte_data->k;
1842 u32 t_max = dte_data->max_t;
1843 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844 u32 t_0 = dte_data->t0;
1845 u32 i;
1846
1847 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848 dte_data->tdep_count = 3;
1849
1850 for (i = 0; i < k; i++) {
1851 dte_data->r[i] =
1852 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853 (p_limit2 * (u32)100);
1854 }
1855
1856 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857
1858 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859 dte_data->tdep_r[i] = dte_data->r[4];
1860 }
1861 } else {
1862 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863 }
1864}
1865
1866static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867{
1868 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869 struct si_power_info *si_pi = si_get_pi(rdev);
1870 bool update_dte_from_pl2 = false;
1871
1872 if (rdev->family == CHIP_TAHITI) {
1873 si_pi->cac_weights = cac_weights_tahiti;
1874 si_pi->lcac_config = lcac_tahiti;
1875 si_pi->cac_override = cac_override_tahiti;
1876 si_pi->powertune_data = &powertune_data_tahiti;
1877 si_pi->dte_data = dte_data_tahiti;
1878
1879 switch (rdev->pdev->device) {
1880 case 0x6798:
1881 si_pi->dte_data.enable_dte_by_default = true;
1882 break;
1883 case 0x6799:
1884 si_pi->dte_data = dte_data_new_zealand;
1885 break;
1886 case 0x6790:
1887 case 0x6791:
1888 case 0x6792:
1889 case 0x679E:
1890 si_pi->dte_data = dte_data_aruba_pro;
1891 update_dte_from_pl2 = true;
1892 break;
1893 case 0x679B:
1894 si_pi->dte_data = dte_data_malta;
1895 update_dte_from_pl2 = true;
1896 break;
1897 case 0x679A:
1898 si_pi->dte_data = dte_data_tahiti_pro;
1899 update_dte_from_pl2 = true;
1900 break;
1901 default:
1902 if (si_pi->dte_data.enable_dte_by_default == true)
1903 DRM_ERROR("DTE is not enabled!\n");
1904 break;
1905 }
1906 } else if (rdev->family == CHIP_PITCAIRN) {
1907 switch (rdev->pdev->device) {
1908 case 0x6810:
1909 case 0x6818:
1910 si_pi->cac_weights = cac_weights_pitcairn;
1911 si_pi->lcac_config = lcac_pitcairn;
1912 si_pi->cac_override = cac_override_pitcairn;
1913 si_pi->powertune_data = &powertune_data_pitcairn;
1914 si_pi->dte_data = dte_data_curacao_xt;
1915 update_dte_from_pl2 = true;
1916 break;
1917 case 0x6819:
1918 case 0x6811:
1919 si_pi->cac_weights = cac_weights_pitcairn;
1920 si_pi->lcac_config = lcac_pitcairn;
1921 si_pi->cac_override = cac_override_pitcairn;
1922 si_pi->powertune_data = &powertune_data_pitcairn;
1923 si_pi->dte_data = dte_data_curacao_pro;
1924 update_dte_from_pl2 = true;
1925 break;
1926 case 0x6800:
1927 case 0x6806:
1928 si_pi->cac_weights = cac_weights_pitcairn;
1929 si_pi->lcac_config = lcac_pitcairn;
1930 si_pi->cac_override = cac_override_pitcairn;
1931 si_pi->powertune_data = &powertune_data_pitcairn;
1932 si_pi->dte_data = dte_data_neptune_xt;
1933 update_dte_from_pl2 = true;
1934 break;
1935 default:
1936 si_pi->cac_weights = cac_weights_pitcairn;
1937 si_pi->lcac_config = lcac_pitcairn;
1938 si_pi->cac_override = cac_override_pitcairn;
1939 si_pi->powertune_data = &powertune_data_pitcairn;
1940 si_pi->dte_data = dte_data_pitcairn;
1941 break;
1942 }
1943 } else if (rdev->family == CHIP_VERDE) {
1944 si_pi->lcac_config = lcac_cape_verde;
1945 si_pi->cac_override = cac_override_cape_verde;
1946 si_pi->powertune_data = &powertune_data_cape_verde;
1947
1948 switch (rdev->pdev->device) {
1949 case 0x683B:
1950 case 0x683F:
1951 case 0x6829:
1952 case 0x6835:
1953 si_pi->cac_weights = cac_weights_cape_verde_pro;
1954 si_pi->dte_data = dte_data_cape_verde;
1955 break;
1956 case 0x682C:
1957 si_pi->cac_weights = cac_weights_cape_verde_pro;
1958 si_pi->dte_data = dte_data_sun_xt;
1959 break;
1960 case 0x6825:
1961 case 0x6827:
1962 si_pi->cac_weights = cac_weights_heathrow;
1963 si_pi->dte_data = dte_data_cape_verde;
1964 break;
1965 case 0x6824:
1966 case 0x682D:
1967 si_pi->cac_weights = cac_weights_chelsea_xt;
1968 si_pi->dte_data = dte_data_cape_verde;
1969 break;
1970 case 0x682F:
1971 si_pi->cac_weights = cac_weights_chelsea_pro;
1972 si_pi->dte_data = dte_data_cape_verde;
1973 break;
1974 case 0x6820:
1975 si_pi->cac_weights = cac_weights_heathrow;
1976 si_pi->dte_data = dte_data_venus_xtx;
1977 break;
1978 case 0x6821:
1979 si_pi->cac_weights = cac_weights_heathrow;
1980 si_pi->dte_data = dte_data_venus_xt;
1981 break;
1982 case 0x6823:
1983 case 0x682B:
1984 case 0x6822:
1985 case 0x682A:
1986 si_pi->cac_weights = cac_weights_chelsea_pro;
1987 si_pi->dte_data = dte_data_venus_pro;
1988 break;
1989 default:
1990 si_pi->cac_weights = cac_weights_cape_verde;
1991 si_pi->dte_data = dte_data_cape_verde;
1992 break;
1993 }
1994 } else if (rdev->family == CHIP_OLAND) {
1995 switch (rdev->pdev->device) {
1996 case 0x6601:
1997 case 0x6621:
1998 case 0x6603:
1999 case 0x6605:
2000 si_pi->cac_weights = cac_weights_mars_pro;
2001 si_pi->lcac_config = lcac_mars_pro;
2002 si_pi->cac_override = cac_override_oland;
2003 si_pi->powertune_data = &powertune_data_mars_pro;
2004 si_pi->dte_data = dte_data_mars_pro;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x6600:
2008 case 0x6606:
2009 case 0x6620:
2010 case 0x6604:
2011 si_pi->cac_weights = cac_weights_mars_xt;
2012 si_pi->lcac_config = lcac_mars_pro;
2013 si_pi->cac_override = cac_override_oland;
2014 si_pi->powertune_data = &powertune_data_mars_pro;
2015 si_pi->dte_data = dte_data_mars_pro;
2016 update_dte_from_pl2 = true;
2017 break;
2018 case 0x6611:
2019 case 0x6613:
2020 case 0x6608:
2021 si_pi->cac_weights = cac_weights_oland_pro;
2022 si_pi->lcac_config = lcac_mars_pro;
2023 si_pi->cac_override = cac_override_oland;
2024 si_pi->powertune_data = &powertune_data_mars_pro;
2025 si_pi->dte_data = dte_data_mars_pro;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6610:
2029 si_pi->cac_weights = cac_weights_oland_xt;
2030 si_pi->lcac_config = lcac_mars_pro;
2031 si_pi->cac_override = cac_override_oland;
2032 si_pi->powertune_data = &powertune_data_mars_pro;
2033 si_pi->dte_data = dte_data_mars_pro;
2034 update_dte_from_pl2 = true;
2035 break;
2036 default:
2037 si_pi->cac_weights = cac_weights_oland;
2038 si_pi->lcac_config = lcac_oland;
2039 si_pi->cac_override = cac_override_oland;
2040 si_pi->powertune_data = &powertune_data_oland;
2041 si_pi->dte_data = dte_data_oland;
2042 break;
2043 }
2044 } else if (rdev->family == CHIP_HAINAN) {
2045 si_pi->cac_weights = cac_weights_hainan;
2046 si_pi->lcac_config = lcac_oland;
2047 si_pi->cac_override = cac_override_oland;
2048 si_pi->powertune_data = &powertune_data_hainan;
2049 si_pi->dte_data = dte_data_sun_xt;
2050 update_dte_from_pl2 = true;
2051 } else {
2052 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2053 return;
2054 }
2055
2056 ni_pi->enable_power_containment = false;
2057 ni_pi->enable_cac = false;
2058 ni_pi->enable_sq_ramping = false;
2059 si_pi->enable_dte = false;
2060
2061 if (si_pi->powertune_data->enable_powertune_by_default) {
2062 ni_pi->enable_power_containment= true;
2063 ni_pi->enable_cac = true;
2064 if (si_pi->dte_data.enable_dte_by_default) {
2065 si_pi->enable_dte = true;
2066 if (update_dte_from_pl2)
2067 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2068
2069 }
2070 ni_pi->enable_sq_ramping = true;
2071 }
2072
2073 ni_pi->driver_calculate_cac_leakage = true;
2074 ni_pi->cac_configuration_required = true;
2075
2076 if (ni_pi->cac_configuration_required) {
2077 ni_pi->support_cac_long_term_average = true;
2078 si_pi->dyn_powertune_data.l2_lta_window_size =
2079 si_pi->powertune_data->l2_lta_window_size_default;
2080 si_pi->dyn_powertune_data.lts_truncate =
2081 si_pi->powertune_data->lts_truncate_default;
2082 } else {
2083 ni_pi->support_cac_long_term_average = false;
2084 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085 si_pi->dyn_powertune_data.lts_truncate = 0;
2086 }
2087
2088 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2089}
2090
2091static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2092{
2093 return 1;
2094}
2095
2096static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2097{
2098 u32 xclk;
2099 u32 wintime;
2100 u32 cac_window;
2101 u32 cac_window_size;
2102
2103 xclk = radeon_get_xclk(rdev);
2104
2105 if (xclk == 0)
2106 return 0;
2107
2108 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110
2111 wintime = (cac_window_size * 100) / xclk;
2112
2113 return wintime;
2114}
2115
2116static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117{
2118 return power_in_watts;
2119}
2120
2121static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122 bool adjust_polarity,
2123 u32 tdp_adjustment,
2124 u32 *tdp_limit,
2125 u32 *near_tdp_limit)
2126{
2127 u32 adjustment_delta, max_tdp_limit;
2128
2129 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2130 return -EINVAL;
2131
2132 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133
2134 if (adjust_polarity) {
2135 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137 } else {
2138 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142 else
2143 *near_tdp_limit = 0;
2144 }
2145
2146 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147 return -EINVAL;
2148 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2149 return -EINVAL;
2150
2151 return 0;
2152}
2153
2154static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155 struct radeon_ps *radeon_state)
2156{
2157 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158 struct si_power_info *si_pi = si_get_pi(rdev);
2159
2160 if (ni_pi->enable_power_containment) {
2161 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162 PP_SIslands_PAPMParameters *papm_parm;
2163 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2165 u32 tdp_limit;
2166 u32 near_tdp_limit;
2167 int ret;
2168
2169 if (scaling_factor == 0)
2170 return -EINVAL;
2171
2172 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173
2174 ret = si_calculate_adjusted_tdp_limits(rdev,
2175 false, /* ??? */
2176 rdev->pm.dpm.tdp_adjustment,
2177 &tdp_limit,
2178 &near_tdp_limit);
2179 if (ret)
2180 return ret;
2181
2182 smc_table->dpm2Params.TDPLimit =
2183 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184 smc_table->dpm2Params.NearTDPLimit =
2185 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186 smc_table->dpm2Params.SafePowerLimit =
2187 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188
2189 ret = si_copy_bytes_to_smc(rdev,
2190 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2193 sizeof(u32) * 3,
2194 si_pi->sram_end);
2195 if (ret)
2196 return ret;
2197
2198 if (si_pi->enable_ppm) {
2199 papm_parm = &si_pi->papm_parm;
2200 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205 papm_parm->PlatformPowerLimit = 0xffffffff;
2206 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207
2208 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209 (u8 *)papm_parm,
2210 sizeof(PP_SIslands_PAPMParameters),
2211 si_pi->sram_end);
2212 if (ret)
2213 return ret;
2214 }
2215 }
2216 return 0;
2217}
2218
2219static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220 struct radeon_ps *radeon_state)
2221{
2222 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223 struct si_power_info *si_pi = si_get_pi(rdev);
2224
2225 if (ni_pi->enable_power_containment) {
2226 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2228 int ret;
2229
2230 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231
2232 smc_table->dpm2Params.NearTDPLimit =
2233 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234 smc_table->dpm2Params.SafePowerLimit =
2235 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236
2237 ret = si_copy_bytes_to_smc(rdev,
2238 (si_pi->state_table_start +
2239 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2242 sizeof(u32) * 2,
2243 si_pi->sram_end);
2244 if (ret)
2245 return ret;
2246 }
2247
2248 return 0;
2249}
2250
2251static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252 const u16 prev_std_vddc,
2253 const u16 curr_std_vddc)
2254{
2255 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256 u64 prev_vddc = (u64)prev_std_vddc;
2257 u64 curr_vddc = (u64)curr_std_vddc;
2258 u64 pwr_efficiency_ratio, n, d;
2259
2260 if ((prev_vddc == 0) || (curr_vddc == 0))
2261 return 0;
2262
2263 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264 d = prev_vddc * prev_vddc;
2265 pwr_efficiency_ratio = div64_u64(n, d);
2266
2267 if (pwr_efficiency_ratio > (u64)0xFFFF)
2268 return 0;
2269
2270 return (u16)pwr_efficiency_ratio;
2271}
2272
2273static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274 struct radeon_ps *radeon_state)
2275{
2276 struct si_power_info *si_pi = si_get_pi(rdev);
2277
2278 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279 radeon_state->vclk && radeon_state->dclk)
2280 return true;
2281
2282 return false;
2283}
2284
2285static int si_populate_power_containment_values(struct radeon_device *rdev,
2286 struct radeon_ps *radeon_state,
2287 SISLANDS_SMC_SWSTATE *smc_state)
2288{
2289 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291 struct ni_ps *state = ni_get_ps(radeon_state);
2292 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2293 u32 prev_sclk;
2294 u32 max_sclk;
2295 u32 min_sclk;
2296 u16 prev_std_vddc;
2297 u16 curr_std_vddc;
2298 int i;
2299 u16 pwr_efficiency_ratio;
2300 u8 max_ps_percent;
2301 bool disable_uvd_power_tune;
2302 int ret;
2303
2304 if (ni_pi->enable_power_containment == false)
2305 return 0;
2306
2307 if (state->performance_level_count == 0)
2308 return -EINVAL;
2309
2310 if (smc_state->levelCount != state->performance_level_count)
2311 return -EINVAL;
2312
2313 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314
2315 smc_state->levels[0].dpm2.MaxPS = 0;
2316 smc_state->levels[0].dpm2.NearTDPDec = 0;
2317 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320
2321 for (i = 1; i < state->performance_level_count; i++) {
2322 prev_sclk = state->performance_levels[i-1].sclk;
2323 max_sclk = state->performance_levels[i].sclk;
2324 if (i == 1)
2325 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326 else
2327 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328
2329 if (prev_sclk > max_sclk)
2330 return -EINVAL;
2331
2332 if ((max_ps_percent == 0) ||
2333 (prev_sclk == max_sclk) ||
2334 disable_uvd_power_tune) {
2335 min_sclk = max_sclk;
2336 } else if (i == 1) {
2337 min_sclk = prev_sclk;
2338 } else {
2339 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2340 }
2341
2342 if (min_sclk < state->performance_levels[0].sclk)
2343 min_sclk = state->performance_levels[0].sclk;
2344
2345 if (min_sclk == 0)
2346 return -EINVAL;
2347
2348 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349 state->performance_levels[i-1].vddc, &vddc);
2350 if (ret)
2351 return ret;
2352
2353 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2354 if (ret)
2355 return ret;
2356
2357 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358 state->performance_levels[i].vddc, &vddc);
2359 if (ret)
2360 return ret;
2361
2362 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2363 if (ret)
2364 return ret;
2365
2366 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367 prev_std_vddc, curr_std_vddc);
2368
2369 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2374 }
2375
2376 return 0;
2377}
2378
2379static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380 struct radeon_ps *radeon_state,
2381 SISLANDS_SMC_SWSTATE *smc_state)
2382{
2383 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384 struct ni_ps *state = ni_get_ps(radeon_state);
2385 u32 sq_power_throttle, sq_power_throttle2;
2386 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2387 int i;
2388
2389 if (state->performance_level_count == 0)
2390 return -EINVAL;
2391
2392 if (smc_state->levelCount != state->performance_level_count)
2393 return -EINVAL;
2394
2395 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2396 return -EINVAL;
2397
2398 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399 enable_sq_ramping = false;
2400
2401 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402 enable_sq_ramping = false;
2403
2404 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405 enable_sq_ramping = false;
2406
2407 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408 enable_sq_ramping = false;
2409
2410 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411 enable_sq_ramping = false;
2412
2413 for (i = 0; i < state->performance_level_count; i++) {
2414 sq_power_throttle = 0;
2415 sq_power_throttle2 = 0;
2416
2417 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418 enable_sq_ramping) {
2419 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424 } else {
2425 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2427 }
2428
2429 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2431 }
2432
2433 return 0;
2434}
2435
2436static int si_enable_power_containment(struct radeon_device *rdev,
2437 struct radeon_ps *radeon_new_state,
2438 bool enable)
2439{
2440 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441 PPSMC_Result smc_result;
2442 int ret = 0;
2443
2444 if (ni_pi->enable_power_containment) {
2445 if (enable) {
2446 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448 if (smc_result != PPSMC_Result_OK) {
2449 ret = -EINVAL;
2450 ni_pi->pc_enabled = false;
2451 } else {
2452 ni_pi->pc_enabled = true;
2453 }
2454 }
2455 } else {
2456 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457 if (smc_result != PPSMC_Result_OK)
2458 ret = -EINVAL;
2459 ni_pi->pc_enabled = false;
2460 }
2461 }
2462
2463 return ret;
2464}
2465
2466static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467{
2468 struct si_power_info *si_pi = si_get_pi(rdev);
2469 int ret = 0;
2470 struct si_dte_data *dte_data = &si_pi->dte_data;
2471 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2472 u32 table_size;
2473 u8 tdep_count;
2474 u32 i;
2475
2476 if (dte_data == NULL)
2477 si_pi->enable_dte = false;
2478
2479 if (si_pi->enable_dte == false)
2480 return 0;
2481
2482 if (dte_data->k <= 0)
2483 return -EINVAL;
2484
2485 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486 if (dte_tables == NULL) {
2487 si_pi->enable_dte = false;
2488 return -ENOMEM;
2489 }
2490
2491 table_size = dte_data->k;
2492
2493 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495
2496 tdep_count = dte_data->tdep_count;
2497 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499
2500 dte_tables->K = cpu_to_be32(table_size);
2501 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503 dte_tables->WindowSize = dte_data->window_size;
2504 dte_tables->temp_select = dte_data->temp_select;
2505 dte_tables->DTE_mode = dte_data->dte_mode;
2506 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2507
2508 if (tdep_count > 0)
2509 table_size--;
2510
2511 for (i = 0; i < table_size; i++) {
2512 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2514 }
2515
2516 dte_tables->Tdep_count = tdep_count;
2517
2518 for (i = 0; i < (u32)tdep_count; i++) {
2519 dte_tables->T_limits[i] = dte_data->t_limits[i];
2520 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2522 }
2523
2524 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2526 kfree(dte_tables);
2527
2528 return ret;
2529}
2530
2531static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2532 u16 *max, u16 *min)
2533{
2534 struct si_power_info *si_pi = si_get_pi(rdev);
2535 struct radeon_cac_leakage_table *table =
2536 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2537 u32 i;
2538 u32 v0_loadline;
2539
2540
2541 if (table == NULL)
2542 return -EINVAL;
2543
2544 *max = 0;
2545 *min = 0xFFFF;
2546
2547 for (i = 0; i < table->count; i++) {
2548 if (table->entries[i].vddc > *max)
2549 *max = table->entries[i].vddc;
2550 if (table->entries[i].vddc < *min)
2551 *min = table->entries[i].vddc;
2552 }
2553
2554 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2555 return -EINVAL;
2556
2557 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558
2559 if (v0_loadline > 0xFFFFUL)
2560 return -EINVAL;
2561
2562 *min = (u16)v0_loadline;
2563
2564 if ((*min > *max) || (*max == 0) || (*min == 0))
2565 return -EINVAL;
2566
2567 return 0;
2568}
2569
2570static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571{
2572 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2574}
2575
2576static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577 PP_SIslands_CacConfig *cac_tables,
2578 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2579 u16 t0, u16 t_step)
2580{
2581 struct si_power_info *si_pi = si_get_pi(rdev);
2582 u32 leakage;
2583 unsigned int i, j;
2584 s32 t;
2585 u32 smc_leakage;
2586 u32 scaling_factor;
2587 u16 voltage;
2588
2589 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590
2591 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592 t = (1000 * (i * t_step + t0));
2593
2594 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595 voltage = vddc_max - (vddc_step * j);
2596
2597 si_calculate_leakage_for_v_and_t(rdev,
2598 &si_pi->powertune_data->leakage_coefficients,
2599 voltage,
2600 t,
2601 si_pi->dyn_powertune_data.cac_leakage,
2602 &leakage);
2603
2604 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605
2606 if (smc_leakage > 0xFFFF)
2607 smc_leakage = 0xFFFF;
2608
2609 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610 cpu_to_be16((u16)smc_leakage);
2611 }
2612 }
2613 return 0;
2614}
2615
2616static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617 PP_SIslands_CacConfig *cac_tables,
2618 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619{
2620 struct si_power_info *si_pi = si_get_pi(rdev);
2621 u32 leakage;
2622 unsigned int i, j;
2623 u32 smc_leakage;
2624 u32 scaling_factor;
2625 u16 voltage;
2626
2627 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628
2629 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630 voltage = vddc_max - (vddc_step * j);
2631
2632 si_calculate_leakage_for_v(rdev,
2633 &si_pi->powertune_data->leakage_coefficients,
2634 si_pi->powertune_data->fixed_kt,
2635 voltage,
2636 si_pi->dyn_powertune_data.cac_leakage,
2637 &leakage);
2638
2639 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640
2641 if (smc_leakage > 0xFFFF)
2642 smc_leakage = 0xFFFF;
2643
2644 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646 cpu_to_be16((u16)smc_leakage);
2647 }
2648 return 0;
2649}
2650
2651static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652{
2653 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654 struct si_power_info *si_pi = si_get_pi(rdev);
2655 PP_SIslands_CacConfig *cac_tables = NULL;
2656 u16 vddc_max, vddc_min, vddc_step;
2657 u16 t0, t_step;
2658 u32 load_line_slope, reg;
2659 int ret = 0;
2660 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661
2662 if (ni_pi->enable_cac == false)
2663 return 0;
2664
2665 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2666 if (!cac_tables)
2667 return -ENOMEM;
2668
2669 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671 WREG32(CG_CAC_CTRL, reg);
2672
2673 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674 si_pi->dyn_powertune_data.dc_pwr_value =
2675 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678
2679 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680
2681 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2682 if (ret)
2683 goto done_free;
2684
2685 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2687 t_step = 4;
2688 t0 = 60;
2689
2690 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691 ret = si_init_dte_leakage_table(rdev, cac_tables,
2692 vddc_max, vddc_min, vddc_step,
2693 t0, t_step);
2694 else
2695 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696 vddc_max, vddc_min, vddc_step);
2697 if (ret)
2698 goto done_free;
2699
2700 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701
2702 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709 cac_tables->calculation_repeats = cpu_to_be32(2);
2710 cac_tables->dc_cac = cpu_to_be32(0);
2711 cac_tables->log2_PG_LKG_SCALE = 12;
2712 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715
2716 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2718
2719 if (ret)
2720 goto done_free;
2721
2722 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2723
2724done_free:
2725 if (ret) {
2726 ni_pi->enable_cac = false;
2727 ni_pi->enable_power_containment = false;
2728 }
2729
2730 kfree(cac_tables);
2731
2732 return 0;
2733}
2734
2735static int si_program_cac_config_registers(struct radeon_device *rdev,
2736 const struct si_cac_config_reg *cac_config_regs)
2737{
2738 const struct si_cac_config_reg *config_regs = cac_config_regs;
2739 u32 data = 0, offset;
2740
2741 if (!config_regs)
2742 return -EINVAL;
2743
2744 while (config_regs->offset != 0xFFFFFFFF) {
2745 switch (config_regs->type) {
2746 case SISLANDS_CACCONFIG_CGIND:
2747 offset = SMC_CG_IND_START + config_regs->offset;
2748 if (offset < SMC_CG_IND_END)
2749 data = RREG32_SMC(offset);
2750 break;
2751 default:
2752 data = RREG32(config_regs->offset << 2);
2753 break;
2754 }
2755
2756 data &= ~config_regs->mask;
2757 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758
2759 switch (config_regs->type) {
2760 case SISLANDS_CACCONFIG_CGIND:
2761 offset = SMC_CG_IND_START + config_regs->offset;
2762 if (offset < SMC_CG_IND_END)
2763 WREG32_SMC(offset, data);
2764 break;
2765 default:
2766 WREG32(config_regs->offset << 2, data);
2767 break;
2768 }
2769 config_regs++;
2770 }
2771 return 0;
2772}
2773
2774static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775{
2776 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777 struct si_power_info *si_pi = si_get_pi(rdev);
2778 int ret;
2779
2780 if ((ni_pi->enable_cac == false) ||
2781 (ni_pi->cac_configuration_required == false))
2782 return 0;
2783
2784 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2785 if (ret)
2786 return ret;
2787 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2788 if (ret)
2789 return ret;
2790 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2791 if (ret)
2792 return ret;
2793
2794 return 0;
2795}
2796
2797static int si_enable_smc_cac(struct radeon_device *rdev,
2798 struct radeon_ps *radeon_new_state,
2799 bool enable)
2800{
2801 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802 struct si_power_info *si_pi = si_get_pi(rdev);
2803 PPSMC_Result smc_result;
2804 int ret = 0;
2805
2806 if (ni_pi->enable_cac) {
2807 if (enable) {
2808 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809 if (ni_pi->support_cac_long_term_average) {
2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811 if (smc_result != PPSMC_Result_OK)
2812 ni_pi->support_cac_long_term_average = false;
2813 }
2814
2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816 if (smc_result != PPSMC_Result_OK) {
2817 ret = -EINVAL;
2818 ni_pi->cac_enabled = false;
2819 } else {
2820 ni_pi->cac_enabled = true;
2821 }
2822
2823 if (si_pi->enable_dte) {
2824 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825 if (smc_result != PPSMC_Result_OK)
2826 ret = -EINVAL;
2827 }
2828 }
2829 } else if (ni_pi->cac_enabled) {
2830 if (si_pi->enable_dte)
2831 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832
2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834
2835 ni_pi->cac_enabled = false;
2836
2837 if (ni_pi->support_cac_long_term_average)
2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2839 }
2840 }
2841 return ret;
2842}
2843
2844static int si_init_smc_spll_table(struct radeon_device *rdev)
2845{
2846 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847 struct si_power_info *si_pi = si_get_pi(rdev);
2848 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849 SISLANDS_SMC_SCLK_VALUE sclk_params;
2850 u32 fb_div, p_div;
2851 u32 clk_s, clk_v;
2852 u32 sclk = 0;
2853 int ret = 0;
2854 u32 tmp;
2855 int i;
2856
2857 if (si_pi->spll_table_start == 0)
2858 return -EINVAL;
2859
2860 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861 if (spll_table == NULL)
2862 return -ENOMEM;
2863
2864 for (i = 0; i < 256; i++) {
2865 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2866 if (ret)
2867 break;
2868
2869 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873
2874 fb_div &= ~0x00001FFF;
2875 fb_div >>= 1;
2876 clk_v >>= 6;
2877
2878 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879 ret = -EINVAL;
2880 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881 ret = -EINVAL;
2882 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883 ret = -EINVAL;
2884 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2885 ret = -EINVAL;
2886
2887 if (ret)
2888 break;
2889
2890 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892 spll_table->freq[i] = cpu_to_be32(tmp);
2893
2894 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896 spll_table->ss[i] = cpu_to_be32(tmp);
2897
2898 sclk += 512;
2899 }
2900
2901
2902 if (!ret)
2903 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2905 si_pi->sram_end);
2906
2907 if (ret)
2908 ni_pi->enable_power_containment = false;
2909
2910 kfree(spll_table);
2911
2912 return ret;
2913}
2914
2915struct si_dpm_quirk {
2916 u32 chip_vendor;
2917 u32 chip_device;
2918 u32 subsys_vendor;
2919 u32 subsys_device;
2920 u32 max_sclk;
2921 u32 max_mclk;
2922};
2923
2924/* cards with dpm stability problems */
2925static struct si_dpm_quirk si_dpm_quirk_list[] = {
2926 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2927 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2928 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2929 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2930 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2934 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
2935 { 0, 0, 0, 0 },
2936};
2937
2938static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2939 u16 vce_voltage)
2940{
2941 u16 highest_leakage = 0;
2942 struct si_power_info *si_pi = si_get_pi(rdev);
2943 int i;
2944
2945 for (i = 0; i < si_pi->leakage_voltage.count; i++){
2946 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2947 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2948 }
2949
2950 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2951 return highest_leakage;
2952
2953 return vce_voltage;
2954}
2955
2956static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2957 u32 evclk, u32 ecclk, u16 *voltage)
2958{
2959 u32 i;
2960 int ret = -EINVAL;
2961 struct radeon_vce_clock_voltage_dependency_table *table =
2962 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2963
2964 if (((evclk == 0) && (ecclk == 0)) ||
2965 (table && (table->count == 0))) {
2966 *voltage = 0;
2967 return 0;
2968 }
2969
2970 for (i = 0; i < table->count; i++) {
2971 if ((evclk <= table->entries[i].evclk) &&
2972 (ecclk <= table->entries[i].ecclk)) {
2973 *voltage = table->entries[i].v;
2974 ret = 0;
2975 break;
2976 }
2977 }
2978
2979 /* if no match return the highest voltage */
2980 if (ret)
2981 *voltage = table->entries[table->count - 1].v;
2982
2983 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2984
2985 return ret;
2986}
2987
2988static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2989 struct radeon_ps *rps)
2990{
2991 struct ni_ps *ps = ni_get_ps(rps);
2992 struct radeon_clock_and_voltage_limits *max_limits;
2993 bool disable_mclk_switching = false;
2994 bool disable_sclk_switching = false;
2995 u32 mclk, sclk;
2996 u16 vddc, vddci, min_vce_voltage = 0;
2997 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2998 u32 max_sclk = 0, max_mclk = 0;
2999 int i;
3000 struct si_dpm_quirk *p = si_dpm_quirk_list;
3001
3002 /* Apply dpm quirks */
3003 while (p && p->chip_device != 0) {
3004 if (rdev->pdev->vendor == p->chip_vendor &&
3005 rdev->pdev->device == p->chip_device &&
3006 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3007 rdev->pdev->subsystem_device == p->subsys_device) {
3008 max_sclk = p->max_sclk;
3009 max_mclk = p->max_mclk;
3010 break;
3011 }
3012 ++p;
3013 }
3014 /* limit mclk on all R7 370 parts for stability */
3015 if (rdev->pdev->device == 0x6811 &&
3016 rdev->pdev->revision == 0x81)
3017 max_mclk = 120000;
3018
3019 if (rps->vce_active) {
3020 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3021 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3022 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3023 &min_vce_voltage);
3024 } else {
3025 rps->evclk = 0;
3026 rps->ecclk = 0;
3027 }
3028
3029 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3030 ni_dpm_vblank_too_short(rdev))
3031 disable_mclk_switching = true;
3032
3033 if (rps->vclk || rps->dclk) {
3034 disable_mclk_switching = true;
3035 disable_sclk_switching = true;
3036 }
3037
3038 if (rdev->pm.dpm.ac_power)
3039 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3040 else
3041 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3042
3043 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3044 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3045 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3046 }
3047 if (rdev->pm.dpm.ac_power == false) {
3048 for (i = 0; i < ps->performance_level_count; i++) {
3049 if (ps->performance_levels[i].mclk > max_limits->mclk)
3050 ps->performance_levels[i].mclk = max_limits->mclk;
3051 if (ps->performance_levels[i].sclk > max_limits->sclk)
3052 ps->performance_levels[i].sclk = max_limits->sclk;
3053 if (ps->performance_levels[i].vddc > max_limits->vddc)
3054 ps->performance_levels[i].vddc = max_limits->vddc;
3055 if (ps->performance_levels[i].vddci > max_limits->vddci)
3056 ps->performance_levels[i].vddci = max_limits->vddci;
3057 }
3058 }
3059
3060 /* limit clocks to max supported clocks based on voltage dependency tables */
3061 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3062 &max_sclk_vddc);
3063 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3064 &max_mclk_vddci);
3065 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3066 &max_mclk_vddc);
3067
3068 for (i = 0; i < ps->performance_level_count; i++) {
3069 if (max_sclk_vddc) {
3070 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3071 ps->performance_levels[i].sclk = max_sclk_vddc;
3072 }
3073 if (max_mclk_vddci) {
3074 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3075 ps->performance_levels[i].mclk = max_mclk_vddci;
3076 }
3077 if (max_mclk_vddc) {
3078 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3079 ps->performance_levels[i].mclk = max_mclk_vddc;
3080 }
3081 if (max_mclk) {
3082 if (ps->performance_levels[i].mclk > max_mclk)
3083 ps->performance_levels[i].mclk = max_mclk;
3084 }
3085 if (max_sclk) {
3086 if (ps->performance_levels[i].sclk > max_sclk)
3087 ps->performance_levels[i].sclk = max_sclk;
3088 }
3089 }
3090
3091 /* XXX validate the min clocks required for display */
3092
3093 if (disable_mclk_switching) {
3094 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3095 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3096 } else {
3097 mclk = ps->performance_levels[0].mclk;
3098 vddci = ps->performance_levels[0].vddci;
3099 }
3100
3101 if (disable_sclk_switching) {
3102 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3103 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3104 } else {
3105 sclk = ps->performance_levels[0].sclk;
3106 vddc = ps->performance_levels[0].vddc;
3107 }
3108
3109 if (rps->vce_active) {
3110 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3111 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3112 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3113 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3114 }
3115
3116 /* adjusted low state */
3117 ps->performance_levels[0].sclk = sclk;
3118 ps->performance_levels[0].mclk = mclk;
3119 ps->performance_levels[0].vddc = vddc;
3120 ps->performance_levels[0].vddci = vddci;
3121
3122 if (disable_sclk_switching) {
3123 sclk = ps->performance_levels[0].sclk;
3124 for (i = 1; i < ps->performance_level_count; i++) {
3125 if (sclk < ps->performance_levels[i].sclk)
3126 sclk = ps->performance_levels[i].sclk;
3127 }
3128 for (i = 0; i < ps->performance_level_count; i++) {
3129 ps->performance_levels[i].sclk = sclk;
3130 ps->performance_levels[i].vddc = vddc;
3131 }
3132 } else {
3133 for (i = 1; i < ps->performance_level_count; i++) {
3134 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3135 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3136 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3137 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3138 }
3139 }
3140
3141 if (disable_mclk_switching) {
3142 mclk = ps->performance_levels[0].mclk;
3143 for (i = 1; i < ps->performance_level_count; i++) {
3144 if (mclk < ps->performance_levels[i].mclk)
3145 mclk = ps->performance_levels[i].mclk;
3146 }
3147 for (i = 0; i < ps->performance_level_count; i++) {
3148 ps->performance_levels[i].mclk = mclk;
3149 ps->performance_levels[i].vddci = vddci;
3150 }
3151 } else {
3152 for (i = 1; i < ps->performance_level_count; i++) {
3153 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3154 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3155 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3156 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3157 }
3158 }
3159
3160 for (i = 0; i < ps->performance_level_count; i++)
3161 btc_adjust_clock_combinations(rdev, max_limits,
3162 &ps->performance_levels[i]);
3163
3164 for (i = 0; i < ps->performance_level_count; i++) {
3165 if (ps->performance_levels[i].vddc < min_vce_voltage)
3166 ps->performance_levels[i].vddc = min_vce_voltage;
3167 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3168 ps->performance_levels[i].sclk,
3169 max_limits->vddc, &ps->performance_levels[i].vddc);
3170 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3171 ps->performance_levels[i].mclk,
3172 max_limits->vddci, &ps->performance_levels[i].vddci);
3173 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3174 ps->performance_levels[i].mclk,
3175 max_limits->vddc, &ps->performance_levels[i].vddc);
3176 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3177 rdev->clock.current_dispclk,
3178 max_limits->vddc, &ps->performance_levels[i].vddc);
3179 }
3180
3181 for (i = 0; i < ps->performance_level_count; i++) {
3182 btc_apply_voltage_delta_rules(rdev,
3183 max_limits->vddc, max_limits->vddci,
3184 &ps->performance_levels[i].vddc,
3185 &ps->performance_levels[i].vddci);
3186 }
3187
3188 ps->dc_compatible = true;
3189 for (i = 0; i < ps->performance_level_count; i++) {
3190 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3191 ps->dc_compatible = false;
3192 }
3193}
3194
3195#if 0
3196static int si_read_smc_soft_register(struct radeon_device *rdev,
3197 u16 reg_offset, u32 *value)
3198{
3199 struct si_power_info *si_pi = si_get_pi(rdev);
3200
3201 return si_read_smc_sram_dword(rdev,
3202 si_pi->soft_regs_start + reg_offset, value,
3203 si_pi->sram_end);
3204}
3205#endif
3206
3207static int si_write_smc_soft_register(struct radeon_device *rdev,
3208 u16 reg_offset, u32 value)
3209{
3210 struct si_power_info *si_pi = si_get_pi(rdev);
3211
3212 return si_write_smc_sram_dword(rdev,
3213 si_pi->soft_regs_start + reg_offset,
3214 value, si_pi->sram_end);
3215}
3216
3217static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3218{
3219 bool ret = false;
3220 u32 tmp, width, row, column, bank, density;
3221 bool is_memory_gddr5, is_special;
3222
3223 tmp = RREG32(MC_SEQ_MISC0);
3224 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3225 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3226 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3227
3228 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3229 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3230
3231 tmp = RREG32(MC_ARB_RAMCFG);
3232 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3233 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3234 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3235
3236 density = (1 << (row + column - 20 + bank)) * width;
3237
3238 if ((rdev->pdev->device == 0x6819) &&
3239 is_memory_gddr5 && is_special && (density == 0x400))
3240 ret = true;
3241
3242 return ret;
3243}
3244
3245static void si_get_leakage_vddc(struct radeon_device *rdev)
3246{
3247 struct si_power_info *si_pi = si_get_pi(rdev);
3248 u16 vddc, count = 0;
3249 int i, ret;
3250
3251 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3252 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3253
3254 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3255 si_pi->leakage_voltage.entries[count].voltage = vddc;
3256 si_pi->leakage_voltage.entries[count].leakage_index =
3257 SISLANDS_LEAKAGE_INDEX0 + i;
3258 count++;
3259 }
3260 }
3261 si_pi->leakage_voltage.count = count;
3262}
3263
3264static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3265 u32 index, u16 *leakage_voltage)
3266{
3267 struct si_power_info *si_pi = si_get_pi(rdev);
3268 int i;
3269
3270 if (leakage_voltage == NULL)
3271 return -EINVAL;
3272
3273 if ((index & 0xff00) != 0xff00)
3274 return -EINVAL;
3275
3276 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3277 return -EINVAL;
3278
3279 if (index < SISLANDS_LEAKAGE_INDEX0)
3280 return -EINVAL;
3281
3282 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3283 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3284 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3285 return 0;
3286 }
3287 }
3288 return -EAGAIN;
3289}
3290
3291static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3292{
3293 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3294 bool want_thermal_protection;
3295 enum radeon_dpm_event_src dpm_event_src;
3296
3297 switch (sources) {
3298 case 0:
3299 default:
3300 want_thermal_protection = false;
3301 break;
3302 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3303 want_thermal_protection = true;
3304 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3305 break;
3306 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3307 want_thermal_protection = true;
3308 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3309 break;
3310 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3311 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3312 want_thermal_protection = true;
3313 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3314 break;
3315 }
3316
3317 if (want_thermal_protection) {
3318 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3319 if (pi->thermal_protection)
3320 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3321 } else {
3322 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3323 }
3324}
3325
3326static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3327 enum radeon_dpm_auto_throttle_src source,
3328 bool enable)
3329{
3330 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3331
3332 if (enable) {
3333 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3334 pi->active_auto_throttle_sources |= 1 << source;
3335 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3336 }
3337 } else {
3338 if (pi->active_auto_throttle_sources & (1 << source)) {
3339 pi->active_auto_throttle_sources &= ~(1 << source);
3340 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3341 }
3342 }
3343}
3344
3345static void si_start_dpm(struct radeon_device *rdev)
3346{
3347 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3348}
3349
3350static void si_stop_dpm(struct radeon_device *rdev)
3351{
3352 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3353}
3354
3355static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3356{
3357 if (enable)
3358 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3359 else
3360 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3361
3362}
3363
3364#if 0
3365static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3366 u32 thermal_level)
3367{
3368 PPSMC_Result ret;
3369
3370 if (thermal_level == 0) {
3371 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3372 if (ret == PPSMC_Result_OK)
3373 return 0;
3374 else
3375 return -EINVAL;
3376 }
3377 return 0;
3378}
3379
3380static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3381{
3382 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3383}
3384#endif
3385
3386#if 0
3387static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3388{
3389 if (ac_power)
3390 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3391 0 : -EINVAL;
3392
3393 return 0;
3394}
3395#endif
3396
3397static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3398 PPSMC_Msg msg, u32 parameter)
3399{
3400 WREG32(SMC_SCRATCH0, parameter);
3401 return si_send_msg_to_smc(rdev, msg);
3402}
3403
3404static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3405{
3406 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3407 return -EINVAL;
3408
3409 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3410 0 : -EINVAL;
3411}
3412
3413int si_dpm_force_performance_level(struct radeon_device *rdev,
3414 enum radeon_dpm_forced_level level)
3415{
3416 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3417 struct ni_ps *ps = ni_get_ps(rps);
3418 u32 levels = ps->performance_level_count;
3419
3420 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3421 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3422 return -EINVAL;
3423
3424 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3425 return -EINVAL;
3426 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3427 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3428 return -EINVAL;
3429
3430 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3431 return -EINVAL;
3432 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3433 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3434 return -EINVAL;
3435
3436 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3437 return -EINVAL;
3438 }
3439
3440 rdev->pm.dpm.forced_level = level;
3441
3442 return 0;
3443}
3444
3445#if 0
3446static int si_set_boot_state(struct radeon_device *rdev)
3447{
3448 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3449 0 : -EINVAL;
3450}
3451#endif
3452
3453static int si_set_sw_state(struct radeon_device *rdev)
3454{
3455 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3456 0 : -EINVAL;
3457}
3458
3459static int si_halt_smc(struct radeon_device *rdev)
3460{
3461 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3462 return -EINVAL;
3463
3464 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3465 0 : -EINVAL;
3466}
3467
3468static int si_resume_smc(struct radeon_device *rdev)
3469{
3470 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3471 return -EINVAL;
3472
3473 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3474 0 : -EINVAL;
3475}
3476
3477static void si_dpm_start_smc(struct radeon_device *rdev)
3478{
3479 si_program_jump_on_start(rdev);
3480 si_start_smc(rdev);
3481 si_start_smc_clock(rdev);
3482}
3483
3484static void si_dpm_stop_smc(struct radeon_device *rdev)
3485{
3486 si_reset_smc(rdev);
3487 si_stop_smc_clock(rdev);
3488}
3489
3490static int si_process_firmware_header(struct radeon_device *rdev)
3491{
3492 struct si_power_info *si_pi = si_get_pi(rdev);
3493 u32 tmp;
3494 int ret;
3495
3496 ret = si_read_smc_sram_dword(rdev,
3497 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3498 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3499 &tmp, si_pi->sram_end);
3500 if (ret)
3501 return ret;
3502
3503 si_pi->state_table_start = tmp;
3504
3505 ret = si_read_smc_sram_dword(rdev,
3506 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3507 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3508 &tmp, si_pi->sram_end);
3509 if (ret)
3510 return ret;
3511
3512 si_pi->soft_regs_start = tmp;
3513
3514 ret = si_read_smc_sram_dword(rdev,
3515 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3516 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3517 &tmp, si_pi->sram_end);
3518 if (ret)
3519 return ret;
3520
3521 si_pi->mc_reg_table_start = tmp;
3522
3523 ret = si_read_smc_sram_dword(rdev,
3524 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3525 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3526 &tmp, si_pi->sram_end);
3527 if (ret)
3528 return ret;
3529
3530 si_pi->fan_table_start = tmp;
3531
3532 ret = si_read_smc_sram_dword(rdev,
3533 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3534 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3535 &tmp, si_pi->sram_end);
3536 if (ret)
3537 return ret;
3538
3539 si_pi->arb_table_start = tmp;
3540
3541 ret = si_read_smc_sram_dword(rdev,
3542 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3543 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3544 &tmp, si_pi->sram_end);
3545 if (ret)
3546 return ret;
3547
3548 si_pi->cac_table_start = tmp;
3549
3550 ret = si_read_smc_sram_dword(rdev,
3551 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3552 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3553 &tmp, si_pi->sram_end);
3554 if (ret)
3555 return ret;
3556
3557 si_pi->dte_table_start = tmp;
3558
3559 ret = si_read_smc_sram_dword(rdev,
3560 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3561 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3562 &tmp, si_pi->sram_end);
3563 if (ret)
3564 return ret;
3565
3566 si_pi->spll_table_start = tmp;
3567
3568 ret = si_read_smc_sram_dword(rdev,
3569 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3570 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3571 &tmp, si_pi->sram_end);
3572 if (ret)
3573 return ret;
3574
3575 si_pi->papm_cfg_table_start = tmp;
3576
3577 return ret;
3578}
3579
3580static void si_read_clock_registers(struct radeon_device *rdev)
3581{
3582 struct si_power_info *si_pi = si_get_pi(rdev);
3583
3584 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3585 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3586 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3587 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3588 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3589 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3590 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3591 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3592 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3593 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3594 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3595 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3596 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3597 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3598 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3599}
3600
3601static void si_enable_thermal_protection(struct radeon_device *rdev,
3602 bool enable)
3603{
3604 if (enable)
3605 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3606 else
3607 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3608}
3609
3610static void si_enable_acpi_power_management(struct radeon_device *rdev)
3611{
3612 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3613}
3614
3615#if 0
3616static int si_enter_ulp_state(struct radeon_device *rdev)
3617{
3618 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3619
3620 udelay(25000);
3621
3622 return 0;
3623}
3624
3625static int si_exit_ulp_state(struct radeon_device *rdev)
3626{
3627 int i;
3628
3629 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3630
3631 udelay(7000);
3632
3633 for (i = 0; i < rdev->usec_timeout; i++) {
3634 if (RREG32(SMC_RESP_0) == 1)
3635 break;
3636 udelay(1000);
3637 }
3638
3639 return 0;
3640}
3641#endif
3642
3643static int si_notify_smc_display_change(struct radeon_device *rdev,
3644 bool has_display)
3645{
3646 PPSMC_Msg msg = has_display ?
3647 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3648
3649 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3650 0 : -EINVAL;
3651}
3652
3653static void si_program_response_times(struct radeon_device *rdev)
3654{
3655 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3656 u32 vddc_dly, acpi_dly, vbi_dly;
3657 u32 reference_clock;
3658
3659 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3660
3661 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3662 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3663
3664 if (voltage_response_time == 0)
3665 voltage_response_time = 1000;
3666
3667 acpi_delay_time = 15000;
3668 vbi_time_out = 100000;
3669
3670 reference_clock = radeon_get_xclk(rdev);
3671
3672 vddc_dly = (voltage_response_time * reference_clock) / 100;
3673 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3674 vbi_dly = (vbi_time_out * reference_clock) / 100;
3675
3676 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3677 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3678 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3679 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3680}
3681
3682static void si_program_ds_registers(struct radeon_device *rdev)
3683{
3684 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3685 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3686
3687 if (eg_pi->sclk_deep_sleep) {
3688 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3689 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3690 ~AUTOSCALE_ON_SS_CLEAR);
3691 }
3692}
3693
3694static void si_program_display_gap(struct radeon_device *rdev)
3695{
3696 u32 tmp, pipe;
3697 int i;
3698
3699 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3700 if (rdev->pm.dpm.new_active_crtc_count > 0)
3701 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3702 else
3703 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3704
3705 if (rdev->pm.dpm.new_active_crtc_count > 1)
3706 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3707 else
3708 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3709
3710 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3711
3712 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3713 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3714
3715 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3716 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3717 /* find the first active crtc */
3718 for (i = 0; i < rdev->num_crtc; i++) {
3719 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3720 break;
3721 }
3722 if (i == rdev->num_crtc)
3723 pipe = 0;
3724 else
3725 pipe = i;
3726
3727 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3728 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3729 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3730 }
3731
3732 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3733 * This can be a problem on PowerXpress systems or if you want to use the card
3734 * for offscreen rendering or compute if there are no crtcs enabled.
3735 */
3736 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3737}
3738
3739static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3740{
3741 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3742
3743 if (enable) {
3744 if (pi->sclk_ss)
3745 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3746 } else {
3747 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3748 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3749 }
3750}
3751
3752static void si_setup_bsp(struct radeon_device *rdev)
3753{
3754 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3755 u32 xclk = radeon_get_xclk(rdev);
3756
3757 r600_calculate_u_and_p(pi->asi,
3758 xclk,
3759 16,
3760 &pi->bsp,
3761 &pi->bsu);
3762
3763 r600_calculate_u_and_p(pi->pasi,
3764 xclk,
3765 16,
3766 &pi->pbsp,
3767 &pi->pbsu);
3768
3769
3770 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3771 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3772
3773 WREG32(CG_BSP, pi->dsp);
3774}
3775
3776static void si_program_git(struct radeon_device *rdev)
3777{
3778 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3779}
3780
3781static void si_program_tp(struct radeon_device *rdev)
3782{
3783 int i;
3784 enum r600_td td = R600_TD_DFLT;
3785
3786 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3787 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3788
3789 if (td == R600_TD_AUTO)
3790 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3791 else
3792 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3793
3794 if (td == R600_TD_UP)
3795 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3796
3797 if (td == R600_TD_DOWN)
3798 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3799}
3800
3801static void si_program_tpp(struct radeon_device *rdev)
3802{
3803 WREG32(CG_TPC, R600_TPC_DFLT);
3804}
3805
3806static void si_program_sstp(struct radeon_device *rdev)
3807{
3808 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3809}
3810
3811static void si_enable_display_gap(struct radeon_device *rdev)
3812{
3813 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3814
3815 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3816 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3817 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3818
3819 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3820 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3821 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3822 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3823}
3824
3825static void si_program_vc(struct radeon_device *rdev)
3826{
3827 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3828
3829 WREG32(CG_FTV, pi->vrc);
3830}
3831
3832static void si_clear_vc(struct radeon_device *rdev)
3833{
3834 WREG32(CG_FTV, 0);
3835}
3836
3837u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3838{
3839 u8 mc_para_index;
3840
3841 if (memory_clock < 10000)
3842 mc_para_index = 0;
3843 else if (memory_clock >= 80000)
3844 mc_para_index = 0x0f;
3845 else
3846 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3847 return mc_para_index;
3848}
3849
3850u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3851{
3852 u8 mc_para_index;
3853
3854 if (strobe_mode) {
3855 if (memory_clock < 12500)
3856 mc_para_index = 0x00;
3857 else if (memory_clock > 47500)
3858 mc_para_index = 0x0f;
3859 else
3860 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3861 } else {
3862 if (memory_clock < 65000)
3863 mc_para_index = 0x00;
3864 else if (memory_clock > 135000)
3865 mc_para_index = 0x0f;
3866 else
3867 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3868 }
3869 return mc_para_index;
3870}
3871
3872static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3873{
3874 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3875 bool strobe_mode = false;
3876 u8 result = 0;
3877
3878 if (mclk <= pi->mclk_strobe_mode_threshold)
3879 strobe_mode = true;
3880
3881 if (pi->mem_gddr5)
3882 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3883 else
3884 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3885
3886 if (strobe_mode)
3887 result |= SISLANDS_SMC_STROBE_ENABLE;
3888
3889 return result;
3890}
3891
3892static int si_upload_firmware(struct radeon_device *rdev)
3893{
3894 struct si_power_info *si_pi = si_get_pi(rdev);
3895 int ret;
3896
3897 si_reset_smc(rdev);
3898 si_stop_smc_clock(rdev);
3899
3900 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3901
3902 return ret;
3903}
3904
3905static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3906 const struct atom_voltage_table *table,
3907 const struct radeon_phase_shedding_limits_table *limits)
3908{
3909 u32 data, num_bits, num_levels;
3910
3911 if ((table == NULL) || (limits == NULL))
3912 return false;
3913
3914 data = table->mask_low;
3915
3916 num_bits = hweight32(data);
3917
3918 if (num_bits == 0)
3919 return false;
3920
3921 num_levels = (1 << num_bits);
3922
3923 if (table->count != num_levels)
3924 return false;
3925
3926 if (limits->count != (num_levels - 1))
3927 return false;
3928
3929 return true;
3930}
3931
3932void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3933 u32 max_voltage_steps,
3934 struct atom_voltage_table *voltage_table)
3935{
3936 unsigned int i, diff;
3937
3938 if (voltage_table->count <= max_voltage_steps)
3939 return;
3940
3941 diff = voltage_table->count - max_voltage_steps;
3942
3943 for (i= 0; i < max_voltage_steps; i++)
3944 voltage_table->entries[i] = voltage_table->entries[i + diff];
3945
3946 voltage_table->count = max_voltage_steps;
3947}
3948
3949static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3950 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3951 struct atom_voltage_table *voltage_table)
3952{
3953 u32 i;
3954
3955 if (voltage_dependency_table == NULL)
3956 return -EINVAL;
3957
3958 voltage_table->mask_low = 0;
3959 voltage_table->phase_delay = 0;
3960
3961 voltage_table->count = voltage_dependency_table->count;
3962 for (i = 0; i < voltage_table->count; i++) {
3963 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3964 voltage_table->entries[i].smio_low = 0;
3965 }
3966
3967 return 0;
3968}
3969
3970static int si_construct_voltage_tables(struct radeon_device *rdev)
3971{
3972 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3973 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3974 struct si_power_info *si_pi = si_get_pi(rdev);
3975 int ret;
3976
3977 if (pi->voltage_control) {
3978 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3979 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3980 if (ret)
3981 return ret;
3982
3983 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3984 si_trim_voltage_table_to_fit_state_table(rdev,
3985 SISLANDS_MAX_NO_VREG_STEPS,
3986 &eg_pi->vddc_voltage_table);
3987 } else if (si_pi->voltage_control_svi2) {
3988 ret = si_get_svi2_voltage_table(rdev,
3989 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3990 &eg_pi->vddc_voltage_table);
3991 if (ret)
3992 return ret;
3993 } else {
3994 return -EINVAL;
3995 }
3996
3997 if (eg_pi->vddci_control) {
3998 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3999 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4000 if (ret)
4001 return ret;
4002
4003 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4004 si_trim_voltage_table_to_fit_state_table(rdev,
4005 SISLANDS_MAX_NO_VREG_STEPS,
4006 &eg_pi->vddci_voltage_table);
4007 }
4008 if (si_pi->vddci_control_svi2) {
4009 ret = si_get_svi2_voltage_table(rdev,
4010 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4011 &eg_pi->vddci_voltage_table);
4012 if (ret)
4013 return ret;
4014 }
4015
4016 if (pi->mvdd_control) {
4017 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4018 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4019
4020 if (ret) {
4021 pi->mvdd_control = false;
4022 return ret;
4023 }
4024
4025 if (si_pi->mvdd_voltage_table.count == 0) {
4026 pi->mvdd_control = false;
4027 return -EINVAL;
4028 }
4029
4030 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4031 si_trim_voltage_table_to_fit_state_table(rdev,
4032 SISLANDS_MAX_NO_VREG_STEPS,
4033 &si_pi->mvdd_voltage_table);
4034 }
4035
4036 if (si_pi->vddc_phase_shed_control) {
4037 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4038 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4039 if (ret)
4040 si_pi->vddc_phase_shed_control = false;
4041
4042 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4043 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4044 si_pi->vddc_phase_shed_control = false;
4045 }
4046
4047 return 0;
4048}
4049
4050static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4051 const struct atom_voltage_table *voltage_table,
4052 SISLANDS_SMC_STATETABLE *table)
4053{
4054 unsigned int i;
4055
4056 for (i = 0; i < voltage_table->count; i++)
4057 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4058}
4059
4060static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4061 SISLANDS_SMC_STATETABLE *table)
4062{
4063 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4064 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4065 struct si_power_info *si_pi = si_get_pi(rdev);
4066 u8 i;
4067
4068 if (si_pi->voltage_control_svi2) {
4069 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4070 si_pi->svc_gpio_id);
4071 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4072 si_pi->svd_gpio_id);
4073 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4074 2);
4075 } else {
4076 if (eg_pi->vddc_voltage_table.count) {
4077 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4078 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4079 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4080
4081 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4082 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4083 table->maxVDDCIndexInPPTable = i;
4084 break;
4085 }
4086 }
4087 }
4088
4089 if (eg_pi->vddci_voltage_table.count) {
4090 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4091
4092 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4093 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4094 }
4095
4096
4097 if (si_pi->mvdd_voltage_table.count) {
4098 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4099
4100 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4101 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4102 }
4103
4104 if (si_pi->vddc_phase_shed_control) {
4105 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4106 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4107 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4108
4109 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4110 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4111
4112 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4113 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4114 } else {
4115 si_pi->vddc_phase_shed_control = false;
4116 }
4117 }
4118 }
4119
4120 return 0;
4121}
4122
4123static int si_populate_voltage_value(struct radeon_device *rdev,
4124 const struct atom_voltage_table *table,
4125 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4126{
4127 unsigned int i;
4128
4129 for (i = 0; i < table->count; i++) {
4130 if (value <= table->entries[i].value) {
4131 voltage->index = (u8)i;
4132 voltage->value = cpu_to_be16(table->entries[i].value);
4133 break;
4134 }
4135 }
4136
4137 if (i >= table->count)
4138 return -EINVAL;
4139
4140 return 0;
4141}
4142
4143static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4144 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4145{
4146 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4147 struct si_power_info *si_pi = si_get_pi(rdev);
4148
4149 if (pi->mvdd_control) {
4150 if (mclk <= pi->mvdd_split_frequency)
4151 voltage->index = 0;
4152 else
4153 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4154
4155 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4156 }
4157 return 0;
4158}
4159
4160static int si_get_std_voltage_value(struct radeon_device *rdev,
4161 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4162 u16 *std_voltage)
4163{
4164 u16 v_index;
4165 bool voltage_found = false;
4166 *std_voltage = be16_to_cpu(voltage->value);
4167
4168 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4169 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4170 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4171 return -EINVAL;
4172
4173 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4174 if (be16_to_cpu(voltage->value) ==
4175 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4176 voltage_found = true;
4177 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4178 *std_voltage =
4179 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4180 else
4181 *std_voltage =
4182 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4183 break;
4184 }
4185 }
4186
4187 if (!voltage_found) {
4188 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4189 if (be16_to_cpu(voltage->value) <=
4190 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4191 voltage_found = true;
4192 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4193 *std_voltage =
4194 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4195 else
4196 *std_voltage =
4197 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4198 break;
4199 }
4200 }
4201 }
4202 } else {
4203 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4204 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4205 }
4206 }
4207
4208 return 0;
4209}
4210
4211static int si_populate_std_voltage_value(struct radeon_device *rdev,
4212 u16 value, u8 index,
4213 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4214{
4215 voltage->index = index;
4216 voltage->value = cpu_to_be16(value);
4217
4218 return 0;
4219}
4220
4221static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4222 const struct radeon_phase_shedding_limits_table *limits,
4223 u16 voltage, u32 sclk, u32 mclk,
4224 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4225{
4226 unsigned int i;
4227
4228 for (i = 0; i < limits->count; i++) {
4229 if ((voltage <= limits->entries[i].voltage) &&
4230 (sclk <= limits->entries[i].sclk) &&
4231 (mclk <= limits->entries[i].mclk))
4232 break;
4233 }
4234
4235 smc_voltage->phase_settings = (u8)i;
4236
4237 return 0;
4238}
4239
4240static int si_init_arb_table_index(struct radeon_device *rdev)
4241{
4242 struct si_power_info *si_pi = si_get_pi(rdev);
4243 u32 tmp;
4244 int ret;
4245
4246 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4247 if (ret)
4248 return ret;
4249
4250 tmp &= 0x00FFFFFF;
4251 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4252
4253 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4254}
4255
4256static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4257{
4258 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4259}
4260
4261static int si_reset_to_default(struct radeon_device *rdev)
4262{
4263 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4264 0 : -EINVAL;
4265}
4266
4267static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4268{
4269 struct si_power_info *si_pi = si_get_pi(rdev);
4270 u32 tmp;
4271 int ret;
4272
4273 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4274 &tmp, si_pi->sram_end);
4275 if (ret)
4276 return ret;
4277
4278 tmp = (tmp >> 24) & 0xff;
4279
4280 if (tmp == MC_CG_ARB_FREQ_F0)
4281 return 0;
4282
4283 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4284}
4285
4286static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4287 u32 engine_clock)
4288{
4289 u32 dram_rows;
4290 u32 dram_refresh_rate;
4291 u32 mc_arb_rfsh_rate;
4292 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4293
4294 if (tmp >= 4)
4295 dram_rows = 16384;
4296 else
4297 dram_rows = 1 << (tmp + 10);
4298
4299 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4300 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4301
4302 return mc_arb_rfsh_rate;
4303}
4304
4305static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4306 struct rv7xx_pl *pl,
4307 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4308{
4309 u32 dram_timing;
4310 u32 dram_timing2;
4311 u32 burst_time;
4312
4313 arb_regs->mc_arb_rfsh_rate =
4314 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4315
4316 radeon_atom_set_engine_dram_timings(rdev,
4317 pl->sclk,
4318 pl->mclk);
4319
4320 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4321 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4322 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4323
4324 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4325 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4326 arb_regs->mc_arb_burst_time = (u8)burst_time;
4327
4328 return 0;
4329}
4330
4331static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4332 struct radeon_ps *radeon_state,
4333 unsigned int first_arb_set)
4334{
4335 struct si_power_info *si_pi = si_get_pi(rdev);
4336 struct ni_ps *state = ni_get_ps(radeon_state);
4337 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4338 int i, ret = 0;
4339
4340 for (i = 0; i < state->performance_level_count; i++) {
4341 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4342 if (ret)
4343 break;
4344 ret = si_copy_bytes_to_smc(rdev,
4345 si_pi->arb_table_start +
4346 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4347 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4348 (u8 *)&arb_regs,
4349 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4350 si_pi->sram_end);
4351 if (ret)
4352 break;
4353 }
4354
4355 return ret;
4356}
4357
4358static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4359 struct radeon_ps *radeon_new_state)
4360{
4361 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4362 SISLANDS_DRIVER_STATE_ARB_INDEX);
4363}
4364
4365static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4366 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4367{
4368 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4369 struct si_power_info *si_pi = si_get_pi(rdev);
4370
4371 if (pi->mvdd_control)
4372 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4373 si_pi->mvdd_bootup_value, voltage);
4374
4375 return 0;
4376}
4377
4378static int si_populate_smc_initial_state(struct radeon_device *rdev,
4379 struct radeon_ps *radeon_initial_state,
4380 SISLANDS_SMC_STATETABLE *table)
4381{
4382 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4383 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4384 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4385 struct si_power_info *si_pi = si_get_pi(rdev);
4386 u32 reg;
4387 int ret;
4388
4389 table->initialState.levels[0].mclk.vDLL_CNTL =
4390 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4391 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4392 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4393 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4394 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4395 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4396 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4397 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4398 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4399 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4400 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4401 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4402 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4403 table->initialState.levels[0].mclk.vMPLL_SS =
4404 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4405 table->initialState.levels[0].mclk.vMPLL_SS2 =
4406 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4407
4408 table->initialState.levels[0].mclk.mclk_value =
4409 cpu_to_be32(initial_state->performance_levels[0].mclk);
4410
4411 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4412 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4413 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4414 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4415 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4416 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4417 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4418 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4419 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4420 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4421 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4422 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4423
4424 table->initialState.levels[0].sclk.sclk_value =
4425 cpu_to_be32(initial_state->performance_levels[0].sclk);
4426
4427 table->initialState.levels[0].arbRefreshState =
4428 SISLANDS_INITIAL_STATE_ARB_INDEX;
4429
4430 table->initialState.levels[0].ACIndex = 0;
4431
4432 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4433 initial_state->performance_levels[0].vddc,
4434 &table->initialState.levels[0].vddc);
4435
4436 if (!ret) {
4437 u16 std_vddc;
4438
4439 ret = si_get_std_voltage_value(rdev,
4440 &table->initialState.levels[0].vddc,
4441 &std_vddc);
4442 if (!ret)
4443 si_populate_std_voltage_value(rdev, std_vddc,
4444 table->initialState.levels[0].vddc.index,
4445 &table->initialState.levels[0].std_vddc);
4446 }
4447
4448 if (eg_pi->vddci_control)
4449 si_populate_voltage_value(rdev,
4450 &eg_pi->vddci_voltage_table,
4451 initial_state->performance_levels[0].vddci,
4452 &table->initialState.levels[0].vddci);
4453
4454 if (si_pi->vddc_phase_shed_control)
4455 si_populate_phase_shedding_value(rdev,
4456 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4457 initial_state->performance_levels[0].vddc,
4458 initial_state->performance_levels[0].sclk,
4459 initial_state->performance_levels[0].mclk,
4460 &table->initialState.levels[0].vddc);
4461
4462 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4463
4464 reg = CG_R(0xffff) | CG_L(0);
4465 table->initialState.levels[0].aT = cpu_to_be32(reg);
4466
4467 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4468
4469 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4470
4471 if (pi->mem_gddr5) {
4472 table->initialState.levels[0].strobeMode =
4473 si_get_strobe_mode_settings(rdev,
4474 initial_state->performance_levels[0].mclk);
4475
4476 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4477 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4478 else
4479 table->initialState.levels[0].mcFlags = 0;
4480 }
4481
4482 table->initialState.levelCount = 1;
4483
4484 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4485
4486 table->initialState.levels[0].dpm2.MaxPS = 0;
4487 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4488 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4489 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4490 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4491
4492 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4493 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4494
4495 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4496 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4497
4498 return 0;
4499}
4500
4501static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4502 SISLANDS_SMC_STATETABLE *table)
4503{
4504 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4505 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4506 struct si_power_info *si_pi = si_get_pi(rdev);
4507 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4508 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4509 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4510 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4511 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4512 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4513 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4514 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4515 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4516 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4517 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4518 u32 reg;
4519 int ret;
4520
4521 table->ACPIState = table->initialState;
4522
4523 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4524
4525 if (pi->acpi_vddc) {
4526 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4527 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4528 if (!ret) {
4529 u16 std_vddc;
4530
4531 ret = si_get_std_voltage_value(rdev,
4532 &table->ACPIState.levels[0].vddc, &std_vddc);
4533 if (!ret)
4534 si_populate_std_voltage_value(rdev, std_vddc,
4535 table->ACPIState.levels[0].vddc.index,
4536 &table->ACPIState.levels[0].std_vddc);
4537 }
4538 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4539
4540 if (si_pi->vddc_phase_shed_control) {
4541 si_populate_phase_shedding_value(rdev,
4542 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4543 pi->acpi_vddc,
4544 0,
4545 0,
4546 &table->ACPIState.levels[0].vddc);
4547 }
4548 } else {
4549 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4550 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4551 if (!ret) {
4552 u16 std_vddc;
4553
4554 ret = si_get_std_voltage_value(rdev,
4555 &table->ACPIState.levels[0].vddc, &std_vddc);
4556
4557 if (!ret)
4558 si_populate_std_voltage_value(rdev, std_vddc,
4559 table->ACPIState.levels[0].vddc.index,
4560 &table->ACPIState.levels[0].std_vddc);
4561 }
4562 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4563 si_pi->sys_pcie_mask,
4564 si_pi->boot_pcie_gen,
4565 RADEON_PCIE_GEN1);
4566
4567 if (si_pi->vddc_phase_shed_control)
4568 si_populate_phase_shedding_value(rdev,
4569 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4570 pi->min_vddc_in_table,
4571 0,
4572 0,
4573 &table->ACPIState.levels[0].vddc);
4574 }
4575
4576 if (pi->acpi_vddc) {
4577 if (eg_pi->acpi_vddci)
4578 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4579 eg_pi->acpi_vddci,
4580 &table->ACPIState.levels[0].vddci);
4581 }
4582
4583 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4584 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4585
4586 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4587
4588 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4589 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4590
4591 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4592 cpu_to_be32(dll_cntl);
4593 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4594 cpu_to_be32(mclk_pwrmgt_cntl);
4595 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4596 cpu_to_be32(mpll_ad_func_cntl);
4597 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4598 cpu_to_be32(mpll_dq_func_cntl);
4599 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4600 cpu_to_be32(mpll_func_cntl);
4601 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4602 cpu_to_be32(mpll_func_cntl_1);
4603 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4604 cpu_to_be32(mpll_func_cntl_2);
4605 table->ACPIState.levels[0].mclk.vMPLL_SS =
4606 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4607 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4608 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4609
4610 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4611 cpu_to_be32(spll_func_cntl);
4612 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4613 cpu_to_be32(spll_func_cntl_2);
4614 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4615 cpu_to_be32(spll_func_cntl_3);
4616 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4617 cpu_to_be32(spll_func_cntl_4);
4618
4619 table->ACPIState.levels[0].mclk.mclk_value = 0;
4620 table->ACPIState.levels[0].sclk.sclk_value = 0;
4621
4622 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4623
4624 if (eg_pi->dynamic_ac_timing)
4625 table->ACPIState.levels[0].ACIndex = 0;
4626
4627 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4628 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4629 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4630 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4631 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4632
4633 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4634 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4635
4636 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4637 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4638
4639 return 0;
4640}
4641
4642static int si_populate_ulv_state(struct radeon_device *rdev,
4643 SISLANDS_SMC_SWSTATE *state)
4644{
4645 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4646 struct si_power_info *si_pi = si_get_pi(rdev);
4647 struct si_ulv_param *ulv = &si_pi->ulv;
4648 u32 sclk_in_sr = 1350; /* ??? */
4649 int ret;
4650
4651 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4652 &state->levels[0]);
4653 if (!ret) {
4654 if (eg_pi->sclk_deep_sleep) {
4655 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4656 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4657 else
4658 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4659 }
4660 if (ulv->one_pcie_lane_in_ulv)
4661 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4662 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4663 state->levels[0].ACIndex = 1;
4664 state->levels[0].std_vddc = state->levels[0].vddc;
4665 state->levelCount = 1;
4666
4667 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4668 }
4669
4670 return ret;
4671}
4672
4673static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4674{
4675 struct si_power_info *si_pi = si_get_pi(rdev);
4676 struct si_ulv_param *ulv = &si_pi->ulv;
4677 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4678 int ret;
4679
4680 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4681 &arb_regs);
4682 if (ret)
4683 return ret;
4684
4685 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4686 ulv->volt_change_delay);
4687
4688 ret = si_copy_bytes_to_smc(rdev,
4689 si_pi->arb_table_start +
4690 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4691 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4692 (u8 *)&arb_regs,
4693 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4694 si_pi->sram_end);
4695
4696 return ret;
4697}
4698
4699static void si_get_mvdd_configuration(struct radeon_device *rdev)
4700{
4701 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4702
4703 pi->mvdd_split_frequency = 30000;
4704}
4705
4706static int si_init_smc_table(struct radeon_device *rdev)
4707{
4708 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4709 struct si_power_info *si_pi = si_get_pi(rdev);
4710 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4711 const struct si_ulv_param *ulv = &si_pi->ulv;
4712 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4713 int ret;
4714 u32 lane_width;
4715 u32 vr_hot_gpio;
4716
4717 si_populate_smc_voltage_tables(rdev, table);
4718
4719 switch (rdev->pm.int_thermal_type) {
4720 case THERMAL_TYPE_SI:
4721 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4722 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4723 break;
4724 case THERMAL_TYPE_NONE:
4725 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4726 break;
4727 default:
4728 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4729 break;
4730 }
4731
4732 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4733 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4734
4735 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4736 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4737 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4738 }
4739
4740 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4741 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4742
4743 if (pi->mem_gddr5)
4744 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4745
4746 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4747 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4748
4749 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4750 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4751 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4752 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4753 vr_hot_gpio);
4754 }
4755
4756 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4757 if (ret)
4758 return ret;
4759
4760 ret = si_populate_smc_acpi_state(rdev, table);
4761 if (ret)
4762 return ret;
4763
4764 table->driverState = table->initialState;
4765
4766 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4767 SISLANDS_INITIAL_STATE_ARB_INDEX);
4768 if (ret)
4769 return ret;
4770
4771 if (ulv->supported && ulv->pl.vddc) {
4772 ret = si_populate_ulv_state(rdev, &table->ULVState);
4773 if (ret)
4774 return ret;
4775
4776 ret = si_program_ulv_memory_timing_parameters(rdev);
4777 if (ret)
4778 return ret;
4779
4780 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4781 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4782
4783 lane_width = radeon_get_pcie_lanes(rdev);
4784 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4785 } else {
4786 table->ULVState = table->initialState;
4787 }
4788
4789 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4790 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4791 si_pi->sram_end);
4792}
4793
4794static int si_calculate_sclk_params(struct radeon_device *rdev,
4795 u32 engine_clock,
4796 SISLANDS_SMC_SCLK_VALUE *sclk)
4797{
4798 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4799 struct si_power_info *si_pi = si_get_pi(rdev);
4800 struct atom_clock_dividers dividers;
4801 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4802 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4803 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4804 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4805 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4806 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4807 u64 tmp;
4808 u32 reference_clock = rdev->clock.spll.reference_freq;
4809 u32 reference_divider;
4810 u32 fbdiv;
4811 int ret;
4812
4813 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4814 engine_clock, false, ÷rs);
4815 if (ret)
4816 return ret;
4817
4818 reference_divider = 1 + dividers.ref_div;
4819
4820 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4821 do_div(tmp, reference_clock);
4822 fbdiv = (u32) tmp;
4823
4824 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4825 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4826 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4827
4828 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4829 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4830
4831 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4832 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4833 spll_func_cntl_3 |= SPLL_DITHEN;
4834
4835 if (pi->sclk_ss) {
4836 struct radeon_atom_ss ss;
4837 u32 vco_freq = engine_clock * dividers.post_div;
4838
4839 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4840 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4841 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4842 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4843
4844 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4845 cg_spll_spread_spectrum |= CLK_S(clk_s);
4846 cg_spll_spread_spectrum |= SSEN;
4847
4848 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4849 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4850 }
4851 }
4852
4853 sclk->sclk_value = engine_clock;
4854 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4855 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4856 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4857 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4858 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4859 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4860
4861 return 0;
4862}
4863
4864static int si_populate_sclk_value(struct radeon_device *rdev,
4865 u32 engine_clock,
4866 SISLANDS_SMC_SCLK_VALUE *sclk)
4867{
4868 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4869 int ret;
4870
4871 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4872 if (!ret) {
4873 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4874 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4875 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4876 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4877 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4878 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4879 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4880 }
4881
4882 return ret;
4883}
4884
4885static int si_populate_mclk_value(struct radeon_device *rdev,
4886 u32 engine_clock,
4887 u32 memory_clock,
4888 SISLANDS_SMC_MCLK_VALUE *mclk,
4889 bool strobe_mode,
4890 bool dll_state_on)
4891{
4892 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4893 struct si_power_info *si_pi = si_get_pi(rdev);
4894 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4895 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4896 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4897 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4898 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4899 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4900 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4901 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4902 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4903 struct atom_mpll_param mpll_param;
4904 int ret;
4905
4906 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4907 if (ret)
4908 return ret;
4909
4910 mpll_func_cntl &= ~BWCTRL_MASK;
4911 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4912
4913 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4914 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4915 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4916
4917 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4918 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4919
4920 if (pi->mem_gddr5) {
4921 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4922 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4923 YCLK_POST_DIV(mpll_param.post_div);
4924 }
4925
4926 if (pi->mclk_ss) {
4927 struct radeon_atom_ss ss;
4928 u32 freq_nom;
4929 u32 tmp;
4930 u32 reference_clock = rdev->clock.mpll.reference_freq;
4931
4932 if (pi->mem_gddr5)
4933 freq_nom = memory_clock * 4;
4934 else
4935 freq_nom = memory_clock * 2;
4936
4937 tmp = freq_nom / reference_clock;
4938 tmp = tmp * tmp;
4939 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4940 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4941 u32 clks = reference_clock * 5 / ss.rate;
4942 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4943
4944 mpll_ss1 &= ~CLKV_MASK;
4945 mpll_ss1 |= CLKV(clkv);
4946
4947 mpll_ss2 &= ~CLKS_MASK;
4948 mpll_ss2 |= CLKS(clks);
4949 }
4950 }
4951
4952 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4953 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4954
4955 if (dll_state_on)
4956 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4957 else
4958 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4959
4960 mclk->mclk_value = cpu_to_be32(memory_clock);
4961 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4962 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4963 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4964 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4965 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4966 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4967 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4968 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4969 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4970
4971 return 0;
4972}
4973
4974static void si_populate_smc_sp(struct radeon_device *rdev,
4975 struct radeon_ps *radeon_state,
4976 SISLANDS_SMC_SWSTATE *smc_state)
4977{
4978 struct ni_ps *ps = ni_get_ps(radeon_state);
4979 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4980 int i;
4981
4982 for (i = 0; i < ps->performance_level_count - 1; i++)
4983 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4984
4985 smc_state->levels[ps->performance_level_count - 1].bSP =
4986 cpu_to_be32(pi->psp);
4987}
4988
4989static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4990 struct rv7xx_pl *pl,
4991 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4992{
4993 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4994 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4995 struct si_power_info *si_pi = si_get_pi(rdev);
4996 int ret;
4997 bool dll_state_on;
4998 u16 std_vddc;
4999 bool gmc_pg = false;
5000
5001 if (eg_pi->pcie_performance_request &&
5002 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
5003 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5004 else
5005 level->gen2PCIE = (u8)pl->pcie_gen;
5006
5007 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5008 if (ret)
5009 return ret;
5010
5011 level->mcFlags = 0;
5012
5013 if (pi->mclk_stutter_mode_threshold &&
5014 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5015 !eg_pi->uvd_enabled &&
5016 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5017 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5018 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5019
5020 if (gmc_pg)
5021 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5022 }
5023
5024 if (pi->mem_gddr5) {
5025 if (pl->mclk > pi->mclk_edc_enable_threshold)
5026 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5027
5028 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5029 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5030
5031 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5032
5033 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5034 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5035 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5036 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5037 else
5038 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5039 } else {
5040 dll_state_on = false;
5041 }
5042 } else {
5043 level->strobeMode = si_get_strobe_mode_settings(rdev,
5044 pl->mclk);
5045
5046 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5047 }
5048
5049 ret = si_populate_mclk_value(rdev,
5050 pl->sclk,
5051 pl->mclk,
5052 &level->mclk,
5053 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5054 if (ret)
5055 return ret;
5056
5057 ret = si_populate_voltage_value(rdev,
5058 &eg_pi->vddc_voltage_table,
5059 pl->vddc, &level->vddc);
5060 if (ret)
5061 return ret;
5062
5063
5064 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5065 if (ret)
5066 return ret;
5067
5068 ret = si_populate_std_voltage_value(rdev, std_vddc,
5069 level->vddc.index, &level->std_vddc);
5070 if (ret)
5071 return ret;
5072
5073 if (eg_pi->vddci_control) {
5074 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5075 pl->vddci, &level->vddci);
5076 if (ret)
5077 return ret;
5078 }
5079
5080 if (si_pi->vddc_phase_shed_control) {
5081 ret = si_populate_phase_shedding_value(rdev,
5082 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5083 pl->vddc,
5084 pl->sclk,
5085 pl->mclk,
5086 &level->vddc);
5087 if (ret)
5088 return ret;
5089 }
5090
5091 level->MaxPoweredUpCU = si_pi->max_cu;
5092
5093 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5094
5095 return ret;
5096}
5097
5098static int si_populate_smc_t(struct radeon_device *rdev,
5099 struct radeon_ps *radeon_state,
5100 SISLANDS_SMC_SWSTATE *smc_state)
5101{
5102 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5103 struct ni_ps *state = ni_get_ps(radeon_state);
5104 u32 a_t;
5105 u32 t_l, t_h;
5106 u32 high_bsp;
5107 int i, ret;
5108
5109 if (state->performance_level_count >= 9)
5110 return -EINVAL;
5111
5112 if (state->performance_level_count < 2) {
5113 a_t = CG_R(0xffff) | CG_L(0);
5114 smc_state->levels[0].aT = cpu_to_be32(a_t);
5115 return 0;
5116 }
5117
5118 smc_state->levels[0].aT = cpu_to_be32(0);
5119
5120 for (i = 0; i <= state->performance_level_count - 2; i++) {
5121 ret = r600_calculate_at(
5122 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5123 100 * R600_AH_DFLT,
5124 state->performance_levels[i + 1].sclk,
5125 state->performance_levels[i].sclk,
5126 &t_l,
5127 &t_h);
5128
5129 if (ret) {
5130 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5131 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5132 }
5133
5134 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5135 a_t |= CG_R(t_l * pi->bsp / 20000);
5136 smc_state->levels[i].aT = cpu_to_be32(a_t);
5137
5138 high_bsp = (i == state->performance_level_count - 2) ?
5139 pi->pbsp : pi->bsp;
5140 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5141 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5142 }
5143
5144 return 0;
5145}
5146
5147static int si_disable_ulv(struct radeon_device *rdev)
5148{
5149 struct si_power_info *si_pi = si_get_pi(rdev);
5150 struct si_ulv_param *ulv = &si_pi->ulv;
5151
5152 if (ulv->supported)
5153 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5154 0 : -EINVAL;
5155
5156 return 0;
5157}
5158
5159static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5160 struct radeon_ps *radeon_state)
5161{
5162 const struct si_power_info *si_pi = si_get_pi(rdev);
5163 const struct si_ulv_param *ulv = &si_pi->ulv;
5164 const struct ni_ps *state = ni_get_ps(radeon_state);
5165 int i;
5166
5167 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5168 return false;
5169
5170 /* XXX validate against display requirements! */
5171
5172 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5173 if (rdev->clock.current_dispclk <=
5174 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5175 if (ulv->pl.vddc <
5176 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5177 return false;
5178 }
5179 }
5180
5181 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5182 return false;
5183
5184 return true;
5185}
5186
5187static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5188 struct radeon_ps *radeon_new_state)
5189{
5190 const struct si_power_info *si_pi = si_get_pi(rdev);
5191 const struct si_ulv_param *ulv = &si_pi->ulv;
5192
5193 if (ulv->supported) {
5194 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5195 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5196 0 : -EINVAL;
5197 }
5198 return 0;
5199}
5200
5201static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5202 struct radeon_ps *radeon_state,
5203 SISLANDS_SMC_SWSTATE *smc_state)
5204{
5205 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5206 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5207 struct si_power_info *si_pi = si_get_pi(rdev);
5208 struct ni_ps *state = ni_get_ps(radeon_state);
5209 int i, ret;
5210 u32 threshold;
5211 u32 sclk_in_sr = 1350; /* ??? */
5212
5213 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5214 return -EINVAL;
5215
5216 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5217
5218 if (radeon_state->vclk && radeon_state->dclk) {
5219 eg_pi->uvd_enabled = true;
5220 if (eg_pi->smu_uvd_hs)
5221 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5222 } else {
5223 eg_pi->uvd_enabled = false;
5224 }
5225
5226 if (state->dc_compatible)
5227 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5228
5229 smc_state->levelCount = 0;
5230 for (i = 0; i < state->performance_level_count; i++) {
5231 if (eg_pi->sclk_deep_sleep) {
5232 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5233 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5234 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5235 else
5236 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5237 }
5238 }
5239
5240 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5241 &smc_state->levels[i]);
5242 smc_state->levels[i].arbRefreshState =
5243 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5244
5245 if (ret)
5246 return ret;
5247
5248 if (ni_pi->enable_power_containment)
5249 smc_state->levels[i].displayWatermark =
5250 (state->performance_levels[i].sclk < threshold) ?
5251 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5252 else
5253 smc_state->levels[i].displayWatermark = (i < 2) ?
5254 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5255
5256 if (eg_pi->dynamic_ac_timing)
5257 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5258 else
5259 smc_state->levels[i].ACIndex = 0;
5260
5261 smc_state->levelCount++;
5262 }
5263
5264 si_write_smc_soft_register(rdev,
5265 SI_SMC_SOFT_REGISTER_watermark_threshold,
5266 threshold / 512);
5267
5268 si_populate_smc_sp(rdev, radeon_state, smc_state);
5269
5270 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5271 if (ret)
5272 ni_pi->enable_power_containment = false;
5273
5274 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5275 if (ret)
5276 ni_pi->enable_sq_ramping = false;
5277
5278 return si_populate_smc_t(rdev, radeon_state, smc_state);
5279}
5280
5281static int si_upload_sw_state(struct radeon_device *rdev,
5282 struct radeon_ps *radeon_new_state)
5283{
5284 struct si_power_info *si_pi = si_get_pi(rdev);
5285 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5286 int ret;
5287 u32 address = si_pi->state_table_start +
5288 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5289 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5290 ((new_state->performance_level_count - 1) *
5291 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5292 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5293
5294 memset(smc_state, 0, state_size);
5295
5296 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5297 if (ret)
5298 return ret;
5299
5300 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5301 state_size, si_pi->sram_end);
5302
5303 return ret;
5304}
5305
5306static int si_upload_ulv_state(struct radeon_device *rdev)
5307{
5308 struct si_power_info *si_pi = si_get_pi(rdev);
5309 struct si_ulv_param *ulv = &si_pi->ulv;
5310 int ret = 0;
5311
5312 if (ulv->supported && ulv->pl.vddc) {
5313 u32 address = si_pi->state_table_start +
5314 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5315 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5316 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5317
5318 memset(smc_state, 0, state_size);
5319
5320 ret = si_populate_ulv_state(rdev, smc_state);
5321 if (!ret)
5322 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5323 state_size, si_pi->sram_end);
5324 }
5325
5326 return ret;
5327}
5328
5329static int si_upload_smc_data(struct radeon_device *rdev)
5330{
5331 struct radeon_crtc *radeon_crtc = NULL;
5332 int i;
5333
5334 if (rdev->pm.dpm.new_active_crtc_count == 0)
5335 return 0;
5336
5337 for (i = 0; i < rdev->num_crtc; i++) {
5338 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5339 radeon_crtc = rdev->mode_info.crtcs[i];
5340 break;
5341 }
5342 }
5343
5344 if (radeon_crtc == NULL)
5345 return 0;
5346
5347 if (radeon_crtc->line_time <= 0)
5348 return 0;
5349
5350 if (si_write_smc_soft_register(rdev,
5351 SI_SMC_SOFT_REGISTER_crtc_index,
5352 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5353 return 0;
5354
5355 if (si_write_smc_soft_register(rdev,
5356 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5357 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5358 return 0;
5359
5360 if (si_write_smc_soft_register(rdev,
5361 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5362 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5363 return 0;
5364
5365 return 0;
5366}
5367
5368static int si_set_mc_special_registers(struct radeon_device *rdev,
5369 struct si_mc_reg_table *table)
5370{
5371 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5372 u8 i, j, k;
5373 u32 temp_reg;
5374
5375 for (i = 0, j = table->last; i < table->last; i++) {
5376 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5377 return -EINVAL;
5378 switch (table->mc_reg_address[i].s1 << 2) {
5379 case MC_SEQ_MISC1:
5380 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5381 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5382 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5383 for (k = 0; k < table->num_entries; k++)
5384 table->mc_reg_table_entry[k].mc_data[j] =
5385 ((temp_reg & 0xffff0000)) |
5386 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5387 j++;
5388 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5389 return -EINVAL;
5390
5391 temp_reg = RREG32(MC_PMG_CMD_MRS);
5392 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5393 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5394 for (k = 0; k < table->num_entries; k++) {
5395 table->mc_reg_table_entry[k].mc_data[j] =
5396 (temp_reg & 0xffff0000) |
5397 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5398 if (!pi->mem_gddr5)
5399 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5400 }
5401 j++;
5402 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5403 return -EINVAL;
5404
5405 if (!pi->mem_gddr5) {
5406 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5407 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5408 for (k = 0; k < table->num_entries; k++)
5409 table->mc_reg_table_entry[k].mc_data[j] =
5410 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5411 j++;
5412 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5413 return -EINVAL;
5414 }
5415 break;
5416 case MC_SEQ_RESERVE_M:
5417 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5418 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5419 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5420 for(k = 0; k < table->num_entries; k++)
5421 table->mc_reg_table_entry[k].mc_data[j] =
5422 (temp_reg & 0xffff0000) |
5423 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5424 j++;
5425 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5426 return -EINVAL;
5427 break;
5428 default:
5429 break;
5430 }
5431 }
5432
5433 table->last = j;
5434
5435 return 0;
5436}
5437
5438static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5439{
5440 bool result = true;
5441
5442 switch (in_reg) {
5443 case MC_SEQ_RAS_TIMING >> 2:
5444 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5445 break;
5446 case MC_SEQ_CAS_TIMING >> 2:
5447 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5448 break;
5449 case MC_SEQ_MISC_TIMING >> 2:
5450 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5451 break;
5452 case MC_SEQ_MISC_TIMING2 >> 2:
5453 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5454 break;
5455 case MC_SEQ_RD_CTL_D0 >> 2:
5456 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5457 break;
5458 case MC_SEQ_RD_CTL_D1 >> 2:
5459 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5460 break;
5461 case MC_SEQ_WR_CTL_D0 >> 2:
5462 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5463 break;
5464 case MC_SEQ_WR_CTL_D1 >> 2:
5465 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5466 break;
5467 case MC_PMG_CMD_EMRS >> 2:
5468 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5469 break;
5470 case MC_PMG_CMD_MRS >> 2:
5471 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5472 break;
5473 case MC_PMG_CMD_MRS1 >> 2:
5474 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5475 break;
5476 case MC_SEQ_PMG_TIMING >> 2:
5477 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5478 break;
5479 case MC_PMG_CMD_MRS2 >> 2:
5480 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5481 break;
5482 case MC_SEQ_WR_CTL_2 >> 2:
5483 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5484 break;
5485 default:
5486 result = false;
5487 break;
5488 }
5489
5490 return result;
5491}
5492
5493static void si_set_valid_flag(struct si_mc_reg_table *table)
5494{
5495 u8 i, j;
5496
5497 for (i = 0; i < table->last; i++) {
5498 for (j = 1; j < table->num_entries; j++) {
5499 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5500 table->valid_flag |= 1 << i;
5501 break;
5502 }
5503 }
5504 }
5505}
5506
5507static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5508{
5509 u32 i;
5510 u16 address;
5511
5512 for (i = 0; i < table->last; i++)
5513 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5514 address : table->mc_reg_address[i].s1;
5515
5516}
5517
5518static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5519 struct si_mc_reg_table *si_table)
5520{
5521 u8 i, j;
5522
5523 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5524 return -EINVAL;
5525 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5526 return -EINVAL;
5527
5528 for (i = 0; i < table->last; i++)
5529 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5530 si_table->last = table->last;
5531
5532 for (i = 0; i < table->num_entries; i++) {
5533 si_table->mc_reg_table_entry[i].mclk_max =
5534 table->mc_reg_table_entry[i].mclk_max;
5535 for (j = 0; j < table->last; j++) {
5536 si_table->mc_reg_table_entry[i].mc_data[j] =
5537 table->mc_reg_table_entry[i].mc_data[j];
5538 }
5539 }
5540 si_table->num_entries = table->num_entries;
5541
5542 return 0;
5543}
5544
5545static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5546{
5547 struct si_power_info *si_pi = si_get_pi(rdev);
5548 struct atom_mc_reg_table *table;
5549 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5550 u8 module_index = rv770_get_memory_module_index(rdev);
5551 int ret;
5552
5553 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5554 if (!table)
5555 return -ENOMEM;
5556
5557 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5558 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5559 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5560 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5561 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5562 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5563 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5564 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5565 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5566 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5567 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5568 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5569 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5570 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5571
5572 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5573 if (ret)
5574 goto init_mc_done;
5575
5576 ret = si_copy_vbios_mc_reg_table(table, si_table);
5577 if (ret)
5578 goto init_mc_done;
5579
5580 si_set_s0_mc_reg_index(si_table);
5581
5582 ret = si_set_mc_special_registers(rdev, si_table);
5583 if (ret)
5584 goto init_mc_done;
5585
5586 si_set_valid_flag(si_table);
5587
5588init_mc_done:
5589 kfree(table);
5590
5591 return ret;
5592
5593}
5594
5595static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5596 SMC_SIslands_MCRegisters *mc_reg_table)
5597{
5598 struct si_power_info *si_pi = si_get_pi(rdev);
5599 u32 i, j;
5600
5601 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5602 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5603 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5604 break;
5605 mc_reg_table->address[i].s0 =
5606 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5607 mc_reg_table->address[i].s1 =
5608 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5609 i++;
5610 }
5611 }
5612 mc_reg_table->last = (u8)i;
5613}
5614
5615static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5616 SMC_SIslands_MCRegisterSet *data,
5617 u32 num_entries, u32 valid_flag)
5618{
5619 u32 i, j;
5620
5621 for(i = 0, j = 0; j < num_entries; j++) {
5622 if (valid_flag & (1 << j)) {
5623 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5624 i++;
5625 }
5626 }
5627}
5628
5629static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5630 struct rv7xx_pl *pl,
5631 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5632{
5633 struct si_power_info *si_pi = si_get_pi(rdev);
5634 u32 i = 0;
5635
5636 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5637 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5638 break;
5639 }
5640
5641 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5642 --i;
5643
5644 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5645 mc_reg_table_data, si_pi->mc_reg_table.last,
5646 si_pi->mc_reg_table.valid_flag);
5647}
5648
5649static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5650 struct radeon_ps *radeon_state,
5651 SMC_SIslands_MCRegisters *mc_reg_table)
5652{
5653 struct ni_ps *state = ni_get_ps(radeon_state);
5654 int i;
5655
5656 for (i = 0; i < state->performance_level_count; i++) {
5657 si_convert_mc_reg_table_entry_to_smc(rdev,
5658 &state->performance_levels[i],
5659 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5660 }
5661}
5662
5663static int si_populate_mc_reg_table(struct radeon_device *rdev,
5664 struct radeon_ps *radeon_boot_state)
5665{
5666 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5667 struct si_power_info *si_pi = si_get_pi(rdev);
5668 struct si_ulv_param *ulv = &si_pi->ulv;
5669 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5670
5671 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5672
5673 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5674
5675 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5676
5677 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5678 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5679
5680 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5681 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5682 si_pi->mc_reg_table.last,
5683 si_pi->mc_reg_table.valid_flag);
5684
5685 if (ulv->supported && ulv->pl.vddc != 0)
5686 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5687 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5688 else
5689 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5690 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5691 si_pi->mc_reg_table.last,
5692 si_pi->mc_reg_table.valid_flag);
5693
5694 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5695
5696 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5697 (u8 *)smc_mc_reg_table,
5698 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5699}
5700
5701static int si_upload_mc_reg_table(struct radeon_device *rdev,
5702 struct radeon_ps *radeon_new_state)
5703{
5704 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5705 struct si_power_info *si_pi = si_get_pi(rdev);
5706 u32 address = si_pi->mc_reg_table_start +
5707 offsetof(SMC_SIslands_MCRegisters,
5708 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5709 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5710
5711 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5712
5713 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5714
5715
5716 return si_copy_bytes_to_smc(rdev, address,
5717 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5718 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5719 si_pi->sram_end);
5720
5721}
5722
5723static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5724{
5725 if (enable)
5726 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5727 else
5728 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5729}
5730
5731static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5732 struct radeon_ps *radeon_state)
5733{
5734 struct ni_ps *state = ni_get_ps(radeon_state);
5735 int i;
5736 u16 pcie_speed, max_speed = 0;
5737
5738 for (i = 0; i < state->performance_level_count; i++) {
5739 pcie_speed = state->performance_levels[i].pcie_gen;
5740 if (max_speed < pcie_speed)
5741 max_speed = pcie_speed;
5742 }
5743 return max_speed;
5744}
5745
5746static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5747{
5748 u32 speed_cntl;
5749
5750 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5751 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5752
5753 return (u16)speed_cntl;
5754}
5755
5756static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5757 struct radeon_ps *radeon_new_state,
5758 struct radeon_ps *radeon_current_state)
5759{
5760 struct si_power_info *si_pi = si_get_pi(rdev);
5761 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5762 enum radeon_pcie_gen current_link_speed;
5763
5764 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5765 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5766 else
5767 current_link_speed = si_pi->force_pcie_gen;
5768
5769 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5770 si_pi->pspp_notify_required = false;
5771 if (target_link_speed > current_link_speed) {
5772 switch (target_link_speed) {
5773#if defined(CONFIG_ACPI)
5774 case RADEON_PCIE_GEN3:
5775 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5776 break;
5777 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5778 if (current_link_speed == RADEON_PCIE_GEN2)
5779 break;
5780 case RADEON_PCIE_GEN2:
5781 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5782 break;
5783#endif
5784 default:
5785 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5786 break;
5787 }
5788 } else {
5789 if (target_link_speed < current_link_speed)
5790 si_pi->pspp_notify_required = true;
5791 }
5792}
5793
5794static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5795 struct radeon_ps *radeon_new_state,
5796 struct radeon_ps *radeon_current_state)
5797{
5798 struct si_power_info *si_pi = si_get_pi(rdev);
5799 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5800 u8 request;
5801
5802 if (si_pi->pspp_notify_required) {
5803 if (target_link_speed == RADEON_PCIE_GEN3)
5804 request = PCIE_PERF_REQ_PECI_GEN3;
5805 else if (target_link_speed == RADEON_PCIE_GEN2)
5806 request = PCIE_PERF_REQ_PECI_GEN2;
5807 else
5808 request = PCIE_PERF_REQ_PECI_GEN1;
5809
5810 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5811 (si_get_current_pcie_speed(rdev) > 0))
5812 return;
5813
5814#if defined(CONFIG_ACPI)
5815 radeon_acpi_pcie_performance_request(rdev, request, false);
5816#endif
5817 }
5818}
5819
5820#if 0
5821static int si_ds_request(struct radeon_device *rdev,
5822 bool ds_status_on, u32 count_write)
5823{
5824 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5825
5826 if (eg_pi->sclk_deep_sleep) {
5827 if (ds_status_on)
5828 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5829 PPSMC_Result_OK) ?
5830 0 : -EINVAL;
5831 else
5832 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5833 PPSMC_Result_OK) ? 0 : -EINVAL;
5834 }
5835 return 0;
5836}
5837#endif
5838
5839static void si_set_max_cu_value(struct radeon_device *rdev)
5840{
5841 struct si_power_info *si_pi = si_get_pi(rdev);
5842
5843 if (rdev->family == CHIP_VERDE) {
5844 switch (rdev->pdev->device) {
5845 case 0x6820:
5846 case 0x6825:
5847 case 0x6821:
5848 case 0x6823:
5849 case 0x6827:
5850 si_pi->max_cu = 10;
5851 break;
5852 case 0x682D:
5853 case 0x6824:
5854 case 0x682F:
5855 case 0x6826:
5856 si_pi->max_cu = 8;
5857 break;
5858 case 0x6828:
5859 case 0x6830:
5860 case 0x6831:
5861 case 0x6838:
5862 case 0x6839:
5863 case 0x683D:
5864 si_pi->max_cu = 10;
5865 break;
5866 case 0x683B:
5867 case 0x683F:
5868 case 0x6829:
5869 si_pi->max_cu = 8;
5870 break;
5871 default:
5872 si_pi->max_cu = 0;
5873 break;
5874 }
5875 } else {
5876 si_pi->max_cu = 0;
5877 }
5878}
5879
5880static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5881 struct radeon_clock_voltage_dependency_table *table)
5882{
5883 u32 i;
5884 int j;
5885 u16 leakage_voltage;
5886
5887 if (table) {
5888 for (i = 0; i < table->count; i++) {
5889 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5890 table->entries[i].v,
5891 &leakage_voltage)) {
5892 case 0:
5893 table->entries[i].v = leakage_voltage;
5894 break;
5895 case -EAGAIN:
5896 return -EINVAL;
5897 case -EINVAL:
5898 default:
5899 break;
5900 }
5901 }
5902
5903 for (j = (table->count - 2); j >= 0; j--) {
5904 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5905 table->entries[j].v : table->entries[j + 1].v;
5906 }
5907 }
5908 return 0;
5909}
5910
5911static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5912{
5913 int ret = 0;
5914
5915 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5916 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5917 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5918 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5919 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5920 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5921 return ret;
5922}
5923
5924static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5925 struct radeon_ps *radeon_new_state,
5926 struct radeon_ps *radeon_current_state)
5927{
5928 u32 lane_width;
5929 u32 new_lane_width =
5930 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5931 u32 current_lane_width =
5932 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5933
5934 if (new_lane_width != current_lane_width) {
5935 radeon_set_pcie_lanes(rdev, new_lane_width);
5936 lane_width = radeon_get_pcie_lanes(rdev);
5937 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5938 }
5939}
5940
5941static void si_set_vce_clock(struct radeon_device *rdev,
5942 struct radeon_ps *new_rps,
5943 struct radeon_ps *old_rps)
5944{
5945 if ((old_rps->evclk != new_rps->evclk) ||
5946 (old_rps->ecclk != new_rps->ecclk)) {
5947 /* turn the clocks on when encoding, off otherwise */
5948 if (new_rps->evclk || new_rps->ecclk)
5949 vce_v1_0_enable_mgcg(rdev, false);
5950 else
5951 vce_v1_0_enable_mgcg(rdev, true);
5952 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5953 }
5954}
5955
5956void si_dpm_setup_asic(struct radeon_device *rdev)
5957{
5958 int r;
5959
5960 r = si_mc_load_microcode(rdev);
5961 if (r)
5962 DRM_ERROR("Failed to load MC firmware!\n");
5963 rv770_get_memory_type(rdev);
5964 si_read_clock_registers(rdev);
5965 si_enable_acpi_power_management(rdev);
5966}
5967
5968static int si_thermal_enable_alert(struct radeon_device *rdev,
5969 bool enable)
5970{
5971 u32 thermal_int = RREG32(CG_THERMAL_INT);
5972
5973 if (enable) {
5974 PPSMC_Result result;
5975
5976 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5977 WREG32(CG_THERMAL_INT, thermal_int);
5978 rdev->irq.dpm_thermal = false;
5979 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5980 if (result != PPSMC_Result_OK) {
5981 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5982 return -EINVAL;
5983 }
5984 } else {
5985 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5986 WREG32(CG_THERMAL_INT, thermal_int);
5987 rdev->irq.dpm_thermal = true;
5988 }
5989
5990 return 0;
5991}
5992
5993static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5994 int min_temp, int max_temp)
5995{
5996 int low_temp = 0 * 1000;
5997 int high_temp = 255 * 1000;
5998
5999 if (low_temp < min_temp)
6000 low_temp = min_temp;
6001 if (high_temp > max_temp)
6002 high_temp = max_temp;
6003 if (high_temp < low_temp) {
6004 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6005 return -EINVAL;
6006 }
6007
6008 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6009 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6010 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6011
6012 rdev->pm.dpm.thermal.min_temp = low_temp;
6013 rdev->pm.dpm.thermal.max_temp = high_temp;
6014
6015 return 0;
6016}
6017
6018static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6019{
6020 struct si_power_info *si_pi = si_get_pi(rdev);
6021 u32 tmp;
6022
6023 if (si_pi->fan_ctrl_is_in_default_mode) {
6024 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6025 si_pi->fan_ctrl_default_mode = tmp;
6026 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6027 si_pi->t_min = tmp;
6028 si_pi->fan_ctrl_is_in_default_mode = false;
6029 }
6030
6031 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6032 tmp |= TMIN(0);
6033 WREG32(CG_FDO_CTRL2, tmp);
6034
6035 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6036 tmp |= FDO_PWM_MODE(mode);
6037 WREG32(CG_FDO_CTRL2, tmp);
6038}
6039
6040static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6041{
6042 struct si_power_info *si_pi = si_get_pi(rdev);
6043 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6044 u32 duty100;
6045 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6046 u16 fdo_min, slope1, slope2;
6047 u32 reference_clock, tmp;
6048 int ret;
6049 u64 tmp64;
6050
6051 if (!si_pi->fan_table_start) {
6052 rdev->pm.dpm.fan.ucode_fan_control = false;
6053 return 0;
6054 }
6055
6056 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6057
6058 if (duty100 == 0) {
6059 rdev->pm.dpm.fan.ucode_fan_control = false;
6060 return 0;
6061 }
6062
6063 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6064 do_div(tmp64, 10000);
6065 fdo_min = (u16)tmp64;
6066
6067 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6068 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6069
6070 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6071 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6072
6073 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6074 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6075
6076 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6077 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6078 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6079
6080 fan_table.slope1 = cpu_to_be16(slope1);
6081 fan_table.slope2 = cpu_to_be16(slope2);
6082
6083 fan_table.fdo_min = cpu_to_be16(fdo_min);
6084
6085 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6086
6087 fan_table.hys_up = cpu_to_be16(1);
6088
6089 fan_table.hys_slope = cpu_to_be16(1);
6090
6091 fan_table.temp_resp_lim = cpu_to_be16(5);
6092
6093 reference_clock = radeon_get_xclk(rdev);
6094
6095 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6096 reference_clock) / 1600);
6097
6098 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6099
6100 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6101 fan_table.temp_src = (uint8_t)tmp;
6102
6103 ret = si_copy_bytes_to_smc(rdev,
6104 si_pi->fan_table_start,
6105 (u8 *)(&fan_table),
6106 sizeof(fan_table),
6107 si_pi->sram_end);
6108
6109 if (ret) {
6110 DRM_ERROR("Failed to load fan table to the SMC.");
6111 rdev->pm.dpm.fan.ucode_fan_control = false;
6112 }
6113
6114 return 0;
6115}
6116
6117static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6118{
6119 struct si_power_info *si_pi = si_get_pi(rdev);
6120 PPSMC_Result ret;
6121
6122 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6123 if (ret == PPSMC_Result_OK) {
6124 si_pi->fan_is_controlled_by_smc = true;
6125 return 0;
6126 } else {
6127 return -EINVAL;
6128 }
6129}
6130
6131static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6132{
6133 struct si_power_info *si_pi = si_get_pi(rdev);
6134 PPSMC_Result ret;
6135
6136 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6137
6138 if (ret == PPSMC_Result_OK) {
6139 si_pi->fan_is_controlled_by_smc = false;
6140 return 0;
6141 } else {
6142 return -EINVAL;
6143 }
6144}
6145
6146int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6147 u32 *speed)
6148{
6149 u32 duty, duty100;
6150 u64 tmp64;
6151
6152 if (rdev->pm.no_fan)
6153 return -ENOENT;
6154
6155 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6156 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6157
6158 if (duty100 == 0)
6159 return -EINVAL;
6160
6161 tmp64 = (u64)duty * 100;
6162 do_div(tmp64, duty100);
6163 *speed = (u32)tmp64;
6164
6165 if (*speed > 100)
6166 *speed = 100;
6167
6168 return 0;
6169}
6170
6171int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6172 u32 speed)
6173{
6174 struct si_power_info *si_pi = si_get_pi(rdev);
6175 u32 tmp;
6176 u32 duty, duty100;
6177 u64 tmp64;
6178
6179 if (rdev->pm.no_fan)
6180 return -ENOENT;
6181
6182 if (si_pi->fan_is_controlled_by_smc)
6183 return -EINVAL;
6184
6185 if (speed > 100)
6186 return -EINVAL;
6187
6188 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6189
6190 if (duty100 == 0)
6191 return -EINVAL;
6192
6193 tmp64 = (u64)speed * duty100;
6194 do_div(tmp64, 100);
6195 duty = (u32)tmp64;
6196
6197 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6198 tmp |= FDO_STATIC_DUTY(duty);
6199 WREG32(CG_FDO_CTRL0, tmp);
6200
6201 return 0;
6202}
6203
6204void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6205{
6206 if (mode) {
6207 /* stop auto-manage */
6208 if (rdev->pm.dpm.fan.ucode_fan_control)
6209 si_fan_ctrl_stop_smc_fan_control(rdev);
6210 si_fan_ctrl_set_static_mode(rdev, mode);
6211 } else {
6212 /* restart auto-manage */
6213 if (rdev->pm.dpm.fan.ucode_fan_control)
6214 si_thermal_start_smc_fan_control(rdev);
6215 else
6216 si_fan_ctrl_set_default_mode(rdev);
6217 }
6218}
6219
6220u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6221{
6222 struct si_power_info *si_pi = si_get_pi(rdev);
6223 u32 tmp;
6224
6225 if (si_pi->fan_is_controlled_by_smc)
6226 return 0;
6227
6228 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6229 return (tmp >> FDO_PWM_MODE_SHIFT);
6230}
6231
6232#if 0
6233static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6234 u32 *speed)
6235{
6236 u32 tach_period;
6237 u32 xclk = radeon_get_xclk(rdev);
6238
6239 if (rdev->pm.no_fan)
6240 return -ENOENT;
6241
6242 if (rdev->pm.fan_pulses_per_revolution == 0)
6243 return -ENOENT;
6244
6245 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6246 if (tach_period == 0)
6247 return -ENOENT;
6248
6249 *speed = 60 * xclk * 10000 / tach_period;
6250
6251 return 0;
6252}
6253
6254static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6255 u32 speed)
6256{
6257 u32 tach_period, tmp;
6258 u32 xclk = radeon_get_xclk(rdev);
6259
6260 if (rdev->pm.no_fan)
6261 return -ENOENT;
6262
6263 if (rdev->pm.fan_pulses_per_revolution == 0)
6264 return -ENOENT;
6265
6266 if ((speed < rdev->pm.fan_min_rpm) ||
6267 (speed > rdev->pm.fan_max_rpm))
6268 return -EINVAL;
6269
6270 if (rdev->pm.dpm.fan.ucode_fan_control)
6271 si_fan_ctrl_stop_smc_fan_control(rdev);
6272
6273 tach_period = 60 * xclk * 10000 / (8 * speed);
6274 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6275 tmp |= TARGET_PERIOD(tach_period);
6276 WREG32(CG_TACH_CTRL, tmp);
6277
6278 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6279
6280 return 0;
6281}
6282#endif
6283
6284static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6285{
6286 struct si_power_info *si_pi = si_get_pi(rdev);
6287 u32 tmp;
6288
6289 if (!si_pi->fan_ctrl_is_in_default_mode) {
6290 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6291 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6292 WREG32(CG_FDO_CTRL2, tmp);
6293
6294 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6295 tmp |= TMIN(si_pi->t_min);
6296 WREG32(CG_FDO_CTRL2, tmp);
6297 si_pi->fan_ctrl_is_in_default_mode = true;
6298 }
6299}
6300
6301static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6302{
6303 if (rdev->pm.dpm.fan.ucode_fan_control) {
6304 si_fan_ctrl_start_smc_fan_control(rdev);
6305 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6306 }
6307}
6308
6309static void si_thermal_initialize(struct radeon_device *rdev)
6310{
6311 u32 tmp;
6312
6313 if (rdev->pm.fan_pulses_per_revolution) {
6314 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6315 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6316 WREG32(CG_TACH_CTRL, tmp);
6317 }
6318
6319 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6320 tmp |= TACH_PWM_RESP_RATE(0x28);
6321 WREG32(CG_FDO_CTRL2, tmp);
6322}
6323
6324static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6325{
6326 int ret;
6327
6328 si_thermal_initialize(rdev);
6329 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6330 if (ret)
6331 return ret;
6332 ret = si_thermal_enable_alert(rdev, true);
6333 if (ret)
6334 return ret;
6335 if (rdev->pm.dpm.fan.ucode_fan_control) {
6336 ret = si_halt_smc(rdev);
6337 if (ret)
6338 return ret;
6339 ret = si_thermal_setup_fan_table(rdev);
6340 if (ret)
6341 return ret;
6342 ret = si_resume_smc(rdev);
6343 if (ret)
6344 return ret;
6345 si_thermal_start_smc_fan_control(rdev);
6346 }
6347
6348 return 0;
6349}
6350
6351static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6352{
6353 if (!rdev->pm.no_fan) {
6354 si_fan_ctrl_set_default_mode(rdev);
6355 si_fan_ctrl_stop_smc_fan_control(rdev);
6356 }
6357}
6358
6359int si_dpm_enable(struct radeon_device *rdev)
6360{
6361 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6362 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6363 struct si_power_info *si_pi = si_get_pi(rdev);
6364 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6365 int ret;
6366
6367 if (si_is_smc_running(rdev))
6368 return -EINVAL;
6369 if (pi->voltage_control || si_pi->voltage_control_svi2)
6370 si_enable_voltage_control(rdev, true);
6371 if (pi->mvdd_control)
6372 si_get_mvdd_configuration(rdev);
6373 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6374 ret = si_construct_voltage_tables(rdev);
6375 if (ret) {
6376 DRM_ERROR("si_construct_voltage_tables failed\n");
6377 return ret;
6378 }
6379 }
6380 if (eg_pi->dynamic_ac_timing) {
6381 ret = si_initialize_mc_reg_table(rdev);
6382 if (ret)
6383 eg_pi->dynamic_ac_timing = false;
6384 }
6385 if (pi->dynamic_ss)
6386 si_enable_spread_spectrum(rdev, true);
6387 if (pi->thermal_protection)
6388 si_enable_thermal_protection(rdev, true);
6389 si_setup_bsp(rdev);
6390 si_program_git(rdev);
6391 si_program_tp(rdev);
6392 si_program_tpp(rdev);
6393 si_program_sstp(rdev);
6394 si_enable_display_gap(rdev);
6395 si_program_vc(rdev);
6396 ret = si_upload_firmware(rdev);
6397 if (ret) {
6398 DRM_ERROR("si_upload_firmware failed\n");
6399 return ret;
6400 }
6401 ret = si_process_firmware_header(rdev);
6402 if (ret) {
6403 DRM_ERROR("si_process_firmware_header failed\n");
6404 return ret;
6405 }
6406 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6407 if (ret) {
6408 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6409 return ret;
6410 }
6411 ret = si_init_smc_table(rdev);
6412 if (ret) {
6413 DRM_ERROR("si_init_smc_table failed\n");
6414 return ret;
6415 }
6416 ret = si_init_smc_spll_table(rdev);
6417 if (ret) {
6418 DRM_ERROR("si_init_smc_spll_table failed\n");
6419 return ret;
6420 }
6421 ret = si_init_arb_table_index(rdev);
6422 if (ret) {
6423 DRM_ERROR("si_init_arb_table_index failed\n");
6424 return ret;
6425 }
6426 if (eg_pi->dynamic_ac_timing) {
6427 ret = si_populate_mc_reg_table(rdev, boot_ps);
6428 if (ret) {
6429 DRM_ERROR("si_populate_mc_reg_table failed\n");
6430 return ret;
6431 }
6432 }
6433 ret = si_initialize_smc_cac_tables(rdev);
6434 if (ret) {
6435 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6436 return ret;
6437 }
6438 ret = si_initialize_hardware_cac_manager(rdev);
6439 if (ret) {
6440 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6441 return ret;
6442 }
6443 ret = si_initialize_smc_dte_tables(rdev);
6444 if (ret) {
6445 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6446 return ret;
6447 }
6448 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6449 if (ret) {
6450 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6451 return ret;
6452 }
6453 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6454 if (ret) {
6455 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6456 return ret;
6457 }
6458 si_program_response_times(rdev);
6459 si_program_ds_registers(rdev);
6460 si_dpm_start_smc(rdev);
6461 ret = si_notify_smc_display_change(rdev, false);
6462 if (ret) {
6463 DRM_ERROR("si_notify_smc_display_change failed\n");
6464 return ret;
6465 }
6466 si_enable_sclk_control(rdev, true);
6467 si_start_dpm(rdev);
6468
6469 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6470
6471 si_thermal_start_thermal_controller(rdev);
6472
6473 ni_update_current_ps(rdev, boot_ps);
6474
6475 return 0;
6476}
6477
6478static int si_set_temperature_range(struct radeon_device *rdev)
6479{
6480 int ret;
6481
6482 ret = si_thermal_enable_alert(rdev, false);
6483 if (ret)
6484 return ret;
6485 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6486 if (ret)
6487 return ret;
6488 ret = si_thermal_enable_alert(rdev, true);
6489 if (ret)
6490 return ret;
6491
6492 return ret;
6493}
6494
6495int si_dpm_late_enable(struct radeon_device *rdev)
6496{
6497 int ret;
6498
6499 ret = si_set_temperature_range(rdev);
6500 if (ret)
6501 return ret;
6502
6503 return ret;
6504}
6505
6506void si_dpm_disable(struct radeon_device *rdev)
6507{
6508 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6509 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6510
6511 if (!si_is_smc_running(rdev))
6512 return;
6513 si_thermal_stop_thermal_controller(rdev);
6514 si_disable_ulv(rdev);
6515 si_clear_vc(rdev);
6516 if (pi->thermal_protection)
6517 si_enable_thermal_protection(rdev, false);
6518 si_enable_power_containment(rdev, boot_ps, false);
6519 si_enable_smc_cac(rdev, boot_ps, false);
6520 si_enable_spread_spectrum(rdev, false);
6521 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6522 si_stop_dpm(rdev);
6523 si_reset_to_default(rdev);
6524 si_dpm_stop_smc(rdev);
6525 si_force_switch_to_arb_f0(rdev);
6526
6527 ni_update_current_ps(rdev, boot_ps);
6528}
6529
6530int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6531{
6532 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6533 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6534 struct radeon_ps *new_ps = &requested_ps;
6535
6536 ni_update_requested_ps(rdev, new_ps);
6537
6538 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6539
6540 return 0;
6541}
6542
6543static int si_power_control_set_level(struct radeon_device *rdev)
6544{
6545 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6546 int ret;
6547
6548 ret = si_restrict_performance_levels_before_switch(rdev);
6549 if (ret)
6550 return ret;
6551 ret = si_halt_smc(rdev);
6552 if (ret)
6553 return ret;
6554 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6555 if (ret)
6556 return ret;
6557 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6558 if (ret)
6559 return ret;
6560 ret = si_resume_smc(rdev);
6561 if (ret)
6562 return ret;
6563 ret = si_set_sw_state(rdev);
6564 if (ret)
6565 return ret;
6566 return 0;
6567}
6568
6569int si_dpm_set_power_state(struct radeon_device *rdev)
6570{
6571 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6572 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6573 struct radeon_ps *old_ps = &eg_pi->current_rps;
6574 int ret;
6575
6576 ret = si_disable_ulv(rdev);
6577 if (ret) {
6578 DRM_ERROR("si_disable_ulv failed\n");
6579 return ret;
6580 }
6581 ret = si_restrict_performance_levels_before_switch(rdev);
6582 if (ret) {
6583 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6584 return ret;
6585 }
6586 if (eg_pi->pcie_performance_request)
6587 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6588 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6589 ret = si_enable_power_containment(rdev, new_ps, false);
6590 if (ret) {
6591 DRM_ERROR("si_enable_power_containment failed\n");
6592 return ret;
6593 }
6594 ret = si_enable_smc_cac(rdev, new_ps, false);
6595 if (ret) {
6596 DRM_ERROR("si_enable_smc_cac failed\n");
6597 return ret;
6598 }
6599 ret = si_halt_smc(rdev);
6600 if (ret) {
6601 DRM_ERROR("si_halt_smc failed\n");
6602 return ret;
6603 }
6604 ret = si_upload_sw_state(rdev, new_ps);
6605 if (ret) {
6606 DRM_ERROR("si_upload_sw_state failed\n");
6607 return ret;
6608 }
6609 ret = si_upload_smc_data(rdev);
6610 if (ret) {
6611 DRM_ERROR("si_upload_smc_data failed\n");
6612 return ret;
6613 }
6614 ret = si_upload_ulv_state(rdev);
6615 if (ret) {
6616 DRM_ERROR("si_upload_ulv_state failed\n");
6617 return ret;
6618 }
6619 if (eg_pi->dynamic_ac_timing) {
6620 ret = si_upload_mc_reg_table(rdev, new_ps);
6621 if (ret) {
6622 DRM_ERROR("si_upload_mc_reg_table failed\n");
6623 return ret;
6624 }
6625 }
6626 ret = si_program_memory_timing_parameters(rdev, new_ps);
6627 if (ret) {
6628 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6629 return ret;
6630 }
6631 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6632
6633 ret = si_resume_smc(rdev);
6634 if (ret) {
6635 DRM_ERROR("si_resume_smc failed\n");
6636 return ret;
6637 }
6638 ret = si_set_sw_state(rdev);
6639 if (ret) {
6640 DRM_ERROR("si_set_sw_state failed\n");
6641 return ret;
6642 }
6643 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6644 si_set_vce_clock(rdev, new_ps, old_ps);
6645 if (eg_pi->pcie_performance_request)
6646 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6647 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6648 if (ret) {
6649 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6650 return ret;
6651 }
6652 ret = si_enable_smc_cac(rdev, new_ps, true);
6653 if (ret) {
6654 DRM_ERROR("si_enable_smc_cac failed\n");
6655 return ret;
6656 }
6657 ret = si_enable_power_containment(rdev, new_ps, true);
6658 if (ret) {
6659 DRM_ERROR("si_enable_power_containment failed\n");
6660 return ret;
6661 }
6662
6663 ret = si_power_control_set_level(rdev);
6664 if (ret) {
6665 DRM_ERROR("si_power_control_set_level failed\n");
6666 return ret;
6667 }
6668
6669 return 0;
6670}
6671
6672void si_dpm_post_set_power_state(struct radeon_device *rdev)
6673{
6674 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6675 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6676
6677 ni_update_current_ps(rdev, new_ps);
6678}
6679
6680#if 0
6681void si_dpm_reset_asic(struct radeon_device *rdev)
6682{
6683 si_restrict_performance_levels_before_switch(rdev);
6684 si_disable_ulv(rdev);
6685 si_set_boot_state(rdev);
6686}
6687#endif
6688
6689void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6690{
6691 si_program_display_gap(rdev);
6692}
6693
6694union power_info {
6695 struct _ATOM_POWERPLAY_INFO info;
6696 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6697 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6698 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6699 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6700 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6701};
6702
6703union pplib_clock_info {
6704 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6705 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6706 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6707 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6708 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6709};
6710
6711union pplib_power_state {
6712 struct _ATOM_PPLIB_STATE v1;
6713 struct _ATOM_PPLIB_STATE_V2 v2;
6714};
6715
6716static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6717 struct radeon_ps *rps,
6718 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6719 u8 table_rev)
6720{
6721 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6722 rps->class = le16_to_cpu(non_clock_info->usClassification);
6723 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6724
6725 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6726 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6727 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6728 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6729 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6730 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6731 } else {
6732 rps->vclk = 0;
6733 rps->dclk = 0;
6734 }
6735
6736 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6737 rdev->pm.dpm.boot_ps = rps;
6738 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6739 rdev->pm.dpm.uvd_ps = rps;
6740}
6741
6742static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6743 struct radeon_ps *rps, int index,
6744 union pplib_clock_info *clock_info)
6745{
6746 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6747 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6748 struct si_power_info *si_pi = si_get_pi(rdev);
6749 struct ni_ps *ps = ni_get_ps(rps);
6750 u16 leakage_voltage;
6751 struct rv7xx_pl *pl = &ps->performance_levels[index];
6752 int ret;
6753
6754 ps->performance_level_count = index + 1;
6755
6756 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6757 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6758 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6759 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6760
6761 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6762 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6763 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6764 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6765 si_pi->sys_pcie_mask,
6766 si_pi->boot_pcie_gen,
6767 clock_info->si.ucPCIEGen);
6768
6769 /* patch up vddc if necessary */
6770 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6771 &leakage_voltage);
6772 if (ret == 0)
6773 pl->vddc = leakage_voltage;
6774
6775 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6776 pi->acpi_vddc = pl->vddc;
6777 eg_pi->acpi_vddci = pl->vddci;
6778 si_pi->acpi_pcie_gen = pl->pcie_gen;
6779 }
6780
6781 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6782 index == 0) {
6783 /* XXX disable for A0 tahiti */
6784 si_pi->ulv.supported = false;
6785 si_pi->ulv.pl = *pl;
6786 si_pi->ulv.one_pcie_lane_in_ulv = false;
6787 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6788 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6789 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6790 }
6791
6792 if (pi->min_vddc_in_table > pl->vddc)
6793 pi->min_vddc_in_table = pl->vddc;
6794
6795 if (pi->max_vddc_in_table < pl->vddc)
6796 pi->max_vddc_in_table = pl->vddc;
6797
6798 /* patch up boot state */
6799 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6800 u16 vddc, vddci, mvdd;
6801 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6802 pl->mclk = rdev->clock.default_mclk;
6803 pl->sclk = rdev->clock.default_sclk;
6804 pl->vddc = vddc;
6805 pl->vddci = vddci;
6806 si_pi->mvdd_bootup_value = mvdd;
6807 }
6808
6809 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6810 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6811 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6812 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6813 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6814 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6815 }
6816}
6817
6818static int si_parse_power_table(struct radeon_device *rdev)
6819{
6820 struct radeon_mode_info *mode_info = &rdev->mode_info;
6821 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6822 union pplib_power_state *power_state;
6823 int i, j, k, non_clock_array_index, clock_array_index;
6824 union pplib_clock_info *clock_info;
6825 struct _StateArray *state_array;
6826 struct _ClockInfoArray *clock_info_array;
6827 struct _NonClockInfoArray *non_clock_info_array;
6828 union power_info *power_info;
6829 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6830 u16 data_offset;
6831 u8 frev, crev;
6832 u8 *power_state_offset;
6833 struct ni_ps *ps;
6834
6835 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6836 &frev, &crev, &data_offset))
6837 return -EINVAL;
6838 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6839
6840 state_array = (struct _StateArray *)
6841 (mode_info->atom_context->bios + data_offset +
6842 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6843 clock_info_array = (struct _ClockInfoArray *)
6844 (mode_info->atom_context->bios + data_offset +
6845 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6846 non_clock_info_array = (struct _NonClockInfoArray *)
6847 (mode_info->atom_context->bios + data_offset +
6848 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6849
6850 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6851 state_array->ucNumEntries, GFP_KERNEL);
6852 if (!rdev->pm.dpm.ps)
6853 return -ENOMEM;
6854 power_state_offset = (u8 *)state_array->states;
6855 for (i = 0; i < state_array->ucNumEntries; i++) {
6856 u8 *idx;
6857 power_state = (union pplib_power_state *)power_state_offset;
6858 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6859 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6860 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6861 if (!rdev->pm.power_state[i].clock_info)
6862 return -EINVAL;
6863 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6864 if (ps == NULL) {
6865 kfree(rdev->pm.dpm.ps);
6866 return -ENOMEM;
6867 }
6868 rdev->pm.dpm.ps[i].ps_priv = ps;
6869 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6870 non_clock_info,
6871 non_clock_info_array->ucEntrySize);
6872 k = 0;
6873 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6874 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6875 clock_array_index = idx[j];
6876 if (clock_array_index >= clock_info_array->ucNumEntries)
6877 continue;
6878 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6879 break;
6880 clock_info = (union pplib_clock_info *)
6881 ((u8 *)&clock_info_array->clockInfo[0] +
6882 (clock_array_index * clock_info_array->ucEntrySize));
6883 si_parse_pplib_clock_info(rdev,
6884 &rdev->pm.dpm.ps[i], k,
6885 clock_info);
6886 k++;
6887 }
6888 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6889 }
6890 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6891
6892 /* fill in the vce power states */
6893 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6894 u32 sclk, mclk;
6895 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6896 clock_info = (union pplib_clock_info *)
6897 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6898 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6899 sclk |= clock_info->si.ucEngineClockHigh << 16;
6900 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6901 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6902 rdev->pm.dpm.vce_states[i].sclk = sclk;
6903 rdev->pm.dpm.vce_states[i].mclk = mclk;
6904 }
6905
6906 return 0;
6907}
6908
6909int si_dpm_init(struct radeon_device *rdev)
6910{
6911 struct rv7xx_power_info *pi;
6912 struct evergreen_power_info *eg_pi;
6913 struct ni_power_info *ni_pi;
6914 struct si_power_info *si_pi;
6915 struct atom_clock_dividers dividers;
6916 int ret;
6917 u32 mask;
6918
6919 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6920 if (si_pi == NULL)
6921 return -ENOMEM;
6922 rdev->pm.dpm.priv = si_pi;
6923 ni_pi = &si_pi->ni;
6924 eg_pi = &ni_pi->eg;
6925 pi = &eg_pi->rv7xx;
6926
6927 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6928 if (ret)
6929 si_pi->sys_pcie_mask = 0;
6930 else
6931 si_pi->sys_pcie_mask = mask;
6932 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6933 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6934
6935 si_set_max_cu_value(rdev);
6936
6937 rv770_get_max_vddc(rdev);
6938 si_get_leakage_vddc(rdev);
6939 si_patch_dependency_tables_based_on_leakage(rdev);
6940
6941 pi->acpi_vddc = 0;
6942 eg_pi->acpi_vddci = 0;
6943 pi->min_vddc_in_table = 0;
6944 pi->max_vddc_in_table = 0;
6945
6946 ret = r600_get_platform_caps(rdev);
6947 if (ret)
6948 return ret;
6949
6950 ret = r600_parse_extended_power_table(rdev);
6951 if (ret)
6952 return ret;
6953
6954 ret = si_parse_power_table(rdev);
6955 if (ret)
6956 return ret;
6957
6958 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6959 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6960 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6961 r600_free_extended_power_table(rdev);
6962 return -ENOMEM;
6963 }
6964 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6965 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6966 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6967 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6968 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6969 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6970 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6971 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6972 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6973
6974 if (rdev->pm.dpm.voltage_response_time == 0)
6975 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6976 if (rdev->pm.dpm.backbias_response_time == 0)
6977 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6978
6979 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6980 0, false, ÷rs);
6981 if (ret)
6982 pi->ref_div = dividers.ref_div + 1;
6983 else
6984 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6985
6986 eg_pi->smu_uvd_hs = false;
6987
6988 pi->mclk_strobe_mode_threshold = 40000;
6989 if (si_is_special_1gb_platform(rdev))
6990 pi->mclk_stutter_mode_threshold = 0;
6991 else
6992 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6993 pi->mclk_edc_enable_threshold = 40000;
6994 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6995
6996 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6997
6998 pi->voltage_control =
6999 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7000 VOLTAGE_OBJ_GPIO_LUT);
7001 if (!pi->voltage_control) {
7002 si_pi->voltage_control_svi2 =
7003 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7004 VOLTAGE_OBJ_SVID2);
7005 if (si_pi->voltage_control_svi2)
7006 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7007 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7008 }
7009
7010 pi->mvdd_control =
7011 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7012 VOLTAGE_OBJ_GPIO_LUT);
7013
7014 eg_pi->vddci_control =
7015 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7016 VOLTAGE_OBJ_GPIO_LUT);
7017 if (!eg_pi->vddci_control)
7018 si_pi->vddci_control_svi2 =
7019 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7020 VOLTAGE_OBJ_SVID2);
7021
7022 si_pi->vddc_phase_shed_control =
7023 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7024 VOLTAGE_OBJ_PHASE_LUT);
7025
7026 rv770_get_engine_memory_ss(rdev);
7027
7028 pi->asi = RV770_ASI_DFLT;
7029 pi->pasi = CYPRESS_HASI_DFLT;
7030 pi->vrc = SISLANDS_VRC_DFLT;
7031
7032 pi->gfx_clock_gating = true;
7033
7034 eg_pi->sclk_deep_sleep = true;
7035 si_pi->sclk_deep_sleep_above_low = false;
7036
7037 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7038 pi->thermal_protection = true;
7039 else
7040 pi->thermal_protection = false;
7041
7042 eg_pi->dynamic_ac_timing = true;
7043
7044 eg_pi->light_sleep = true;
7045#if defined(CONFIG_ACPI)
7046 eg_pi->pcie_performance_request =
7047 radeon_acpi_is_pcie_performance_request_supported(rdev);
7048#else
7049 eg_pi->pcie_performance_request = false;
7050#endif
7051
7052 si_pi->sram_end = SMC_RAM_END;
7053
7054 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7055 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7056 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7057 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7058 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7059 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7060 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7061
7062 si_initialize_powertune_defaults(rdev);
7063
7064 /* make sure dc limits are valid */
7065 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7066 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7067 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7068 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7069
7070 si_pi->fan_ctrl_is_in_default_mode = true;
7071
7072 return 0;
7073}
7074
7075void si_dpm_fini(struct radeon_device *rdev)
7076{
7077 int i;
7078
7079 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7080 kfree(rdev->pm.dpm.ps[i].ps_priv);
7081 }
7082 kfree(rdev->pm.dpm.ps);
7083 kfree(rdev->pm.dpm.priv);
7084 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7085 r600_free_extended_power_table(rdev);
7086}
7087
7088void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7089 struct seq_file *m)
7090{
7091 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7092 struct radeon_ps *rps = &eg_pi->current_rps;
7093 struct ni_ps *ps = ni_get_ps(rps);
7094 struct rv7xx_pl *pl;
7095 u32 current_index =
7096 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7097 CURRENT_STATE_INDEX_SHIFT;
7098
7099 if (current_index >= ps->performance_level_count) {
7100 seq_printf(m, "invalid dpm profile %d\n", current_index);
7101 } else {
7102 pl = &ps->performance_levels[current_index];
7103 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7104 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7105 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7106 }
7107}
7108
7109u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7110{
7111 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7112 struct radeon_ps *rps = &eg_pi->current_rps;
7113 struct ni_ps *ps = ni_get_ps(rps);
7114 struct rv7xx_pl *pl;
7115 u32 current_index =
7116 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7117 CURRENT_STATE_INDEX_SHIFT;
7118
7119 if (current_index >= ps->performance_level_count) {
7120 return 0;
7121 } else {
7122 pl = &ps->performance_levels[current_index];
7123 return pl->sclk;
7124 }
7125}
7126
7127u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7128{
7129 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7130 struct radeon_ps *rps = &eg_pi->current_rps;
7131 struct ni_ps *ps = ni_get_ps(rps);
7132 struct rv7xx_pl *pl;
7133 u32 current_index =
7134 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7135 CURRENT_STATE_INDEX_SHIFT;
7136
7137 if (current_index >= ps->performance_level_count) {
7138 return 0;
7139 } else {
7140 pl = &ps->performance_levels[current_index];
7141 return pl->mclk;
7142 }
7143}
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/math64.h>
25#include <linux/pci.h>
26#include <linux/seq_file.h>
27
28#include "atom.h"
29#include "r600_dpm.h"
30#include "radeon.h"
31#include "radeon_asic.h"
32#include "si_dpm.h"
33#include "sid.h"
34
35#define MC_CG_ARB_FREQ_F0 0x0a
36#define MC_CG_ARB_FREQ_F1 0x0b
37#define MC_CG_ARB_FREQ_F2 0x0c
38#define MC_CG_ARB_FREQ_F3 0x0d
39
40#define SMC_RAM_END 0x20000
41
42#define SCLK_MIN_DEEPSLEEP_FREQ 1350
43
44static const struct si_cac_config_reg cac_weights_tahiti[] =
45{
46 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
47 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
49 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
50 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
56 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
58 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
59 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
61 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
63 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
64 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
65 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
67 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
68 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
77 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
80 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
81 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
83 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
84 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
86 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
105 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
106 { 0xFFFFFFFF }
107};
108
109static const struct si_cac_config_reg lcac_tahiti[] =
110{
111 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
112 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
114 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
116 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
118 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
120 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
122 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
124 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
126 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
128 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
130 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
132 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
134 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
136 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
138 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
140 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
142 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
144 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
146 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
148 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
150 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
152 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
154 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
156 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
158 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
160 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
162 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
164 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
166 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
168 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
170 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
172 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
174 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
176 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
178 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
180 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
182 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
184 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
186 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
188 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
190 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
192 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
194 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
196 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
197 { 0xFFFFFFFF }
198
199};
200
201static const struct si_cac_config_reg cac_override_tahiti[] =
202{
203 { 0xFFFFFFFF }
204};
205
206static const struct si_powertune_data powertune_data_tahiti =
207{
208 ((1 << 16) | 27027),
209 6,
210 0,
211 4,
212 95,
213 {
214 0UL,
215 0UL,
216 4521550UL,
217 309631529UL,
218 -1270850L,
219 4513710L,
220 40
221 },
222 595000000UL,
223 12,
224 {
225 0,
226 0,
227 0,
228 0,
229 0,
230 0,
231 0,
232 0
233 },
234 true
235};
236
237static const struct si_dte_data dte_data_tahiti =
238{
239 { 1159409, 0, 0, 0, 0 },
240 { 777, 0, 0, 0, 0 },
241 2,
242 54000,
243 127000,
244 25,
245 2,
246 10,
247 13,
248 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
249 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
250 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
251 85,
252 false
253};
254
255static const struct si_dte_data dte_data_tahiti_pro =
256{
257 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
258 { 0x0, 0x0, 0x0, 0x0, 0x0 },
259 5,
260 45000,
261 100,
262 0xA,
263 1,
264 0,
265 0x10,
266 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
267 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
268 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
269 90,
270 true
271};
272
273static const struct si_dte_data dte_data_new_zealand =
274{
275 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
276 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
277 0x5,
278 0xAFC8,
279 0x69,
280 0x32,
281 1,
282 0,
283 0x10,
284 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
285 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
286 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
287 85,
288 true
289};
290
291static const struct si_dte_data dte_data_aruba_pro =
292{
293 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
294 { 0x0, 0x0, 0x0, 0x0, 0x0 },
295 5,
296 45000,
297 100,
298 0xA,
299 1,
300 0,
301 0x10,
302 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
303 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
304 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
305 90,
306 true
307};
308
309static const struct si_dte_data dte_data_malta =
310{
311 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
312 { 0x0, 0x0, 0x0, 0x0, 0x0 },
313 5,
314 45000,
315 100,
316 0xA,
317 1,
318 0,
319 0x10,
320 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
321 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
322 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
323 90,
324 true
325};
326
327struct si_cac_config_reg cac_weights_pitcairn[] =
328{
329 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
330 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
331 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
332 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
333 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
334 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
335 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
336 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
337 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
338 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
339 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
340 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
341 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
342 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
343 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
344 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
345 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
346 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
347 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
348 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
349 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
350 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
351 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
352 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
354 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
355 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
356 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
357 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
358 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
359 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
360 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
362 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
364 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
365 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
366 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
367 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
368 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
369 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
372 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
373 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
377 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
379 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
381 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
382 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
383 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
385 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
389 { 0xFFFFFFFF }
390};
391
392static const struct si_cac_config_reg lcac_pitcairn[] =
393{
394 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
395 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
396 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
397 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
398 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
399 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
400 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
401 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
402 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
403 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
404 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
405 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
406 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
407 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
408 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
409 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
410 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
411 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
412 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
413 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
414 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
415 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
416 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
417 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
418 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
419 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
420 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
421 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
422 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
423 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
424 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
425 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
426 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
427 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
428 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
429 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
430 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
431 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
432 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
433 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
434 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
435 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
436 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
437 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
438 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
439 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
440 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
441 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
442 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
443 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
444 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
445 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
446 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
447 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
448 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
449 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
450 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
451 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
452 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
453 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
454 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
455 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
456 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
457 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
458 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
459 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
460 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
461 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
462 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
463 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
464 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
465 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
466 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
467 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
468 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
469 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
470 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
471 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
472 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
473 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
474 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
475 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
476 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
477 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
478 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
479 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
480 { 0xFFFFFFFF }
481};
482
483static const struct si_cac_config_reg cac_override_pitcairn[] =
484{
485 { 0xFFFFFFFF }
486};
487
488static const struct si_powertune_data powertune_data_pitcairn =
489{
490 ((1 << 16) | 27027),
491 5,
492 0,
493 6,
494 100,
495 {
496 51600000UL,
497 1800000UL,
498 7194395UL,
499 309631529UL,
500 -1270850L,
501 4513710L,
502 100
503 },
504 117830498UL,
505 12,
506 {
507 0,
508 0,
509 0,
510 0,
511 0,
512 0,
513 0,
514 0
515 },
516 true
517};
518
519static const struct si_dte_data dte_data_pitcairn =
520{
521 { 0, 0, 0, 0, 0 },
522 { 0, 0, 0, 0, 0 },
523 0,
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
531 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
532 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
533 0,
534 false
535};
536
537static const struct si_dte_data dte_data_curacao_xt =
538{
539 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
540 { 0x0, 0x0, 0x0, 0x0, 0x0 },
541 5,
542 45000,
543 100,
544 0xA,
545 1,
546 0,
547 0x10,
548 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
549 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
550 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
551 90,
552 true
553};
554
555static const struct si_dte_data dte_data_curacao_pro =
556{
557 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
558 { 0x0, 0x0, 0x0, 0x0, 0x0 },
559 5,
560 45000,
561 100,
562 0xA,
563 1,
564 0,
565 0x10,
566 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
567 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
568 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
569 90,
570 true
571};
572
573static const struct si_dte_data dte_data_neptune_xt =
574{
575 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
576 { 0x0, 0x0, 0x0, 0x0, 0x0 },
577 5,
578 45000,
579 100,
580 0xA,
581 1,
582 0,
583 0x10,
584 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
585 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
586 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
587 90,
588 true
589};
590
591static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
592{
593 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
594 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
595 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
596 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
597 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
598 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
599 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
600 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
601 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
602 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
603 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
604 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
605 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
606 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
607 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
608 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
609 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
610 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
611 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
612 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
613 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
614 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
615 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
616 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
617 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
618 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
619 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
620 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
621 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
622 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
623 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
624 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
625 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
626 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
627 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
628 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
629 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
630 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
631 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
632 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
633 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
634 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
635 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
636 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
637 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
639 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
640 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
641 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
642 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
643 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
644 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
645 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
646 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
647 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
648 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
649 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
650 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
651 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
652 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
653 { 0xFFFFFFFF }
654};
655
656static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
657{
658 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
659 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
660 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
661 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
662 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
663 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
664 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
665 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
666 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
667 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
668 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
669 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
670 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
671 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
672 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
673 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
674 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
675 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
676 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
677 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
678 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
679 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
680 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
681 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
682 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
683 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
684 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
685 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
686 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
687 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
688 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
689 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
690 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
691 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
692 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
693 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
694 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
695 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
696 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
697 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
698 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
699 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
700 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
701 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
702 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
704 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
705 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
706 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
707 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
708 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
709 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
710 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
711 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
712 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
713 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
714 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
715 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
716 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
717 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
718 { 0xFFFFFFFF }
719};
720
721static const struct si_cac_config_reg cac_weights_heathrow[] =
722{
723 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
724 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
725 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
726 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
727 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
728 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
729 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
730 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
731 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
732 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
733 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
734 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
735 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
736 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
737 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
738 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
739 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
740 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
741 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
742 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
743 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
744 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
745 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
746 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
747 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
748 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
749 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
750 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
751 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
752 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
753 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
754 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
755 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
756 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
757 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
758 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
759 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
760 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
761 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
762 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
763 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
764 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
765 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
766 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
767 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
769 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
770 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
771 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
772 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
773 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
774 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
775 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
776 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
777 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
778 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
779 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
780 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
781 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
782 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
783 { 0xFFFFFFFF }
784};
785
786static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
787{
788 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
789 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
790 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
791 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
792 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
793 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
794 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
795 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
796 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
797 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
798 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
799 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
800 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
801 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
802 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
803 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
804 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
805 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
806 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
807 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
808 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
809 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
810 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
811 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
812 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
813 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
814 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
815 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
816 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
817 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
818 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
819 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
820 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
821 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
822 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
823 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
824 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
825 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
826 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
827 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
828 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
829 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
830 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
831 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
832 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
834 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
835 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
836 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
837 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
838 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
839 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
840 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
841 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
842 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
843 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
844 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
845 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
846 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
847 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
848 { 0xFFFFFFFF }
849};
850
851static const struct si_cac_config_reg cac_weights_cape_verde[] =
852{
853 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
854 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
855 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
856 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
857 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
858 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
859 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
860 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
861 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
862 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
863 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
864 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
865 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
866 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
867 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
868 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
869 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
870 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
871 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
872 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
873 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
874 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
875 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
876 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
877 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
878 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
879 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
880 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
881 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
882 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
883 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
884 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
885 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
886 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
887 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
888 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
889 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
890 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
891 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
892 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
893 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
894 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
895 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
896 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
897 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
899 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
900 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
901 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
902 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
903 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
904 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
905 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
906 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
907 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
908 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
909 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
910 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
911 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
912 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
913 { 0xFFFFFFFF }
914};
915
916static const struct si_cac_config_reg lcac_cape_verde[] =
917{
918 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
919 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
920 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
921 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
922 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
923 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
924 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
925 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
926 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
927 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
928 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
929 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
930 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
931 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
932 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
933 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
934 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
935 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
936 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
937 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
938 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
940 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
943 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
944 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
945 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
947 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
948 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
949 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
950 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
951 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
952 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
953 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
954 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
955 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
957 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
959 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
960 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
962 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
963 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
964 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
966 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
968 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
970 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
972 { 0xFFFFFFFF }
973};
974
975static const struct si_cac_config_reg cac_override_cape_verde[] =
976{
977 { 0xFFFFFFFF }
978};
979
980static const struct si_powertune_data powertune_data_cape_verde =
981{
982 ((1 << 16) | 0x6993),
983 5,
984 0,
985 7,
986 105,
987 {
988 0UL,
989 0UL,
990 7194395UL,
991 309631529UL,
992 -1270850L,
993 4513710L,
994 100
995 },
996 117830498UL,
997 12,
998 {
999 0,
1000 0,
1001 0,
1002 0,
1003 0,
1004 0,
1005 0,
1006 0
1007 },
1008 true
1009};
1010
1011static const struct si_dte_data dte_data_cape_verde =
1012{
1013 { 0, 0, 0, 0, 0 },
1014 { 0, 0, 0, 0, 0 },
1015 0,
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1023 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1024 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1025 0,
1026 false
1027};
1028
1029static const struct si_dte_data dte_data_venus_xtx =
1030{
1031 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1032 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1033 5,
1034 55000,
1035 0x69,
1036 0xA,
1037 1,
1038 0,
1039 0x3,
1040 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1041 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1042 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1043 90,
1044 true
1045};
1046
1047static const struct si_dte_data dte_data_venus_xt =
1048{
1049 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1050 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1051 5,
1052 55000,
1053 0x69,
1054 0xA,
1055 1,
1056 0,
1057 0x3,
1058 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1061 90,
1062 true
1063};
1064
1065static const struct si_dte_data dte_data_venus_pro =
1066{
1067 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1068 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1069 5,
1070 55000,
1071 0x69,
1072 0xA,
1073 1,
1074 0,
1075 0x3,
1076 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1079 90,
1080 true
1081};
1082
1083struct si_cac_config_reg cac_weights_oland[] =
1084{
1085 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1086 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1087 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1088 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1089 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1090 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1091 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1092 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1093 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1094 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1095 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1096 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1097 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1098 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1099 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1100 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1101 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1102 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1103 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1104 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1105 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1106 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1107 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1108 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1109 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1110 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1111 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1112 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1113 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1114 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1115 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1116 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1117 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1118 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1119 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1120 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1121 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1122 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1123 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1124 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1125 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1126 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1127 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1128 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1131 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1132 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1133 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1134 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1135 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1136 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1137 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1138 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1140 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1142 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1143 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1145 { 0xFFFFFFFF }
1146};
1147
1148static const struct si_cac_config_reg cac_weights_mars_pro[] =
1149{
1150 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1151 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1154 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1157 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1159 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1160 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1162 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1163 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1164 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1165 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1166 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1167 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1168 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1169 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1170 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1171 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1172 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1173 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1174 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1175 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1176 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1177 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1178 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1179 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1180 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1181 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1182 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1183 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1184 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1185 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1186 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1187 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1188 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1189 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1190 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1191 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1192 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1193 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1194 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1195 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1196 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1197 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1199 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1200 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1201 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1202 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1205 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1207 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1208 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1210 { 0xFFFFFFFF }
1211};
1212
1213static const struct si_cac_config_reg cac_weights_mars_xt[] =
1214{
1215 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1216 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1219 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1222 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1224 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1225 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1227 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1228 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1229 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1230 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1231 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1232 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1233 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1234 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1235 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1236 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1237 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1238 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1239 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1240 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1241 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1242 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1243 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1244 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1245 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1246 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1247 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1248 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1249 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1250 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1251 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1253 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1254 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1255 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1256 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1257 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1258 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1259 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1260 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1262 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1265 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1266 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1267 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1270 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1272 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1273 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1275 { 0xFFFFFFFF }
1276};
1277
1278static const struct si_cac_config_reg cac_weights_oland_pro[] =
1279{
1280 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1281 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1284 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1287 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1289 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1290 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1292 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1293 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1294 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1295 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1296 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1297 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1298 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1299 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1300 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1301 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1302 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1303 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1304 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1305 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1306 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1307 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1308 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1309 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1310 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1311 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1312 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1313 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1314 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1315 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1316 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1318 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1319 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1320 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1321 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1322 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1323 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1324 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1325 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1327 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1330 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1331 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1332 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1335 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1337 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1338 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1340 { 0xFFFFFFFF }
1341};
1342
1343static const struct si_cac_config_reg cac_weights_oland_xt[] =
1344{
1345 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1346 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1349 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1352 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1354 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1355 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1357 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1358 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1359 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1360 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1361 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1362 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1363 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1364 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1365 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1366 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1367 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1368 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1369 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1370 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1371 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1372 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1373 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1374 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1375 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1376 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1377 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1378 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1379 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1380 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1381 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1383 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1384 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1385 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1392 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1395 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1396 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1400 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1402 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1403 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1405 { 0xFFFFFFFF }
1406};
1407
1408static const struct si_cac_config_reg lcac_oland[] =
1409{
1410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1414 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1416 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1418 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1420 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1422 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1423 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1424 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1425 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1426 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1427 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0xFFFFFFFF }
1453};
1454
1455static const struct si_cac_config_reg lcac_mars_pro[] =
1456{
1457 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1458 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1460 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1462 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1464 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1466 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1468 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1470 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1471 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1472 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1473 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0xFFFFFFFF }
1500};
1501
1502static const struct si_cac_config_reg cac_override_oland[] =
1503{
1504 { 0xFFFFFFFF }
1505};
1506
1507static const struct si_powertune_data powertune_data_oland =
1508{
1509 ((1 << 16) | 0x6993),
1510 5,
1511 0,
1512 7,
1513 105,
1514 {
1515 0UL,
1516 0UL,
1517 7194395UL,
1518 309631529UL,
1519 -1270850L,
1520 4513710L,
1521 100
1522 },
1523 117830498UL,
1524 12,
1525 {
1526 0,
1527 0,
1528 0,
1529 0,
1530 0,
1531 0,
1532 0,
1533 0
1534 },
1535 true
1536};
1537
1538static const struct si_powertune_data powertune_data_mars_pro =
1539{
1540 ((1 << 16) | 0x6993),
1541 5,
1542 0,
1543 7,
1544 105,
1545 {
1546 0UL,
1547 0UL,
1548 7194395UL,
1549 309631529UL,
1550 -1270850L,
1551 4513710L,
1552 100
1553 },
1554 117830498UL,
1555 12,
1556 {
1557 0,
1558 0,
1559 0,
1560 0,
1561 0,
1562 0,
1563 0,
1564 0
1565 },
1566 true
1567};
1568
1569static const struct si_dte_data dte_data_oland =
1570{
1571 { 0, 0, 0, 0, 0 },
1572 { 0, 0, 0, 0, 0 },
1573 0,
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1581 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1582 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1583 0,
1584 false
1585};
1586
1587static const struct si_dte_data dte_data_mars_pro =
1588{
1589 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1590 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1591 5,
1592 55000,
1593 105,
1594 0xA,
1595 1,
1596 0,
1597 0x10,
1598 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1599 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1600 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1601 90,
1602 true
1603};
1604
1605static const struct si_dte_data dte_data_sun_xt =
1606{
1607 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1608 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1609 5,
1610 55000,
1611 105,
1612 0xA,
1613 1,
1614 0,
1615 0x10,
1616 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1617 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1618 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1619 90,
1620 true
1621};
1622
1623
1624static const struct si_cac_config_reg cac_weights_hainan[] =
1625{
1626 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1627 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1628 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1629 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1630 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1631 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1632 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1633 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1634 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1635 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1636 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1637 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1638 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1639 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1640 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1641 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1642 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1643 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1644 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1645 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1646 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1647 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1648 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1649 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1650 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1652 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1653 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1654 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1655 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1656 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1657 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1661 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1662 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1663 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1664 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1665 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1666 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1668 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1669 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1674 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1678 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1679 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1680 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1683 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1685 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1686 { 0xFFFFFFFF }
1687};
1688
1689static const struct si_powertune_data powertune_data_hainan =
1690{
1691 ((1 << 16) | 0x6993),
1692 5,
1693 0,
1694 9,
1695 105,
1696 {
1697 0UL,
1698 0UL,
1699 7194395UL,
1700 309631529UL,
1701 -1270850L,
1702 4513710L,
1703 100
1704 },
1705 117830498UL,
1706 12,
1707 {
1708 0,
1709 0,
1710 0,
1711 0,
1712 0,
1713 0,
1714 0,
1715 0
1716 },
1717 true
1718};
1719
1720struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1721struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1722struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1723struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1724
1725extern int si_mc_load_microcode(struct radeon_device *rdev);
1726extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1727
1728static int si_populate_voltage_value(struct radeon_device *rdev,
1729 const struct atom_voltage_table *table,
1730 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1731static int si_get_std_voltage_value(struct radeon_device *rdev,
1732 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1733 u16 *std_voltage);
1734static int si_write_smc_soft_register(struct radeon_device *rdev,
1735 u16 reg_offset, u32 value);
1736static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1737 struct rv7xx_pl *pl,
1738 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1739static int si_calculate_sclk_params(struct radeon_device *rdev,
1740 u32 engine_clock,
1741 SISLANDS_SMC_SCLK_VALUE *sclk);
1742
1743static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1744static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1745
1746static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1747{
1748 struct si_power_info *pi = rdev->pm.dpm.priv;
1749
1750 return pi;
1751}
1752
1753static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1754 u16 v, s32 t, u32 ileakage, u32 *leakage)
1755{
1756 s64 kt, kv, leakage_w, i_leakage, vddc;
1757 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1758 s64 tmp;
1759
1760 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1761 vddc = div64_s64(drm_int2fixp(v), 1000);
1762 temperature = div64_s64(drm_int2fixp(t), 1000);
1763
1764 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1765 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1766 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1767 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1768 t_ref = drm_int2fixp(coeff->t_ref);
1769
1770 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1771 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1772 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1773 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1774
1775 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1776
1777 *leakage = drm_fixp2int(leakage_w * 1000);
1778}
1779
1780static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1781 const struct ni_leakage_coeffients *coeff,
1782 u16 v,
1783 s32 t,
1784 u32 i_leakage,
1785 u32 *leakage)
1786{
1787 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1788}
1789
1790static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1791 const u32 fixed_kt, u16 v,
1792 u32 ileakage, u32 *leakage)
1793{
1794 s64 kt, kv, leakage_w, i_leakage, vddc;
1795
1796 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1797 vddc = div64_s64(drm_int2fixp(v), 1000);
1798
1799 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1800 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1801 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1802
1803 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1804
1805 *leakage = drm_fixp2int(leakage_w * 1000);
1806}
1807
1808static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1809 const struct ni_leakage_coeffients *coeff,
1810 const u32 fixed_kt,
1811 u16 v,
1812 u32 i_leakage,
1813 u32 *leakage)
1814{
1815 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1816}
1817
1818
1819static void si_update_dte_from_pl2(struct radeon_device *rdev,
1820 struct si_dte_data *dte_data)
1821{
1822 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1823 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1824 u32 k = dte_data->k;
1825 u32 t_max = dte_data->max_t;
1826 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1827 u32 t_0 = dte_data->t0;
1828 u32 i;
1829
1830 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1831 dte_data->tdep_count = 3;
1832
1833 for (i = 0; i < k; i++) {
1834 dte_data->r[i] =
1835 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1836 (p_limit2 * (u32)100);
1837 }
1838
1839 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1840
1841 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1842 dte_data->tdep_r[i] = dte_data->r[4];
1843 }
1844 } else {
1845 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1846 }
1847}
1848
1849static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1850{
1851 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1852 struct si_power_info *si_pi = si_get_pi(rdev);
1853 bool update_dte_from_pl2 = false;
1854
1855 if (rdev->family == CHIP_TAHITI) {
1856 si_pi->cac_weights = cac_weights_tahiti;
1857 si_pi->lcac_config = lcac_tahiti;
1858 si_pi->cac_override = cac_override_tahiti;
1859 si_pi->powertune_data = &powertune_data_tahiti;
1860 si_pi->dte_data = dte_data_tahiti;
1861
1862 switch (rdev->pdev->device) {
1863 case 0x6798:
1864 si_pi->dte_data.enable_dte_by_default = true;
1865 break;
1866 case 0x6799:
1867 si_pi->dte_data = dte_data_new_zealand;
1868 break;
1869 case 0x6790:
1870 case 0x6791:
1871 case 0x6792:
1872 case 0x679E:
1873 si_pi->dte_data = dte_data_aruba_pro;
1874 update_dte_from_pl2 = true;
1875 break;
1876 case 0x679B:
1877 si_pi->dte_data = dte_data_malta;
1878 update_dte_from_pl2 = true;
1879 break;
1880 case 0x679A:
1881 si_pi->dte_data = dte_data_tahiti_pro;
1882 update_dte_from_pl2 = true;
1883 break;
1884 default:
1885 if (si_pi->dte_data.enable_dte_by_default == true)
1886 DRM_ERROR("DTE is not enabled!\n");
1887 break;
1888 }
1889 } else if (rdev->family == CHIP_PITCAIRN) {
1890 switch (rdev->pdev->device) {
1891 case 0x6810:
1892 case 0x6818:
1893 si_pi->cac_weights = cac_weights_pitcairn;
1894 si_pi->lcac_config = lcac_pitcairn;
1895 si_pi->cac_override = cac_override_pitcairn;
1896 si_pi->powertune_data = &powertune_data_pitcairn;
1897 si_pi->dte_data = dte_data_curacao_xt;
1898 update_dte_from_pl2 = true;
1899 break;
1900 case 0x6819:
1901 case 0x6811:
1902 si_pi->cac_weights = cac_weights_pitcairn;
1903 si_pi->lcac_config = lcac_pitcairn;
1904 si_pi->cac_override = cac_override_pitcairn;
1905 si_pi->powertune_data = &powertune_data_pitcairn;
1906 si_pi->dte_data = dte_data_curacao_pro;
1907 update_dte_from_pl2 = true;
1908 break;
1909 case 0x6800:
1910 case 0x6806:
1911 si_pi->cac_weights = cac_weights_pitcairn;
1912 si_pi->lcac_config = lcac_pitcairn;
1913 si_pi->cac_override = cac_override_pitcairn;
1914 si_pi->powertune_data = &powertune_data_pitcairn;
1915 si_pi->dte_data = dte_data_neptune_xt;
1916 update_dte_from_pl2 = true;
1917 break;
1918 default:
1919 si_pi->cac_weights = cac_weights_pitcairn;
1920 si_pi->lcac_config = lcac_pitcairn;
1921 si_pi->cac_override = cac_override_pitcairn;
1922 si_pi->powertune_data = &powertune_data_pitcairn;
1923 si_pi->dte_data = dte_data_pitcairn;
1924 break;
1925 }
1926 } else if (rdev->family == CHIP_VERDE) {
1927 si_pi->lcac_config = lcac_cape_verde;
1928 si_pi->cac_override = cac_override_cape_verde;
1929 si_pi->powertune_data = &powertune_data_cape_verde;
1930
1931 switch (rdev->pdev->device) {
1932 case 0x683B:
1933 case 0x683F:
1934 case 0x6829:
1935 case 0x6835:
1936 si_pi->cac_weights = cac_weights_cape_verde_pro;
1937 si_pi->dte_data = dte_data_cape_verde;
1938 break;
1939 case 0x682C:
1940 si_pi->cac_weights = cac_weights_cape_verde_pro;
1941 si_pi->dte_data = dte_data_sun_xt;
1942 update_dte_from_pl2 = true;
1943 break;
1944 case 0x6825:
1945 case 0x6827:
1946 si_pi->cac_weights = cac_weights_heathrow;
1947 si_pi->dte_data = dte_data_cape_verde;
1948 break;
1949 case 0x6824:
1950 case 0x682D:
1951 si_pi->cac_weights = cac_weights_chelsea_xt;
1952 si_pi->dte_data = dte_data_cape_verde;
1953 break;
1954 case 0x682F:
1955 si_pi->cac_weights = cac_weights_chelsea_pro;
1956 si_pi->dte_data = dte_data_cape_verde;
1957 break;
1958 case 0x6820:
1959 si_pi->cac_weights = cac_weights_heathrow;
1960 si_pi->dte_data = dte_data_venus_xtx;
1961 break;
1962 case 0x6821:
1963 si_pi->cac_weights = cac_weights_heathrow;
1964 si_pi->dte_data = dte_data_venus_xt;
1965 break;
1966 case 0x6823:
1967 case 0x682B:
1968 case 0x6822:
1969 case 0x682A:
1970 si_pi->cac_weights = cac_weights_chelsea_pro;
1971 si_pi->dte_data = dte_data_venus_pro;
1972 break;
1973 default:
1974 si_pi->cac_weights = cac_weights_cape_verde;
1975 si_pi->dte_data = dte_data_cape_verde;
1976 break;
1977 }
1978 } else if (rdev->family == CHIP_OLAND) {
1979 switch (rdev->pdev->device) {
1980 case 0x6601:
1981 case 0x6621:
1982 case 0x6603:
1983 case 0x6605:
1984 si_pi->cac_weights = cac_weights_mars_pro;
1985 si_pi->lcac_config = lcac_mars_pro;
1986 si_pi->cac_override = cac_override_oland;
1987 si_pi->powertune_data = &powertune_data_mars_pro;
1988 si_pi->dte_data = dte_data_mars_pro;
1989 update_dte_from_pl2 = true;
1990 break;
1991 case 0x6600:
1992 case 0x6606:
1993 case 0x6620:
1994 case 0x6604:
1995 si_pi->cac_weights = cac_weights_mars_xt;
1996 si_pi->lcac_config = lcac_mars_pro;
1997 si_pi->cac_override = cac_override_oland;
1998 si_pi->powertune_data = &powertune_data_mars_pro;
1999 si_pi->dte_data = dte_data_mars_pro;
2000 update_dte_from_pl2 = true;
2001 break;
2002 case 0x6611:
2003 case 0x6613:
2004 case 0x6608:
2005 si_pi->cac_weights = cac_weights_oland_pro;
2006 si_pi->lcac_config = lcac_mars_pro;
2007 si_pi->cac_override = cac_override_oland;
2008 si_pi->powertune_data = &powertune_data_mars_pro;
2009 si_pi->dte_data = dte_data_mars_pro;
2010 update_dte_from_pl2 = true;
2011 break;
2012 case 0x6610:
2013 si_pi->cac_weights = cac_weights_oland_xt;
2014 si_pi->lcac_config = lcac_mars_pro;
2015 si_pi->cac_override = cac_override_oland;
2016 si_pi->powertune_data = &powertune_data_mars_pro;
2017 si_pi->dte_data = dte_data_mars_pro;
2018 update_dte_from_pl2 = true;
2019 break;
2020 default:
2021 si_pi->cac_weights = cac_weights_oland;
2022 si_pi->lcac_config = lcac_oland;
2023 si_pi->cac_override = cac_override_oland;
2024 si_pi->powertune_data = &powertune_data_oland;
2025 si_pi->dte_data = dte_data_oland;
2026 break;
2027 }
2028 } else if (rdev->family == CHIP_HAINAN) {
2029 si_pi->cac_weights = cac_weights_hainan;
2030 si_pi->lcac_config = lcac_oland;
2031 si_pi->cac_override = cac_override_oland;
2032 si_pi->powertune_data = &powertune_data_hainan;
2033 si_pi->dte_data = dte_data_sun_xt;
2034 update_dte_from_pl2 = true;
2035 } else {
2036 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2037 return;
2038 }
2039
2040 ni_pi->enable_power_containment = false;
2041 ni_pi->enable_cac = false;
2042 ni_pi->enable_sq_ramping = false;
2043 si_pi->enable_dte = false;
2044
2045 if (si_pi->powertune_data->enable_powertune_by_default) {
2046 ni_pi->enable_power_containment= true;
2047 ni_pi->enable_cac = true;
2048 if (si_pi->dte_data.enable_dte_by_default) {
2049 si_pi->enable_dte = true;
2050 if (update_dte_from_pl2)
2051 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2052
2053 }
2054 ni_pi->enable_sq_ramping = true;
2055 }
2056
2057 ni_pi->driver_calculate_cac_leakage = true;
2058 ni_pi->cac_configuration_required = true;
2059
2060 if (ni_pi->cac_configuration_required) {
2061 ni_pi->support_cac_long_term_average = true;
2062 si_pi->dyn_powertune_data.l2_lta_window_size =
2063 si_pi->powertune_data->l2_lta_window_size_default;
2064 si_pi->dyn_powertune_data.lts_truncate =
2065 si_pi->powertune_data->lts_truncate_default;
2066 } else {
2067 ni_pi->support_cac_long_term_average = false;
2068 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2069 si_pi->dyn_powertune_data.lts_truncate = 0;
2070 }
2071
2072 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2073}
2074
2075static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2076{
2077 return 1;
2078}
2079
2080static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2081{
2082 u32 xclk;
2083 u32 wintime;
2084 u32 cac_window;
2085 u32 cac_window_size;
2086
2087 xclk = radeon_get_xclk(rdev);
2088
2089 if (xclk == 0)
2090 return 0;
2091
2092 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2093 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2094
2095 wintime = (cac_window_size * 100) / xclk;
2096
2097 return wintime;
2098}
2099
2100static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2101{
2102 return power_in_watts;
2103}
2104
2105static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2106 bool adjust_polarity,
2107 u32 tdp_adjustment,
2108 u32 *tdp_limit,
2109 u32 *near_tdp_limit)
2110{
2111 u32 adjustment_delta, max_tdp_limit;
2112
2113 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2114 return -EINVAL;
2115
2116 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2117
2118 if (adjust_polarity) {
2119 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2120 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2121 } else {
2122 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2123 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2124 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2125 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2126 else
2127 *near_tdp_limit = 0;
2128 }
2129
2130 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2131 return -EINVAL;
2132 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2133 return -EINVAL;
2134
2135 return 0;
2136}
2137
2138static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2139 struct radeon_ps *radeon_state)
2140{
2141 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2142 struct si_power_info *si_pi = si_get_pi(rdev);
2143
2144 if (ni_pi->enable_power_containment) {
2145 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2146 PP_SIslands_PAPMParameters *papm_parm;
2147 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2148 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2149 u32 tdp_limit;
2150 u32 near_tdp_limit;
2151 int ret;
2152
2153 if (scaling_factor == 0)
2154 return -EINVAL;
2155
2156 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2157
2158 ret = si_calculate_adjusted_tdp_limits(rdev,
2159 false, /* ??? */
2160 rdev->pm.dpm.tdp_adjustment,
2161 &tdp_limit,
2162 &near_tdp_limit);
2163 if (ret)
2164 return ret;
2165
2166 smc_table->dpm2Params.TDPLimit =
2167 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2168 smc_table->dpm2Params.NearTDPLimit =
2169 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2170 smc_table->dpm2Params.SafePowerLimit =
2171 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2172
2173 ret = si_copy_bytes_to_smc(rdev,
2174 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2175 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2176 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2177 sizeof(u32) * 3,
2178 si_pi->sram_end);
2179 if (ret)
2180 return ret;
2181
2182 if (si_pi->enable_ppm) {
2183 papm_parm = &si_pi->papm_parm;
2184 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2185 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2186 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2187 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2188 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2189 papm_parm->PlatformPowerLimit = 0xffffffff;
2190 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2191
2192 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2193 (u8 *)papm_parm,
2194 sizeof(PP_SIslands_PAPMParameters),
2195 si_pi->sram_end);
2196 if (ret)
2197 return ret;
2198 }
2199 }
2200 return 0;
2201}
2202
2203static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2204 struct radeon_ps *radeon_state)
2205{
2206 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2207 struct si_power_info *si_pi = si_get_pi(rdev);
2208
2209 if (ni_pi->enable_power_containment) {
2210 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2211 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2212 int ret;
2213
2214 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2215
2216 smc_table->dpm2Params.NearTDPLimit =
2217 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2218 smc_table->dpm2Params.SafePowerLimit =
2219 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2220
2221 ret = si_copy_bytes_to_smc(rdev,
2222 (si_pi->state_table_start +
2223 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2224 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2225 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2226 sizeof(u32) * 2,
2227 si_pi->sram_end);
2228 if (ret)
2229 return ret;
2230 }
2231
2232 return 0;
2233}
2234
2235static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2236 const u16 prev_std_vddc,
2237 const u16 curr_std_vddc)
2238{
2239 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2240 u64 prev_vddc = (u64)prev_std_vddc;
2241 u64 curr_vddc = (u64)curr_std_vddc;
2242 u64 pwr_efficiency_ratio, n, d;
2243
2244 if ((prev_vddc == 0) || (curr_vddc == 0))
2245 return 0;
2246
2247 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2248 d = prev_vddc * prev_vddc;
2249 pwr_efficiency_ratio = div64_u64(n, d);
2250
2251 if (pwr_efficiency_ratio > (u64)0xFFFF)
2252 return 0;
2253
2254 return (u16)pwr_efficiency_ratio;
2255}
2256
2257static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2258 struct radeon_ps *radeon_state)
2259{
2260 struct si_power_info *si_pi = si_get_pi(rdev);
2261
2262 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2263 radeon_state->vclk && radeon_state->dclk)
2264 return true;
2265
2266 return false;
2267}
2268
2269static int si_populate_power_containment_values(struct radeon_device *rdev,
2270 struct radeon_ps *radeon_state,
2271 SISLANDS_SMC_SWSTATE *smc_state)
2272{
2273 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2274 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2275 struct ni_ps *state = ni_get_ps(radeon_state);
2276 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2277 u32 prev_sclk;
2278 u32 max_sclk;
2279 u32 min_sclk;
2280 u16 prev_std_vddc;
2281 u16 curr_std_vddc;
2282 int i;
2283 u16 pwr_efficiency_ratio;
2284 u8 max_ps_percent;
2285 bool disable_uvd_power_tune;
2286 int ret;
2287
2288 if (ni_pi->enable_power_containment == false)
2289 return 0;
2290
2291 if (state->performance_level_count == 0)
2292 return -EINVAL;
2293
2294 if (smc_state->levelCount != state->performance_level_count)
2295 return -EINVAL;
2296
2297 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2298
2299 smc_state->levels[0].dpm2.MaxPS = 0;
2300 smc_state->levels[0].dpm2.NearTDPDec = 0;
2301 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2302 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2303 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2304
2305 for (i = 1; i < state->performance_level_count; i++) {
2306 prev_sclk = state->performance_levels[i-1].sclk;
2307 max_sclk = state->performance_levels[i].sclk;
2308 if (i == 1)
2309 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2310 else
2311 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2312
2313 if (prev_sclk > max_sclk)
2314 return -EINVAL;
2315
2316 if ((max_ps_percent == 0) ||
2317 (prev_sclk == max_sclk) ||
2318 disable_uvd_power_tune) {
2319 min_sclk = max_sclk;
2320 } else if (i == 1) {
2321 min_sclk = prev_sclk;
2322 } else {
2323 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2324 }
2325
2326 if (min_sclk < state->performance_levels[0].sclk)
2327 min_sclk = state->performance_levels[0].sclk;
2328
2329 if (min_sclk == 0)
2330 return -EINVAL;
2331
2332 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2333 state->performance_levels[i-1].vddc, &vddc);
2334 if (ret)
2335 return ret;
2336
2337 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2338 if (ret)
2339 return ret;
2340
2341 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2342 state->performance_levels[i].vddc, &vddc);
2343 if (ret)
2344 return ret;
2345
2346 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2347 if (ret)
2348 return ret;
2349
2350 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2351 prev_std_vddc, curr_std_vddc);
2352
2353 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2354 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2355 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2356 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2357 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2358 }
2359
2360 return 0;
2361}
2362
2363static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2364 struct radeon_ps *radeon_state,
2365 SISLANDS_SMC_SWSTATE *smc_state)
2366{
2367 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2368 struct ni_ps *state = ni_get_ps(radeon_state);
2369 u32 sq_power_throttle, sq_power_throttle2;
2370 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2371 int i;
2372
2373 if (state->performance_level_count == 0)
2374 return -EINVAL;
2375
2376 if (smc_state->levelCount != state->performance_level_count)
2377 return -EINVAL;
2378
2379 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2380 return -EINVAL;
2381
2382 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2383 enable_sq_ramping = false;
2384
2385 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2386 enable_sq_ramping = false;
2387
2388 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2389 enable_sq_ramping = false;
2390
2391 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2392 enable_sq_ramping = false;
2393
2394 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2395 enable_sq_ramping = false;
2396
2397 for (i = 0; i < state->performance_level_count; i++) {
2398 sq_power_throttle = 0;
2399 sq_power_throttle2 = 0;
2400
2401 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2402 enable_sq_ramping) {
2403 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2404 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2405 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2406 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2407 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2408 } else {
2409 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2410 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2411 }
2412
2413 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2414 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2415 }
2416
2417 return 0;
2418}
2419
2420static int si_enable_power_containment(struct radeon_device *rdev,
2421 struct radeon_ps *radeon_new_state,
2422 bool enable)
2423{
2424 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2425 PPSMC_Result smc_result;
2426 int ret = 0;
2427
2428 if (ni_pi->enable_power_containment) {
2429 if (enable) {
2430 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2431 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2432 if (smc_result != PPSMC_Result_OK) {
2433 ret = -EINVAL;
2434 ni_pi->pc_enabled = false;
2435 } else {
2436 ni_pi->pc_enabled = true;
2437 }
2438 }
2439 } else {
2440 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2441 if (smc_result != PPSMC_Result_OK)
2442 ret = -EINVAL;
2443 ni_pi->pc_enabled = false;
2444 }
2445 }
2446
2447 return ret;
2448}
2449
2450static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2451{
2452 struct si_power_info *si_pi = si_get_pi(rdev);
2453 int ret = 0;
2454 struct si_dte_data *dte_data = &si_pi->dte_data;
2455 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2456 u32 table_size;
2457 u8 tdep_count;
2458 u32 i;
2459
2460 if (dte_data == NULL)
2461 si_pi->enable_dte = false;
2462
2463 if (si_pi->enable_dte == false)
2464 return 0;
2465
2466 if (dte_data->k <= 0)
2467 return -EINVAL;
2468
2469 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2470 if (dte_tables == NULL) {
2471 si_pi->enable_dte = false;
2472 return -ENOMEM;
2473 }
2474
2475 table_size = dte_data->k;
2476
2477 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2478 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2479
2480 tdep_count = dte_data->tdep_count;
2481 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2482 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2483
2484 dte_tables->K = cpu_to_be32(table_size);
2485 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2486 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2487 dte_tables->WindowSize = dte_data->window_size;
2488 dte_tables->temp_select = dte_data->temp_select;
2489 dte_tables->DTE_mode = dte_data->dte_mode;
2490 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2491
2492 if (tdep_count > 0)
2493 table_size--;
2494
2495 for (i = 0; i < table_size; i++) {
2496 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2497 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2498 }
2499
2500 dte_tables->Tdep_count = tdep_count;
2501
2502 for (i = 0; i < (u32)tdep_count; i++) {
2503 dte_tables->T_limits[i] = dte_data->t_limits[i];
2504 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2505 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2506 }
2507
2508 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2509 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2510 kfree(dte_tables);
2511
2512 return ret;
2513}
2514
2515static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2516 u16 *max, u16 *min)
2517{
2518 struct si_power_info *si_pi = si_get_pi(rdev);
2519 struct radeon_cac_leakage_table *table =
2520 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2521 u32 i;
2522 u32 v0_loadline;
2523
2524
2525 if (table == NULL)
2526 return -EINVAL;
2527
2528 *max = 0;
2529 *min = 0xFFFF;
2530
2531 for (i = 0; i < table->count; i++) {
2532 if (table->entries[i].vddc > *max)
2533 *max = table->entries[i].vddc;
2534 if (table->entries[i].vddc < *min)
2535 *min = table->entries[i].vddc;
2536 }
2537
2538 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2539 return -EINVAL;
2540
2541 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2542
2543 if (v0_loadline > 0xFFFFUL)
2544 return -EINVAL;
2545
2546 *min = (u16)v0_loadline;
2547
2548 if ((*min > *max) || (*max == 0) || (*min == 0))
2549 return -EINVAL;
2550
2551 return 0;
2552}
2553
2554static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2555{
2556 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2557 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2558}
2559
2560static int si_init_dte_leakage_table(struct radeon_device *rdev,
2561 PP_SIslands_CacConfig *cac_tables,
2562 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2563 u16 t0, u16 t_step)
2564{
2565 struct si_power_info *si_pi = si_get_pi(rdev);
2566 u32 leakage;
2567 unsigned int i, j;
2568 s32 t;
2569 u32 smc_leakage;
2570 u32 scaling_factor;
2571 u16 voltage;
2572
2573 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2574
2575 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2576 t = (1000 * (i * t_step + t0));
2577
2578 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2579 voltage = vddc_max - (vddc_step * j);
2580
2581 si_calculate_leakage_for_v_and_t(rdev,
2582 &si_pi->powertune_data->leakage_coefficients,
2583 voltage,
2584 t,
2585 si_pi->dyn_powertune_data.cac_leakage,
2586 &leakage);
2587
2588 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2589
2590 if (smc_leakage > 0xFFFF)
2591 smc_leakage = 0xFFFF;
2592
2593 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2594 cpu_to_be16((u16)smc_leakage);
2595 }
2596 }
2597 return 0;
2598}
2599
2600static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2601 PP_SIslands_CacConfig *cac_tables,
2602 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2603{
2604 struct si_power_info *si_pi = si_get_pi(rdev);
2605 u32 leakage;
2606 unsigned int i, j;
2607 u32 smc_leakage;
2608 u32 scaling_factor;
2609 u16 voltage;
2610
2611 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2612
2613 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2614 voltage = vddc_max - (vddc_step * j);
2615
2616 si_calculate_leakage_for_v(rdev,
2617 &si_pi->powertune_data->leakage_coefficients,
2618 si_pi->powertune_data->fixed_kt,
2619 voltage,
2620 si_pi->dyn_powertune_data.cac_leakage,
2621 &leakage);
2622
2623 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2624
2625 if (smc_leakage > 0xFFFF)
2626 smc_leakage = 0xFFFF;
2627
2628 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2629 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2630 cpu_to_be16((u16)smc_leakage);
2631 }
2632 return 0;
2633}
2634
2635static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2636{
2637 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2638 struct si_power_info *si_pi = si_get_pi(rdev);
2639 PP_SIslands_CacConfig *cac_tables = NULL;
2640 u16 vddc_max, vddc_min, vddc_step;
2641 u16 t0, t_step;
2642 u32 load_line_slope, reg;
2643 int ret = 0;
2644 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2645
2646 if (ni_pi->enable_cac == false)
2647 return 0;
2648
2649 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2650 if (!cac_tables)
2651 return -ENOMEM;
2652
2653 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2654 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2655 WREG32(CG_CAC_CTRL, reg);
2656
2657 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2658 si_pi->dyn_powertune_data.dc_pwr_value =
2659 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2660 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2661 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2662
2663 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2664
2665 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2666 if (ret)
2667 goto done_free;
2668
2669 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2670 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2671 t_step = 4;
2672 t0 = 60;
2673
2674 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2675 ret = si_init_dte_leakage_table(rdev, cac_tables,
2676 vddc_max, vddc_min, vddc_step,
2677 t0, t_step);
2678 else
2679 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2680 vddc_max, vddc_min, vddc_step);
2681 if (ret)
2682 goto done_free;
2683
2684 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2685
2686 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2687 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2688 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2689 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2690 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2691 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2692 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2693 cac_tables->calculation_repeats = cpu_to_be32(2);
2694 cac_tables->dc_cac = cpu_to_be32(0);
2695 cac_tables->log2_PG_LKG_SCALE = 12;
2696 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2697 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2698 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2699
2700 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2701 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2702
2703 if (ret)
2704 goto done_free;
2705
2706 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2707
2708done_free:
2709 if (ret) {
2710 ni_pi->enable_cac = false;
2711 ni_pi->enable_power_containment = false;
2712 }
2713
2714 kfree(cac_tables);
2715
2716 return 0;
2717}
2718
2719static int si_program_cac_config_registers(struct radeon_device *rdev,
2720 const struct si_cac_config_reg *cac_config_regs)
2721{
2722 const struct si_cac_config_reg *config_regs = cac_config_regs;
2723 u32 data = 0, offset;
2724
2725 if (!config_regs)
2726 return -EINVAL;
2727
2728 while (config_regs->offset != 0xFFFFFFFF) {
2729 switch (config_regs->type) {
2730 case SISLANDS_CACCONFIG_CGIND:
2731 offset = SMC_CG_IND_START + config_regs->offset;
2732 if (offset < SMC_CG_IND_END)
2733 data = RREG32_SMC(offset);
2734 break;
2735 default:
2736 data = RREG32(config_regs->offset << 2);
2737 break;
2738 }
2739
2740 data &= ~config_regs->mask;
2741 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2742
2743 switch (config_regs->type) {
2744 case SISLANDS_CACCONFIG_CGIND:
2745 offset = SMC_CG_IND_START + config_regs->offset;
2746 if (offset < SMC_CG_IND_END)
2747 WREG32_SMC(offset, data);
2748 break;
2749 default:
2750 WREG32(config_regs->offset << 2, data);
2751 break;
2752 }
2753 config_regs++;
2754 }
2755 return 0;
2756}
2757
2758static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2759{
2760 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2761 struct si_power_info *si_pi = si_get_pi(rdev);
2762 int ret;
2763
2764 if ((ni_pi->enable_cac == false) ||
2765 (ni_pi->cac_configuration_required == false))
2766 return 0;
2767
2768 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2769 if (ret)
2770 return ret;
2771 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2772 if (ret)
2773 return ret;
2774 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2775 if (ret)
2776 return ret;
2777
2778 return 0;
2779}
2780
2781static int si_enable_smc_cac(struct radeon_device *rdev,
2782 struct radeon_ps *radeon_new_state,
2783 bool enable)
2784{
2785 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2786 struct si_power_info *si_pi = si_get_pi(rdev);
2787 PPSMC_Result smc_result;
2788 int ret = 0;
2789
2790 if (ni_pi->enable_cac) {
2791 if (enable) {
2792 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2793 if (ni_pi->support_cac_long_term_average) {
2794 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2795 if (smc_result != PPSMC_Result_OK)
2796 ni_pi->support_cac_long_term_average = false;
2797 }
2798
2799 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2800 if (smc_result != PPSMC_Result_OK) {
2801 ret = -EINVAL;
2802 ni_pi->cac_enabled = false;
2803 } else {
2804 ni_pi->cac_enabled = true;
2805 }
2806
2807 if (si_pi->enable_dte) {
2808 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2809 if (smc_result != PPSMC_Result_OK)
2810 ret = -EINVAL;
2811 }
2812 }
2813 } else if (ni_pi->cac_enabled) {
2814 if (si_pi->enable_dte)
2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2816
2817 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2818
2819 ni_pi->cac_enabled = false;
2820
2821 if (ni_pi->support_cac_long_term_average)
2822 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2823 }
2824 }
2825 return ret;
2826}
2827
2828static int si_init_smc_spll_table(struct radeon_device *rdev)
2829{
2830 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2831 struct si_power_info *si_pi = si_get_pi(rdev);
2832 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2833 SISLANDS_SMC_SCLK_VALUE sclk_params;
2834 u32 fb_div, p_div;
2835 u32 clk_s, clk_v;
2836 u32 sclk = 0;
2837 int ret = 0;
2838 u32 tmp;
2839 int i;
2840
2841 if (si_pi->spll_table_start == 0)
2842 return -EINVAL;
2843
2844 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2845 if (spll_table == NULL)
2846 return -ENOMEM;
2847
2848 for (i = 0; i < 256; i++) {
2849 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2850 if (ret)
2851 break;
2852
2853 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2854 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2855 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2856 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2857
2858 fb_div &= ~0x00001FFF;
2859 fb_div >>= 1;
2860 clk_v >>= 6;
2861
2862 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2863 ret = -EINVAL;
2864 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2865 ret = -EINVAL;
2866 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2867 ret = -EINVAL;
2868 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2869 ret = -EINVAL;
2870
2871 if (ret)
2872 break;
2873
2874 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2875 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2876 spll_table->freq[i] = cpu_to_be32(tmp);
2877
2878 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2879 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2880 spll_table->ss[i] = cpu_to_be32(tmp);
2881
2882 sclk += 512;
2883 }
2884
2885
2886 if (!ret)
2887 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2888 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2889 si_pi->sram_end);
2890
2891 if (ret)
2892 ni_pi->enable_power_containment = false;
2893
2894 kfree(spll_table);
2895
2896 return ret;
2897}
2898
2899static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2900 u16 vce_voltage)
2901{
2902 u16 highest_leakage = 0;
2903 struct si_power_info *si_pi = si_get_pi(rdev);
2904 int i;
2905
2906 for (i = 0; i < si_pi->leakage_voltage.count; i++){
2907 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2908 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2909 }
2910
2911 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2912 return highest_leakage;
2913
2914 return vce_voltage;
2915}
2916
2917static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2918 u32 evclk, u32 ecclk, u16 *voltage)
2919{
2920 u32 i;
2921 int ret = -EINVAL;
2922 struct radeon_vce_clock_voltage_dependency_table *table =
2923 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2924
2925 if (((evclk == 0) && (ecclk == 0)) ||
2926 (table && (table->count == 0))) {
2927 *voltage = 0;
2928 return 0;
2929 }
2930
2931 for (i = 0; i < table->count; i++) {
2932 if ((evclk <= table->entries[i].evclk) &&
2933 (ecclk <= table->entries[i].ecclk)) {
2934 *voltage = table->entries[i].v;
2935 ret = 0;
2936 break;
2937 }
2938 }
2939
2940 /* if no match return the highest voltage */
2941 if (ret)
2942 *voltage = table->entries[table->count - 1].v;
2943
2944 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2945
2946 return ret;
2947}
2948
2949static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2950 struct radeon_ps *rps)
2951{
2952 struct ni_ps *ps = ni_get_ps(rps);
2953 struct radeon_clock_and_voltage_limits *max_limits;
2954 bool disable_mclk_switching = false;
2955 bool disable_sclk_switching = false;
2956 u32 mclk, sclk;
2957 u16 vddc, vddci, min_vce_voltage = 0;
2958 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2959 u32 max_sclk = 0, max_mclk = 0;
2960 int i;
2961
2962 if (rdev->family == CHIP_HAINAN) {
2963 if ((rdev->pdev->revision == 0x81) ||
2964 (rdev->pdev->revision == 0xC3) ||
2965 (rdev->pdev->device == 0x6664) ||
2966 (rdev->pdev->device == 0x6665) ||
2967 (rdev->pdev->device == 0x6667)) {
2968 max_sclk = 75000;
2969 }
2970 if ((rdev->pdev->revision == 0xC3) ||
2971 (rdev->pdev->device == 0x6665)) {
2972 max_sclk = 60000;
2973 max_mclk = 80000;
2974 }
2975 } else if (rdev->family == CHIP_OLAND) {
2976 if ((rdev->pdev->revision == 0xC7) ||
2977 (rdev->pdev->revision == 0x80) ||
2978 (rdev->pdev->revision == 0x81) ||
2979 (rdev->pdev->revision == 0x83) ||
2980 (rdev->pdev->revision == 0x87) ||
2981 (rdev->pdev->device == 0x6604) ||
2982 (rdev->pdev->device == 0x6605)) {
2983 max_sclk = 75000;
2984 }
2985 }
2986
2987 if (rps->vce_active) {
2988 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
2989 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
2990 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
2991 &min_vce_voltage);
2992 } else {
2993 rps->evclk = 0;
2994 rps->ecclk = 0;
2995 }
2996
2997 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2998 ni_dpm_vblank_too_short(rdev))
2999 disable_mclk_switching = true;
3000
3001 if (rps->vclk || rps->dclk) {
3002 disable_mclk_switching = true;
3003 disable_sclk_switching = true;
3004 }
3005
3006 if (rdev->pm.dpm.ac_power)
3007 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3008 else
3009 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3010
3011 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3012 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3013 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3014 }
3015 if (rdev->pm.dpm.ac_power == false) {
3016 for (i = 0; i < ps->performance_level_count; i++) {
3017 if (ps->performance_levels[i].mclk > max_limits->mclk)
3018 ps->performance_levels[i].mclk = max_limits->mclk;
3019 if (ps->performance_levels[i].sclk > max_limits->sclk)
3020 ps->performance_levels[i].sclk = max_limits->sclk;
3021 if (ps->performance_levels[i].vddc > max_limits->vddc)
3022 ps->performance_levels[i].vddc = max_limits->vddc;
3023 if (ps->performance_levels[i].vddci > max_limits->vddci)
3024 ps->performance_levels[i].vddci = max_limits->vddci;
3025 }
3026 }
3027
3028 /* limit clocks to max supported clocks based on voltage dependency tables */
3029 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3030 &max_sclk_vddc);
3031 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3032 &max_mclk_vddci);
3033 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3034 &max_mclk_vddc);
3035
3036 for (i = 0; i < ps->performance_level_count; i++) {
3037 if (max_sclk_vddc) {
3038 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3039 ps->performance_levels[i].sclk = max_sclk_vddc;
3040 }
3041 if (max_mclk_vddci) {
3042 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3043 ps->performance_levels[i].mclk = max_mclk_vddci;
3044 }
3045 if (max_mclk_vddc) {
3046 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3047 ps->performance_levels[i].mclk = max_mclk_vddc;
3048 }
3049 if (max_mclk) {
3050 if (ps->performance_levels[i].mclk > max_mclk)
3051 ps->performance_levels[i].mclk = max_mclk;
3052 }
3053 if (max_sclk) {
3054 if (ps->performance_levels[i].sclk > max_sclk)
3055 ps->performance_levels[i].sclk = max_sclk;
3056 }
3057 }
3058
3059 /* XXX validate the min clocks required for display */
3060
3061 if (disable_mclk_switching) {
3062 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3063 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3064 } else {
3065 mclk = ps->performance_levels[0].mclk;
3066 vddci = ps->performance_levels[0].vddci;
3067 }
3068
3069 if (disable_sclk_switching) {
3070 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3071 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3072 } else {
3073 sclk = ps->performance_levels[0].sclk;
3074 vddc = ps->performance_levels[0].vddc;
3075 }
3076
3077 if (rps->vce_active) {
3078 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3079 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3080 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3081 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3082 }
3083
3084 /* adjusted low state */
3085 ps->performance_levels[0].sclk = sclk;
3086 ps->performance_levels[0].mclk = mclk;
3087 ps->performance_levels[0].vddc = vddc;
3088 ps->performance_levels[0].vddci = vddci;
3089
3090 if (disable_sclk_switching) {
3091 sclk = ps->performance_levels[0].sclk;
3092 for (i = 1; i < ps->performance_level_count; i++) {
3093 if (sclk < ps->performance_levels[i].sclk)
3094 sclk = ps->performance_levels[i].sclk;
3095 }
3096 for (i = 0; i < ps->performance_level_count; i++) {
3097 ps->performance_levels[i].sclk = sclk;
3098 ps->performance_levels[i].vddc = vddc;
3099 }
3100 } else {
3101 for (i = 1; i < ps->performance_level_count; i++) {
3102 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3103 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3104 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3105 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3106 }
3107 }
3108
3109 if (disable_mclk_switching) {
3110 mclk = ps->performance_levels[0].mclk;
3111 for (i = 1; i < ps->performance_level_count; i++) {
3112 if (mclk < ps->performance_levels[i].mclk)
3113 mclk = ps->performance_levels[i].mclk;
3114 }
3115 for (i = 0; i < ps->performance_level_count; i++) {
3116 ps->performance_levels[i].mclk = mclk;
3117 ps->performance_levels[i].vddci = vddci;
3118 }
3119 } else {
3120 for (i = 1; i < ps->performance_level_count; i++) {
3121 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3122 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3123 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3124 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3125 }
3126 }
3127
3128 for (i = 0; i < ps->performance_level_count; i++)
3129 btc_adjust_clock_combinations(rdev, max_limits,
3130 &ps->performance_levels[i]);
3131
3132 for (i = 0; i < ps->performance_level_count; i++) {
3133 if (ps->performance_levels[i].vddc < min_vce_voltage)
3134 ps->performance_levels[i].vddc = min_vce_voltage;
3135 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3136 ps->performance_levels[i].sclk,
3137 max_limits->vddc, &ps->performance_levels[i].vddc);
3138 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3139 ps->performance_levels[i].mclk,
3140 max_limits->vddci, &ps->performance_levels[i].vddci);
3141 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3142 ps->performance_levels[i].mclk,
3143 max_limits->vddc, &ps->performance_levels[i].vddc);
3144 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3145 rdev->clock.current_dispclk,
3146 max_limits->vddc, &ps->performance_levels[i].vddc);
3147 }
3148
3149 for (i = 0; i < ps->performance_level_count; i++) {
3150 btc_apply_voltage_delta_rules(rdev,
3151 max_limits->vddc, max_limits->vddci,
3152 &ps->performance_levels[i].vddc,
3153 &ps->performance_levels[i].vddci);
3154 }
3155
3156 ps->dc_compatible = true;
3157 for (i = 0; i < ps->performance_level_count; i++) {
3158 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3159 ps->dc_compatible = false;
3160 }
3161}
3162
3163#if 0
3164static int si_read_smc_soft_register(struct radeon_device *rdev,
3165 u16 reg_offset, u32 *value)
3166{
3167 struct si_power_info *si_pi = si_get_pi(rdev);
3168
3169 return si_read_smc_sram_dword(rdev,
3170 si_pi->soft_regs_start + reg_offset, value,
3171 si_pi->sram_end);
3172}
3173#endif
3174
3175static int si_write_smc_soft_register(struct radeon_device *rdev,
3176 u16 reg_offset, u32 value)
3177{
3178 struct si_power_info *si_pi = si_get_pi(rdev);
3179
3180 return si_write_smc_sram_dword(rdev,
3181 si_pi->soft_regs_start + reg_offset,
3182 value, si_pi->sram_end);
3183}
3184
3185static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3186{
3187 bool ret = false;
3188 u32 tmp, width, row, column, bank, density;
3189 bool is_memory_gddr5, is_special;
3190
3191 tmp = RREG32(MC_SEQ_MISC0);
3192 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3193 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3194 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3195
3196 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3197 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3198
3199 tmp = RREG32(MC_ARB_RAMCFG);
3200 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3201 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3202 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3203
3204 density = (1 << (row + column - 20 + bank)) * width;
3205
3206 if ((rdev->pdev->device == 0x6819) &&
3207 is_memory_gddr5 && is_special && (density == 0x400))
3208 ret = true;
3209
3210 return ret;
3211}
3212
3213static void si_get_leakage_vddc(struct radeon_device *rdev)
3214{
3215 struct si_power_info *si_pi = si_get_pi(rdev);
3216 u16 vddc, count = 0;
3217 int i, ret;
3218
3219 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3220 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3221
3222 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3223 si_pi->leakage_voltage.entries[count].voltage = vddc;
3224 si_pi->leakage_voltage.entries[count].leakage_index =
3225 SISLANDS_LEAKAGE_INDEX0 + i;
3226 count++;
3227 }
3228 }
3229 si_pi->leakage_voltage.count = count;
3230}
3231
3232static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3233 u32 index, u16 *leakage_voltage)
3234{
3235 struct si_power_info *si_pi = si_get_pi(rdev);
3236 int i;
3237
3238 if (leakage_voltage == NULL)
3239 return -EINVAL;
3240
3241 if ((index & 0xff00) != 0xff00)
3242 return -EINVAL;
3243
3244 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3245 return -EINVAL;
3246
3247 if (index < SISLANDS_LEAKAGE_INDEX0)
3248 return -EINVAL;
3249
3250 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3251 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3252 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3253 return 0;
3254 }
3255 }
3256 return -EAGAIN;
3257}
3258
3259static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3260{
3261 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3262 bool want_thermal_protection;
3263 enum radeon_dpm_event_src dpm_event_src;
3264
3265 switch (sources) {
3266 case 0:
3267 default:
3268 want_thermal_protection = false;
3269 break;
3270 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3271 want_thermal_protection = true;
3272 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3273 break;
3274 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3275 want_thermal_protection = true;
3276 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3277 break;
3278 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3279 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3280 want_thermal_protection = true;
3281 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3282 break;
3283 }
3284
3285 if (want_thermal_protection) {
3286 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3287 if (pi->thermal_protection)
3288 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3289 } else {
3290 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3291 }
3292}
3293
3294static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3295 enum radeon_dpm_auto_throttle_src source,
3296 bool enable)
3297{
3298 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3299
3300 if (enable) {
3301 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3302 pi->active_auto_throttle_sources |= 1 << source;
3303 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3304 }
3305 } else {
3306 if (pi->active_auto_throttle_sources & (1 << source)) {
3307 pi->active_auto_throttle_sources &= ~(1 << source);
3308 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3309 }
3310 }
3311}
3312
3313static void si_start_dpm(struct radeon_device *rdev)
3314{
3315 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3316}
3317
3318static void si_stop_dpm(struct radeon_device *rdev)
3319{
3320 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3321}
3322
3323static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3324{
3325 if (enable)
3326 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3327 else
3328 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3329
3330}
3331
3332#if 0
3333static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3334 u32 thermal_level)
3335{
3336 PPSMC_Result ret;
3337
3338 if (thermal_level == 0) {
3339 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3340 if (ret == PPSMC_Result_OK)
3341 return 0;
3342 else
3343 return -EINVAL;
3344 }
3345 return 0;
3346}
3347
3348static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3349{
3350 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3351}
3352#endif
3353
3354#if 0
3355static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3356{
3357 if (ac_power)
3358 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3359 0 : -EINVAL;
3360
3361 return 0;
3362}
3363#endif
3364
3365static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3366 PPSMC_Msg msg, u32 parameter)
3367{
3368 WREG32(SMC_SCRATCH0, parameter);
3369 return si_send_msg_to_smc(rdev, msg);
3370}
3371
3372static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3373{
3374 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3375 return -EINVAL;
3376
3377 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3378 0 : -EINVAL;
3379}
3380
3381int si_dpm_force_performance_level(struct radeon_device *rdev,
3382 enum radeon_dpm_forced_level level)
3383{
3384 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3385 struct ni_ps *ps = ni_get_ps(rps);
3386 u32 levels = ps->performance_level_count;
3387
3388 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3389 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3390 return -EINVAL;
3391
3392 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3393 return -EINVAL;
3394 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3395 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3396 return -EINVAL;
3397
3398 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3399 return -EINVAL;
3400 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3401 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3402 return -EINVAL;
3403
3404 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3405 return -EINVAL;
3406 }
3407
3408 rdev->pm.dpm.forced_level = level;
3409
3410 return 0;
3411}
3412
3413#if 0
3414static int si_set_boot_state(struct radeon_device *rdev)
3415{
3416 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3417 0 : -EINVAL;
3418}
3419#endif
3420
3421static int si_set_sw_state(struct radeon_device *rdev)
3422{
3423 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3424 0 : -EINVAL;
3425}
3426
3427static int si_halt_smc(struct radeon_device *rdev)
3428{
3429 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3430 return -EINVAL;
3431
3432 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3433 0 : -EINVAL;
3434}
3435
3436static int si_resume_smc(struct radeon_device *rdev)
3437{
3438 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3439 return -EINVAL;
3440
3441 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3442 0 : -EINVAL;
3443}
3444
3445static void si_dpm_start_smc(struct radeon_device *rdev)
3446{
3447 si_program_jump_on_start(rdev);
3448 si_start_smc(rdev);
3449 si_start_smc_clock(rdev);
3450}
3451
3452static void si_dpm_stop_smc(struct radeon_device *rdev)
3453{
3454 si_reset_smc(rdev);
3455 si_stop_smc_clock(rdev);
3456}
3457
3458static int si_process_firmware_header(struct radeon_device *rdev)
3459{
3460 struct si_power_info *si_pi = si_get_pi(rdev);
3461 u32 tmp;
3462 int ret;
3463
3464 ret = si_read_smc_sram_dword(rdev,
3465 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3466 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3467 &tmp, si_pi->sram_end);
3468 if (ret)
3469 return ret;
3470
3471 si_pi->state_table_start = tmp;
3472
3473 ret = si_read_smc_sram_dword(rdev,
3474 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3475 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3476 &tmp, si_pi->sram_end);
3477 if (ret)
3478 return ret;
3479
3480 si_pi->soft_regs_start = tmp;
3481
3482 ret = si_read_smc_sram_dword(rdev,
3483 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3484 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3485 &tmp, si_pi->sram_end);
3486 if (ret)
3487 return ret;
3488
3489 si_pi->mc_reg_table_start = tmp;
3490
3491 ret = si_read_smc_sram_dword(rdev,
3492 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3493 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3494 &tmp, si_pi->sram_end);
3495 if (ret)
3496 return ret;
3497
3498 si_pi->fan_table_start = tmp;
3499
3500 ret = si_read_smc_sram_dword(rdev,
3501 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3502 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3503 &tmp, si_pi->sram_end);
3504 if (ret)
3505 return ret;
3506
3507 si_pi->arb_table_start = tmp;
3508
3509 ret = si_read_smc_sram_dword(rdev,
3510 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3511 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3512 &tmp, si_pi->sram_end);
3513 if (ret)
3514 return ret;
3515
3516 si_pi->cac_table_start = tmp;
3517
3518 ret = si_read_smc_sram_dword(rdev,
3519 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3520 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3521 &tmp, si_pi->sram_end);
3522 if (ret)
3523 return ret;
3524
3525 si_pi->dte_table_start = tmp;
3526
3527 ret = si_read_smc_sram_dword(rdev,
3528 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3529 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3530 &tmp, si_pi->sram_end);
3531 if (ret)
3532 return ret;
3533
3534 si_pi->spll_table_start = tmp;
3535
3536 ret = si_read_smc_sram_dword(rdev,
3537 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3538 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3539 &tmp, si_pi->sram_end);
3540 if (ret)
3541 return ret;
3542
3543 si_pi->papm_cfg_table_start = tmp;
3544
3545 return ret;
3546}
3547
3548static void si_read_clock_registers(struct radeon_device *rdev)
3549{
3550 struct si_power_info *si_pi = si_get_pi(rdev);
3551
3552 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3553 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3554 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3555 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3556 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3557 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3558 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3559 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3560 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3561 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3562 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3563 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3564 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3565 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3566 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3567}
3568
3569static void si_enable_thermal_protection(struct radeon_device *rdev,
3570 bool enable)
3571{
3572 if (enable)
3573 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3574 else
3575 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3576}
3577
3578static void si_enable_acpi_power_management(struct radeon_device *rdev)
3579{
3580 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3581}
3582
3583#if 0
3584static int si_enter_ulp_state(struct radeon_device *rdev)
3585{
3586 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3587
3588 udelay(25000);
3589
3590 return 0;
3591}
3592
3593static int si_exit_ulp_state(struct radeon_device *rdev)
3594{
3595 int i;
3596
3597 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3598
3599 udelay(7000);
3600
3601 for (i = 0; i < rdev->usec_timeout; i++) {
3602 if (RREG32(SMC_RESP_0) == 1)
3603 break;
3604 udelay(1000);
3605 }
3606
3607 return 0;
3608}
3609#endif
3610
3611static int si_notify_smc_display_change(struct radeon_device *rdev,
3612 bool has_display)
3613{
3614 PPSMC_Msg msg = has_display ?
3615 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3616
3617 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3618 0 : -EINVAL;
3619}
3620
3621static void si_program_response_times(struct radeon_device *rdev)
3622{
3623 u32 voltage_response_time, acpi_delay_time, vbi_time_out;
3624 u32 vddc_dly, acpi_dly, vbi_dly;
3625 u32 reference_clock;
3626
3627 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3628
3629 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3630
3631 if (voltage_response_time == 0)
3632 voltage_response_time = 1000;
3633
3634 acpi_delay_time = 15000;
3635 vbi_time_out = 100000;
3636
3637 reference_clock = radeon_get_xclk(rdev);
3638
3639 vddc_dly = (voltage_response_time * reference_clock) / 100;
3640 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3641 vbi_dly = (vbi_time_out * reference_clock) / 100;
3642
3643 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3644 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3645 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3646 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3647}
3648
3649static void si_program_ds_registers(struct radeon_device *rdev)
3650{
3651 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3652 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3653
3654 if (eg_pi->sclk_deep_sleep) {
3655 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3656 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3657 ~AUTOSCALE_ON_SS_CLEAR);
3658 }
3659}
3660
3661static void si_program_display_gap(struct radeon_device *rdev)
3662{
3663 u32 tmp, pipe;
3664 int i;
3665
3666 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3667 if (rdev->pm.dpm.new_active_crtc_count > 0)
3668 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3669 else
3670 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3671
3672 if (rdev->pm.dpm.new_active_crtc_count > 1)
3673 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3674 else
3675 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3676
3677 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3678
3679 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3680 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3681
3682 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3683 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3684 /* find the first active crtc */
3685 for (i = 0; i < rdev->num_crtc; i++) {
3686 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3687 break;
3688 }
3689 if (i == rdev->num_crtc)
3690 pipe = 0;
3691 else
3692 pipe = i;
3693
3694 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3695 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3696 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3697 }
3698
3699 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3700 * This can be a problem on PowerXpress systems or if you want to use the card
3701 * for offscreen rendering or compute if there are no crtcs enabled.
3702 */
3703 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3704}
3705
3706static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3707{
3708 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3709
3710 if (enable) {
3711 if (pi->sclk_ss)
3712 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3713 } else {
3714 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3715 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3716 }
3717}
3718
3719static void si_setup_bsp(struct radeon_device *rdev)
3720{
3721 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3722 u32 xclk = radeon_get_xclk(rdev);
3723
3724 r600_calculate_u_and_p(pi->asi,
3725 xclk,
3726 16,
3727 &pi->bsp,
3728 &pi->bsu);
3729
3730 r600_calculate_u_and_p(pi->pasi,
3731 xclk,
3732 16,
3733 &pi->pbsp,
3734 &pi->pbsu);
3735
3736
3737 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3738 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3739
3740 WREG32(CG_BSP, pi->dsp);
3741}
3742
3743static void si_program_git(struct radeon_device *rdev)
3744{
3745 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3746}
3747
3748static void si_program_tp(struct radeon_device *rdev)
3749{
3750 int i;
3751 enum r600_td td = R600_TD_DFLT;
3752
3753 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3754 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3755
3756 if (td == R600_TD_AUTO)
3757 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3758 else
3759 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3760
3761 if (td == R600_TD_UP)
3762 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3763
3764 if (td == R600_TD_DOWN)
3765 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3766}
3767
3768static void si_program_tpp(struct radeon_device *rdev)
3769{
3770 WREG32(CG_TPC, R600_TPC_DFLT);
3771}
3772
3773static void si_program_sstp(struct radeon_device *rdev)
3774{
3775 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3776}
3777
3778static void si_enable_display_gap(struct radeon_device *rdev)
3779{
3780 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3781
3782 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3783 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3784 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3785
3786 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3787 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3788 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3789 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3790}
3791
3792static void si_program_vc(struct radeon_device *rdev)
3793{
3794 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3795
3796 WREG32(CG_FTV, pi->vrc);
3797}
3798
3799static void si_clear_vc(struct radeon_device *rdev)
3800{
3801 WREG32(CG_FTV, 0);
3802}
3803
3804u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3805{
3806 u8 mc_para_index;
3807
3808 if (memory_clock < 10000)
3809 mc_para_index = 0;
3810 else if (memory_clock >= 80000)
3811 mc_para_index = 0x0f;
3812 else
3813 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3814 return mc_para_index;
3815}
3816
3817u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3818{
3819 u8 mc_para_index;
3820
3821 if (strobe_mode) {
3822 if (memory_clock < 12500)
3823 mc_para_index = 0x00;
3824 else if (memory_clock > 47500)
3825 mc_para_index = 0x0f;
3826 else
3827 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3828 } else {
3829 if (memory_clock < 65000)
3830 mc_para_index = 0x00;
3831 else if (memory_clock > 135000)
3832 mc_para_index = 0x0f;
3833 else
3834 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3835 }
3836 return mc_para_index;
3837}
3838
3839static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3840{
3841 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3842 bool strobe_mode = false;
3843 u8 result = 0;
3844
3845 if (mclk <= pi->mclk_strobe_mode_threshold)
3846 strobe_mode = true;
3847
3848 if (pi->mem_gddr5)
3849 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3850 else
3851 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3852
3853 if (strobe_mode)
3854 result |= SISLANDS_SMC_STROBE_ENABLE;
3855
3856 return result;
3857}
3858
3859static int si_upload_firmware(struct radeon_device *rdev)
3860{
3861 struct si_power_info *si_pi = si_get_pi(rdev);
3862 int ret;
3863
3864 si_reset_smc(rdev);
3865 si_stop_smc_clock(rdev);
3866
3867 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3868
3869 return ret;
3870}
3871
3872static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3873 const struct atom_voltage_table *table,
3874 const struct radeon_phase_shedding_limits_table *limits)
3875{
3876 u32 data, num_bits, num_levels;
3877
3878 if ((table == NULL) || (limits == NULL))
3879 return false;
3880
3881 data = table->mask_low;
3882
3883 num_bits = hweight32(data);
3884
3885 if (num_bits == 0)
3886 return false;
3887
3888 num_levels = (1 << num_bits);
3889
3890 if (table->count != num_levels)
3891 return false;
3892
3893 if (limits->count != (num_levels - 1))
3894 return false;
3895
3896 return true;
3897}
3898
3899void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3900 u32 max_voltage_steps,
3901 struct atom_voltage_table *voltage_table)
3902{
3903 unsigned int i, diff;
3904
3905 if (voltage_table->count <= max_voltage_steps)
3906 return;
3907
3908 diff = voltage_table->count - max_voltage_steps;
3909
3910 for (i= 0; i < max_voltage_steps; i++)
3911 voltage_table->entries[i] = voltage_table->entries[i + diff];
3912
3913 voltage_table->count = max_voltage_steps;
3914}
3915
3916static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3917 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3918 struct atom_voltage_table *voltage_table)
3919{
3920 u32 i;
3921
3922 if (voltage_dependency_table == NULL)
3923 return -EINVAL;
3924
3925 voltage_table->mask_low = 0;
3926 voltage_table->phase_delay = 0;
3927
3928 voltage_table->count = voltage_dependency_table->count;
3929 for (i = 0; i < voltage_table->count; i++) {
3930 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3931 voltage_table->entries[i].smio_low = 0;
3932 }
3933
3934 return 0;
3935}
3936
3937static int si_construct_voltage_tables(struct radeon_device *rdev)
3938{
3939 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3940 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3941 struct si_power_info *si_pi = si_get_pi(rdev);
3942 int ret;
3943
3944 if (pi->voltage_control) {
3945 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3946 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3947 if (ret)
3948 return ret;
3949
3950 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3951 si_trim_voltage_table_to_fit_state_table(rdev,
3952 SISLANDS_MAX_NO_VREG_STEPS,
3953 &eg_pi->vddc_voltage_table);
3954 } else if (si_pi->voltage_control_svi2) {
3955 ret = si_get_svi2_voltage_table(rdev,
3956 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3957 &eg_pi->vddc_voltage_table);
3958 if (ret)
3959 return ret;
3960 } else {
3961 return -EINVAL;
3962 }
3963
3964 if (eg_pi->vddci_control) {
3965 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3966 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3967 if (ret)
3968 return ret;
3969
3970 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3971 si_trim_voltage_table_to_fit_state_table(rdev,
3972 SISLANDS_MAX_NO_VREG_STEPS,
3973 &eg_pi->vddci_voltage_table);
3974 }
3975 if (si_pi->vddci_control_svi2) {
3976 ret = si_get_svi2_voltage_table(rdev,
3977 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3978 &eg_pi->vddci_voltage_table);
3979 if (ret)
3980 return ret;
3981 }
3982
3983 if (pi->mvdd_control) {
3984 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3985 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3986
3987 if (ret) {
3988 pi->mvdd_control = false;
3989 return ret;
3990 }
3991
3992 if (si_pi->mvdd_voltage_table.count == 0) {
3993 pi->mvdd_control = false;
3994 return -EINVAL;
3995 }
3996
3997 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3998 si_trim_voltage_table_to_fit_state_table(rdev,
3999 SISLANDS_MAX_NO_VREG_STEPS,
4000 &si_pi->mvdd_voltage_table);
4001 }
4002
4003 if (si_pi->vddc_phase_shed_control) {
4004 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4005 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4006 if (ret)
4007 si_pi->vddc_phase_shed_control = false;
4008
4009 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4010 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4011 si_pi->vddc_phase_shed_control = false;
4012 }
4013
4014 return 0;
4015}
4016
4017static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4018 const struct atom_voltage_table *voltage_table,
4019 SISLANDS_SMC_STATETABLE *table)
4020{
4021 unsigned int i;
4022
4023 for (i = 0; i < voltage_table->count; i++)
4024 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4025}
4026
4027static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4028 SISLANDS_SMC_STATETABLE *table)
4029{
4030 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4031 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4032 struct si_power_info *si_pi = si_get_pi(rdev);
4033 u8 i;
4034
4035 if (si_pi->voltage_control_svi2) {
4036 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4037 si_pi->svc_gpio_id);
4038 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4039 si_pi->svd_gpio_id);
4040 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4041 2);
4042 } else {
4043 if (eg_pi->vddc_voltage_table.count) {
4044 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4045 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4046 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4047
4048 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4049 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4050 table->maxVDDCIndexInPPTable = i;
4051 break;
4052 }
4053 }
4054 }
4055
4056 if (eg_pi->vddci_voltage_table.count) {
4057 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4058
4059 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4060 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4061 }
4062
4063
4064 if (si_pi->mvdd_voltage_table.count) {
4065 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4066
4067 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4068 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4069 }
4070
4071 if (si_pi->vddc_phase_shed_control) {
4072 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4073 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4074 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4075
4076 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4077 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4078
4079 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4080 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4081 } else {
4082 si_pi->vddc_phase_shed_control = false;
4083 }
4084 }
4085 }
4086
4087 return 0;
4088}
4089
4090static int si_populate_voltage_value(struct radeon_device *rdev,
4091 const struct atom_voltage_table *table,
4092 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4093{
4094 unsigned int i;
4095
4096 for (i = 0; i < table->count; i++) {
4097 if (value <= table->entries[i].value) {
4098 voltage->index = (u8)i;
4099 voltage->value = cpu_to_be16(table->entries[i].value);
4100 break;
4101 }
4102 }
4103
4104 if (i >= table->count)
4105 return -EINVAL;
4106
4107 return 0;
4108}
4109
4110static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4111 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4112{
4113 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4114 struct si_power_info *si_pi = si_get_pi(rdev);
4115
4116 if (pi->mvdd_control) {
4117 if (mclk <= pi->mvdd_split_frequency)
4118 voltage->index = 0;
4119 else
4120 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4121
4122 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4123 }
4124 return 0;
4125}
4126
4127static int si_get_std_voltage_value(struct radeon_device *rdev,
4128 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4129 u16 *std_voltage)
4130{
4131 u16 v_index;
4132 bool voltage_found = false;
4133 *std_voltage = be16_to_cpu(voltage->value);
4134
4135 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4136 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4137 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4138 return -EINVAL;
4139
4140 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4141 if (be16_to_cpu(voltage->value) ==
4142 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4143 voltage_found = true;
4144 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4145 *std_voltage =
4146 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4147 else
4148 *std_voltage =
4149 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4150 break;
4151 }
4152 }
4153
4154 if (!voltage_found) {
4155 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4156 if (be16_to_cpu(voltage->value) <=
4157 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4158 voltage_found = true;
4159 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4160 *std_voltage =
4161 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4162 else
4163 *std_voltage =
4164 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4165 break;
4166 }
4167 }
4168 }
4169 } else {
4170 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4171 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4172 }
4173 }
4174
4175 return 0;
4176}
4177
4178static int si_populate_std_voltage_value(struct radeon_device *rdev,
4179 u16 value, u8 index,
4180 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4181{
4182 voltage->index = index;
4183 voltage->value = cpu_to_be16(value);
4184
4185 return 0;
4186}
4187
4188static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4189 const struct radeon_phase_shedding_limits_table *limits,
4190 u16 voltage, u32 sclk, u32 mclk,
4191 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4192{
4193 unsigned int i;
4194
4195 for (i = 0; i < limits->count; i++) {
4196 if ((voltage <= limits->entries[i].voltage) &&
4197 (sclk <= limits->entries[i].sclk) &&
4198 (mclk <= limits->entries[i].mclk))
4199 break;
4200 }
4201
4202 smc_voltage->phase_settings = (u8)i;
4203
4204 return 0;
4205}
4206
4207static int si_init_arb_table_index(struct radeon_device *rdev)
4208{
4209 struct si_power_info *si_pi = si_get_pi(rdev);
4210 u32 tmp;
4211 int ret;
4212
4213 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4214 if (ret)
4215 return ret;
4216
4217 tmp &= 0x00FFFFFF;
4218 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4219
4220 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4221}
4222
4223static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4224{
4225 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4226}
4227
4228static int si_reset_to_default(struct radeon_device *rdev)
4229{
4230 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4231 0 : -EINVAL;
4232}
4233
4234static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4235{
4236 struct si_power_info *si_pi = si_get_pi(rdev);
4237 u32 tmp;
4238 int ret;
4239
4240 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4241 &tmp, si_pi->sram_end);
4242 if (ret)
4243 return ret;
4244
4245 tmp = (tmp >> 24) & 0xff;
4246
4247 if (tmp == MC_CG_ARB_FREQ_F0)
4248 return 0;
4249
4250 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4251}
4252
4253static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4254 u32 engine_clock)
4255{
4256 u32 dram_rows;
4257 u32 dram_refresh_rate;
4258 u32 mc_arb_rfsh_rate;
4259 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4260
4261 if (tmp >= 4)
4262 dram_rows = 16384;
4263 else
4264 dram_rows = 1 << (tmp + 10);
4265
4266 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4267 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4268
4269 return mc_arb_rfsh_rate;
4270}
4271
4272static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4273 struct rv7xx_pl *pl,
4274 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4275{
4276 u32 dram_timing;
4277 u32 dram_timing2;
4278 u32 burst_time;
4279
4280 arb_regs->mc_arb_rfsh_rate =
4281 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4282
4283 radeon_atom_set_engine_dram_timings(rdev,
4284 pl->sclk,
4285 pl->mclk);
4286
4287 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4288 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4289 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4290
4291 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4292 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4293 arb_regs->mc_arb_burst_time = (u8)burst_time;
4294
4295 return 0;
4296}
4297
4298static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4299 struct radeon_ps *radeon_state,
4300 unsigned int first_arb_set)
4301{
4302 struct si_power_info *si_pi = si_get_pi(rdev);
4303 struct ni_ps *state = ni_get_ps(radeon_state);
4304 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4305 int i, ret = 0;
4306
4307 for (i = 0; i < state->performance_level_count; i++) {
4308 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4309 if (ret)
4310 break;
4311 ret = si_copy_bytes_to_smc(rdev,
4312 si_pi->arb_table_start +
4313 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4314 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4315 (u8 *)&arb_regs,
4316 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4317 si_pi->sram_end);
4318 if (ret)
4319 break;
4320 }
4321
4322 return ret;
4323}
4324
4325static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4326 struct radeon_ps *radeon_new_state)
4327{
4328 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4329 SISLANDS_DRIVER_STATE_ARB_INDEX);
4330}
4331
4332static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4333 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4334{
4335 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4336 struct si_power_info *si_pi = si_get_pi(rdev);
4337
4338 if (pi->mvdd_control)
4339 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4340 si_pi->mvdd_bootup_value, voltage);
4341
4342 return 0;
4343}
4344
4345static int si_populate_smc_initial_state(struct radeon_device *rdev,
4346 struct radeon_ps *radeon_initial_state,
4347 SISLANDS_SMC_STATETABLE *table)
4348{
4349 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4350 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4351 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4352 struct si_power_info *si_pi = si_get_pi(rdev);
4353 u32 reg;
4354 int ret;
4355
4356 table->initialState.levels[0].mclk.vDLL_CNTL =
4357 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4358 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4359 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4360 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4361 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4362 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4363 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4364 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4365 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4366 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4367 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4368 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4369 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4370 table->initialState.levels[0].mclk.vMPLL_SS =
4371 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4372 table->initialState.levels[0].mclk.vMPLL_SS2 =
4373 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4374
4375 table->initialState.levels[0].mclk.mclk_value =
4376 cpu_to_be32(initial_state->performance_levels[0].mclk);
4377
4378 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4379 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4380 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4381 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4382 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4383 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4384 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4385 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4386 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4387 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4388 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4389 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4390
4391 table->initialState.levels[0].sclk.sclk_value =
4392 cpu_to_be32(initial_state->performance_levels[0].sclk);
4393
4394 table->initialState.levels[0].arbRefreshState =
4395 SISLANDS_INITIAL_STATE_ARB_INDEX;
4396
4397 table->initialState.levels[0].ACIndex = 0;
4398
4399 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4400 initial_state->performance_levels[0].vddc,
4401 &table->initialState.levels[0].vddc);
4402
4403 if (!ret) {
4404 u16 std_vddc;
4405
4406 ret = si_get_std_voltage_value(rdev,
4407 &table->initialState.levels[0].vddc,
4408 &std_vddc);
4409 if (!ret)
4410 si_populate_std_voltage_value(rdev, std_vddc,
4411 table->initialState.levels[0].vddc.index,
4412 &table->initialState.levels[0].std_vddc);
4413 }
4414
4415 if (eg_pi->vddci_control)
4416 si_populate_voltage_value(rdev,
4417 &eg_pi->vddci_voltage_table,
4418 initial_state->performance_levels[0].vddci,
4419 &table->initialState.levels[0].vddci);
4420
4421 if (si_pi->vddc_phase_shed_control)
4422 si_populate_phase_shedding_value(rdev,
4423 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4424 initial_state->performance_levels[0].vddc,
4425 initial_state->performance_levels[0].sclk,
4426 initial_state->performance_levels[0].mclk,
4427 &table->initialState.levels[0].vddc);
4428
4429 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4430
4431 reg = CG_R(0xffff) | CG_L(0);
4432 table->initialState.levels[0].aT = cpu_to_be32(reg);
4433
4434 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4435
4436 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4437
4438 if (pi->mem_gddr5) {
4439 table->initialState.levels[0].strobeMode =
4440 si_get_strobe_mode_settings(rdev,
4441 initial_state->performance_levels[0].mclk);
4442
4443 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4444 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4445 else
4446 table->initialState.levels[0].mcFlags = 0;
4447 }
4448
4449 table->initialState.levelCount = 1;
4450
4451 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4452
4453 table->initialState.levels[0].dpm2.MaxPS = 0;
4454 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4455 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4456 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4457 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4458
4459 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4460 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4461
4462 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4463 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4464
4465 return 0;
4466}
4467
4468static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4469 SISLANDS_SMC_STATETABLE *table)
4470{
4471 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4472 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4473 struct si_power_info *si_pi = si_get_pi(rdev);
4474 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4475 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4476 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4477 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4478 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4479 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4480 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4481 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4482 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4483 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4484 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4485 u32 reg;
4486 int ret;
4487
4488 table->ACPIState = table->initialState;
4489
4490 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4491
4492 if (pi->acpi_vddc) {
4493 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4494 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4495 if (!ret) {
4496 u16 std_vddc;
4497
4498 ret = si_get_std_voltage_value(rdev,
4499 &table->ACPIState.levels[0].vddc, &std_vddc);
4500 if (!ret)
4501 si_populate_std_voltage_value(rdev, std_vddc,
4502 table->ACPIState.levels[0].vddc.index,
4503 &table->ACPIState.levels[0].std_vddc);
4504 }
4505 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4506
4507 if (si_pi->vddc_phase_shed_control) {
4508 si_populate_phase_shedding_value(rdev,
4509 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4510 pi->acpi_vddc,
4511 0,
4512 0,
4513 &table->ACPIState.levels[0].vddc);
4514 }
4515 } else {
4516 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4517 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4518 if (!ret) {
4519 u16 std_vddc;
4520
4521 ret = si_get_std_voltage_value(rdev,
4522 &table->ACPIState.levels[0].vddc, &std_vddc);
4523
4524 if (!ret)
4525 si_populate_std_voltage_value(rdev, std_vddc,
4526 table->ACPIState.levels[0].vddc.index,
4527 &table->ACPIState.levels[0].std_vddc);
4528 }
4529 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4530 si_pi->sys_pcie_mask,
4531 si_pi->boot_pcie_gen,
4532 RADEON_PCIE_GEN1);
4533
4534 if (si_pi->vddc_phase_shed_control)
4535 si_populate_phase_shedding_value(rdev,
4536 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4537 pi->min_vddc_in_table,
4538 0,
4539 0,
4540 &table->ACPIState.levels[0].vddc);
4541 }
4542
4543 if (pi->acpi_vddc) {
4544 if (eg_pi->acpi_vddci)
4545 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4546 eg_pi->acpi_vddci,
4547 &table->ACPIState.levels[0].vddci);
4548 }
4549
4550 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4551 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4552
4553 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4554
4555 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4556 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4557
4558 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4559 cpu_to_be32(dll_cntl);
4560 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4561 cpu_to_be32(mclk_pwrmgt_cntl);
4562 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4563 cpu_to_be32(mpll_ad_func_cntl);
4564 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4565 cpu_to_be32(mpll_dq_func_cntl);
4566 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4567 cpu_to_be32(mpll_func_cntl);
4568 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4569 cpu_to_be32(mpll_func_cntl_1);
4570 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4571 cpu_to_be32(mpll_func_cntl_2);
4572 table->ACPIState.levels[0].mclk.vMPLL_SS =
4573 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4574 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4575 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4576
4577 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4578 cpu_to_be32(spll_func_cntl);
4579 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4580 cpu_to_be32(spll_func_cntl_2);
4581 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4582 cpu_to_be32(spll_func_cntl_3);
4583 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4584 cpu_to_be32(spll_func_cntl_4);
4585
4586 table->ACPIState.levels[0].mclk.mclk_value = 0;
4587 table->ACPIState.levels[0].sclk.sclk_value = 0;
4588
4589 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4590
4591 if (eg_pi->dynamic_ac_timing)
4592 table->ACPIState.levels[0].ACIndex = 0;
4593
4594 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4595 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4596 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4597 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4598 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4599
4600 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4601 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4602
4603 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4604 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4605
4606 return 0;
4607}
4608
4609static int si_populate_ulv_state(struct radeon_device *rdev,
4610 SISLANDS_SMC_SWSTATE *state)
4611{
4612 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4613 struct si_power_info *si_pi = si_get_pi(rdev);
4614 struct si_ulv_param *ulv = &si_pi->ulv;
4615 u32 sclk_in_sr = 1350; /* ??? */
4616 int ret;
4617
4618 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4619 &state->levels[0]);
4620 if (!ret) {
4621 if (eg_pi->sclk_deep_sleep) {
4622 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4623 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4624 else
4625 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4626 }
4627 if (ulv->one_pcie_lane_in_ulv)
4628 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4629 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4630 state->levels[0].ACIndex = 1;
4631 state->levels[0].std_vddc = state->levels[0].vddc;
4632 state->levelCount = 1;
4633
4634 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4635 }
4636
4637 return ret;
4638}
4639
4640static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4641{
4642 struct si_power_info *si_pi = si_get_pi(rdev);
4643 struct si_ulv_param *ulv = &si_pi->ulv;
4644 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4645 int ret;
4646
4647 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4648 &arb_regs);
4649 if (ret)
4650 return ret;
4651
4652 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4653 ulv->volt_change_delay);
4654
4655 ret = si_copy_bytes_to_smc(rdev,
4656 si_pi->arb_table_start +
4657 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4658 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4659 (u8 *)&arb_regs,
4660 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4661 si_pi->sram_end);
4662
4663 return ret;
4664}
4665
4666static void si_get_mvdd_configuration(struct radeon_device *rdev)
4667{
4668 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4669
4670 pi->mvdd_split_frequency = 30000;
4671}
4672
4673static int si_init_smc_table(struct radeon_device *rdev)
4674{
4675 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4676 struct si_power_info *si_pi = si_get_pi(rdev);
4677 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4678 const struct si_ulv_param *ulv = &si_pi->ulv;
4679 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4680 int ret;
4681 u32 lane_width;
4682 u32 vr_hot_gpio;
4683
4684 si_populate_smc_voltage_tables(rdev, table);
4685
4686 switch (rdev->pm.int_thermal_type) {
4687 case THERMAL_TYPE_SI:
4688 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4689 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4690 break;
4691 case THERMAL_TYPE_NONE:
4692 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4693 break;
4694 default:
4695 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4696 break;
4697 }
4698
4699 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4700 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4701
4702 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4703 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4704 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4705 }
4706
4707 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4708 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4709
4710 if (pi->mem_gddr5)
4711 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4712
4713 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4714 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4715
4716 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4717 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4718 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4719 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4720 vr_hot_gpio);
4721 }
4722
4723 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4724 if (ret)
4725 return ret;
4726
4727 ret = si_populate_smc_acpi_state(rdev, table);
4728 if (ret)
4729 return ret;
4730
4731 table->driverState = table->initialState;
4732
4733 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4734 SISLANDS_INITIAL_STATE_ARB_INDEX);
4735 if (ret)
4736 return ret;
4737
4738 if (ulv->supported && ulv->pl.vddc) {
4739 ret = si_populate_ulv_state(rdev, &table->ULVState);
4740 if (ret)
4741 return ret;
4742
4743 ret = si_program_ulv_memory_timing_parameters(rdev);
4744 if (ret)
4745 return ret;
4746
4747 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4748 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4749
4750 lane_width = radeon_get_pcie_lanes(rdev);
4751 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4752 } else {
4753 table->ULVState = table->initialState;
4754 }
4755
4756 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4757 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4758 si_pi->sram_end);
4759}
4760
4761static int si_calculate_sclk_params(struct radeon_device *rdev,
4762 u32 engine_clock,
4763 SISLANDS_SMC_SCLK_VALUE *sclk)
4764{
4765 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4766 struct si_power_info *si_pi = si_get_pi(rdev);
4767 struct atom_clock_dividers dividers;
4768 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4769 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4770 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4771 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4772 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4773 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4774 u64 tmp;
4775 u32 reference_clock = rdev->clock.spll.reference_freq;
4776 u32 reference_divider;
4777 u32 fbdiv;
4778 int ret;
4779
4780 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4781 engine_clock, false, ÷rs);
4782 if (ret)
4783 return ret;
4784
4785 reference_divider = 1 + dividers.ref_div;
4786
4787 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4788 do_div(tmp, reference_clock);
4789 fbdiv = (u32) tmp;
4790
4791 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4792 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4793 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4794
4795 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4796 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4797
4798 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4799 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4800 spll_func_cntl_3 |= SPLL_DITHEN;
4801
4802 if (pi->sclk_ss) {
4803 struct radeon_atom_ss ss;
4804 u32 vco_freq = engine_clock * dividers.post_div;
4805
4806 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4807 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4808 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4809 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4810
4811 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4812 cg_spll_spread_spectrum |= CLK_S(clk_s);
4813 cg_spll_spread_spectrum |= SSEN;
4814
4815 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4816 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4817 }
4818 }
4819
4820 sclk->sclk_value = engine_clock;
4821 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4822 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4823 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4824 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4825 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4826 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4827
4828 return 0;
4829}
4830
4831static int si_populate_sclk_value(struct radeon_device *rdev,
4832 u32 engine_clock,
4833 SISLANDS_SMC_SCLK_VALUE *sclk)
4834{
4835 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4836 int ret;
4837
4838 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4839 if (!ret) {
4840 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4841 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4842 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4843 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4844 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4845 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4846 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4847 }
4848
4849 return ret;
4850}
4851
4852static int si_populate_mclk_value(struct radeon_device *rdev,
4853 u32 engine_clock,
4854 u32 memory_clock,
4855 SISLANDS_SMC_MCLK_VALUE *mclk,
4856 bool strobe_mode,
4857 bool dll_state_on)
4858{
4859 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4860 struct si_power_info *si_pi = si_get_pi(rdev);
4861 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4862 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4863 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4864 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4865 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4866 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4867 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4868 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4869 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4870 struct atom_mpll_param mpll_param;
4871 int ret;
4872
4873 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4874 if (ret)
4875 return ret;
4876
4877 mpll_func_cntl &= ~BWCTRL_MASK;
4878 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4879
4880 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4881 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4882 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4883
4884 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4885 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4886
4887 if (pi->mem_gddr5) {
4888 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4889 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4890 YCLK_POST_DIV(mpll_param.post_div);
4891 }
4892
4893 if (pi->mclk_ss) {
4894 struct radeon_atom_ss ss;
4895 u32 freq_nom;
4896 u32 tmp;
4897 u32 reference_clock = rdev->clock.mpll.reference_freq;
4898
4899 if (pi->mem_gddr5)
4900 freq_nom = memory_clock * 4;
4901 else
4902 freq_nom = memory_clock * 2;
4903
4904 tmp = freq_nom / reference_clock;
4905 tmp = tmp * tmp;
4906 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4907 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4908 u32 clks = reference_clock * 5 / ss.rate;
4909 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4910
4911 mpll_ss1 &= ~CLKV_MASK;
4912 mpll_ss1 |= CLKV(clkv);
4913
4914 mpll_ss2 &= ~CLKS_MASK;
4915 mpll_ss2 |= CLKS(clks);
4916 }
4917 }
4918
4919 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4920 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4921
4922 if (dll_state_on)
4923 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4924 else
4925 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4926
4927 mclk->mclk_value = cpu_to_be32(memory_clock);
4928 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4929 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4930 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4931 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4932 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4933 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4934 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4935 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4936 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4937
4938 return 0;
4939}
4940
4941static void si_populate_smc_sp(struct radeon_device *rdev,
4942 struct radeon_ps *radeon_state,
4943 SISLANDS_SMC_SWSTATE *smc_state)
4944{
4945 struct ni_ps *ps = ni_get_ps(radeon_state);
4946 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4947 int i;
4948
4949 for (i = 0; i < ps->performance_level_count - 1; i++)
4950 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4951
4952 smc_state->levels[ps->performance_level_count - 1].bSP =
4953 cpu_to_be32(pi->psp);
4954}
4955
4956static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4957 struct rv7xx_pl *pl,
4958 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4959{
4960 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4961 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4962 struct si_power_info *si_pi = si_get_pi(rdev);
4963 int ret;
4964 bool dll_state_on;
4965 u16 std_vddc;
4966 bool gmc_pg = false;
4967
4968 if (eg_pi->pcie_performance_request &&
4969 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4970 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4971 else
4972 level->gen2PCIE = (u8)pl->pcie_gen;
4973
4974 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4975 if (ret)
4976 return ret;
4977
4978 level->mcFlags = 0;
4979
4980 if (pi->mclk_stutter_mode_threshold &&
4981 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4982 !eg_pi->uvd_enabled &&
4983 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4984 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4985 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4986
4987 if (gmc_pg)
4988 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4989 }
4990
4991 if (pi->mem_gddr5) {
4992 if (pl->mclk > pi->mclk_edc_enable_threshold)
4993 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4994
4995 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4996 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4997
4998 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4999
5000 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5001 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5002 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5003 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5004 else
5005 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5006 } else {
5007 dll_state_on = false;
5008 }
5009 } else {
5010 level->strobeMode = si_get_strobe_mode_settings(rdev,
5011 pl->mclk);
5012
5013 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5014 }
5015
5016 ret = si_populate_mclk_value(rdev,
5017 pl->sclk,
5018 pl->mclk,
5019 &level->mclk,
5020 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5021 if (ret)
5022 return ret;
5023
5024 ret = si_populate_voltage_value(rdev,
5025 &eg_pi->vddc_voltage_table,
5026 pl->vddc, &level->vddc);
5027 if (ret)
5028 return ret;
5029
5030
5031 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5032 if (ret)
5033 return ret;
5034
5035 ret = si_populate_std_voltage_value(rdev, std_vddc,
5036 level->vddc.index, &level->std_vddc);
5037 if (ret)
5038 return ret;
5039
5040 if (eg_pi->vddci_control) {
5041 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5042 pl->vddci, &level->vddci);
5043 if (ret)
5044 return ret;
5045 }
5046
5047 if (si_pi->vddc_phase_shed_control) {
5048 ret = si_populate_phase_shedding_value(rdev,
5049 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5050 pl->vddc,
5051 pl->sclk,
5052 pl->mclk,
5053 &level->vddc);
5054 if (ret)
5055 return ret;
5056 }
5057
5058 level->MaxPoweredUpCU = si_pi->max_cu;
5059
5060 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5061
5062 return ret;
5063}
5064
5065static int si_populate_smc_t(struct radeon_device *rdev,
5066 struct radeon_ps *radeon_state,
5067 SISLANDS_SMC_SWSTATE *smc_state)
5068{
5069 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5070 struct ni_ps *state = ni_get_ps(radeon_state);
5071 u32 a_t;
5072 u32 t_l, t_h;
5073 u32 high_bsp;
5074 int i, ret;
5075
5076 if (state->performance_level_count >= 9)
5077 return -EINVAL;
5078
5079 if (state->performance_level_count < 2) {
5080 a_t = CG_R(0xffff) | CG_L(0);
5081 smc_state->levels[0].aT = cpu_to_be32(a_t);
5082 return 0;
5083 }
5084
5085 smc_state->levels[0].aT = cpu_to_be32(0);
5086
5087 for (i = 0; i <= state->performance_level_count - 2; i++) {
5088 ret = r600_calculate_at(
5089 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5090 100 * R600_AH_DFLT,
5091 state->performance_levels[i + 1].sclk,
5092 state->performance_levels[i].sclk,
5093 &t_l,
5094 &t_h);
5095
5096 if (ret) {
5097 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5098 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5099 }
5100
5101 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5102 a_t |= CG_R(t_l * pi->bsp / 20000);
5103 smc_state->levels[i].aT = cpu_to_be32(a_t);
5104
5105 high_bsp = (i == state->performance_level_count - 2) ?
5106 pi->pbsp : pi->bsp;
5107 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5108 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5109 }
5110
5111 return 0;
5112}
5113
5114static int si_disable_ulv(struct radeon_device *rdev)
5115{
5116 struct si_power_info *si_pi = si_get_pi(rdev);
5117 struct si_ulv_param *ulv = &si_pi->ulv;
5118
5119 if (ulv->supported)
5120 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5121 0 : -EINVAL;
5122
5123 return 0;
5124}
5125
5126static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5127 struct radeon_ps *radeon_state)
5128{
5129 const struct si_power_info *si_pi = si_get_pi(rdev);
5130 const struct si_ulv_param *ulv = &si_pi->ulv;
5131 const struct ni_ps *state = ni_get_ps(radeon_state);
5132 int i;
5133
5134 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5135 return false;
5136
5137 /* XXX validate against display requirements! */
5138
5139 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5140 if (rdev->clock.current_dispclk <=
5141 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5142 if (ulv->pl.vddc <
5143 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5144 return false;
5145 }
5146 }
5147
5148 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5149 return false;
5150
5151 return true;
5152}
5153
5154static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5155 struct radeon_ps *radeon_new_state)
5156{
5157 const struct si_power_info *si_pi = si_get_pi(rdev);
5158 const struct si_ulv_param *ulv = &si_pi->ulv;
5159
5160 if (ulv->supported) {
5161 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5162 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5163 0 : -EINVAL;
5164 }
5165 return 0;
5166}
5167
5168static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5169 struct radeon_ps *radeon_state,
5170 SISLANDS_SMC_SWSTATE *smc_state)
5171{
5172 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5173 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5174 struct si_power_info *si_pi = si_get_pi(rdev);
5175 struct ni_ps *state = ni_get_ps(radeon_state);
5176 int i, ret;
5177 u32 threshold;
5178 u32 sclk_in_sr = 1350; /* ??? */
5179
5180 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5181 return -EINVAL;
5182
5183 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5184
5185 if (radeon_state->vclk && radeon_state->dclk) {
5186 eg_pi->uvd_enabled = true;
5187 if (eg_pi->smu_uvd_hs)
5188 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5189 } else {
5190 eg_pi->uvd_enabled = false;
5191 }
5192
5193 if (state->dc_compatible)
5194 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5195
5196 smc_state->levelCount = 0;
5197 for (i = 0; i < state->performance_level_count; i++) {
5198 if (eg_pi->sclk_deep_sleep) {
5199 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5200 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5201 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5202 else
5203 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5204 }
5205 }
5206
5207 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5208 &smc_state->levels[i]);
5209 smc_state->levels[i].arbRefreshState =
5210 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5211
5212 if (ret)
5213 return ret;
5214
5215 if (ni_pi->enable_power_containment)
5216 smc_state->levels[i].displayWatermark =
5217 (state->performance_levels[i].sclk < threshold) ?
5218 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5219 else
5220 smc_state->levels[i].displayWatermark = (i < 2) ?
5221 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5222
5223 if (eg_pi->dynamic_ac_timing)
5224 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5225 else
5226 smc_state->levels[i].ACIndex = 0;
5227
5228 smc_state->levelCount++;
5229 }
5230
5231 si_write_smc_soft_register(rdev,
5232 SI_SMC_SOFT_REGISTER_watermark_threshold,
5233 threshold / 512);
5234
5235 si_populate_smc_sp(rdev, radeon_state, smc_state);
5236
5237 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5238 if (ret)
5239 ni_pi->enable_power_containment = false;
5240
5241 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5242 if (ret)
5243 ni_pi->enable_sq_ramping = false;
5244
5245 return si_populate_smc_t(rdev, radeon_state, smc_state);
5246}
5247
5248static int si_upload_sw_state(struct radeon_device *rdev,
5249 struct radeon_ps *radeon_new_state)
5250{
5251 struct si_power_info *si_pi = si_get_pi(rdev);
5252 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5253 int ret;
5254 u32 address = si_pi->state_table_start +
5255 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5256 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5257 ((new_state->performance_level_count - 1) *
5258 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5259 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5260
5261 memset(smc_state, 0, state_size);
5262
5263 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5264 if (ret)
5265 return ret;
5266
5267 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5268 state_size, si_pi->sram_end);
5269
5270 return ret;
5271}
5272
5273static int si_upload_ulv_state(struct radeon_device *rdev)
5274{
5275 struct si_power_info *si_pi = si_get_pi(rdev);
5276 struct si_ulv_param *ulv = &si_pi->ulv;
5277 int ret = 0;
5278
5279 if (ulv->supported && ulv->pl.vddc) {
5280 u32 address = si_pi->state_table_start +
5281 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5282 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5283 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5284
5285 memset(smc_state, 0, state_size);
5286
5287 ret = si_populate_ulv_state(rdev, smc_state);
5288 if (!ret)
5289 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5290 state_size, si_pi->sram_end);
5291 }
5292
5293 return ret;
5294}
5295
5296static int si_upload_smc_data(struct radeon_device *rdev)
5297{
5298 struct radeon_crtc *radeon_crtc = NULL;
5299 int i;
5300
5301 if (rdev->pm.dpm.new_active_crtc_count == 0)
5302 return 0;
5303
5304 for (i = 0; i < rdev->num_crtc; i++) {
5305 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5306 radeon_crtc = rdev->mode_info.crtcs[i];
5307 break;
5308 }
5309 }
5310
5311 if (radeon_crtc == NULL)
5312 return 0;
5313
5314 if (radeon_crtc->line_time <= 0)
5315 return 0;
5316
5317 if (si_write_smc_soft_register(rdev,
5318 SI_SMC_SOFT_REGISTER_crtc_index,
5319 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5320 return 0;
5321
5322 if (si_write_smc_soft_register(rdev,
5323 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5324 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5325 return 0;
5326
5327 if (si_write_smc_soft_register(rdev,
5328 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5329 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5330 return 0;
5331
5332 return 0;
5333}
5334
5335static int si_set_mc_special_registers(struct radeon_device *rdev,
5336 struct si_mc_reg_table *table)
5337{
5338 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5339 u8 i, j, k;
5340 u32 temp_reg;
5341
5342 for (i = 0, j = table->last; i < table->last; i++) {
5343 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5344 return -EINVAL;
5345 switch (table->mc_reg_address[i].s1 << 2) {
5346 case MC_SEQ_MISC1:
5347 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5348 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5349 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5350 for (k = 0; k < table->num_entries; k++)
5351 table->mc_reg_table_entry[k].mc_data[j] =
5352 ((temp_reg & 0xffff0000)) |
5353 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5354 j++;
5355 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5356 return -EINVAL;
5357
5358 temp_reg = RREG32(MC_PMG_CMD_MRS);
5359 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5360 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5361 for (k = 0; k < table->num_entries; k++) {
5362 table->mc_reg_table_entry[k].mc_data[j] =
5363 (temp_reg & 0xffff0000) |
5364 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5365 if (!pi->mem_gddr5)
5366 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5367 }
5368 j++;
5369 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5370 return -EINVAL;
5371
5372 if (!pi->mem_gddr5) {
5373 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5374 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5375 for (k = 0; k < table->num_entries; k++)
5376 table->mc_reg_table_entry[k].mc_data[j] =
5377 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5378 j++;
5379 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5380 return -EINVAL;
5381 }
5382 break;
5383 case MC_SEQ_RESERVE_M:
5384 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5385 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5386 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5387 for(k = 0; k < table->num_entries; k++)
5388 table->mc_reg_table_entry[k].mc_data[j] =
5389 (temp_reg & 0xffff0000) |
5390 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5391 j++;
5392 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5393 return -EINVAL;
5394 break;
5395 default:
5396 break;
5397 }
5398 }
5399
5400 table->last = j;
5401
5402 return 0;
5403}
5404
5405static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5406{
5407 bool result = true;
5408
5409 switch (in_reg) {
5410 case MC_SEQ_RAS_TIMING >> 2:
5411 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5412 break;
5413 case MC_SEQ_CAS_TIMING >> 2:
5414 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5415 break;
5416 case MC_SEQ_MISC_TIMING >> 2:
5417 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5418 break;
5419 case MC_SEQ_MISC_TIMING2 >> 2:
5420 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5421 break;
5422 case MC_SEQ_RD_CTL_D0 >> 2:
5423 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5424 break;
5425 case MC_SEQ_RD_CTL_D1 >> 2:
5426 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5427 break;
5428 case MC_SEQ_WR_CTL_D0 >> 2:
5429 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5430 break;
5431 case MC_SEQ_WR_CTL_D1 >> 2:
5432 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5433 break;
5434 case MC_PMG_CMD_EMRS >> 2:
5435 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5436 break;
5437 case MC_PMG_CMD_MRS >> 2:
5438 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5439 break;
5440 case MC_PMG_CMD_MRS1 >> 2:
5441 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5442 break;
5443 case MC_SEQ_PMG_TIMING >> 2:
5444 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5445 break;
5446 case MC_PMG_CMD_MRS2 >> 2:
5447 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5448 break;
5449 case MC_SEQ_WR_CTL_2 >> 2:
5450 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5451 break;
5452 default:
5453 result = false;
5454 break;
5455 }
5456
5457 return result;
5458}
5459
5460static void si_set_valid_flag(struct si_mc_reg_table *table)
5461{
5462 u8 i, j;
5463
5464 for (i = 0; i < table->last; i++) {
5465 for (j = 1; j < table->num_entries; j++) {
5466 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5467 table->valid_flag |= 1 << i;
5468 break;
5469 }
5470 }
5471 }
5472}
5473
5474static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5475{
5476 u32 i;
5477 u16 address;
5478
5479 for (i = 0; i < table->last; i++)
5480 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5481 address : table->mc_reg_address[i].s1;
5482
5483}
5484
5485static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5486 struct si_mc_reg_table *si_table)
5487{
5488 u8 i, j;
5489
5490 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5491 return -EINVAL;
5492 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5493 return -EINVAL;
5494
5495 for (i = 0; i < table->last; i++)
5496 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5497 si_table->last = table->last;
5498
5499 for (i = 0; i < table->num_entries; i++) {
5500 si_table->mc_reg_table_entry[i].mclk_max =
5501 table->mc_reg_table_entry[i].mclk_max;
5502 for (j = 0; j < table->last; j++) {
5503 si_table->mc_reg_table_entry[i].mc_data[j] =
5504 table->mc_reg_table_entry[i].mc_data[j];
5505 }
5506 }
5507 si_table->num_entries = table->num_entries;
5508
5509 return 0;
5510}
5511
5512static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5513{
5514 struct si_power_info *si_pi = si_get_pi(rdev);
5515 struct atom_mc_reg_table *table;
5516 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5517 u8 module_index = rv770_get_memory_module_index(rdev);
5518 int ret;
5519
5520 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5521 if (!table)
5522 return -ENOMEM;
5523
5524 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5525 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5526 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5527 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5528 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5529 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5530 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5531 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5532 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5533 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5534 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5535 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5536 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5537 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5538
5539 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5540 if (ret)
5541 goto init_mc_done;
5542
5543 ret = si_copy_vbios_mc_reg_table(table, si_table);
5544 if (ret)
5545 goto init_mc_done;
5546
5547 si_set_s0_mc_reg_index(si_table);
5548
5549 ret = si_set_mc_special_registers(rdev, si_table);
5550 if (ret)
5551 goto init_mc_done;
5552
5553 si_set_valid_flag(si_table);
5554
5555init_mc_done:
5556 kfree(table);
5557
5558 return ret;
5559
5560}
5561
5562static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5563 SMC_SIslands_MCRegisters *mc_reg_table)
5564{
5565 struct si_power_info *si_pi = si_get_pi(rdev);
5566 u32 i, j;
5567
5568 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5569 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5570 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5571 break;
5572 mc_reg_table->address[i].s0 =
5573 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5574 mc_reg_table->address[i].s1 =
5575 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5576 i++;
5577 }
5578 }
5579 mc_reg_table->last = (u8)i;
5580}
5581
5582static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5583 SMC_SIslands_MCRegisterSet *data,
5584 u32 num_entries, u32 valid_flag)
5585{
5586 u32 i, j;
5587
5588 for(i = 0, j = 0; j < num_entries; j++) {
5589 if (valid_flag & (1 << j)) {
5590 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5591 i++;
5592 }
5593 }
5594}
5595
5596static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5597 struct rv7xx_pl *pl,
5598 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5599{
5600 struct si_power_info *si_pi = si_get_pi(rdev);
5601 u32 i = 0;
5602
5603 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5604 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5605 break;
5606 }
5607
5608 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5609 --i;
5610
5611 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5612 mc_reg_table_data, si_pi->mc_reg_table.last,
5613 si_pi->mc_reg_table.valid_flag);
5614}
5615
5616static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5617 struct radeon_ps *radeon_state,
5618 SMC_SIslands_MCRegisters *mc_reg_table)
5619{
5620 struct ni_ps *state = ni_get_ps(radeon_state);
5621 int i;
5622
5623 for (i = 0; i < state->performance_level_count; i++) {
5624 si_convert_mc_reg_table_entry_to_smc(rdev,
5625 &state->performance_levels[i],
5626 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5627 }
5628}
5629
5630static int si_populate_mc_reg_table(struct radeon_device *rdev,
5631 struct radeon_ps *radeon_boot_state)
5632{
5633 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5634 struct si_power_info *si_pi = si_get_pi(rdev);
5635 struct si_ulv_param *ulv = &si_pi->ulv;
5636 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5637
5638 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5639
5640 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5641
5642 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5643
5644 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5645 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5646
5647 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5648 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5649 si_pi->mc_reg_table.last,
5650 si_pi->mc_reg_table.valid_flag);
5651
5652 if (ulv->supported && ulv->pl.vddc != 0)
5653 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5654 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5655 else
5656 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5657 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5658 si_pi->mc_reg_table.last,
5659 si_pi->mc_reg_table.valid_flag);
5660
5661 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5662
5663 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5664 (u8 *)smc_mc_reg_table,
5665 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5666}
5667
5668static int si_upload_mc_reg_table(struct radeon_device *rdev,
5669 struct radeon_ps *radeon_new_state)
5670{
5671 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5672 struct si_power_info *si_pi = si_get_pi(rdev);
5673 u32 address = si_pi->mc_reg_table_start +
5674 offsetof(SMC_SIslands_MCRegisters,
5675 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5676 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5677
5678 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5679
5680 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5681
5682
5683 return si_copy_bytes_to_smc(rdev, address,
5684 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5685 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5686 si_pi->sram_end);
5687
5688}
5689
5690static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5691{
5692 if (enable)
5693 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5694 else
5695 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5696}
5697
5698static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5699 struct radeon_ps *radeon_state)
5700{
5701 struct ni_ps *state = ni_get_ps(radeon_state);
5702 int i;
5703 u16 pcie_speed, max_speed = 0;
5704
5705 for (i = 0; i < state->performance_level_count; i++) {
5706 pcie_speed = state->performance_levels[i].pcie_gen;
5707 if (max_speed < pcie_speed)
5708 max_speed = pcie_speed;
5709 }
5710 return max_speed;
5711}
5712
5713static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5714{
5715 u32 speed_cntl;
5716
5717 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5718 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5719
5720 return (u16)speed_cntl;
5721}
5722
5723static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5724 struct radeon_ps *radeon_new_state,
5725 struct radeon_ps *radeon_current_state)
5726{
5727 struct si_power_info *si_pi = si_get_pi(rdev);
5728 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5729 enum radeon_pcie_gen current_link_speed;
5730
5731 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5732 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5733 else
5734 current_link_speed = si_pi->force_pcie_gen;
5735
5736 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5737 si_pi->pspp_notify_required = false;
5738 if (target_link_speed > current_link_speed) {
5739 switch (target_link_speed) {
5740#if defined(CONFIG_ACPI)
5741 case RADEON_PCIE_GEN3:
5742 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5743 break;
5744 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5745 if (current_link_speed == RADEON_PCIE_GEN2)
5746 break;
5747 fallthrough;
5748 case RADEON_PCIE_GEN2:
5749 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5750 break;
5751#endif
5752 /* fall through */
5753 default:
5754 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5755 break;
5756 }
5757 } else {
5758 if (target_link_speed < current_link_speed)
5759 si_pi->pspp_notify_required = true;
5760 }
5761}
5762
5763static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5764 struct radeon_ps *radeon_new_state,
5765 struct radeon_ps *radeon_current_state)
5766{
5767 struct si_power_info *si_pi = si_get_pi(rdev);
5768 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5769 u8 request;
5770
5771 if (si_pi->pspp_notify_required) {
5772 if (target_link_speed == RADEON_PCIE_GEN3)
5773 request = PCIE_PERF_REQ_PECI_GEN3;
5774 else if (target_link_speed == RADEON_PCIE_GEN2)
5775 request = PCIE_PERF_REQ_PECI_GEN2;
5776 else
5777 request = PCIE_PERF_REQ_PECI_GEN1;
5778
5779 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5780 (si_get_current_pcie_speed(rdev) > 0))
5781 return;
5782
5783#if defined(CONFIG_ACPI)
5784 radeon_acpi_pcie_performance_request(rdev, request, false);
5785#endif
5786 }
5787}
5788
5789#if 0
5790static int si_ds_request(struct radeon_device *rdev,
5791 bool ds_status_on, u32 count_write)
5792{
5793 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5794
5795 if (eg_pi->sclk_deep_sleep) {
5796 if (ds_status_on)
5797 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5798 PPSMC_Result_OK) ?
5799 0 : -EINVAL;
5800 else
5801 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5802 PPSMC_Result_OK) ? 0 : -EINVAL;
5803 }
5804 return 0;
5805}
5806#endif
5807
5808static void si_set_max_cu_value(struct radeon_device *rdev)
5809{
5810 struct si_power_info *si_pi = si_get_pi(rdev);
5811
5812 if (rdev->family == CHIP_VERDE) {
5813 switch (rdev->pdev->device) {
5814 case 0x6820:
5815 case 0x6825:
5816 case 0x6821:
5817 case 0x6823:
5818 case 0x6827:
5819 si_pi->max_cu = 10;
5820 break;
5821 case 0x682D:
5822 case 0x6824:
5823 case 0x682F:
5824 case 0x6826:
5825 si_pi->max_cu = 8;
5826 break;
5827 case 0x6828:
5828 case 0x6830:
5829 case 0x6831:
5830 case 0x6838:
5831 case 0x6839:
5832 case 0x683D:
5833 si_pi->max_cu = 10;
5834 break;
5835 case 0x683B:
5836 case 0x683F:
5837 case 0x6829:
5838 si_pi->max_cu = 8;
5839 break;
5840 default:
5841 si_pi->max_cu = 0;
5842 break;
5843 }
5844 } else {
5845 si_pi->max_cu = 0;
5846 }
5847}
5848
5849static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5850 struct radeon_clock_voltage_dependency_table *table)
5851{
5852 u32 i;
5853 int j;
5854 u16 leakage_voltage;
5855
5856 if (table) {
5857 for (i = 0; i < table->count; i++) {
5858 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5859 table->entries[i].v,
5860 &leakage_voltage)) {
5861 case 0:
5862 table->entries[i].v = leakage_voltage;
5863 break;
5864 case -EAGAIN:
5865 return -EINVAL;
5866 case -EINVAL:
5867 default:
5868 break;
5869 }
5870 }
5871
5872 for (j = (table->count - 2); j >= 0; j--) {
5873 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5874 table->entries[j].v : table->entries[j + 1].v;
5875 }
5876 }
5877 return 0;
5878}
5879
5880static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5881{
5882 int ret;
5883
5884 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5885 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5886 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5887 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5888 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5889 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5890 return ret;
5891}
5892
5893static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5894 struct radeon_ps *radeon_new_state,
5895 struct radeon_ps *radeon_current_state)
5896{
5897 u32 lane_width;
5898 u32 new_lane_width =
5899 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5900 u32 current_lane_width =
5901 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5902
5903 if (new_lane_width != current_lane_width) {
5904 radeon_set_pcie_lanes(rdev, new_lane_width);
5905 lane_width = radeon_get_pcie_lanes(rdev);
5906 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5907 }
5908}
5909
5910static void si_set_vce_clock(struct radeon_device *rdev,
5911 struct radeon_ps *new_rps,
5912 struct radeon_ps *old_rps)
5913{
5914 if ((old_rps->evclk != new_rps->evclk) ||
5915 (old_rps->ecclk != new_rps->ecclk)) {
5916 /* turn the clocks on when encoding, off otherwise */
5917 if (new_rps->evclk || new_rps->ecclk)
5918 vce_v1_0_enable_mgcg(rdev, false);
5919 else
5920 vce_v1_0_enable_mgcg(rdev, true);
5921 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5922 }
5923}
5924
5925void si_dpm_setup_asic(struct radeon_device *rdev)
5926{
5927 int r;
5928
5929 r = si_mc_load_microcode(rdev);
5930 if (r)
5931 DRM_ERROR("Failed to load MC firmware!\n");
5932 rv770_get_memory_type(rdev);
5933 si_read_clock_registers(rdev);
5934 si_enable_acpi_power_management(rdev);
5935}
5936
5937static int si_thermal_enable_alert(struct radeon_device *rdev,
5938 bool enable)
5939{
5940 u32 thermal_int = RREG32(CG_THERMAL_INT);
5941
5942 if (enable) {
5943 PPSMC_Result result;
5944
5945 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5946 WREG32(CG_THERMAL_INT, thermal_int);
5947 rdev->irq.dpm_thermal = false;
5948 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5949 if (result != PPSMC_Result_OK) {
5950 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5951 return -EINVAL;
5952 }
5953 } else {
5954 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5955 WREG32(CG_THERMAL_INT, thermal_int);
5956 rdev->irq.dpm_thermal = true;
5957 }
5958
5959 return 0;
5960}
5961
5962static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5963 int min_temp, int max_temp)
5964{
5965 int low_temp = 0 * 1000;
5966 int high_temp = 255 * 1000;
5967
5968 if (low_temp < min_temp)
5969 low_temp = min_temp;
5970 if (high_temp > max_temp)
5971 high_temp = max_temp;
5972 if (high_temp < low_temp) {
5973 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5974 return -EINVAL;
5975 }
5976
5977 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5978 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5979 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5980
5981 rdev->pm.dpm.thermal.min_temp = low_temp;
5982 rdev->pm.dpm.thermal.max_temp = high_temp;
5983
5984 return 0;
5985}
5986
5987static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
5988{
5989 struct si_power_info *si_pi = si_get_pi(rdev);
5990 u32 tmp;
5991
5992 if (si_pi->fan_ctrl_is_in_default_mode) {
5993 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
5994 si_pi->fan_ctrl_default_mode = tmp;
5995 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
5996 si_pi->t_min = tmp;
5997 si_pi->fan_ctrl_is_in_default_mode = false;
5998 }
5999
6000 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6001 tmp |= TMIN(0);
6002 WREG32(CG_FDO_CTRL2, tmp);
6003
6004 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6005 tmp |= FDO_PWM_MODE(mode);
6006 WREG32(CG_FDO_CTRL2, tmp);
6007}
6008
6009static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6010{
6011 struct si_power_info *si_pi = si_get_pi(rdev);
6012 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6013 u32 duty100;
6014 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6015 u16 fdo_min, slope1, slope2;
6016 u32 reference_clock, tmp;
6017 int ret;
6018 u64 tmp64;
6019
6020 if (!si_pi->fan_table_start) {
6021 rdev->pm.dpm.fan.ucode_fan_control = false;
6022 return 0;
6023 }
6024
6025 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6026
6027 if (duty100 == 0) {
6028 rdev->pm.dpm.fan.ucode_fan_control = false;
6029 return 0;
6030 }
6031
6032 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6033 do_div(tmp64, 10000);
6034 fdo_min = (u16)tmp64;
6035
6036 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6037 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6038
6039 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6040 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6041
6042 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6043 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6044
6045 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6046 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6047 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6048
6049 fan_table.slope1 = cpu_to_be16(slope1);
6050 fan_table.slope2 = cpu_to_be16(slope2);
6051
6052 fan_table.fdo_min = cpu_to_be16(fdo_min);
6053
6054 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6055
6056 fan_table.hys_up = cpu_to_be16(1);
6057
6058 fan_table.hys_slope = cpu_to_be16(1);
6059
6060 fan_table.temp_resp_lim = cpu_to_be16(5);
6061
6062 reference_clock = radeon_get_xclk(rdev);
6063
6064 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6065 reference_clock) / 1600);
6066
6067 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6068
6069 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6070 fan_table.temp_src = (uint8_t)tmp;
6071
6072 ret = si_copy_bytes_to_smc(rdev,
6073 si_pi->fan_table_start,
6074 (u8 *)(&fan_table),
6075 sizeof(fan_table),
6076 si_pi->sram_end);
6077
6078 if (ret) {
6079 DRM_ERROR("Failed to load fan table to the SMC.");
6080 rdev->pm.dpm.fan.ucode_fan_control = false;
6081 }
6082
6083 return 0;
6084}
6085
6086static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6087{
6088 struct si_power_info *si_pi = si_get_pi(rdev);
6089 PPSMC_Result ret;
6090
6091 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6092 if (ret == PPSMC_Result_OK) {
6093 si_pi->fan_is_controlled_by_smc = true;
6094 return 0;
6095 } else {
6096 return -EINVAL;
6097 }
6098}
6099
6100static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6101{
6102 struct si_power_info *si_pi = si_get_pi(rdev);
6103 PPSMC_Result ret;
6104
6105 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6106
6107 if (ret == PPSMC_Result_OK) {
6108 si_pi->fan_is_controlled_by_smc = false;
6109 return 0;
6110 } else {
6111 return -EINVAL;
6112 }
6113}
6114
6115int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6116 u32 *speed)
6117{
6118 u32 duty, duty100;
6119 u64 tmp64;
6120
6121 if (rdev->pm.no_fan)
6122 return -ENOENT;
6123
6124 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6125 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6126
6127 if (duty100 == 0)
6128 return -EINVAL;
6129
6130 tmp64 = (u64)duty * 100;
6131 do_div(tmp64, duty100);
6132 *speed = (u32)tmp64;
6133
6134 if (*speed > 100)
6135 *speed = 100;
6136
6137 return 0;
6138}
6139
6140int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6141 u32 speed)
6142{
6143 struct si_power_info *si_pi = si_get_pi(rdev);
6144 u32 tmp;
6145 u32 duty, duty100;
6146 u64 tmp64;
6147
6148 if (rdev->pm.no_fan)
6149 return -ENOENT;
6150
6151 if (si_pi->fan_is_controlled_by_smc)
6152 return -EINVAL;
6153
6154 if (speed > 100)
6155 return -EINVAL;
6156
6157 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6158
6159 if (duty100 == 0)
6160 return -EINVAL;
6161
6162 tmp64 = (u64)speed * duty100;
6163 do_div(tmp64, 100);
6164 duty = (u32)tmp64;
6165
6166 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6167 tmp |= FDO_STATIC_DUTY(duty);
6168 WREG32(CG_FDO_CTRL0, tmp);
6169
6170 return 0;
6171}
6172
6173void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6174{
6175 if (mode) {
6176 /* stop auto-manage */
6177 if (rdev->pm.dpm.fan.ucode_fan_control)
6178 si_fan_ctrl_stop_smc_fan_control(rdev);
6179 si_fan_ctrl_set_static_mode(rdev, mode);
6180 } else {
6181 /* restart auto-manage */
6182 if (rdev->pm.dpm.fan.ucode_fan_control)
6183 si_thermal_start_smc_fan_control(rdev);
6184 else
6185 si_fan_ctrl_set_default_mode(rdev);
6186 }
6187}
6188
6189u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6190{
6191 struct si_power_info *si_pi = si_get_pi(rdev);
6192 u32 tmp;
6193
6194 if (si_pi->fan_is_controlled_by_smc)
6195 return 0;
6196
6197 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6198 return (tmp >> FDO_PWM_MODE_SHIFT);
6199}
6200
6201#if 0
6202static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6203 u32 *speed)
6204{
6205 u32 tach_period;
6206 u32 xclk = radeon_get_xclk(rdev);
6207
6208 if (rdev->pm.no_fan)
6209 return -ENOENT;
6210
6211 if (rdev->pm.fan_pulses_per_revolution == 0)
6212 return -ENOENT;
6213
6214 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6215 if (tach_period == 0)
6216 return -ENOENT;
6217
6218 *speed = 60 * xclk * 10000 / tach_period;
6219
6220 return 0;
6221}
6222
6223static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6224 u32 speed)
6225{
6226 u32 tach_period, tmp;
6227 u32 xclk = radeon_get_xclk(rdev);
6228
6229 if (rdev->pm.no_fan)
6230 return -ENOENT;
6231
6232 if (rdev->pm.fan_pulses_per_revolution == 0)
6233 return -ENOENT;
6234
6235 if ((speed < rdev->pm.fan_min_rpm) ||
6236 (speed > rdev->pm.fan_max_rpm))
6237 return -EINVAL;
6238
6239 if (rdev->pm.dpm.fan.ucode_fan_control)
6240 si_fan_ctrl_stop_smc_fan_control(rdev);
6241
6242 tach_period = 60 * xclk * 10000 / (8 * speed);
6243 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6244 tmp |= TARGET_PERIOD(tach_period);
6245 WREG32(CG_TACH_CTRL, tmp);
6246
6247 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6248
6249 return 0;
6250}
6251#endif
6252
6253static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6254{
6255 struct si_power_info *si_pi = si_get_pi(rdev);
6256 u32 tmp;
6257
6258 if (!si_pi->fan_ctrl_is_in_default_mode) {
6259 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6260 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6261 WREG32(CG_FDO_CTRL2, tmp);
6262
6263 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6264 tmp |= TMIN(si_pi->t_min);
6265 WREG32(CG_FDO_CTRL2, tmp);
6266 si_pi->fan_ctrl_is_in_default_mode = true;
6267 }
6268}
6269
6270static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6271{
6272 if (rdev->pm.dpm.fan.ucode_fan_control) {
6273 si_fan_ctrl_start_smc_fan_control(rdev);
6274 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6275 }
6276}
6277
6278static void si_thermal_initialize(struct radeon_device *rdev)
6279{
6280 u32 tmp;
6281
6282 if (rdev->pm.fan_pulses_per_revolution) {
6283 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6284 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6285 WREG32(CG_TACH_CTRL, tmp);
6286 }
6287
6288 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6289 tmp |= TACH_PWM_RESP_RATE(0x28);
6290 WREG32(CG_FDO_CTRL2, tmp);
6291}
6292
6293static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6294{
6295 int ret;
6296
6297 si_thermal_initialize(rdev);
6298 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6299 if (ret)
6300 return ret;
6301 ret = si_thermal_enable_alert(rdev, true);
6302 if (ret)
6303 return ret;
6304 if (rdev->pm.dpm.fan.ucode_fan_control) {
6305 ret = si_halt_smc(rdev);
6306 if (ret)
6307 return ret;
6308 ret = si_thermal_setup_fan_table(rdev);
6309 if (ret)
6310 return ret;
6311 ret = si_resume_smc(rdev);
6312 if (ret)
6313 return ret;
6314 si_thermal_start_smc_fan_control(rdev);
6315 }
6316
6317 return 0;
6318}
6319
6320static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6321{
6322 if (!rdev->pm.no_fan) {
6323 si_fan_ctrl_set_default_mode(rdev);
6324 si_fan_ctrl_stop_smc_fan_control(rdev);
6325 }
6326}
6327
6328int si_dpm_enable(struct radeon_device *rdev)
6329{
6330 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6331 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6332 struct si_power_info *si_pi = si_get_pi(rdev);
6333 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6334 int ret;
6335
6336 if (si_is_smc_running(rdev))
6337 return -EINVAL;
6338 if (pi->voltage_control || si_pi->voltage_control_svi2)
6339 si_enable_voltage_control(rdev, true);
6340 if (pi->mvdd_control)
6341 si_get_mvdd_configuration(rdev);
6342 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6343 ret = si_construct_voltage_tables(rdev);
6344 if (ret) {
6345 DRM_ERROR("si_construct_voltage_tables failed\n");
6346 return ret;
6347 }
6348 }
6349 if (eg_pi->dynamic_ac_timing) {
6350 ret = si_initialize_mc_reg_table(rdev);
6351 if (ret)
6352 eg_pi->dynamic_ac_timing = false;
6353 }
6354 if (pi->dynamic_ss)
6355 si_enable_spread_spectrum(rdev, true);
6356 if (pi->thermal_protection)
6357 si_enable_thermal_protection(rdev, true);
6358 si_setup_bsp(rdev);
6359 si_program_git(rdev);
6360 si_program_tp(rdev);
6361 si_program_tpp(rdev);
6362 si_program_sstp(rdev);
6363 si_enable_display_gap(rdev);
6364 si_program_vc(rdev);
6365 ret = si_upload_firmware(rdev);
6366 if (ret) {
6367 DRM_ERROR("si_upload_firmware failed\n");
6368 return ret;
6369 }
6370 ret = si_process_firmware_header(rdev);
6371 if (ret) {
6372 DRM_ERROR("si_process_firmware_header failed\n");
6373 return ret;
6374 }
6375 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6376 if (ret) {
6377 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6378 return ret;
6379 }
6380 ret = si_init_smc_table(rdev);
6381 if (ret) {
6382 DRM_ERROR("si_init_smc_table failed\n");
6383 return ret;
6384 }
6385 ret = si_init_smc_spll_table(rdev);
6386 if (ret) {
6387 DRM_ERROR("si_init_smc_spll_table failed\n");
6388 return ret;
6389 }
6390 ret = si_init_arb_table_index(rdev);
6391 if (ret) {
6392 DRM_ERROR("si_init_arb_table_index failed\n");
6393 return ret;
6394 }
6395 if (eg_pi->dynamic_ac_timing) {
6396 ret = si_populate_mc_reg_table(rdev, boot_ps);
6397 if (ret) {
6398 DRM_ERROR("si_populate_mc_reg_table failed\n");
6399 return ret;
6400 }
6401 }
6402 ret = si_initialize_smc_cac_tables(rdev);
6403 if (ret) {
6404 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6405 return ret;
6406 }
6407 ret = si_initialize_hardware_cac_manager(rdev);
6408 if (ret) {
6409 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6410 return ret;
6411 }
6412 ret = si_initialize_smc_dte_tables(rdev);
6413 if (ret) {
6414 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6415 return ret;
6416 }
6417 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6418 if (ret) {
6419 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6420 return ret;
6421 }
6422 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6423 if (ret) {
6424 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6425 return ret;
6426 }
6427 si_program_response_times(rdev);
6428 si_program_ds_registers(rdev);
6429 si_dpm_start_smc(rdev);
6430 ret = si_notify_smc_display_change(rdev, false);
6431 if (ret) {
6432 DRM_ERROR("si_notify_smc_display_change failed\n");
6433 return ret;
6434 }
6435 si_enable_sclk_control(rdev, true);
6436 si_start_dpm(rdev);
6437
6438 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6439
6440 si_thermal_start_thermal_controller(rdev);
6441
6442 ni_update_current_ps(rdev, boot_ps);
6443
6444 return 0;
6445}
6446
6447static int si_set_temperature_range(struct radeon_device *rdev)
6448{
6449 int ret;
6450
6451 ret = si_thermal_enable_alert(rdev, false);
6452 if (ret)
6453 return ret;
6454 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6455 if (ret)
6456 return ret;
6457 ret = si_thermal_enable_alert(rdev, true);
6458 if (ret)
6459 return ret;
6460
6461 return ret;
6462}
6463
6464int si_dpm_late_enable(struct radeon_device *rdev)
6465{
6466 int ret;
6467
6468 ret = si_set_temperature_range(rdev);
6469 if (ret)
6470 return ret;
6471
6472 return ret;
6473}
6474
6475void si_dpm_disable(struct radeon_device *rdev)
6476{
6477 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6478 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6479
6480 if (!si_is_smc_running(rdev))
6481 return;
6482 si_thermal_stop_thermal_controller(rdev);
6483 si_disable_ulv(rdev);
6484 si_clear_vc(rdev);
6485 if (pi->thermal_protection)
6486 si_enable_thermal_protection(rdev, false);
6487 si_enable_power_containment(rdev, boot_ps, false);
6488 si_enable_smc_cac(rdev, boot_ps, false);
6489 si_enable_spread_spectrum(rdev, false);
6490 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6491 si_stop_dpm(rdev);
6492 si_reset_to_default(rdev);
6493 si_dpm_stop_smc(rdev);
6494 si_force_switch_to_arb_f0(rdev);
6495
6496 ni_update_current_ps(rdev, boot_ps);
6497}
6498
6499int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6500{
6501 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6502 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6503 struct radeon_ps *new_ps = &requested_ps;
6504
6505 ni_update_requested_ps(rdev, new_ps);
6506
6507 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6508
6509 return 0;
6510}
6511
6512static int si_power_control_set_level(struct radeon_device *rdev)
6513{
6514 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6515 int ret;
6516
6517 ret = si_restrict_performance_levels_before_switch(rdev);
6518 if (ret)
6519 return ret;
6520 ret = si_halt_smc(rdev);
6521 if (ret)
6522 return ret;
6523 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6524 if (ret)
6525 return ret;
6526 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6527 if (ret)
6528 return ret;
6529 ret = si_resume_smc(rdev);
6530 if (ret)
6531 return ret;
6532 ret = si_set_sw_state(rdev);
6533 if (ret)
6534 return ret;
6535 return 0;
6536}
6537
6538int si_dpm_set_power_state(struct radeon_device *rdev)
6539{
6540 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6541 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6542 struct radeon_ps *old_ps = &eg_pi->current_rps;
6543 int ret;
6544
6545 ret = si_disable_ulv(rdev);
6546 if (ret) {
6547 DRM_ERROR("si_disable_ulv failed\n");
6548 return ret;
6549 }
6550 ret = si_restrict_performance_levels_before_switch(rdev);
6551 if (ret) {
6552 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6553 return ret;
6554 }
6555 if (eg_pi->pcie_performance_request)
6556 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6557 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6558 ret = si_enable_power_containment(rdev, new_ps, false);
6559 if (ret) {
6560 DRM_ERROR("si_enable_power_containment failed\n");
6561 return ret;
6562 }
6563 ret = si_enable_smc_cac(rdev, new_ps, false);
6564 if (ret) {
6565 DRM_ERROR("si_enable_smc_cac failed\n");
6566 return ret;
6567 }
6568 ret = si_halt_smc(rdev);
6569 if (ret) {
6570 DRM_ERROR("si_halt_smc failed\n");
6571 return ret;
6572 }
6573 ret = si_upload_sw_state(rdev, new_ps);
6574 if (ret) {
6575 DRM_ERROR("si_upload_sw_state failed\n");
6576 return ret;
6577 }
6578 ret = si_upload_smc_data(rdev);
6579 if (ret) {
6580 DRM_ERROR("si_upload_smc_data failed\n");
6581 return ret;
6582 }
6583 ret = si_upload_ulv_state(rdev);
6584 if (ret) {
6585 DRM_ERROR("si_upload_ulv_state failed\n");
6586 return ret;
6587 }
6588 if (eg_pi->dynamic_ac_timing) {
6589 ret = si_upload_mc_reg_table(rdev, new_ps);
6590 if (ret) {
6591 DRM_ERROR("si_upload_mc_reg_table failed\n");
6592 return ret;
6593 }
6594 }
6595 ret = si_program_memory_timing_parameters(rdev, new_ps);
6596 if (ret) {
6597 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6598 return ret;
6599 }
6600 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6601
6602 ret = si_resume_smc(rdev);
6603 if (ret) {
6604 DRM_ERROR("si_resume_smc failed\n");
6605 return ret;
6606 }
6607 ret = si_set_sw_state(rdev);
6608 if (ret) {
6609 DRM_ERROR("si_set_sw_state failed\n");
6610 return ret;
6611 }
6612 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6613 si_set_vce_clock(rdev, new_ps, old_ps);
6614 if (eg_pi->pcie_performance_request)
6615 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6616 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6617 if (ret) {
6618 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6619 return ret;
6620 }
6621 ret = si_enable_smc_cac(rdev, new_ps, true);
6622 if (ret) {
6623 DRM_ERROR("si_enable_smc_cac failed\n");
6624 return ret;
6625 }
6626 ret = si_enable_power_containment(rdev, new_ps, true);
6627 if (ret) {
6628 DRM_ERROR("si_enable_power_containment failed\n");
6629 return ret;
6630 }
6631
6632 ret = si_power_control_set_level(rdev);
6633 if (ret) {
6634 DRM_ERROR("si_power_control_set_level failed\n");
6635 return ret;
6636 }
6637
6638 return 0;
6639}
6640
6641void si_dpm_post_set_power_state(struct radeon_device *rdev)
6642{
6643 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6644 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6645
6646 ni_update_current_ps(rdev, new_ps);
6647}
6648
6649#if 0
6650void si_dpm_reset_asic(struct radeon_device *rdev)
6651{
6652 si_restrict_performance_levels_before_switch(rdev);
6653 si_disable_ulv(rdev);
6654 si_set_boot_state(rdev);
6655}
6656#endif
6657
6658void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6659{
6660 si_program_display_gap(rdev);
6661}
6662
6663union power_info {
6664 struct _ATOM_POWERPLAY_INFO info;
6665 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6666 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6667 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6668 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6669 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6670};
6671
6672union pplib_clock_info {
6673 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6674 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6675 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6676 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6677 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6678};
6679
6680union pplib_power_state {
6681 struct _ATOM_PPLIB_STATE v1;
6682 struct _ATOM_PPLIB_STATE_V2 v2;
6683};
6684
6685static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6686 struct radeon_ps *rps,
6687 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6688 u8 table_rev)
6689{
6690 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6691 rps->class = le16_to_cpu(non_clock_info->usClassification);
6692 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6693
6694 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6695 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6696 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6697 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6698 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6699 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6700 } else {
6701 rps->vclk = 0;
6702 rps->dclk = 0;
6703 }
6704
6705 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6706 rdev->pm.dpm.boot_ps = rps;
6707 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6708 rdev->pm.dpm.uvd_ps = rps;
6709}
6710
6711static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6712 struct radeon_ps *rps, int index,
6713 union pplib_clock_info *clock_info)
6714{
6715 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6716 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6717 struct si_power_info *si_pi = si_get_pi(rdev);
6718 struct ni_ps *ps = ni_get_ps(rps);
6719 u16 leakage_voltage;
6720 struct rv7xx_pl *pl = &ps->performance_levels[index];
6721 int ret;
6722
6723 ps->performance_level_count = index + 1;
6724
6725 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6726 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6727 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6728 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6729
6730 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6731 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6732 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6733 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6734 si_pi->sys_pcie_mask,
6735 si_pi->boot_pcie_gen,
6736 clock_info->si.ucPCIEGen);
6737
6738 /* patch up vddc if necessary */
6739 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6740 &leakage_voltage);
6741 if (ret == 0)
6742 pl->vddc = leakage_voltage;
6743
6744 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6745 pi->acpi_vddc = pl->vddc;
6746 eg_pi->acpi_vddci = pl->vddci;
6747 si_pi->acpi_pcie_gen = pl->pcie_gen;
6748 }
6749
6750 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6751 index == 0) {
6752 /* XXX disable for A0 tahiti */
6753 si_pi->ulv.supported = false;
6754 si_pi->ulv.pl = *pl;
6755 si_pi->ulv.one_pcie_lane_in_ulv = false;
6756 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6757 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6758 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6759 }
6760
6761 if (pi->min_vddc_in_table > pl->vddc)
6762 pi->min_vddc_in_table = pl->vddc;
6763
6764 if (pi->max_vddc_in_table < pl->vddc)
6765 pi->max_vddc_in_table = pl->vddc;
6766
6767 /* patch up boot state */
6768 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6769 u16 vddc, vddci, mvdd;
6770 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6771 pl->mclk = rdev->clock.default_mclk;
6772 pl->sclk = rdev->clock.default_sclk;
6773 pl->vddc = vddc;
6774 pl->vddci = vddci;
6775 si_pi->mvdd_bootup_value = mvdd;
6776 }
6777
6778 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6779 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6780 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6781 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6782 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6783 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6784 }
6785}
6786
6787static int si_parse_power_table(struct radeon_device *rdev)
6788{
6789 struct radeon_mode_info *mode_info = &rdev->mode_info;
6790 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6791 union pplib_power_state *power_state;
6792 int i, j, k, non_clock_array_index, clock_array_index;
6793 union pplib_clock_info *clock_info;
6794 struct _StateArray *state_array;
6795 struct _ClockInfoArray *clock_info_array;
6796 struct _NonClockInfoArray *non_clock_info_array;
6797 union power_info *power_info;
6798 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6799 u16 data_offset;
6800 u8 frev, crev;
6801 u8 *power_state_offset;
6802 struct ni_ps *ps;
6803
6804 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6805 &frev, &crev, &data_offset))
6806 return -EINVAL;
6807 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6808
6809 state_array = (struct _StateArray *)
6810 (mode_info->atom_context->bios + data_offset +
6811 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6812 clock_info_array = (struct _ClockInfoArray *)
6813 (mode_info->atom_context->bios + data_offset +
6814 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6815 non_clock_info_array = (struct _NonClockInfoArray *)
6816 (mode_info->atom_context->bios + data_offset +
6817 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6818
6819 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
6820 sizeof(struct radeon_ps),
6821 GFP_KERNEL);
6822 if (!rdev->pm.dpm.ps)
6823 return -ENOMEM;
6824 power_state_offset = (u8 *)state_array->states;
6825 for (i = 0; i < state_array->ucNumEntries; i++) {
6826 u8 *idx;
6827 power_state = (union pplib_power_state *)power_state_offset;
6828 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6829 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6830 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6831 if (!rdev->pm.power_state[i].clock_info)
6832 return -EINVAL;
6833 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6834 if (ps == NULL) {
6835 kfree(rdev->pm.dpm.ps);
6836 return -ENOMEM;
6837 }
6838 rdev->pm.dpm.ps[i].ps_priv = ps;
6839 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6840 non_clock_info,
6841 non_clock_info_array->ucEntrySize);
6842 k = 0;
6843 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6844 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6845 clock_array_index = idx[j];
6846 if (clock_array_index >= clock_info_array->ucNumEntries)
6847 continue;
6848 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6849 break;
6850 clock_info = (union pplib_clock_info *)
6851 ((u8 *)&clock_info_array->clockInfo[0] +
6852 (clock_array_index * clock_info_array->ucEntrySize));
6853 si_parse_pplib_clock_info(rdev,
6854 &rdev->pm.dpm.ps[i], k,
6855 clock_info);
6856 k++;
6857 }
6858 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6859 }
6860 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6861
6862 /* fill in the vce power states */
6863 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6864 u32 sclk, mclk;
6865 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6866 clock_info = (union pplib_clock_info *)
6867 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6868 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6869 sclk |= clock_info->si.ucEngineClockHigh << 16;
6870 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6871 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6872 rdev->pm.dpm.vce_states[i].sclk = sclk;
6873 rdev->pm.dpm.vce_states[i].mclk = mclk;
6874 }
6875
6876 return 0;
6877}
6878
6879int si_dpm_init(struct radeon_device *rdev)
6880{
6881 struct rv7xx_power_info *pi;
6882 struct evergreen_power_info *eg_pi;
6883 struct ni_power_info *ni_pi;
6884 struct si_power_info *si_pi;
6885 struct atom_clock_dividers dividers;
6886 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN;
6887 struct pci_dev *root = rdev->pdev->bus->self;
6888 int ret;
6889
6890 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6891 if (si_pi == NULL)
6892 return -ENOMEM;
6893 rdev->pm.dpm.priv = si_pi;
6894 ni_pi = &si_pi->ni;
6895 eg_pi = &ni_pi->eg;
6896 pi = &eg_pi->rv7xx;
6897
6898 if (!pci_is_root_bus(rdev->pdev->bus))
6899 speed_cap = pcie_get_speed_cap(root);
6900 if (speed_cap == PCI_SPEED_UNKNOWN) {
6901 si_pi->sys_pcie_mask = 0;
6902 } else {
6903 if (speed_cap == PCIE_SPEED_8_0GT)
6904 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
6905 RADEON_PCIE_SPEED_50 |
6906 RADEON_PCIE_SPEED_80;
6907 else if (speed_cap == PCIE_SPEED_5_0GT)
6908 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
6909 RADEON_PCIE_SPEED_50;
6910 else
6911 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;
6912 }
6913 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6914 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6915
6916 si_set_max_cu_value(rdev);
6917
6918 rv770_get_max_vddc(rdev);
6919 si_get_leakage_vddc(rdev);
6920 si_patch_dependency_tables_based_on_leakage(rdev);
6921
6922 pi->acpi_vddc = 0;
6923 eg_pi->acpi_vddci = 0;
6924 pi->min_vddc_in_table = 0;
6925 pi->max_vddc_in_table = 0;
6926
6927 ret = r600_get_platform_caps(rdev);
6928 if (ret)
6929 return ret;
6930
6931 ret = r600_parse_extended_power_table(rdev);
6932 if (ret)
6933 return ret;
6934
6935 ret = si_parse_power_table(rdev);
6936 if (ret)
6937 return ret;
6938
6939 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6940 kcalloc(4,
6941 sizeof(struct radeon_clock_voltage_dependency_entry),
6942 GFP_KERNEL);
6943 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6944 r600_free_extended_power_table(rdev);
6945 return -ENOMEM;
6946 }
6947 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6948 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6949 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6950 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6951 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6952 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6953 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6954 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6955 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6956
6957 if (rdev->pm.dpm.voltage_response_time == 0)
6958 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6959 if (rdev->pm.dpm.backbias_response_time == 0)
6960 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6961
6962 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6963 0, false, ÷rs);
6964 if (ret)
6965 pi->ref_div = dividers.ref_div + 1;
6966 else
6967 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6968
6969 eg_pi->smu_uvd_hs = false;
6970
6971 pi->mclk_strobe_mode_threshold = 40000;
6972 if (si_is_special_1gb_platform(rdev))
6973 pi->mclk_stutter_mode_threshold = 0;
6974 else
6975 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6976 pi->mclk_edc_enable_threshold = 40000;
6977 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6978
6979 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6980
6981 pi->voltage_control =
6982 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6983 VOLTAGE_OBJ_GPIO_LUT);
6984 if (!pi->voltage_control) {
6985 si_pi->voltage_control_svi2 =
6986 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6987 VOLTAGE_OBJ_SVID2);
6988 if (si_pi->voltage_control_svi2)
6989 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6990 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
6991 }
6992
6993 pi->mvdd_control =
6994 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
6995 VOLTAGE_OBJ_GPIO_LUT);
6996
6997 eg_pi->vddci_control =
6998 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6999 VOLTAGE_OBJ_GPIO_LUT);
7000 if (!eg_pi->vddci_control)
7001 si_pi->vddci_control_svi2 =
7002 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7003 VOLTAGE_OBJ_SVID2);
7004
7005 si_pi->vddc_phase_shed_control =
7006 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7007 VOLTAGE_OBJ_PHASE_LUT);
7008
7009 rv770_get_engine_memory_ss(rdev);
7010
7011 pi->asi = RV770_ASI_DFLT;
7012 pi->pasi = CYPRESS_HASI_DFLT;
7013 pi->vrc = SISLANDS_VRC_DFLT;
7014
7015 pi->gfx_clock_gating = true;
7016
7017 eg_pi->sclk_deep_sleep = true;
7018 si_pi->sclk_deep_sleep_above_low = false;
7019
7020 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7021 pi->thermal_protection = true;
7022 else
7023 pi->thermal_protection = false;
7024
7025 eg_pi->dynamic_ac_timing = true;
7026
7027 eg_pi->light_sleep = true;
7028#if defined(CONFIG_ACPI)
7029 eg_pi->pcie_performance_request =
7030 radeon_acpi_is_pcie_performance_request_supported(rdev);
7031#else
7032 eg_pi->pcie_performance_request = false;
7033#endif
7034
7035 si_pi->sram_end = SMC_RAM_END;
7036
7037 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7038 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7039 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7040 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7041 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7042 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7043 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7044
7045 si_initialize_powertune_defaults(rdev);
7046
7047 /* make sure dc limits are valid */
7048 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7049 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7050 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7051 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7052
7053 si_pi->fan_ctrl_is_in_default_mode = true;
7054
7055 return 0;
7056}
7057
7058void si_dpm_fini(struct radeon_device *rdev)
7059{
7060 int i;
7061
7062 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7063 kfree(rdev->pm.dpm.ps[i].ps_priv);
7064 }
7065 kfree(rdev->pm.dpm.ps);
7066 kfree(rdev->pm.dpm.priv);
7067 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7068 r600_free_extended_power_table(rdev);
7069}
7070
7071void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7072 struct seq_file *m)
7073{
7074 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7075 struct radeon_ps *rps = &eg_pi->current_rps;
7076 struct ni_ps *ps = ni_get_ps(rps);
7077 struct rv7xx_pl *pl;
7078 u32 current_index =
7079 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7080 CURRENT_STATE_INDEX_SHIFT;
7081
7082 if (current_index >= ps->performance_level_count) {
7083 seq_printf(m, "invalid dpm profile %d\n", current_index);
7084 } else {
7085 pl = &ps->performance_levels[current_index];
7086 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7087 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7088 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7089 }
7090}
7091
7092u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7093{
7094 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7095 struct radeon_ps *rps = &eg_pi->current_rps;
7096 struct ni_ps *ps = ni_get_ps(rps);
7097 struct rv7xx_pl *pl;
7098 u32 current_index =
7099 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7100 CURRENT_STATE_INDEX_SHIFT;
7101
7102 if (current_index >= ps->performance_level_count) {
7103 return 0;
7104 } else {
7105 pl = &ps->performance_levels[current_index];
7106 return pl->sclk;
7107 }
7108}
7109
7110u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7111{
7112 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7113 struct radeon_ps *rps = &eg_pi->current_rps;
7114 struct ni_ps *ps = ni_get_ps(rps);
7115 struct rv7xx_pl *pl;
7116 u32 current_index =
7117 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7118 CURRENT_STATE_INDEX_SHIFT;
7119
7120 if (current_index >= ps->performance_level_count) {
7121 return 0;
7122 } else {
7123 pl = &ps->performance_levels[current_index];
7124 return pl->mclk;
7125 }
7126}