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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#include <drm/drmP.h>
28#include <drm/radeon_drm.h>
29#include "radeon.h"
30
31#include "atom.h"
32#include "atom-bits.h"
33#include <drm/drm_dp_helper.h>
34
35/* move these to drm_dp_helper.c/h */
36#define DP_LINK_CONFIGURATION_SIZE 9
37#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
45
46/***** radeon AUX functions *****/
47
48/* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
51 * dw units.
52 */
53void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
54{
55#ifdef __BIG_ENDIAN
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
57 u32 *dst32, *src32;
58 int i;
59
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
63 if (to_le) {
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
67 } else {
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
72 if (num_bytes % 4) {
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
75 }
76 }
77#else
78 memcpy(dst, src, num_bytes);
79#endif
80}
81
82union aux_channel_transaction {
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
85};
86
87static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 u8 *send, int send_bytes,
89 u8 *recv, int recv_size,
90 u8 delay, u8 *ack)
91{
92 struct drm_device *dev = chan->dev;
93 struct radeon_device *rdev = dev->dev_private;
94 union aux_channel_transaction args;
95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
96 unsigned char *base;
97 int recv_bytes;
98 int r = 0;
99
100 memset(&args, 0, sizeof(args));
101
102 mutex_lock(&chan->mutex);
103 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
104
105 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
106
107 radeon_atom_copy_swap(base, send, send_bytes, true);
108
109 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
110 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
111 args.v1.ucDataOutLen = 0;
112 args.v1.ucChannelID = chan->rec.i2c_id;
113 args.v1.ucDelay = delay / 10;
114 if (ASIC_IS_DCE4(rdev))
115 args.v2.ucHPD_ID = chan->rec.hpd;
116
117 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
118
119 *ack = args.v1.ucReplyStatus;
120
121 /* timeout */
122 if (args.v1.ucReplyStatus == 1) {
123 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
124 r = -ETIMEDOUT;
125 goto done;
126 }
127
128 /* flags not zero */
129 if (args.v1.ucReplyStatus == 2) {
130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
131 r = -EIO;
132 goto done;
133 }
134
135 /* error */
136 if (args.v1.ucReplyStatus == 3) {
137 DRM_DEBUG_KMS("dp_aux_ch error\n");
138 r = -EIO;
139 goto done;
140 }
141
142 recv_bytes = args.v1.ucDataOutLen;
143 if (recv_bytes > recv_size)
144 recv_bytes = recv_size;
145
146 if (recv && recv_size)
147 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
148
149 r = recv_bytes;
150done:
151 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
152 mutex_unlock(&chan->mutex);
153
154 return r;
155}
156
157#define BARE_ADDRESS_SIZE 3
158#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
159
160static ssize_t
161radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
162{
163 struct radeon_i2c_chan *chan =
164 container_of(aux, struct radeon_i2c_chan, aux);
165 int ret;
166 u8 tx_buf[20];
167 size_t tx_size;
168 u8 ack, delay = 0;
169
170 if (WARN_ON(msg->size > 16))
171 return -E2BIG;
172
173 tx_buf[0] = msg->address & 0xff;
174 tx_buf[1] = (msg->address >> 8) & 0xff;
175 tx_buf[2] = (msg->request << 4) |
176 ((msg->address >> 16) & 0xf);
177 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
178
179 switch (msg->request & ~DP_AUX_I2C_MOT) {
180 case DP_AUX_NATIVE_WRITE:
181 case DP_AUX_I2C_WRITE:
182 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
183 /* The atom implementation only supports writes with a max payload of
184 * 12 bytes since it uses 4 bits for the total count (header + payload)
185 * in the parameter space. The atom interface supports 16 byte
186 * payloads for reads. The hw itself supports up to 16 bytes of payload.
187 */
188 if (WARN_ON_ONCE(msg->size > 12))
189 return -E2BIG;
190 /* tx_size needs to be 4 even for bare address packets since the atom
191 * table needs the info in tx_buf[3].
192 */
193 tx_size = HEADER_SIZE + msg->size;
194 if (msg->size == 0)
195 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
196 else
197 tx_buf[3] |= tx_size << 4;
198 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
199 ret = radeon_process_aux_ch(chan,
200 tx_buf, tx_size, NULL, 0, delay, &ack);
201 if (ret >= 0)
202 /* Return payload size. */
203 ret = msg->size;
204 break;
205 case DP_AUX_NATIVE_READ:
206 case DP_AUX_I2C_READ:
207 /* tx_size needs to be 4 even for bare address packets since the atom
208 * table needs the info in tx_buf[3].
209 */
210 tx_size = HEADER_SIZE;
211 if (msg->size == 0)
212 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
213 else
214 tx_buf[3] |= tx_size << 4;
215 ret = radeon_process_aux_ch(chan,
216 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
217 break;
218 default:
219 ret = -EINVAL;
220 break;
221 }
222
223 if (ret >= 0)
224 msg->reply = ack >> 4;
225
226 return ret;
227}
228
229void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
230{
231 struct drm_device *dev = radeon_connector->base.dev;
232 struct radeon_device *rdev = dev->dev_private;
233 int ret;
234
235 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
236 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
237 if (ASIC_IS_DCE5(rdev)) {
238 if (radeon_auxch)
239 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
240 else
241 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
242 } else {
243 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
244 }
245
246 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
247 if (!ret)
248 radeon_connector->ddc_bus->has_aux = true;
249
250 WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
251}
252
253/***** general DP utility functions *****/
254
255#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
256#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
257
258static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
259 int lane_count,
260 u8 train_set[4])
261{
262 u8 v = 0;
263 u8 p = 0;
264 int lane;
265
266 for (lane = 0; lane < lane_count; lane++) {
267 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
268 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
269
270 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
271 lane,
272 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
273 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
274
275 if (this_v > v)
276 v = this_v;
277 if (this_p > p)
278 p = this_p;
279 }
280
281 if (v >= DP_VOLTAGE_MAX)
282 v |= DP_TRAIN_MAX_SWING_REACHED;
283
284 if (p >= DP_PRE_EMPHASIS_MAX)
285 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
286
287 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
288 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
289 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
290
291 for (lane = 0; lane < 4; lane++)
292 train_set[lane] = v | p;
293}
294
295/* convert bits per color to bits per pixel */
296/* get bpc from the EDID */
297static int convert_bpc_to_bpp(int bpc)
298{
299 if (bpc == 0)
300 return 24;
301 else
302 return bpc * 3;
303}
304
305/***** radeon specific DP functions *****/
306
307int radeon_dp_get_dp_link_config(struct drm_connector *connector,
308 const u8 dpcd[DP_DPCD_SIZE],
309 unsigned pix_clock,
310 unsigned *dp_lanes, unsigned *dp_rate)
311{
312 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
313 static const unsigned link_rates[3] = { 162000, 270000, 540000 };
314 unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
315 unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
316 unsigned lane_num, i, max_pix_clock;
317
318 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
319 ENCODER_OBJECT_ID_NUTMEG) {
320 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
321 max_pix_clock = (lane_num * 270000 * 8) / bpp;
322 if (max_pix_clock >= pix_clock) {
323 *dp_lanes = lane_num;
324 *dp_rate = 270000;
325 return 0;
326 }
327 }
328 } else {
329 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
330 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
331 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
332 if (max_pix_clock >= pix_clock) {
333 *dp_lanes = lane_num;
334 *dp_rate = link_rates[i];
335 return 0;
336 }
337 }
338 }
339 }
340
341 return -EINVAL;
342}
343
344static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
345 int action, int dp_clock,
346 u8 ucconfig, u8 lane_num)
347{
348 DP_ENCODER_SERVICE_PARAMETERS args;
349 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
350
351 memset(&args, 0, sizeof(args));
352 args.ucLinkClock = dp_clock / 10;
353 args.ucConfig = ucconfig;
354 args.ucAction = action;
355 args.ucLaneNum = lane_num;
356 args.ucStatus = 0;
357
358 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
359 return args.ucStatus;
360}
361
362u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
363{
364 struct drm_device *dev = radeon_connector->base.dev;
365 struct radeon_device *rdev = dev->dev_private;
366
367 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
368 radeon_connector->ddc_bus->rec.i2c_id, 0);
369}
370
371static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
372{
373 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
374 u8 buf[3];
375
376 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
377 return;
378
379 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
380 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
381 buf[0], buf[1], buf[2]);
382
383 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
384 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
385 buf[0], buf[1], buf[2]);
386}
387
388bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
389{
390 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
391 u8 msg[DP_DPCD_SIZE];
392 int ret, i;
393
394 for (i = 0; i < 7; i++) {
395 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
396 DP_DPCD_SIZE);
397 if (ret == DP_DPCD_SIZE) {
398 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
399
400 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
401 dig_connector->dpcd);
402
403 radeon_dp_probe_oui(radeon_connector);
404
405 return true;
406 }
407 }
408 dig_connector->dpcd[0] = 0;
409 return false;
410}
411
412int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
413 struct drm_connector *connector)
414{
415 struct drm_device *dev = encoder->dev;
416 struct radeon_device *rdev = dev->dev_private;
417 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
418 struct radeon_connector_atom_dig *dig_connector;
419 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
420 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
421 u8 tmp;
422
423 if (!ASIC_IS_DCE4(rdev))
424 return panel_mode;
425
426 if (!radeon_connector->con_priv)
427 return panel_mode;
428
429 dig_connector = radeon_connector->con_priv;
430
431 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
432 /* DP bridge chips */
433 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
434 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
435 if (tmp & 1)
436 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
437 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
438 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
439 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
440 else
441 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
442 }
443 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
444 /* eDP */
445 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
446 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
447 if (tmp & 1)
448 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
449 }
450 }
451
452 return panel_mode;
453}
454
455void radeon_dp_set_link_config(struct drm_connector *connector,
456 const struct drm_display_mode *mode)
457{
458 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
459 struct radeon_connector_atom_dig *dig_connector;
460 int ret;
461
462 if (!radeon_connector->con_priv)
463 return;
464 dig_connector = radeon_connector->con_priv;
465
466 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
467 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
468 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
469 mode->clock,
470 &dig_connector->dp_lane_count,
471 &dig_connector->dp_clock);
472 if (ret) {
473 dig_connector->dp_clock = 0;
474 dig_connector->dp_lane_count = 0;
475 }
476 }
477}
478
479int radeon_dp_mode_valid_helper(struct drm_connector *connector,
480 struct drm_display_mode *mode)
481{
482 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
483 struct radeon_connector_atom_dig *dig_connector;
484 unsigned dp_clock, dp_lanes;
485 int ret;
486
487 if ((mode->clock > 340000) &&
488 (!radeon_connector_is_dp12_capable(connector)))
489 return MODE_CLOCK_HIGH;
490
491 if (!radeon_connector->con_priv)
492 return MODE_CLOCK_HIGH;
493 dig_connector = radeon_connector->con_priv;
494
495 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
496 mode->clock,
497 &dp_lanes,
498 &dp_clock);
499 if (ret)
500 return MODE_CLOCK_HIGH;
501
502 if ((dp_clock == 540000) &&
503 (!radeon_connector_is_dp12_capable(connector)))
504 return MODE_CLOCK_HIGH;
505
506 return MODE_OK;
507}
508
509bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
510{
511 u8 link_status[DP_LINK_STATUS_SIZE];
512 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
513
514 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
515 <= 0)
516 return false;
517 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
518 return false;
519 return true;
520}
521
522void radeon_dp_set_rx_power_state(struct drm_connector *connector,
523 u8 power_state)
524{
525 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
526 struct radeon_connector_atom_dig *dig_connector;
527
528 if (!radeon_connector->con_priv)
529 return;
530
531 dig_connector = radeon_connector->con_priv;
532
533 /* power up/down the sink */
534 if (dig_connector->dpcd[0] >= 0x11) {
535 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
536 DP_SET_POWER, power_state);
537 usleep_range(1000, 2000);
538 }
539}
540
541
542struct radeon_dp_link_train_info {
543 struct radeon_device *rdev;
544 struct drm_encoder *encoder;
545 struct drm_connector *connector;
546 int enc_id;
547 int dp_clock;
548 int dp_lane_count;
549 bool tp3_supported;
550 u8 dpcd[DP_RECEIVER_CAP_SIZE];
551 u8 train_set[4];
552 u8 link_status[DP_LINK_STATUS_SIZE];
553 u8 tries;
554 bool use_dpencoder;
555 struct drm_dp_aux *aux;
556};
557
558static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
559{
560 /* set the initial vs/emph on the source */
561 atombios_dig_transmitter_setup(dp_info->encoder,
562 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
563 0, dp_info->train_set[0]); /* sets all lanes at once */
564
565 /* set the vs/emph on the sink */
566 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
567 dp_info->train_set, dp_info->dp_lane_count);
568}
569
570static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
571{
572 int rtp = 0;
573
574 /* set training pattern on the source */
575 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
576 switch (tp) {
577 case DP_TRAINING_PATTERN_1:
578 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
579 break;
580 case DP_TRAINING_PATTERN_2:
581 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
582 break;
583 case DP_TRAINING_PATTERN_3:
584 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
585 break;
586 }
587 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
588 } else {
589 switch (tp) {
590 case DP_TRAINING_PATTERN_1:
591 rtp = 0;
592 break;
593 case DP_TRAINING_PATTERN_2:
594 rtp = 1;
595 break;
596 }
597 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
598 dp_info->dp_clock, dp_info->enc_id, rtp);
599 }
600
601 /* enable training pattern on the sink */
602 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
603}
604
605static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
606{
607 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
608 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
609 u8 tmp;
610
611 /* power up the sink */
612 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
613
614 /* possibly enable downspread on the sink */
615 if (dp_info->dpcd[3] & 0x1)
616 drm_dp_dpcd_writeb(dp_info->aux,
617 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
618 else
619 drm_dp_dpcd_writeb(dp_info->aux,
620 DP_DOWNSPREAD_CTRL, 0);
621
622 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
623 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
624
625 /* set the lane count on the sink */
626 tmp = dp_info->dp_lane_count;
627 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
628 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
629 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
630
631 /* set the link rate on the sink */
632 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
633 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
634
635 /* start training on the source */
636 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
637 atombios_dig_encoder_setup(dp_info->encoder,
638 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
639 else
640 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
641 dp_info->dp_clock, dp_info->enc_id, 0);
642
643 /* disable the training pattern on the sink */
644 drm_dp_dpcd_writeb(dp_info->aux,
645 DP_TRAINING_PATTERN_SET,
646 DP_TRAINING_PATTERN_DISABLE);
647
648 return 0;
649}
650
651static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
652{
653 udelay(400);
654
655 /* disable the training pattern on the sink */
656 drm_dp_dpcd_writeb(dp_info->aux,
657 DP_TRAINING_PATTERN_SET,
658 DP_TRAINING_PATTERN_DISABLE);
659
660 /* disable the training pattern on the source */
661 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
662 atombios_dig_encoder_setup(dp_info->encoder,
663 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
664 else
665 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
666 dp_info->dp_clock, dp_info->enc_id, 0);
667
668 return 0;
669}
670
671static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
672{
673 bool clock_recovery;
674 u8 voltage;
675 int i;
676
677 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
678 memset(dp_info->train_set, 0, 4);
679 radeon_dp_update_vs_emph(dp_info);
680
681 udelay(400);
682
683 /* clock recovery loop */
684 clock_recovery = false;
685 dp_info->tries = 0;
686 voltage = 0xff;
687 while (1) {
688 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
689
690 if (drm_dp_dpcd_read_link_status(dp_info->aux,
691 dp_info->link_status) <= 0) {
692 DRM_ERROR("displayport link status failed\n");
693 break;
694 }
695
696 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
697 clock_recovery = true;
698 break;
699 }
700
701 for (i = 0; i < dp_info->dp_lane_count; i++) {
702 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
703 break;
704 }
705 if (i == dp_info->dp_lane_count) {
706 DRM_ERROR("clock recovery reached max voltage\n");
707 break;
708 }
709
710 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
711 ++dp_info->tries;
712 if (dp_info->tries == 5) {
713 DRM_ERROR("clock recovery tried 5 times\n");
714 break;
715 }
716 } else
717 dp_info->tries = 0;
718
719 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
720
721 /* Compute new train_set as requested by sink */
722 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
723
724 radeon_dp_update_vs_emph(dp_info);
725 }
726 if (!clock_recovery) {
727 DRM_ERROR("clock recovery failed\n");
728 return -1;
729 } else {
730 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
731 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
732 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
733 DP_TRAIN_PRE_EMPHASIS_SHIFT);
734 return 0;
735 }
736}
737
738static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
739{
740 bool channel_eq;
741
742 if (dp_info->tp3_supported)
743 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
744 else
745 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
746
747 /* channel equalization loop */
748 dp_info->tries = 0;
749 channel_eq = false;
750 while (1) {
751 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
752
753 if (drm_dp_dpcd_read_link_status(dp_info->aux,
754 dp_info->link_status) <= 0) {
755 DRM_ERROR("displayport link status failed\n");
756 break;
757 }
758
759 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
760 channel_eq = true;
761 break;
762 }
763
764 /* Try 5 times */
765 if (dp_info->tries > 5) {
766 DRM_ERROR("channel eq failed: 5 tries\n");
767 break;
768 }
769
770 /* Compute new train_set as requested by sink */
771 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
772
773 radeon_dp_update_vs_emph(dp_info);
774 dp_info->tries++;
775 }
776
777 if (!channel_eq) {
778 DRM_ERROR("channel eq failed\n");
779 return -1;
780 } else {
781 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
782 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
783 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
784 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
785 return 0;
786 }
787}
788
789void radeon_dp_link_train(struct drm_encoder *encoder,
790 struct drm_connector *connector)
791{
792 struct drm_device *dev = encoder->dev;
793 struct radeon_device *rdev = dev->dev_private;
794 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
795 struct radeon_encoder_atom_dig *dig;
796 struct radeon_connector *radeon_connector;
797 struct radeon_connector_atom_dig *dig_connector;
798 struct radeon_dp_link_train_info dp_info;
799 int index;
800 u8 tmp, frev, crev;
801
802 if (!radeon_encoder->enc_priv)
803 return;
804 dig = radeon_encoder->enc_priv;
805
806 radeon_connector = to_radeon_connector(connector);
807 if (!radeon_connector->con_priv)
808 return;
809 dig_connector = radeon_connector->con_priv;
810
811 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
812 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
813 return;
814
815 /* DPEncoderService newer than 1.1 can't program properly the
816 * training pattern. When facing such version use the
817 * DIGXEncoderControl (X== 1 | 2)
818 */
819 dp_info.use_dpencoder = true;
820 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
821 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
822 if (crev > 1) {
823 dp_info.use_dpencoder = false;
824 }
825 }
826
827 dp_info.enc_id = 0;
828 if (dig->dig_encoder)
829 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
830 else
831 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
832 if (dig->linkb)
833 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
834 else
835 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
836
837 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
838 == 1) {
839 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
840 dp_info.tp3_supported = true;
841 else
842 dp_info.tp3_supported = false;
843 } else {
844 dp_info.tp3_supported = false;
845 }
846
847 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
848 dp_info.rdev = rdev;
849 dp_info.encoder = encoder;
850 dp_info.connector = connector;
851 dp_info.dp_lane_count = dig_connector->dp_lane_count;
852 dp_info.dp_clock = dig_connector->dp_clock;
853 dp_info.aux = &radeon_connector->ddc_bus->aux;
854
855 if (radeon_dp_link_train_init(&dp_info))
856 goto done;
857 if (radeon_dp_link_train_cr(&dp_info))
858 goto done;
859 if (radeon_dp_link_train_ce(&dp_info))
860 goto done;
861done:
862 if (radeon_dp_link_train_finish(&dp_info))
863 return;
864}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27
28#include <drm/radeon_drm.h>
29#include "radeon.h"
30
31#include "atom.h"
32#include "atom-bits.h"
33#include <drm/drm_dp_helper.h>
34
35/* move these to drm_dp_helper.c/h */
36#define DP_LINK_CONFIGURATION_SIZE 9
37#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
45
46/***** radeon AUX functions *****/
47
48/* Atom needs data in little endian format so swap as appropriate when copying
49 * data to or from atom. Note that atom operates on dw units.
50 *
51 * Use to_le=true when sending data to atom and provide at least
52 * ALIGN(num_bytes,4) bytes in the dst buffer.
53 *
54 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
55 * byes in the src buffer.
56 */
57void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
58{
59#ifdef __BIG_ENDIAN
60 u32 src_tmp[5], dst_tmp[5];
61 int i;
62 u8 align_num_bytes = ALIGN(num_bytes, 4);
63
64 if (to_le) {
65 memcpy(src_tmp, src, num_bytes);
66 for (i = 0; i < align_num_bytes / 4; i++)
67 dst_tmp[i] = cpu_to_le32(src_tmp[i]);
68 memcpy(dst, dst_tmp, align_num_bytes);
69 } else {
70 memcpy(src_tmp, src, align_num_bytes);
71 for (i = 0; i < align_num_bytes / 4; i++)
72 dst_tmp[i] = le32_to_cpu(src_tmp[i]);
73 memcpy(dst, dst_tmp, num_bytes);
74 }
75#else
76 memcpy(dst, src, num_bytes);
77#endif
78}
79
80union aux_channel_transaction {
81 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
82 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
83};
84
85static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
86 u8 *send, int send_bytes,
87 u8 *recv, int recv_size,
88 u8 delay, u8 *ack)
89{
90 struct drm_device *dev = chan->dev;
91 struct radeon_device *rdev = dev->dev_private;
92 union aux_channel_transaction args;
93 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
94 unsigned char *base;
95 int recv_bytes;
96 int r = 0;
97
98 memset(&args, 0, sizeof(args));
99
100 mutex_lock(&chan->mutex);
101 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
102
103 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
104
105 radeon_atom_copy_swap(base, send, send_bytes, true);
106
107 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
108 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
109 args.v1.ucDataOutLen = 0;
110 args.v1.ucChannelID = chan->rec.i2c_id;
111 args.v1.ucDelay = delay / 10;
112 if (ASIC_IS_DCE4(rdev))
113 args.v2.ucHPD_ID = chan->rec.hpd;
114
115 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116
117 *ack = args.v1.ucReplyStatus;
118
119 /* timeout */
120 if (args.v1.ucReplyStatus == 1) {
121 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
122 r = -ETIMEDOUT;
123 goto done;
124 }
125
126 /* flags not zero */
127 if (args.v1.ucReplyStatus == 2) {
128 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
129 r = -EIO;
130 goto done;
131 }
132
133 /* error */
134 if (args.v1.ucReplyStatus == 3) {
135 DRM_DEBUG_KMS("dp_aux_ch error\n");
136 r = -EIO;
137 goto done;
138 }
139
140 recv_bytes = args.v1.ucDataOutLen;
141 if (recv_bytes > recv_size)
142 recv_bytes = recv_size;
143
144 if (recv && recv_size)
145 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
146
147 r = recv_bytes;
148done:
149 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
150 mutex_unlock(&chan->mutex);
151
152 return r;
153}
154
155#define BARE_ADDRESS_SIZE 3
156#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
157
158static ssize_t
159radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
160{
161 struct radeon_i2c_chan *chan =
162 container_of(aux, struct radeon_i2c_chan, aux);
163 int ret;
164 u8 tx_buf[20];
165 size_t tx_size;
166 u8 ack, delay = 0;
167
168 if (WARN_ON(msg->size > 16))
169 return -E2BIG;
170
171 tx_buf[0] = msg->address & 0xff;
172 tx_buf[1] = (msg->address >> 8) & 0xff;
173 tx_buf[2] = (msg->request << 4) |
174 ((msg->address >> 16) & 0xf);
175 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
176
177 switch (msg->request & ~DP_AUX_I2C_MOT) {
178 case DP_AUX_NATIVE_WRITE:
179 case DP_AUX_I2C_WRITE:
180 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
181 /* The atom implementation only supports writes with a max payload of
182 * 12 bytes since it uses 4 bits for the total count (header + payload)
183 * in the parameter space. The atom interface supports 16 byte
184 * payloads for reads. The hw itself supports up to 16 bytes of payload.
185 */
186 if (WARN_ON_ONCE(msg->size > 12))
187 return -E2BIG;
188 /* tx_size needs to be 4 even for bare address packets since the atom
189 * table needs the info in tx_buf[3].
190 */
191 tx_size = HEADER_SIZE + msg->size;
192 if (msg->size == 0)
193 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
194 else
195 tx_buf[3] |= tx_size << 4;
196 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
197 ret = radeon_process_aux_ch(chan,
198 tx_buf, tx_size, NULL, 0, delay, &ack);
199 if (ret >= 0)
200 /* Return payload size. */
201 ret = msg->size;
202 break;
203 case DP_AUX_NATIVE_READ:
204 case DP_AUX_I2C_READ:
205 /* tx_size needs to be 4 even for bare address packets since the atom
206 * table needs the info in tx_buf[3].
207 */
208 tx_size = HEADER_SIZE;
209 if (msg->size == 0)
210 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
211 else
212 tx_buf[3] |= tx_size << 4;
213 ret = radeon_process_aux_ch(chan,
214 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
215 break;
216 default:
217 ret = -EINVAL;
218 break;
219 }
220
221 if (ret >= 0)
222 msg->reply = ack >> 4;
223
224 return ret;
225}
226
227void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
228{
229 struct drm_device *dev = radeon_connector->base.dev;
230 struct radeon_device *rdev = dev->dev_private;
231 int ret;
232
233 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
234 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
235 if (ASIC_IS_DCE5(rdev)) {
236 if (radeon_auxch)
237 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
238 else
239 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
240 } else {
241 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
242 }
243
244 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
245 if (!ret)
246 radeon_connector->ddc_bus->has_aux = true;
247
248 WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
249}
250
251/***** general DP utility functions *****/
252
253#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
254#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
255
256static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
257 int lane_count,
258 u8 train_set[4])
259{
260 u8 v = 0;
261 u8 p = 0;
262 int lane;
263
264 for (lane = 0; lane < lane_count; lane++) {
265 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
266 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
267
268 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
269 lane,
270 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
271 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
272
273 if (this_v > v)
274 v = this_v;
275 if (this_p > p)
276 p = this_p;
277 }
278
279 if (v >= DP_VOLTAGE_MAX)
280 v |= DP_TRAIN_MAX_SWING_REACHED;
281
282 if (p >= DP_PRE_EMPHASIS_MAX)
283 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
284
285 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
286 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
287 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
288
289 for (lane = 0; lane < 4; lane++)
290 train_set[lane] = v | p;
291}
292
293/* convert bits per color to bits per pixel */
294/* get bpc from the EDID */
295static int convert_bpc_to_bpp(int bpc)
296{
297 if (bpc == 0)
298 return 24;
299 else
300 return bpc * 3;
301}
302
303/***** radeon specific DP functions *****/
304
305static int radeon_dp_get_dp_link_config(struct drm_connector *connector,
306 const u8 dpcd[DP_DPCD_SIZE],
307 unsigned pix_clock,
308 unsigned *dp_lanes, unsigned *dp_rate)
309{
310 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
311 static const unsigned link_rates[3] = { 162000, 270000, 540000 };
312 unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
313 unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
314 unsigned lane_num, i, max_pix_clock;
315
316 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
317 ENCODER_OBJECT_ID_NUTMEG) {
318 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
319 max_pix_clock = (lane_num * 270000 * 8) / bpp;
320 if (max_pix_clock >= pix_clock) {
321 *dp_lanes = lane_num;
322 *dp_rate = 270000;
323 return 0;
324 }
325 }
326 } else {
327 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
328 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
329 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
330 if (max_pix_clock >= pix_clock) {
331 *dp_lanes = lane_num;
332 *dp_rate = link_rates[i];
333 return 0;
334 }
335 }
336 }
337 }
338
339 return -EINVAL;
340}
341
342static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
343 int action, int dp_clock,
344 u8 ucconfig, u8 lane_num)
345{
346 DP_ENCODER_SERVICE_PARAMETERS args;
347 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
348
349 memset(&args, 0, sizeof(args));
350 args.ucLinkClock = dp_clock / 10;
351 args.ucConfig = ucconfig;
352 args.ucAction = action;
353 args.ucLaneNum = lane_num;
354 args.ucStatus = 0;
355
356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
357 return args.ucStatus;
358}
359
360u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
361{
362 struct drm_device *dev = radeon_connector->base.dev;
363 struct radeon_device *rdev = dev->dev_private;
364
365 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
366 radeon_connector->ddc_bus->rec.i2c_id, 0);
367}
368
369static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
370{
371 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
372 u8 buf[3];
373
374 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
375 return;
376
377 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
378 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
379 buf[0], buf[1], buf[2]);
380
381 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
382 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
383 buf[0], buf[1], buf[2]);
384}
385
386bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
387{
388 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
389 u8 msg[DP_DPCD_SIZE];
390 int ret;
391
392 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
393 DP_DPCD_SIZE);
394 if (ret == DP_DPCD_SIZE) {
395 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
396
397 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
398 dig_connector->dpcd);
399
400 radeon_dp_probe_oui(radeon_connector);
401
402 return true;
403 }
404
405 dig_connector->dpcd[0] = 0;
406 return false;
407}
408
409int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
410 struct drm_connector *connector)
411{
412 struct drm_device *dev = encoder->dev;
413 struct radeon_device *rdev = dev->dev_private;
414 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
415 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
416 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
417 u8 tmp;
418
419 if (!ASIC_IS_DCE4(rdev))
420 return panel_mode;
421
422 if (!radeon_connector->con_priv)
423 return panel_mode;
424
425 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
426 /* DP bridge chips */
427 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
428 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
429 if (tmp & 1)
430 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
431 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
432 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
433 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
434 else
435 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
436 }
437 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
438 /* eDP */
439 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
440 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
441 if (tmp & 1)
442 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
443 }
444 }
445
446 return panel_mode;
447}
448
449void radeon_dp_set_link_config(struct drm_connector *connector,
450 const struct drm_display_mode *mode)
451{
452 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
453 struct radeon_connector_atom_dig *dig_connector;
454 int ret;
455
456 if (!radeon_connector->con_priv)
457 return;
458 dig_connector = radeon_connector->con_priv;
459
460 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
461 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
462 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
463 mode->clock,
464 &dig_connector->dp_lane_count,
465 &dig_connector->dp_clock);
466 if (ret) {
467 dig_connector->dp_clock = 0;
468 dig_connector->dp_lane_count = 0;
469 }
470 }
471}
472
473int radeon_dp_mode_valid_helper(struct drm_connector *connector,
474 struct drm_display_mode *mode)
475{
476 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
477 struct radeon_connector_atom_dig *dig_connector;
478 unsigned dp_clock, dp_lanes;
479 int ret;
480
481 if ((mode->clock > 340000) &&
482 (!radeon_connector_is_dp12_capable(connector)))
483 return MODE_CLOCK_HIGH;
484
485 if (!radeon_connector->con_priv)
486 return MODE_CLOCK_HIGH;
487 dig_connector = radeon_connector->con_priv;
488
489 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
490 mode->clock,
491 &dp_lanes,
492 &dp_clock);
493 if (ret)
494 return MODE_CLOCK_HIGH;
495
496 if ((dp_clock == 540000) &&
497 (!radeon_connector_is_dp12_capable(connector)))
498 return MODE_CLOCK_HIGH;
499
500 return MODE_OK;
501}
502
503bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
504{
505 u8 link_status[DP_LINK_STATUS_SIZE];
506 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
507
508 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
509 <= 0)
510 return false;
511 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
512 return false;
513 return true;
514}
515
516void radeon_dp_set_rx_power_state(struct drm_connector *connector,
517 u8 power_state)
518{
519 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
520 struct radeon_connector_atom_dig *dig_connector;
521
522 if (!radeon_connector->con_priv)
523 return;
524
525 dig_connector = radeon_connector->con_priv;
526
527 /* power up/down the sink */
528 if (dig_connector->dpcd[0] >= 0x11) {
529 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
530 DP_SET_POWER, power_state);
531 usleep_range(1000, 2000);
532 }
533}
534
535
536struct radeon_dp_link_train_info {
537 struct radeon_device *rdev;
538 struct drm_encoder *encoder;
539 struct drm_connector *connector;
540 int enc_id;
541 int dp_clock;
542 int dp_lane_count;
543 bool tp3_supported;
544 u8 dpcd[DP_RECEIVER_CAP_SIZE];
545 u8 train_set[4];
546 u8 link_status[DP_LINK_STATUS_SIZE];
547 u8 tries;
548 bool use_dpencoder;
549 struct drm_dp_aux *aux;
550};
551
552static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
553{
554 /* set the initial vs/emph on the source */
555 atombios_dig_transmitter_setup(dp_info->encoder,
556 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
557 0, dp_info->train_set[0]); /* sets all lanes at once */
558
559 /* set the vs/emph on the sink */
560 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
561 dp_info->train_set, dp_info->dp_lane_count);
562}
563
564static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
565{
566 int rtp = 0;
567
568 /* set training pattern on the source */
569 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
570 switch (tp) {
571 case DP_TRAINING_PATTERN_1:
572 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
573 break;
574 case DP_TRAINING_PATTERN_2:
575 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
576 break;
577 case DP_TRAINING_PATTERN_3:
578 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
579 break;
580 }
581 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
582 } else {
583 switch (tp) {
584 case DP_TRAINING_PATTERN_1:
585 rtp = 0;
586 break;
587 case DP_TRAINING_PATTERN_2:
588 rtp = 1;
589 break;
590 }
591 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
592 dp_info->dp_clock, dp_info->enc_id, rtp);
593 }
594
595 /* enable training pattern on the sink */
596 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
597}
598
599static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
600{
601 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
602 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
603 u8 tmp;
604
605 /* power up the sink */
606 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
607
608 /* possibly enable downspread on the sink */
609 if (dp_info->dpcd[3] & 0x1)
610 drm_dp_dpcd_writeb(dp_info->aux,
611 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
612 else
613 drm_dp_dpcd_writeb(dp_info->aux,
614 DP_DOWNSPREAD_CTRL, 0);
615
616 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
617 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
618
619 /* set the lane count on the sink */
620 tmp = dp_info->dp_lane_count;
621 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
622 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
623 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
624
625 /* set the link rate on the sink */
626 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
627 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
628
629 /* start training on the source */
630 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
631 atombios_dig_encoder_setup(dp_info->encoder,
632 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
633 else
634 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
635 dp_info->dp_clock, dp_info->enc_id, 0);
636
637 /* disable the training pattern on the sink */
638 drm_dp_dpcd_writeb(dp_info->aux,
639 DP_TRAINING_PATTERN_SET,
640 DP_TRAINING_PATTERN_DISABLE);
641
642 return 0;
643}
644
645static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
646{
647 udelay(400);
648
649 /* disable the training pattern on the sink */
650 drm_dp_dpcd_writeb(dp_info->aux,
651 DP_TRAINING_PATTERN_SET,
652 DP_TRAINING_PATTERN_DISABLE);
653
654 /* disable the training pattern on the source */
655 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
656 atombios_dig_encoder_setup(dp_info->encoder,
657 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
658 else
659 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
660 dp_info->dp_clock, dp_info->enc_id, 0);
661
662 return 0;
663}
664
665static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
666{
667 bool clock_recovery;
668 u8 voltage;
669 int i;
670
671 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
672 memset(dp_info->train_set, 0, 4);
673 radeon_dp_update_vs_emph(dp_info);
674
675 udelay(400);
676
677 /* clock recovery loop */
678 clock_recovery = false;
679 dp_info->tries = 0;
680 voltage = 0xff;
681 while (1) {
682 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
683
684 if (drm_dp_dpcd_read_link_status(dp_info->aux,
685 dp_info->link_status) <= 0) {
686 DRM_ERROR("displayport link status failed\n");
687 break;
688 }
689
690 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
691 clock_recovery = true;
692 break;
693 }
694
695 for (i = 0; i < dp_info->dp_lane_count; i++) {
696 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
697 break;
698 }
699 if (i == dp_info->dp_lane_count) {
700 DRM_ERROR("clock recovery reached max voltage\n");
701 break;
702 }
703
704 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
705 ++dp_info->tries;
706 if (dp_info->tries == 5) {
707 DRM_ERROR("clock recovery tried 5 times\n");
708 break;
709 }
710 } else
711 dp_info->tries = 0;
712
713 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
714
715 /* Compute new train_set as requested by sink */
716 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
717
718 radeon_dp_update_vs_emph(dp_info);
719 }
720 if (!clock_recovery) {
721 DRM_ERROR("clock recovery failed\n");
722 return -1;
723 } else {
724 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
725 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
726 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
727 DP_TRAIN_PRE_EMPHASIS_SHIFT);
728 return 0;
729 }
730}
731
732static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
733{
734 bool channel_eq;
735
736 if (dp_info->tp3_supported)
737 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
738 else
739 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
740
741 /* channel equalization loop */
742 dp_info->tries = 0;
743 channel_eq = false;
744 while (1) {
745 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
746
747 if (drm_dp_dpcd_read_link_status(dp_info->aux,
748 dp_info->link_status) <= 0) {
749 DRM_ERROR("displayport link status failed\n");
750 break;
751 }
752
753 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
754 channel_eq = true;
755 break;
756 }
757
758 /* Try 5 times */
759 if (dp_info->tries > 5) {
760 DRM_ERROR("channel eq failed: 5 tries\n");
761 break;
762 }
763
764 /* Compute new train_set as requested by sink */
765 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
766
767 radeon_dp_update_vs_emph(dp_info);
768 dp_info->tries++;
769 }
770
771 if (!channel_eq) {
772 DRM_ERROR("channel eq failed\n");
773 return -1;
774 } else {
775 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
776 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
777 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
778 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
779 return 0;
780 }
781}
782
783void radeon_dp_link_train(struct drm_encoder *encoder,
784 struct drm_connector *connector)
785{
786 struct drm_device *dev = encoder->dev;
787 struct radeon_device *rdev = dev->dev_private;
788 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
789 struct radeon_encoder_atom_dig *dig;
790 struct radeon_connector *radeon_connector;
791 struct radeon_connector_atom_dig *dig_connector;
792 struct radeon_dp_link_train_info dp_info;
793 int index;
794 u8 tmp, frev, crev;
795
796 if (!radeon_encoder->enc_priv)
797 return;
798 dig = radeon_encoder->enc_priv;
799
800 radeon_connector = to_radeon_connector(connector);
801 if (!radeon_connector->con_priv)
802 return;
803 dig_connector = radeon_connector->con_priv;
804
805 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
806 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
807 return;
808
809 /* DPEncoderService newer than 1.1 can't program properly the
810 * training pattern. When facing such version use the
811 * DIGXEncoderControl (X== 1 | 2)
812 */
813 dp_info.use_dpencoder = true;
814 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
815 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
816 if (crev > 1)
817 dp_info.use_dpencoder = false;
818 }
819
820 dp_info.enc_id = 0;
821 if (dig->dig_encoder)
822 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
823 else
824 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
825 if (dig->linkb)
826 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
827 else
828 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
829
830 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
831 == 1) {
832 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
833 dp_info.tp3_supported = true;
834 else
835 dp_info.tp3_supported = false;
836 } else {
837 dp_info.tp3_supported = false;
838 }
839
840 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
841 dp_info.rdev = rdev;
842 dp_info.encoder = encoder;
843 dp_info.connector = connector;
844 dp_info.dp_lane_count = dig_connector->dp_lane_count;
845 dp_info.dp_clock = dig_connector->dp_clock;
846 dp_info.aux = &radeon_connector->ddc_bus->aux;
847
848 if (radeon_dp_link_train_init(&dp_info))
849 goto done;
850 if (radeon_dp_link_train_cr(&dp_info))
851 goto done;
852 if (radeon_dp_link_train_ce(&dp_info))
853 goto done;
854done:
855 if (radeon_dp_link_train_finish(&dp_info))
856 return;
857}