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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Panel driver for the TPO TPG110 400CH LTPS TFT LCD Single Chip
4 * Digital Driver.
5 *
6 * This chip drives a TFT LCD, so it does not know what kind of
7 * display is actually connected to it, so the width and height of that
8 * display needs to be supplied from the machine configuration.
9 *
10 * Author:
11 * Linus Walleij <linus.walleij@linaro.org>
12 */
13#include <drm/drm_modes.h>
14#include <drm/drm_panel.h>
15#include <drm/drm_print.h>
16
17#include <linux/bitops.h>
18#include <linux/delay.h>
19#include <linux/gpio/consumer.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/platform_device.h>
25#include <linux/spi/spi.h>
26
27#define TPG110_TEST 0x00
28#define TPG110_CHIPID 0x01
29#define TPG110_CTRL1 0x02
30#define TPG110_RES_MASK GENMASK(2, 0)
31#define TPG110_RES_800X480 0x07
32#define TPG110_RES_640X480 0x06
33#define TPG110_RES_480X272 0x05
34#define TPG110_RES_480X640 0x04
35#define TPG110_RES_480X272_D 0x01 /* Dual scan: outputs 800x480 */
36#define TPG110_RES_400X240_D 0x00 /* Dual scan: outputs 800x480 */
37#define TPG110_CTRL2 0x03
38#define TPG110_CTRL2_PM BIT(0)
39#define TPG110_CTRL2_RES_PM_CTRL BIT(7)
40
41/**
42 * struct tpg110_panel_mode - lookup struct for the supported modes
43 */
44struct tpg110_panel_mode {
45 /**
46 * @name: the name of this panel
47 */
48 const char *name;
49 /**
50 * @magic: the magic value from the detection register
51 */
52 u32 magic;
53 /**
54 * @mode: the DRM display mode for this panel
55 */
56 struct drm_display_mode mode;
57 /**
58 * @bus_flags: the DRM bus flags for this panel e.g. inverted clock
59 */
60 u32 bus_flags;
61};
62
63/**
64 * struct tpg110 - state container for the TPG110 panel
65 */
66struct tpg110 {
67 /**
68 * @dev: the container device
69 */
70 struct device *dev;
71 /**
72 * @spi: the corresponding SPI device
73 */
74 struct spi_device *spi;
75 /**
76 * @panel: the DRM panel instance for this device
77 */
78 struct drm_panel panel;
79 /**
80 * @panel_type: the panel mode as detected
81 */
82 const struct tpg110_panel_mode *panel_mode;
83 /**
84 * @width: the width of this panel in mm
85 */
86 u32 width;
87 /**
88 * @height: the height of this panel in mm
89 */
90 u32 height;
91 /**
92 * @grestb: reset GPIO line
93 */
94 struct gpio_desc *grestb;
95};
96
97/*
98 * TPG110 modes, these are the simple modes, the dualscan modes that
99 * take 400x240 or 480x272 in and display as 800x480 are not listed.
100 */
101static const struct tpg110_panel_mode tpg110_modes[] = {
102 {
103 .name = "800x480 RGB",
104 .magic = TPG110_RES_800X480,
105 .mode = {
106 .clock = 33200,
107 .hdisplay = 800,
108 .hsync_start = 800 + 40,
109 .hsync_end = 800 + 40 + 1,
110 .htotal = 800 + 40 + 1 + 216,
111 .vdisplay = 480,
112 .vsync_start = 480 + 10,
113 .vsync_end = 480 + 10 + 1,
114 .vtotal = 480 + 10 + 1 + 35,
115 },
116 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
117 },
118 {
119 .name = "640x480 RGB",
120 .magic = TPG110_RES_640X480,
121 .mode = {
122 .clock = 25200,
123 .hdisplay = 640,
124 .hsync_start = 640 + 24,
125 .hsync_end = 640 + 24 + 1,
126 .htotal = 640 + 24 + 1 + 136,
127 .vdisplay = 480,
128 .vsync_start = 480 + 18,
129 .vsync_end = 480 + 18 + 1,
130 .vtotal = 480 + 18 + 1 + 27,
131 },
132 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
133 },
134 {
135 .name = "480x272 RGB",
136 .magic = TPG110_RES_480X272,
137 .mode = {
138 .clock = 9000,
139 .hdisplay = 480,
140 .hsync_start = 480 + 2,
141 .hsync_end = 480 + 2 + 1,
142 .htotal = 480 + 2 + 1 + 43,
143 .vdisplay = 272,
144 .vsync_start = 272 + 2,
145 .vsync_end = 272 + 2 + 1,
146 .vtotal = 272 + 2 + 1 + 12,
147 },
148 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
149 },
150 {
151 .name = "480x640 RGB",
152 .magic = TPG110_RES_480X640,
153 .mode = {
154 .clock = 20500,
155 .hdisplay = 480,
156 .hsync_start = 480 + 2,
157 .hsync_end = 480 + 2 + 1,
158 .htotal = 480 + 2 + 1 + 43,
159 .vdisplay = 640,
160 .vsync_start = 640 + 4,
161 .vsync_end = 640 + 4 + 1,
162 .vtotal = 640 + 4 + 1 + 8,
163 },
164 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
165 },
166 {
167 .name = "400x240 RGB",
168 .magic = TPG110_RES_400X240_D,
169 .mode = {
170 .clock = 8300,
171 .hdisplay = 400,
172 .hsync_start = 400 + 20,
173 .hsync_end = 400 + 20 + 1,
174 .htotal = 400 + 20 + 1 + 108,
175 .vdisplay = 240,
176 .vsync_start = 240 + 2,
177 .vsync_end = 240 + 2 + 1,
178 .vtotal = 240 + 2 + 1 + 20,
179 },
180 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
181 },
182};
183
184static inline struct tpg110 *
185to_tpg110(struct drm_panel *panel)
186{
187 return container_of(panel, struct tpg110, panel);
188}
189
190static u8 tpg110_readwrite_reg(struct tpg110 *tpg, bool write,
191 u8 address, u8 outval)
192{
193 struct spi_message m;
194 struct spi_transfer t[2];
195 u8 buf[2];
196 int ret;
197
198 spi_message_init(&m);
199 memset(t, 0, sizeof(t));
200
201 if (write) {
202 /*
203 * Clear address bit 0, 1 when writing, just to be sure
204 * The actual bit indicating a write here is bit 1, bit
205 * 0 is just surplus to pad it up to 8 bits.
206 */
207 buf[0] = address << 2;
208 buf[0] &= ~0x03;
209 buf[1] = outval;
210
211 t[0].bits_per_word = 8;
212 t[0].tx_buf = &buf[0];
213 t[0].len = 1;
214
215 t[1].tx_buf = &buf[1];
216 t[1].len = 1;
217 t[1].bits_per_word = 8;
218 } else {
219 /* Set address bit 0 to 1 to read */
220 buf[0] = address << 1;
221 buf[0] |= 0x01;
222
223 /*
224 * The last bit/clock is Hi-Z turnaround cycle, so we need
225 * to send only 7 bits here. The 8th bit is the high impedance
226 * turn-around cycle.
227 */
228 t[0].bits_per_word = 7;
229 t[0].tx_buf = &buf[0];
230 t[0].len = 1;
231
232 t[1].rx_buf = &buf[1];
233 t[1].len = 1;
234 t[1].bits_per_word = 8;
235 }
236
237 spi_message_add_tail(&t[0], &m);
238 spi_message_add_tail(&t[1], &m);
239 ret = spi_sync(tpg->spi, &m);
240 if (ret) {
241 DRM_DEV_ERROR(tpg->dev, "SPI message error %d\n", ret);
242 return ret;
243 }
244 if (write)
245 return 0;
246 /* Read */
247 return buf[1];
248}
249
250static u8 tpg110_read_reg(struct tpg110 *tpg, u8 address)
251{
252 return tpg110_readwrite_reg(tpg, false, address, 0);
253}
254
255static void tpg110_write_reg(struct tpg110 *tpg, u8 address, u8 outval)
256{
257 tpg110_readwrite_reg(tpg, true, address, outval);
258}
259
260static int tpg110_startup(struct tpg110 *tpg)
261{
262 u8 val;
263 int i;
264
265 /* De-assert the reset signal */
266 gpiod_set_value_cansleep(tpg->grestb, 0);
267 usleep_range(1000, 2000);
268 DRM_DEV_DEBUG(tpg->dev, "de-asserted GRESTB\n");
269
270 /* Test display communication */
271 tpg110_write_reg(tpg, TPG110_TEST, 0x55);
272 val = tpg110_read_reg(tpg, TPG110_TEST);
273 if (val != 0x55) {
274 DRM_DEV_ERROR(tpg->dev, "failed communication test\n");
275 return -ENODEV;
276 }
277
278 val = tpg110_read_reg(tpg, TPG110_CHIPID);
279 DRM_DEV_INFO(tpg->dev, "TPG110 chip ID: %d version: %d\n",
280 val >> 4, val & 0x0f);
281
282 /* Show display resolution */
283 val = tpg110_read_reg(tpg, TPG110_CTRL1);
284 val &= TPG110_RES_MASK;
285 switch (val) {
286 case TPG110_RES_400X240_D:
287 DRM_DEV_INFO(tpg->dev,
288 "IN 400x240 RGB -> OUT 800x480 RGB (dual scan)\n");
289 break;
290 case TPG110_RES_480X272_D:
291 DRM_DEV_INFO(tpg->dev,
292 "IN 480x272 RGB -> OUT 800x480 RGB (dual scan)\n");
293 break;
294 case TPG110_RES_480X640:
295 DRM_DEV_INFO(tpg->dev, "480x640 RGB\n");
296 break;
297 case TPG110_RES_480X272:
298 DRM_DEV_INFO(tpg->dev, "480x272 RGB\n");
299 break;
300 case TPG110_RES_640X480:
301 DRM_DEV_INFO(tpg->dev, "640x480 RGB\n");
302 break;
303 case TPG110_RES_800X480:
304 DRM_DEV_INFO(tpg->dev, "800x480 RGB\n");
305 break;
306 default:
307 DRM_DEV_ERROR(tpg->dev, "ILLEGAL RESOLUTION 0x%02x\n", val);
308 break;
309 }
310
311 /* From the producer side, this is the same resolution */
312 if (val == TPG110_RES_480X272_D)
313 val = TPG110_RES_480X272;
314
315 for (i = 0; i < ARRAY_SIZE(tpg110_modes); i++) {
316 const struct tpg110_panel_mode *pm;
317
318 pm = &tpg110_modes[i];
319 if (pm->magic == val) {
320 tpg->panel_mode = pm;
321 break;
322 }
323 }
324 if (i == ARRAY_SIZE(tpg110_modes)) {
325 DRM_DEV_ERROR(tpg->dev, "unsupported mode (%02x) detected\n",
326 val);
327 return -ENODEV;
328 }
329
330 val = tpg110_read_reg(tpg, TPG110_CTRL2);
331 DRM_DEV_INFO(tpg->dev, "resolution and standby is controlled by %s\n",
332 (val & TPG110_CTRL2_RES_PM_CTRL) ? "software" : "hardware");
333 /* Take control over resolution and standby */
334 val |= TPG110_CTRL2_RES_PM_CTRL;
335 tpg110_write_reg(tpg, TPG110_CTRL2, val);
336
337 return 0;
338}
339
340static int tpg110_disable(struct drm_panel *panel)
341{
342 struct tpg110 *tpg = to_tpg110(panel);
343 u8 val;
344
345 /* Put chip into standby */
346 val = tpg110_read_reg(tpg, TPG110_CTRL2_PM);
347 val &= ~TPG110_CTRL2_PM;
348 tpg110_write_reg(tpg, TPG110_CTRL2_PM, val);
349
350 return 0;
351}
352
353static int tpg110_enable(struct drm_panel *panel)
354{
355 struct tpg110 *tpg = to_tpg110(panel);
356 u8 val;
357
358 /* Take chip out of standby */
359 val = tpg110_read_reg(tpg, TPG110_CTRL2_PM);
360 val |= TPG110_CTRL2_PM;
361 tpg110_write_reg(tpg, TPG110_CTRL2_PM, val);
362
363 return 0;
364}
365
366/**
367 * tpg110_get_modes() - return the appropriate mode
368 * @panel: the panel to get the mode for
369 *
370 * This currently does not present a forest of modes, instead it
371 * presents the mode that is configured for the system under use,
372 * and which is detected by reading the registers of the display.
373 */
374static int tpg110_get_modes(struct drm_panel *panel,
375 struct drm_connector *connector)
376{
377 struct tpg110 *tpg = to_tpg110(panel);
378 struct drm_display_mode *mode;
379
380 connector->display_info.width_mm = tpg->width;
381 connector->display_info.height_mm = tpg->height;
382 connector->display_info.bus_flags = tpg->panel_mode->bus_flags;
383
384 mode = drm_mode_duplicate(connector->dev, &tpg->panel_mode->mode);
385 drm_mode_set_name(mode);
386 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
387
388 mode->width_mm = tpg->width;
389 mode->height_mm = tpg->height;
390
391 drm_mode_probed_add(connector, mode);
392
393 return 1;
394}
395
396static const struct drm_panel_funcs tpg110_drm_funcs = {
397 .disable = tpg110_disable,
398 .enable = tpg110_enable,
399 .get_modes = tpg110_get_modes,
400};
401
402static int tpg110_probe(struct spi_device *spi)
403{
404 struct device *dev = &spi->dev;
405 struct device_node *np = dev->of_node;
406 struct tpg110 *tpg;
407 int ret;
408
409 tpg = devm_kzalloc(dev, sizeof(*tpg), GFP_KERNEL);
410 if (!tpg)
411 return -ENOMEM;
412 tpg->dev = dev;
413
414 /* We get the physical display dimensions from the DT */
415 ret = of_property_read_u32(np, "width-mm", &tpg->width);
416 if (ret)
417 DRM_DEV_ERROR(dev, "no panel width specified\n");
418 ret = of_property_read_u32(np, "height-mm", &tpg->height);
419 if (ret)
420 DRM_DEV_ERROR(dev, "no panel height specified\n");
421
422 /* This asserts the GRESTB signal, putting the display into reset */
423 tpg->grestb = devm_gpiod_get(dev, "grestb", GPIOD_OUT_HIGH);
424 if (IS_ERR(tpg->grestb)) {
425 DRM_DEV_ERROR(dev, "no GRESTB GPIO\n");
426 return -ENODEV;
427 }
428
429 spi->bits_per_word = 8;
430 spi->mode |= SPI_3WIRE_HIZ;
431 ret = spi_setup(spi);
432 if (ret < 0) {
433 DRM_DEV_ERROR(dev, "spi setup failed.\n");
434 return ret;
435 }
436 tpg->spi = spi;
437
438 ret = tpg110_startup(tpg);
439 if (ret)
440 return ret;
441
442 drm_panel_init(&tpg->panel, dev, &tpg110_drm_funcs,
443 DRM_MODE_CONNECTOR_DPI);
444
445 ret = drm_panel_of_backlight(&tpg->panel);
446 if (ret)
447 return ret;
448
449 spi_set_drvdata(spi, tpg);
450
451 return drm_panel_add(&tpg->panel);
452}
453
454static int tpg110_remove(struct spi_device *spi)
455{
456 struct tpg110 *tpg = spi_get_drvdata(spi);
457
458 drm_panel_remove(&tpg->panel);
459 return 0;
460}
461
462static const struct of_device_id tpg110_match[] = {
463 { .compatible = "tpo,tpg110", },
464 {},
465};
466MODULE_DEVICE_TABLE(of, tpg110_match);
467
468static struct spi_driver tpg110_driver = {
469 .probe = tpg110_probe,
470 .remove = tpg110_remove,
471 .driver = {
472 .name = "tpo-tpg110-panel",
473 .of_match_table = tpg110_match,
474 },
475};
476module_spi_driver(tpg110_driver);
477
478MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
479MODULE_DESCRIPTION("TPO TPG110 panel driver");
480MODULE_LICENSE("GPL v2");