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1#ifndef DSI_XML
2#define DSI_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
21- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
22
23Copyright (C) 2013-2015 by the following authors:
24- Rob Clark <robdclark@gmail.com> (robclark)
25- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27Permission is hereby granted, free of charge, to any person obtaining
28a copy of this software and associated documentation files (the
29"Software"), to deal in the Software without restriction, including
30without limitation the rights to use, copy, modify, merge, publish,
31distribute, sublicense, and/or sell copies of the Software, and to
32permit persons to whom the Software is furnished to do so, subject to
33the following conditions:
34
35The above copyright notice and this permission notice (including the
36next paragraph) shall be included in all copies or substantial
37portions of the Software.
38
39THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46*/
47
48
49enum dsi_traffic_mode {
50 NON_BURST_SYNCH_PULSE = 0,
51 NON_BURST_SYNCH_EVENT = 1,
52 BURST_MODE = 2,
53};
54
55enum dsi_vid_dst_format {
56 VID_DST_FORMAT_RGB565 = 0,
57 VID_DST_FORMAT_RGB666 = 1,
58 VID_DST_FORMAT_RGB666_LOOSE = 2,
59 VID_DST_FORMAT_RGB888 = 3,
60};
61
62enum dsi_rgb_swap {
63 SWAP_RGB = 0,
64 SWAP_RBG = 1,
65 SWAP_BGR = 2,
66 SWAP_BRG = 3,
67 SWAP_GRB = 4,
68 SWAP_GBR = 5,
69};
70
71enum dsi_cmd_trigger {
72 TRIGGER_NONE = 0,
73 TRIGGER_SEOF = 1,
74 TRIGGER_TE = 2,
75 TRIGGER_SW = 4,
76 TRIGGER_SW_SEOF = 5,
77 TRIGGER_SW_TE = 6,
78};
79
80enum dsi_cmd_dst_format {
81 CMD_DST_FORMAT_RGB111 = 0,
82 CMD_DST_FORMAT_RGB332 = 3,
83 CMD_DST_FORMAT_RGB444 = 4,
84 CMD_DST_FORMAT_RGB565 = 6,
85 CMD_DST_FORMAT_RGB666 = 7,
86 CMD_DST_FORMAT_RGB888 = 8,
87};
88
89enum dsi_lane_swap {
90 LANE_SWAP_0123 = 0,
91 LANE_SWAP_3012 = 1,
92 LANE_SWAP_2301 = 2,
93 LANE_SWAP_1230 = 3,
94 LANE_SWAP_0321 = 4,
95 LANE_SWAP_1032 = 5,
96 LANE_SWAP_2103 = 6,
97 LANE_SWAP_3210 = 7,
98};
99
100#define DSI_IRQ_CMD_DMA_DONE 0x00000001
101#define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102#define DSI_IRQ_CMD_MDP_DONE 0x00000100
103#define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
104#define DSI_IRQ_VIDEO_DONE 0x00010000
105#define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
106#define DSI_IRQ_BTA_DONE 0x00100000
107#define DSI_IRQ_MASK_BTA_DONE 0x00200000
108#define DSI_IRQ_ERROR 0x01000000
109#define DSI_IRQ_MASK_ERROR 0x02000000
110#define REG_DSI_6G_HW_VERSION 0x00000000
111#define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
112#define DSI_6G_HW_VERSION_MAJOR__SHIFT 28
113static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
114{
115 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK;
116}
117#define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
118#define DSI_6G_HW_VERSION_MINOR__SHIFT 16
119static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
120{
121 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK;
122}
123#define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
124#define DSI_6G_HW_VERSION_STEP__SHIFT 0
125static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
126{
127 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK;
128}
129
130#define REG_DSI_CTRL 0x00000000
131#define DSI_CTRL_ENABLE 0x00000001
132#define DSI_CTRL_VID_MODE_EN 0x00000002
133#define DSI_CTRL_CMD_MODE_EN 0x00000004
134#define DSI_CTRL_LANE0 0x00000010
135#define DSI_CTRL_LANE1 0x00000020
136#define DSI_CTRL_LANE2 0x00000040
137#define DSI_CTRL_LANE3 0x00000080
138#define DSI_CTRL_CLK_EN 0x00000100
139#define DSI_CTRL_ECC_CHECK 0x00100000
140#define DSI_CTRL_CRC_CHECK 0x01000000
141
142#define REG_DSI_STATUS0 0x00000004
143#define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
144#define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
145#define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
146#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
147#define DSI_STATUS0_DSI_BUSY 0x00000010
148#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
149
150#define REG_DSI_FIFO_STATUS 0x00000008
151#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
152
153#define REG_DSI_VID_CFG0 0x0000000c
154#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
155#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
156static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
157{
158 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
159}
160#define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
161#define DSI_VID_CFG0_DST_FORMAT__SHIFT 4
162static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
163{
164 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
165}
166#define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
167#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8
168static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
169{
170 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
171}
172#define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
173#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
174#define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
175#define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
176#define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
177#define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
178
179#define REG_DSI_VID_CFG1 0x0000001c
180#define DSI_VID_CFG1_R_SEL 0x00000001
181#define DSI_VID_CFG1_G_SEL 0x00000010
182#define DSI_VID_CFG1_B_SEL 0x00000100
183#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
184#define DSI_VID_CFG1_RGB_SWAP__SHIFT 12
185static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
186{
187 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
188}
189
190#define REG_DSI_ACTIVE_H 0x00000020
191#define DSI_ACTIVE_H_START__MASK 0x00000fff
192#define DSI_ACTIVE_H_START__SHIFT 0
193static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
194{
195 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
196}
197#define DSI_ACTIVE_H_END__MASK 0x0fff0000
198#define DSI_ACTIVE_H_END__SHIFT 16
199static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
200{
201 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
202}
203
204#define REG_DSI_ACTIVE_V 0x00000024
205#define DSI_ACTIVE_V_START__MASK 0x00000fff
206#define DSI_ACTIVE_V_START__SHIFT 0
207static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
208{
209 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
210}
211#define DSI_ACTIVE_V_END__MASK 0x0fff0000
212#define DSI_ACTIVE_V_END__SHIFT 16
213static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
214{
215 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
216}
217
218#define REG_DSI_TOTAL 0x00000028
219#define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
220#define DSI_TOTAL_H_TOTAL__SHIFT 0
221static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
222{
223 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
224}
225#define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
226#define DSI_TOTAL_V_TOTAL__SHIFT 16
227static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
228{
229 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
230}
231
232#define REG_DSI_ACTIVE_HSYNC 0x0000002c
233#define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
234#define DSI_ACTIVE_HSYNC_START__SHIFT 0
235static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
236{
237 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
238}
239#define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
240#define DSI_ACTIVE_HSYNC_END__SHIFT 16
241static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
242{
243 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
244}
245
246#define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
247#define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
248#define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
249static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
250{
251 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK;
252}
253#define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
254#define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16
255static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
256{
257 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK;
258}
259
260#define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
261#define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
262#define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
263static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
264{
265 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK;
266}
267#define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
268#define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16
269static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
270{
271 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK;
272}
273
274#define REG_DSI_CMD_DMA_CTRL 0x00000038
275#define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
276#define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
277#define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
278
279#define REG_DSI_CMD_CFG0 0x0000003c
280#define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
281#define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
282static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
283{
284 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK;
285}
286#define DSI_CMD_CFG0_R_SEL 0x00000010
287#define DSI_CMD_CFG0_G_SEL 0x00000100
288#define DSI_CMD_CFG0_B_SEL 0x00001000
289#define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
290#define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20
291static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
292{
293 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK;
294}
295#define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
296#define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16
297static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
298{
299 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK;
300}
301
302#define REG_DSI_CMD_CFG1 0x00000040
303#define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
304#define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
305static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
306{
307 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK;
308}
309#define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
310#define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8
311static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
312{
313 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK;
314}
315#define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
316
317#define REG_DSI_DMA_BASE 0x00000044
318
319#define REG_DSI_DMA_LEN 0x00000048
320
321#define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054
322#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f
323#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0
324static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)
325{
326 return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK;
327}
328#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
329#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8
330static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)
331{
332 return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK;
333}
334#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000
335#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16
336static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)
337{
338 return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK;
339}
340
341#define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058
342#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff
343#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0
344static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)
345{
346 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK;
347}
348#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000
349#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16
350static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)
351{
352 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK;
353}
354
355#define REG_DSI_ACK_ERR_STATUS 0x00000064
356
357static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
358
359static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
360
361#define REG_DSI_TRIG_CTRL 0x00000080
362#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
363#define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
364static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
365{
366 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
367}
368#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
369#define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4
370static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
371{
372 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
373}
374#define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
375#define DSI_TRIG_CTRL_STREAM__SHIFT 8
376static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
377{
378 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK;
379}
380#define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
381#define DSI_TRIG_CTRL_TE 0x80000000
382
383#define REG_DSI_TRIG_DMA 0x0000008c
384
385#define REG_DSI_DLN0_PHY_ERR 0x000000b0
386#define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
387#define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
388#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
389#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
390#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
391
392#define REG_DSI_TIMEOUT_STATUS 0x000000bc
393
394#define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
395#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
396#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
397static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
398{
399 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
400}
401#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
402#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8
403static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
404{
405 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
406}
407
408#define REG_DSI_EOT_PACKET_CTRL 0x000000c8
409#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
410#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
411
412#define REG_DSI_LANE_CTRL 0x000000a8
413#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
414
415#define REG_DSI_LANE_SWAP_CTRL 0x000000ac
416#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
417#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
418static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
419{
420 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK;
421}
422
423#define REG_DSI_ERR_INT_MASK0 0x00000108
424
425#define REG_DSI_INTR_CTRL 0x0000010c
426
427#define REG_DSI_RESET 0x00000114
428
429#define REG_DSI_CLK_CTRL 0x00000118
430#define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
431#define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
432#define DSI_CLK_CTRL_PCLK_ON 0x00000004
433#define DSI_CLK_CTRL_DSICLK_ON 0x00000008
434#define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
435#define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
436#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
437
438#define REG_DSI_CLK_STATUS 0x0000011c
439#define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
440
441#define REG_DSI_PHY_RESET 0x00000128
442#define DSI_PHY_RESET_RESET 0x00000001
443
444#define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
445#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
446
447#define REG_DSI_RDBK_DATA_CTRL 0x000001d0
448#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
449#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
450static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
451{
452 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK;
453}
454#define DSI_RDBK_DATA_CTRL_CLR 0x00000001
455
456#define REG_DSI_VERSION 0x000001f0
457#define DSI_VERSION_MAJOR__MASK 0xff000000
458#define DSI_VERSION_MAJOR__SHIFT 24
459static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
460{
461 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
462}
463
464#define REG_DSI_PHY_PLL_CTRL_0 0x00000200
465#define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001
466
467#define REG_DSI_PHY_PLL_CTRL_1 0x00000204
468
469#define REG_DSI_PHY_PLL_CTRL_2 0x00000208
470
471#define REG_DSI_PHY_PLL_CTRL_3 0x0000020c
472
473#define REG_DSI_PHY_PLL_CTRL_4 0x00000210
474
475#define REG_DSI_PHY_PLL_CTRL_5 0x00000214
476
477#define REG_DSI_PHY_PLL_CTRL_6 0x00000218
478
479#define REG_DSI_PHY_PLL_CTRL_7 0x0000021c
480
481#define REG_DSI_PHY_PLL_CTRL_8 0x00000220
482
483#define REG_DSI_PHY_PLL_CTRL_9 0x00000224
484
485#define REG_DSI_PHY_PLL_CTRL_10 0x00000228
486
487#define REG_DSI_PHY_PLL_CTRL_11 0x0000022c
488
489#define REG_DSI_PHY_PLL_CTRL_12 0x00000230
490
491#define REG_DSI_PHY_PLL_CTRL_13 0x00000234
492
493#define REG_DSI_PHY_PLL_CTRL_14 0x00000238
494
495#define REG_DSI_PHY_PLL_CTRL_15 0x0000023c
496
497#define REG_DSI_PHY_PLL_CTRL_16 0x00000240
498
499#define REG_DSI_PHY_PLL_CTRL_17 0x00000244
500
501#define REG_DSI_PHY_PLL_CTRL_18 0x00000248
502
503#define REG_DSI_PHY_PLL_CTRL_19 0x0000024c
504
505#define REG_DSI_PHY_PLL_CTRL_20 0x00000250
506
507#define REG_DSI_PHY_PLL_STATUS 0x00000280
508#define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001
509
510#define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258
511
512#define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c
513
514#define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260
515
516#define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264
517
518#define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268
519
520#define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c
521
522#define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270
523
524#define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274
525
526#define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278
527
528#define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c
529
530#define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280
531
532#define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284
533
534#define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288
535
536#define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c
537
538#define REG_DSI_8x60_PHY_CTRL_0 0x00000290
539
540#define REG_DSI_8x60_PHY_CTRL_1 0x00000294
541
542#define REG_DSI_8x60_PHY_CTRL_2 0x00000298
543
544#define REG_DSI_8x60_PHY_CTRL_3 0x0000029c
545
546#define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0
547
548#define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4
549
550#define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8
551
552#define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac
553
554#define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc
555
556#define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0
557
558#define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4
559
560#define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8
561
562#define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc
563
564#define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0
565
566#define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4
567
568#define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
569#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
570
571static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
572
573static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
574
575static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
576
577static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
578
579static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
580
581static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
582
583static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
584
585#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
586
587#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
588
589#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
590
591#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
592
593#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
594
595#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
596
597#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
598#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
599#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
600static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
601{
602 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
603}
604
605#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
606#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
607#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
608static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
609{
610 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
611}
612
613#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
614#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
615#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
616static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
617{
618 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
619}
620
621#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
622
623#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
624#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
625#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
626static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
627{
628 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
629}
630
631#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
632#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
633#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
634static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
635{
636 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
637}
638
639#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
640#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
641#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
642static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
643{
644 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
645}
646
647#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
648#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
649#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
650static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
651{
652 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
653}
654
655#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
656#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
657#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
658static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
659{
660 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
661}
662
663#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
664#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
665#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
666static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
667{
668 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
669}
670#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
671#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
672static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
673{
674 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
675}
676
677#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
678#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
679#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
680static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
681{
682 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
683}
684
685#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
686#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
687#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
688static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
689{
690 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
691}
692
693#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
694
695#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
696
697#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
698
699#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
700
701#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
702
703#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
704
705#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
706
707#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
708
709#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
710
711#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
712
713#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
714
715#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
716
717#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
718
719#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
720
721#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
722
723#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
724
725#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
726
727#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
728
729#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
730
731#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
732
733#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
734
735#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
736
737#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
738
739#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
740
741#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
742
743#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
744
745#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
746
747#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
748
749#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
750
751#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
752#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
753
754#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
755#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
756
757#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
758
759#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
760
761#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
762
763#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
764
765#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
766
767#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
768
769#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
770
771#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
772
773#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
774
775#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
776
777#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
778
779#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
780
781#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
782
783#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
784
785#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
786
787#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
788
789#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
790
791#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
792
793#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
794
795#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
796
797#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
798#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
799
800static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
801
802static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
803
804static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
805
806static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
807
808static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
809
810static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
811
812static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
813
814static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
815
816static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
817
818static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
819
820#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
821
822#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
823
824#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
825
826#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
827
828#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
829
830#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
831
832#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
833
834#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
835
836#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
837
838#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
839#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
840#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
841static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
842{
843 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
844}
845
846#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
847#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
848#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
849static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
850{
851 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
852}
853
854#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
855#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
856#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
857static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
858{
859 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
860}
861
862#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
863#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
864
865#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
866#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
867#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
868static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
869{
870 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
871}
872
873#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
874#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
875#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
876static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
877{
878 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
879}
880
881#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
882#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
883#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
884static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
885{
886 return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
887}
888
889#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
890#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
891#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
892static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
893{
894 return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
895}
896
897#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
898#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
899#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
900static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
901{
902 return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
903}
904
905#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
906#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
907#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
908static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
909{
910 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
911}
912#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
913#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
914static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
915{
916 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
917}
918
919#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
920#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
921#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
922static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
923{
924 return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
925}
926
927#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
928#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
929#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
930static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
931{
932 return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
933}
934
935#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
936
937#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
938
939#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
940
941#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
942
943#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
944
945#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
946
947#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
948
949#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
950
951#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
952
953#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
954
955#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
956
957#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
958
959#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
960
961#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
962#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
963
964#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
965
966#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
967
968#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
969
970#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
971
972#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
973
974#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
975
976#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
977
978#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
979
980#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
981#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
982
983#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
984
985#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
986
987#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
988
989#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
990#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
991
992#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
993
994#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
995
996#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
997
998#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
999#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
1000#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
1001#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
1002#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
1003
1004#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
1005
1006#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
1007
1008#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
1009
1010#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
1011
1012#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
1013
1014#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
1015#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
1016#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
1017static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
1018{
1019 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
1020}
1021#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
1022
1023#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
1024#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
1025#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
1026static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
1027{
1028 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
1029}
1030#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
1031#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
1032static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
1033{
1034 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
1035}
1036
1037#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
1038#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
1039#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
1040static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
1041{
1042 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
1043}
1044
1045#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
1046#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
1047#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
1048static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
1049{
1050 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
1051}
1052
1053#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
1054
1055#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
1056
1057#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
1058
1059#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
1060
1061#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
1062
1063#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
1064
1065#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
1066
1067#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
1068
1069#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
1070#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
1071
1072#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
1073
1074#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
1075
1076#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
1077
1078#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
1079
1080#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
1081
1082#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
1083
1084#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
1085
1086#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
1087
1088#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
1089
1090#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
1091
1092#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
1093
1094#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
1095
1096#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
1097
1098#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
1099
1100#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
1101
1102#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
1103
1104#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
1105
1106#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
1107
1108#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
1109
1110#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
1111
1112#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
1113
1114#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
1115#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
1116
1117#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
1118
1119#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
1120
1121#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
1122
1123#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
1124
1125#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
1126
1127static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1128
1129static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1130
1131static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
1132
1133static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
1134
1135static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
1136
1137static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
1138
1139static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
1140
1141static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
1142
1143static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
1144
1145static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
1146
1147#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
1148
1149#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
1150
1151#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
1152
1153#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
1154
1155#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
1156
1157#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
1158
1159#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
1160
1161#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
1162
1163#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
1164
1165#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
1166#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1167#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1168static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1169{
1170 return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1171}
1172
1173#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
1174#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1175#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1176static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1177{
1178 return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1179}
1180
1181#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
1182#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1183#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1184static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1185{
1186 return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1187}
1188
1189#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
1190#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1191
1192#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
1193#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1194#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1195static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1196{
1197 return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1198}
1199
1200#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
1201#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1202#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1203static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1204{
1205 return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1206}
1207
1208#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
1209#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1210#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1211static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1212{
1213 return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1214}
1215
1216#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
1217#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1218#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1219static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1220{
1221 return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1222}
1223
1224#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
1225#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1226#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1227static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1228{
1229 return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1230}
1231
1232#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
1233#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1234#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1235static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1236{
1237 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1238}
1239#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1240#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1241static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1242{
1243 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1244}
1245
1246#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
1247#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1248#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1249static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1250{
1251 return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1252}
1253
1254#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
1255#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1256#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1257static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1258{
1259 return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1260}
1261
1262#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
1263
1264#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
1265
1266#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
1267
1268#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
1269
1270#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
1271
1272#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
1273
1274#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
1275
1276#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
1277
1278#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
1279
1280#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
1281
1282#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
1283
1284#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
1285
1286#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
1287
1288#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
1289#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1290
1291#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
1292
1293#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
1294
1295#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
1296
1297#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
1298
1299#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
1300
1301#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
1302
1303#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
1304
1305#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1306
1307
1308#endif /* DSI_XML */
1#ifndef DSI_XML
2#define DSI_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
22
23Copyright (C) 2013-2020 by the following authors:
24- Rob Clark <robdclark@gmail.com> (robclark)
25- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27Permission is hereby granted, free of charge, to any person obtaining
28a copy of this software and associated documentation files (the
29"Software"), to deal in the Software without restriction, including
30without limitation the rights to use, copy, modify, merge, publish,
31distribute, sublicense, and/or sell copies of the Software, and to
32permit persons to whom the Software is furnished to do so, subject to
33the following conditions:
34
35The above copyright notice and this permission notice (including the
36next paragraph) shall be included in all copies or substantial
37portions of the Software.
38
39THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46*/
47
48
49enum dsi_traffic_mode {
50 NON_BURST_SYNCH_PULSE = 0,
51 NON_BURST_SYNCH_EVENT = 1,
52 BURST_MODE = 2,
53};
54
55enum dsi_vid_dst_format {
56 VID_DST_FORMAT_RGB565 = 0,
57 VID_DST_FORMAT_RGB666 = 1,
58 VID_DST_FORMAT_RGB666_LOOSE = 2,
59 VID_DST_FORMAT_RGB888 = 3,
60};
61
62enum dsi_rgb_swap {
63 SWAP_RGB = 0,
64 SWAP_RBG = 1,
65 SWAP_BGR = 2,
66 SWAP_BRG = 3,
67 SWAP_GRB = 4,
68 SWAP_GBR = 5,
69};
70
71enum dsi_cmd_trigger {
72 TRIGGER_NONE = 0,
73 TRIGGER_SEOF = 1,
74 TRIGGER_TE = 2,
75 TRIGGER_SW = 4,
76 TRIGGER_SW_SEOF = 5,
77 TRIGGER_SW_TE = 6,
78};
79
80enum dsi_cmd_dst_format {
81 CMD_DST_FORMAT_RGB111 = 0,
82 CMD_DST_FORMAT_RGB332 = 3,
83 CMD_DST_FORMAT_RGB444 = 4,
84 CMD_DST_FORMAT_RGB565 = 6,
85 CMD_DST_FORMAT_RGB666 = 7,
86 CMD_DST_FORMAT_RGB888 = 8,
87};
88
89enum dsi_lane_swap {
90 LANE_SWAP_0123 = 0,
91 LANE_SWAP_3012 = 1,
92 LANE_SWAP_2301 = 2,
93 LANE_SWAP_1230 = 3,
94 LANE_SWAP_0321 = 4,
95 LANE_SWAP_1032 = 5,
96 LANE_SWAP_2103 = 6,
97 LANE_SWAP_3210 = 7,
98};
99
100#define DSI_IRQ_CMD_DMA_DONE 0x00000001
101#define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102#define DSI_IRQ_CMD_MDP_DONE 0x00000100
103#define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
104#define DSI_IRQ_VIDEO_DONE 0x00010000
105#define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
106#define DSI_IRQ_BTA_DONE 0x00100000
107#define DSI_IRQ_MASK_BTA_DONE 0x00200000
108#define DSI_IRQ_ERROR 0x01000000
109#define DSI_IRQ_MASK_ERROR 0x02000000
110#define REG_DSI_6G_HW_VERSION 0x00000000
111#define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
112#define DSI_6G_HW_VERSION_MAJOR__SHIFT 28
113static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
114{
115 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK;
116}
117#define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
118#define DSI_6G_HW_VERSION_MINOR__SHIFT 16
119static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
120{
121 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK;
122}
123#define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
124#define DSI_6G_HW_VERSION_STEP__SHIFT 0
125static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
126{
127 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK;
128}
129
130#define REG_DSI_CTRL 0x00000000
131#define DSI_CTRL_ENABLE 0x00000001
132#define DSI_CTRL_VID_MODE_EN 0x00000002
133#define DSI_CTRL_CMD_MODE_EN 0x00000004
134#define DSI_CTRL_LANE0 0x00000010
135#define DSI_CTRL_LANE1 0x00000020
136#define DSI_CTRL_LANE2 0x00000040
137#define DSI_CTRL_LANE3 0x00000080
138#define DSI_CTRL_CLK_EN 0x00000100
139#define DSI_CTRL_ECC_CHECK 0x00100000
140#define DSI_CTRL_CRC_CHECK 0x01000000
141
142#define REG_DSI_STATUS0 0x00000004
143#define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
144#define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
145#define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
146#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
147#define DSI_STATUS0_DSI_BUSY 0x00000010
148#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
149
150#define REG_DSI_FIFO_STATUS 0x00000008
151#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
152#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
153#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
154#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
155#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
156#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
157#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
158#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
159#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
160#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
161#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
162#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
163#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
164#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
165#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
166#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
167#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
168#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
169#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
170#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
171#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
172#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
173#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
174#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
175#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
176
177#define REG_DSI_VID_CFG0 0x0000000c
178#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
179#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
180static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
181{
182 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
183}
184#define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
185#define DSI_VID_CFG0_DST_FORMAT__SHIFT 4
186static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
187{
188 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
189}
190#define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
191#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8
192static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
193{
194 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
195}
196#define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
197#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
198#define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
199#define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
200#define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
201#define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
202
203#define REG_DSI_VID_CFG1 0x0000001c
204#define DSI_VID_CFG1_R_SEL 0x00000001
205#define DSI_VID_CFG1_G_SEL 0x00000010
206#define DSI_VID_CFG1_B_SEL 0x00000100
207#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
208#define DSI_VID_CFG1_RGB_SWAP__SHIFT 12
209static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
210{
211 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
212}
213
214#define REG_DSI_ACTIVE_H 0x00000020
215#define DSI_ACTIVE_H_START__MASK 0x00000fff
216#define DSI_ACTIVE_H_START__SHIFT 0
217static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
218{
219 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
220}
221#define DSI_ACTIVE_H_END__MASK 0x0fff0000
222#define DSI_ACTIVE_H_END__SHIFT 16
223static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
224{
225 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
226}
227
228#define REG_DSI_ACTIVE_V 0x00000024
229#define DSI_ACTIVE_V_START__MASK 0x00000fff
230#define DSI_ACTIVE_V_START__SHIFT 0
231static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
232{
233 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
234}
235#define DSI_ACTIVE_V_END__MASK 0x0fff0000
236#define DSI_ACTIVE_V_END__SHIFT 16
237static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
238{
239 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
240}
241
242#define REG_DSI_TOTAL 0x00000028
243#define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
244#define DSI_TOTAL_H_TOTAL__SHIFT 0
245static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
246{
247 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
248}
249#define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
250#define DSI_TOTAL_V_TOTAL__SHIFT 16
251static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
252{
253 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
254}
255
256#define REG_DSI_ACTIVE_HSYNC 0x0000002c
257#define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
258#define DSI_ACTIVE_HSYNC_START__SHIFT 0
259static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
260{
261 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
262}
263#define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
264#define DSI_ACTIVE_HSYNC_END__SHIFT 16
265static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
266{
267 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
268}
269
270#define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
271#define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
272#define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
273static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
274{
275 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK;
276}
277#define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
278#define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16
279static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
280{
281 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK;
282}
283
284#define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
285#define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
286#define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
287static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
288{
289 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK;
290}
291#define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
292#define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16
293static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
294{
295 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK;
296}
297
298#define REG_DSI_CMD_DMA_CTRL 0x00000038
299#define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
300#define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
301#define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
302
303#define REG_DSI_CMD_CFG0 0x0000003c
304#define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
305#define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
306static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
307{
308 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK;
309}
310#define DSI_CMD_CFG0_R_SEL 0x00000010
311#define DSI_CMD_CFG0_G_SEL 0x00000100
312#define DSI_CMD_CFG0_B_SEL 0x00001000
313#define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
314#define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20
315static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
316{
317 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK;
318}
319#define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
320#define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16
321static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
322{
323 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK;
324}
325
326#define REG_DSI_CMD_CFG1 0x00000040
327#define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
328#define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
329static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
330{
331 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK;
332}
333#define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
334#define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8
335static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
336{
337 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK;
338}
339#define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
340
341#define REG_DSI_DMA_BASE 0x00000044
342
343#define REG_DSI_DMA_LEN 0x00000048
344
345#define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
346#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
347#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
348static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)
349{
350 return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK;
351}
352#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
353#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8
354static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)
355{
356 return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK;
357}
358#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
359#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16
360static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)
361{
362 return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK;
363}
364
365#define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
366#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
367#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
368static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)
369{
370 return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK;
371}
372#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
373#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16
374static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)
375{
376 return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK;
377}
378
379#define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
380#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
381#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
382static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)
383{
384 return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK;
385}
386#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
387#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8
388static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)
389{
390 return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK;
391}
392#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
393#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16
394static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)
395{
396 return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK;
397}
398
399#define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
400#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
401#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
402static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)
403{
404 return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK;
405}
406#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
407#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16
408static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)
409{
410 return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK;
411}
412
413#define REG_DSI_ACK_ERR_STATUS 0x00000064
414
415static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
416
417static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
418
419#define REG_DSI_TRIG_CTRL 0x00000080
420#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
421#define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
422static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
423{
424 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
425}
426#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
427#define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4
428static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
429{
430 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
431}
432#define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
433#define DSI_TRIG_CTRL_STREAM__SHIFT 8
434static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
435{
436 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK;
437}
438#define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
439#define DSI_TRIG_CTRL_TE 0x80000000
440
441#define REG_DSI_TRIG_DMA 0x0000008c
442
443#define REG_DSI_DLN0_PHY_ERR 0x000000b0
444#define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
445#define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
446#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
447#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
448#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
449
450#define REG_DSI_LP_TIMER_CTRL 0x000000b4
451#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
452#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
453static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)
454{
455 return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK;
456}
457#define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
458#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16
459static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)
460{
461 return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK;
462}
463
464#define REG_DSI_HS_TIMER_CTRL 0x000000b8
465#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
466#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
467static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)
468{
469 return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK;
470}
471#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
472#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16
473static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)
474{
475 return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK;
476}
477#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
478
479#define REG_DSI_TIMEOUT_STATUS 0x000000bc
480
481#define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
482#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
483#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
484static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
485{
486 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
487}
488#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
489#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8
490static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
491{
492 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
493}
494
495#define REG_DSI_EOT_PACKET_CTRL 0x000000c8
496#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
497#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
498
499#define REG_DSI_LANE_STATUS 0x000000a4
500#define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
501#define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
502#define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
503#define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
504#define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
505#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
506#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
507#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
508#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
509#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
510#define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
511
512#define REG_DSI_LANE_CTRL 0x000000a8
513#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
514
515#define REG_DSI_LANE_SWAP_CTRL 0x000000ac
516#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
517#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
518static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
519{
520 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK;
521}
522
523#define REG_DSI_ERR_INT_MASK0 0x00000108
524
525#define REG_DSI_INTR_CTRL 0x0000010c
526
527#define REG_DSI_RESET 0x00000114
528
529#define REG_DSI_CLK_CTRL 0x00000118
530#define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
531#define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
532#define DSI_CLK_CTRL_PCLK_ON 0x00000004
533#define DSI_CLK_CTRL_DSICLK_ON 0x00000008
534#define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
535#define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
536#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
537
538#define REG_DSI_CLK_STATUS 0x0000011c
539#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
540#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
541#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
542#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
543#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
544#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
545#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
546#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
547#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
548#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
549#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
550#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
551#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
552#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
553#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
554#define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
555
556#define REG_DSI_PHY_RESET 0x00000128
557#define DSI_PHY_RESET_RESET 0x00000001
558
559#define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
560#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
561
562#define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
563#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
564#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
565static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)
566{
567 return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK;
568}
569#define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
570#define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
571#define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
572#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
573#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
574#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8
575static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)
576{
577 return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK;
578}
579#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
580#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12
581static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)
582{
583 return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
584}
585#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
586
587#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
588#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
589#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
590static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)
591{
592 return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK;
593}
594#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
595#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8
596static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)
597{
598 return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK;
599}
600#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
601#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16
602static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)
603{
604 return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK;
605}
606
607#define REG_DSI_RDBK_DATA_CTRL 0x000001d0
608#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
609#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
610static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
611{
612 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK;
613}
614#define DSI_RDBK_DATA_CTRL_CLR 0x00000001
615
616#define REG_DSI_VERSION 0x000001f0
617#define DSI_VERSION_MAJOR__MASK 0xff000000
618#define DSI_VERSION_MAJOR__SHIFT 24
619static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
620{
621 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
622}
623
624#define REG_DSI_PHY_PLL_CTRL_0 0x00000200
625#define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001
626
627#define REG_DSI_PHY_PLL_CTRL_1 0x00000204
628
629#define REG_DSI_PHY_PLL_CTRL_2 0x00000208
630
631#define REG_DSI_PHY_PLL_CTRL_3 0x0000020c
632
633#define REG_DSI_PHY_PLL_CTRL_4 0x00000210
634
635#define REG_DSI_PHY_PLL_CTRL_5 0x00000214
636
637#define REG_DSI_PHY_PLL_CTRL_6 0x00000218
638
639#define REG_DSI_PHY_PLL_CTRL_7 0x0000021c
640
641#define REG_DSI_PHY_PLL_CTRL_8 0x00000220
642
643#define REG_DSI_PHY_PLL_CTRL_9 0x00000224
644
645#define REG_DSI_PHY_PLL_CTRL_10 0x00000228
646
647#define REG_DSI_PHY_PLL_CTRL_11 0x0000022c
648
649#define REG_DSI_PHY_PLL_CTRL_12 0x00000230
650
651#define REG_DSI_PHY_PLL_CTRL_13 0x00000234
652
653#define REG_DSI_PHY_PLL_CTRL_14 0x00000238
654
655#define REG_DSI_PHY_PLL_CTRL_15 0x0000023c
656
657#define REG_DSI_PHY_PLL_CTRL_16 0x00000240
658
659#define REG_DSI_PHY_PLL_CTRL_17 0x00000244
660
661#define REG_DSI_PHY_PLL_CTRL_18 0x00000248
662
663#define REG_DSI_PHY_PLL_CTRL_19 0x0000024c
664
665#define REG_DSI_PHY_PLL_CTRL_20 0x00000250
666
667#define REG_DSI_PHY_PLL_STATUS 0x00000280
668#define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001
669
670#define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258
671
672#define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c
673
674#define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260
675
676#define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264
677
678#define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268
679
680#define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c
681
682#define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270
683
684#define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274
685
686#define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278
687
688#define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c
689
690#define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280
691
692#define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284
693
694#define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288
695
696#define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c
697
698#define REG_DSI_8x60_PHY_CTRL_0 0x00000290
699
700#define REG_DSI_8x60_PHY_CTRL_1 0x00000294
701
702#define REG_DSI_8x60_PHY_CTRL_2 0x00000298
703
704#define REG_DSI_8x60_PHY_CTRL_3 0x0000029c
705
706#define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0
707
708#define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4
709
710#define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8
711
712#define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac
713
714#define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc
715
716#define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0
717
718#define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4
719
720#define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8
721
722#define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc
723
724#define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0
725
726#define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4
727
728#define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
729#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
730
731static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
732
733static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
734
735static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
736
737static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
738
739static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
740
741static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
742
743static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
744
745#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
746
747#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
748
749#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
750
751#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
752
753#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
754
755#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
756
757#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
758#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
759#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
760static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
761{
762 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
763}
764
765#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
766#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
767#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
768static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
769{
770 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
771}
772
773#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
774#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
775#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
776static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
777{
778 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
779}
780
781#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
782
783#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
784#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
785#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
786static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
787{
788 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
789}
790
791#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
792#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
793#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
794static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
795{
796 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
797}
798
799#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
800#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
801#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
802static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
803{
804 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
805}
806
807#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
808#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
809#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
810static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
811{
812 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
813}
814
815#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
816#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
817#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
818static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
819{
820 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
821}
822
823#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
824#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
825#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
826static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
827{
828 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
829}
830#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
831#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
832static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
833{
834 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
835}
836
837#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
838#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
839#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
840static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
841{
842 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
843}
844
845#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
846#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
847#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
848static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
849{
850 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
851}
852
853#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
854
855#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
856
857#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
858
859#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
860
861#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
862
863#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
864
865#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
866
867#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
868
869#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
870
871#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
872
873#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
874
875#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
876
877#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
878
879#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
880
881#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
882
883#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
884
885#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
886
887#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
888
889#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
890
891#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
892
893#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
894
895#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
896
897#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
898
899#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
900
901#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
902
903#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
904
905#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
906
907#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
908
909#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
910
911#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
912#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
913
914#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
915#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
916
917#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
918
919#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
920
921#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
922
923#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
924
925#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
926
927#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
928
929#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
930
931#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
932
933#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
934
935#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
936
937#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
938
939#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
940
941#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
942
943#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
944
945#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
946
947#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
948
949#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
950
951#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
952
953#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
954
955#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
956
957#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
958#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
959
960static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
961
962static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
963
964static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
965
966static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
967
968static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
969
970static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
971
972static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
973
974static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
975
976static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
977
978static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
979
980#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
981
982#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
983
984#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
985
986#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
987
988#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
989
990#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
991
992#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
993
994#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
995
996#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
997
998#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
999#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1000#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1001static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1002{
1003 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1004}
1005
1006#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
1007#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1008#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1009static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1010{
1011 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1012}
1013
1014#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
1015#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1016#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1017static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1018{
1019 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1020}
1021
1022#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
1023#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1024
1025#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
1026#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1027#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1028static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1029{
1030 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1031}
1032
1033#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
1034#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1035#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1036static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1037{
1038 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1039}
1040
1041#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
1042#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1043#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1044static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1045{
1046 return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1047}
1048
1049#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
1050#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1051#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1052static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1053{
1054 return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1055}
1056
1057#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
1058#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1059#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1060static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1061{
1062 return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1063}
1064
1065#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
1066#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1067#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1068static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1069{
1070 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1071}
1072#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1073#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1074static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1075{
1076 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1077}
1078
1079#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
1080#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1081#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1082static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1083{
1084 return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1085}
1086
1087#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
1088#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1089#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1090static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1091{
1092 return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1093}
1094
1095#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
1096
1097#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
1098
1099#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
1100
1101#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
1102
1103#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
1104
1105#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
1106
1107#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
1108
1109#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
1110
1111#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
1112
1113#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
1114
1115#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
1116
1117#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
1118
1119#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
1120
1121#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
1122#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1123
1124#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
1125
1126#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
1127
1128#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
1129
1130#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
1131
1132#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
1133
1134#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
1135
1136#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
1137
1138#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1139
1140#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
1141#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
1142
1143#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
1144
1145#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
1146
1147#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
1148
1149#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
1150#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
1151
1152#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
1153
1154#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
1155
1156#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
1157
1158#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
1159#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
1160#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
1161#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
1162#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
1163
1164#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
1165
1166#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
1167
1168#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
1169
1170#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
1171
1172#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
1173
1174#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
1175#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
1176#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
1177static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
1178{
1179 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
1180}
1181#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
1182
1183#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
1184#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
1185#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
1186static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
1187{
1188 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
1189}
1190#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
1191#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
1192static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
1193{
1194 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
1195}
1196
1197#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
1198#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
1199#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
1200static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
1201{
1202 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
1203}
1204
1205#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
1206#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
1207#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
1208static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
1209{
1210 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
1211}
1212
1213#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
1214
1215#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
1216
1217#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
1218
1219#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
1220
1221#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
1222
1223#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
1224
1225#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
1226
1227#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
1228
1229#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
1230#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
1231
1232#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
1233
1234#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
1235
1236#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
1237
1238#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
1239
1240#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
1241
1242#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
1243
1244#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
1245
1246#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
1247
1248#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
1249
1250#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
1251
1252#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
1253
1254#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
1255
1256#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
1257
1258#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
1259
1260#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
1261
1262#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
1263
1264#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
1265
1266#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
1267
1268#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
1269
1270#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
1271
1272#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
1273
1274#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
1275#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
1276
1277#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
1278
1279#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
1280
1281#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
1282
1283#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
1284
1285#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
1286
1287static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1288
1289static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1290
1291static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
1292
1293static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
1294
1295static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
1296
1297static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
1298
1299static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
1300
1301static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
1302
1303static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
1304
1305static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
1306
1307#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
1308
1309#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
1310
1311#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
1312
1313#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
1314
1315#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
1316
1317#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
1318
1319#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
1320
1321#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
1322
1323#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
1324
1325#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
1326#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1327#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1328static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1329{
1330 return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1331}
1332
1333#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
1334#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1335#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1336static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1337{
1338 return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1339}
1340
1341#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
1342#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1343#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1344static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1345{
1346 return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1347}
1348
1349#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
1350#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1351
1352#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
1353#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1354#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1355static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1356{
1357 return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1358}
1359
1360#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
1361#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1362#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1363static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1364{
1365 return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1366}
1367
1368#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
1369#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1370#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1371static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1372{
1373 return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1374}
1375
1376#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
1377#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1378#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1379static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1380{
1381 return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1382}
1383
1384#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
1385#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1386#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1387static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1388{
1389 return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1390}
1391
1392#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
1393#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1394#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1395static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1396{
1397 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1398}
1399#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1400#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1401static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1402{
1403 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1404}
1405
1406#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
1407#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1408#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1409static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1410{
1411 return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1412}
1413
1414#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
1415#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1416#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1417static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1418{
1419 return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1420}
1421
1422#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
1423
1424#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
1425
1426#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
1427
1428#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
1429
1430#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
1431
1432#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
1433
1434#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
1435
1436#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
1437
1438#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
1439
1440#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
1441
1442#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
1443
1444#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
1445
1446#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
1447
1448#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
1449#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1450
1451#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
1452
1453#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
1454
1455#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
1456
1457#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
1458
1459#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
1460
1461#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
1462
1463#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
1464
1465#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1466
1467#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
1468
1469#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
1470
1471#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
1472
1473#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
1474
1475#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
1476#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
1477#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
1478static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
1479{
1480 return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
1481}
1482#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
1483#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
1484static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
1485{
1486 return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
1487}
1488
1489#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
1490#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
1491
1492#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
1493#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
1494
1495#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
1496
1497#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
1498
1499#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
1500
1501#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
1502
1503#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
1504
1505#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
1506
1507#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
1508
1509#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
1510
1511#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
1512
1513#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
1514
1515#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
1516
1517#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
1518#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
1519
1520#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
1521#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
1522#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
1523static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
1524{
1525 return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
1526}
1527
1528static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1529
1530static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1531#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
1532#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
1533static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
1534{
1535 return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
1536}
1537
1538static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1539#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
1540
1541static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1542
1543static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1544
1545static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1546
1547static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1548
1549static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1550#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1551#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1552static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1553{
1554 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
1555}
1556
1557static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1558#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1559#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1560static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1561{
1562 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
1563}
1564
1565static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1566#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1567#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1568static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1569{
1570 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
1571}
1572
1573static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1574#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1575#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1576static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1577{
1578 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
1579}
1580
1581static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1582#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1583#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
1584static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
1585{
1586 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
1587}
1588
1589static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1590#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1591#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
1592static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
1593{
1594 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
1595}
1596#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1597#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
1598static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
1599{
1600 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
1601}
1602
1603static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
1604#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1605#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
1606static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
1607{
1608 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
1609}
1610
1611static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
1612#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1613#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1614static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1615{
1616 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
1617}
1618
1619static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
1620
1621static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
1622
1623static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
1624
1625#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
1626
1627#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
1628
1629#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
1630
1631#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
1632
1633#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
1634
1635#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
1636
1637#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
1638
1639#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
1640
1641#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
1642
1643#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
1644
1645#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
1646
1647#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
1648
1649#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
1650
1651#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
1652
1653#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
1654
1655#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
1656
1657#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
1658
1659#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
1660
1661#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
1662
1663#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
1664
1665#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
1666
1667#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
1668
1669#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
1670
1671#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
1672
1673#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
1674
1675#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
1676
1677#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
1678
1679#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
1680
1681#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
1682
1683#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
1684
1685#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
1686
1687#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
1688
1689#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
1690
1691#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
1692
1693#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
1694
1695#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
1696
1697#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
1698
1699#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
1700
1701#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
1702
1703#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
1704
1705#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
1706
1707#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
1708
1709#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
1710
1711#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
1712
1713#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
1714
1715#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
1716
1717#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
1718
1719#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
1720
1721#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
1722
1723#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
1724
1725#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
1726
1727#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
1728
1729#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
1730
1731#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
1732
1733#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
1734
1735#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
1736
1737#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
1738
1739#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
1740
1741#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
1742
1743#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
1744
1745#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
1746
1747#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
1748
1749#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
1750
1751#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
1752
1753#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
1754
1755#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
1756
1757#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
1758
1759#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
1760
1761#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
1762
1763#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
1764
1765#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
1766
1767#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
1768
1769#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
1770
1771#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
1772
1773#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
1774
1775#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
1776
1777#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
1778
1779#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
1780
1781#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
1782
1783#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
1784
1785#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
1786
1787#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
1788
1789static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1790
1791static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1792
1793static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1794
1795static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1796
1797static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1798
1799static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1800
1801static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1802
1803static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1804
1805static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1806
1807static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1808
1809static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1810
1811static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1812
1813static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1814
1815#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
1816
1817#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
1818
1819#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
1820
1821#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
1822
1823#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
1824
1825#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
1826
1827#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
1828
1829#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
1830
1831#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
1832
1833#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
1834
1835#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
1836
1837#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
1838
1839#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
1840
1841#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
1842
1843#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
1844
1845#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
1846
1847#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
1848
1849#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
1850
1851#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
1852
1853#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
1854
1855#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
1856
1857#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
1858
1859#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
1860
1861#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
1862
1863#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
1864
1865#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
1866
1867#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
1868
1869#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
1870
1871#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
1872
1873#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
1874
1875#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
1876
1877#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
1878
1879#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
1880
1881#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
1882
1883#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
1884
1885#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
1886
1887#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
1888
1889
1890#endif /* DSI_XML */