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1/* drivers/gpu/drm/exynos5433_drm_decon.c
2 *
3 * Copyright (C) 2015 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Hyungwon Hwang <human.hwang@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundationr
11 */
12
13#include <linux/platform_device.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/of_device.h>
17#include <linux/of_gpio.h>
18#include <linux/pm_runtime.h>
19
20#include <video/exynos5433_decon.h>
21
22#include "exynos_drm_drv.h"
23#include "exynos_drm_crtc.h"
24#include "exynos_drm_fb.h"
25#include "exynos_drm_plane.h"
26#include "exynos_drm_iommu.h"
27
28#define WINDOWS_NR 3
29#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
30
31static const char * const decon_clks_name[] = {
32 "pclk",
33 "aclk_decon",
34 "aclk_smmu_decon0x",
35 "aclk_xiu_decon0x",
36 "pclk_smmu_decon0x",
37 "sclk_decon_vclk",
38 "sclk_decon_eclk",
39};
40
41enum decon_iftype {
42 IFTYPE_RGB,
43 IFTYPE_I80,
44 IFTYPE_HDMI
45};
46
47enum decon_flag_bits {
48 BIT_CLKS_ENABLED,
49 BIT_IRQS_ENABLED,
50 BIT_WIN_UPDATED,
51 BIT_SUSPENDED
52};
53
54struct decon_context {
55 struct device *dev;
56 struct drm_device *drm_dev;
57 struct exynos_drm_crtc *crtc;
58 struct exynos_drm_plane planes[WINDOWS_NR];
59 struct exynos_drm_plane_config configs[WINDOWS_NR];
60 void __iomem *addr;
61 struct clk *clks[ARRAY_SIZE(decon_clks_name)];
62 int pipe;
63 unsigned long flags;
64 enum decon_iftype out_type;
65 int first_win;
66};
67
68static const uint32_t decon_formats[] = {
69 DRM_FORMAT_XRGB1555,
70 DRM_FORMAT_RGB565,
71 DRM_FORMAT_XRGB8888,
72 DRM_FORMAT_ARGB8888,
73};
74
75static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
76 DRM_PLANE_TYPE_PRIMARY,
77 DRM_PLANE_TYPE_OVERLAY,
78 DRM_PLANE_TYPE_CURSOR,
79};
80
81static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
82 u32 val)
83{
84 val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
85 writel(val, ctx->addr + reg);
86}
87
88static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
89{
90 struct decon_context *ctx = crtc->ctx;
91 u32 val;
92
93 if (test_bit(BIT_SUSPENDED, &ctx->flags))
94 return -EPERM;
95
96 if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
97 val = VIDINTCON0_INTEN;
98 if (ctx->out_type == IFTYPE_I80)
99 val |= VIDINTCON0_FRAMEDONE;
100 else
101 val |= VIDINTCON0_INTFRMEN;
102
103 writel(val, ctx->addr + DECON_VIDINTCON0);
104 }
105
106 return 0;
107}
108
109static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
110{
111 struct decon_context *ctx = crtc->ctx;
112
113 if (test_bit(BIT_SUSPENDED, &ctx->flags))
114 return;
115
116 if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
117 writel(0, ctx->addr + DECON_VIDINTCON0);
118}
119
120static void decon_setup_trigger(struct decon_context *ctx)
121{
122 u32 val = (ctx->out_type != IFTYPE_HDMI)
123 ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
124 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
125 : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
126 TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
127 writel(val, ctx->addr + DECON_TRIGCON);
128}
129
130static void decon_commit(struct exynos_drm_crtc *crtc)
131{
132 struct decon_context *ctx = crtc->ctx;
133 struct drm_display_mode *m = &crtc->base.mode;
134 u32 val;
135
136 if (test_bit(BIT_SUSPENDED, &ctx->flags))
137 return;
138
139 if (ctx->out_type == IFTYPE_HDMI) {
140 m->crtc_hsync_start = m->crtc_hdisplay + 10;
141 m->crtc_hsync_end = m->crtc_htotal - 92;
142 m->crtc_vsync_start = m->crtc_vdisplay + 1;
143 m->crtc_vsync_end = m->crtc_vsync_start + 1;
144 }
145
146 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
147
148 /* enable clock gate */
149 val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
150 writel(val, ctx->addr + DECON_CMU);
151
152 /* lcd on and use command if */
153 val = VIDOUT_LCD_ON;
154 if (ctx->out_type == IFTYPE_I80)
155 val |= VIDOUT_COMMAND_IF;
156 else
157 val |= VIDOUT_RGB_IF;
158 writel(val, ctx->addr + DECON_VIDOUTCON0);
159
160 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
161 VIDTCON2_HOZVAL(m->hdisplay - 1);
162 writel(val, ctx->addr + DECON_VIDTCON2);
163
164 if (ctx->out_type != IFTYPE_I80) {
165 val = VIDTCON00_VBPD_F(
166 m->crtc_vtotal - m->crtc_vsync_end - 1) |
167 VIDTCON00_VFPD_F(
168 m->crtc_vsync_start - m->crtc_vdisplay - 1);
169 writel(val, ctx->addr + DECON_VIDTCON00);
170
171 val = VIDTCON01_VSPW_F(
172 m->crtc_vsync_end - m->crtc_vsync_start - 1);
173 writel(val, ctx->addr + DECON_VIDTCON01);
174
175 val = VIDTCON10_HBPD_F(
176 m->crtc_htotal - m->crtc_hsync_end - 1) |
177 VIDTCON10_HFPD_F(
178 m->crtc_hsync_start - m->crtc_hdisplay - 1);
179 writel(val, ctx->addr + DECON_VIDTCON10);
180
181 val = VIDTCON11_HSPW_F(
182 m->crtc_hsync_end - m->crtc_hsync_start - 1);
183 writel(val, ctx->addr + DECON_VIDTCON11);
184 }
185
186 decon_setup_trigger(ctx);
187
188 /* enable output and display signal */
189 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
190}
191
192static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
193 struct drm_framebuffer *fb)
194{
195 unsigned long val;
196
197 val = readl(ctx->addr + DECON_WINCONx(win));
198 val &= ~WINCONx_BPPMODE_MASK;
199
200 switch (fb->pixel_format) {
201 case DRM_FORMAT_XRGB1555:
202 val |= WINCONx_BPPMODE_16BPP_I1555;
203 val |= WINCONx_HAWSWP_F;
204 val |= WINCONx_BURSTLEN_16WORD;
205 break;
206 case DRM_FORMAT_RGB565:
207 val |= WINCONx_BPPMODE_16BPP_565;
208 val |= WINCONx_HAWSWP_F;
209 val |= WINCONx_BURSTLEN_16WORD;
210 break;
211 case DRM_FORMAT_XRGB8888:
212 val |= WINCONx_BPPMODE_24BPP_888;
213 val |= WINCONx_WSWP_F;
214 val |= WINCONx_BURSTLEN_16WORD;
215 break;
216 case DRM_FORMAT_ARGB8888:
217 val |= WINCONx_BPPMODE_32BPP_A8888;
218 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
219 val |= WINCONx_BURSTLEN_16WORD;
220 break;
221 default:
222 DRM_ERROR("Proper pixel format is not set\n");
223 return;
224 }
225
226 DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
227
228 /*
229 * In case of exynos, setting dma-burst to 16Word causes permanent
230 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
231 * switching which is based on plane size is not recommended as
232 * plane size varies a lot towards the end of the screen and rapid
233 * movement causes unstable DMA which results into iommu crash/tear.
234 */
235
236 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
237 val &= ~WINCONx_BURSTLEN_MASK;
238 val |= WINCONx_BURSTLEN_8WORD;
239 }
240
241 writel(val, ctx->addr + DECON_WINCONx(win));
242}
243
244static void decon_shadow_protect_win(struct decon_context *ctx, int win,
245 bool protect)
246{
247 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
248 protect ? ~0 : 0);
249}
250
251static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
252{
253 struct decon_context *ctx = crtc->ctx;
254 int i;
255
256 if (test_bit(BIT_SUSPENDED, &ctx->flags))
257 return;
258
259 for (i = ctx->first_win; i < WINDOWS_NR; i++)
260 decon_shadow_protect_win(ctx, i, true);
261}
262
263#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
264#define COORDINATE_X(x) BIT_VAL((x), 23, 12)
265#define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
266
267static void decon_update_plane(struct exynos_drm_crtc *crtc,
268 struct exynos_drm_plane *plane)
269{
270 struct exynos_drm_plane_state *state =
271 to_exynos_plane_state(plane->base.state);
272 struct decon_context *ctx = crtc->ctx;
273 struct drm_framebuffer *fb = state->base.fb;
274 unsigned int win = plane->index;
275 unsigned int bpp = fb->bits_per_pixel >> 3;
276 unsigned int pitch = fb->pitches[0];
277 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
278 u32 val;
279
280 if (test_bit(BIT_SUSPENDED, &ctx->flags))
281 return;
282
283 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
284 writel(val, ctx->addr + DECON_VIDOSDxA(win));
285
286 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
287 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
288 writel(val, ctx->addr + DECON_VIDOSDxB(win));
289
290 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
291 VIDOSD_Wx_ALPHA_B_F(0x0);
292 writel(val, ctx->addr + DECON_VIDOSDxC(win));
293
294 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
295 VIDOSD_Wx_ALPHA_B_F(0x0);
296 writel(val, ctx->addr + DECON_VIDOSDxD(win));
297
298 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
299
300 val = dma_addr + pitch * state->src.h;
301 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
302
303 if (ctx->out_type != IFTYPE_HDMI)
304 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
305 | BIT_VAL(state->crtc.w * bpp, 13, 0);
306 else
307 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
308 | BIT_VAL(state->crtc.w * bpp, 14, 0);
309 writel(val, ctx->addr + DECON_VIDW0xADD2(win));
310
311 decon_win_set_pixfmt(ctx, win, fb);
312
313 /* window enable */
314 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
315
316 /* standalone update */
317 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
318}
319
320static void decon_disable_plane(struct exynos_drm_crtc *crtc,
321 struct exynos_drm_plane *plane)
322{
323 struct decon_context *ctx = crtc->ctx;
324 unsigned int win = plane->index;
325
326 if (test_bit(BIT_SUSPENDED, &ctx->flags))
327 return;
328
329 decon_shadow_protect_win(ctx, win, true);
330
331 /* window disable */
332 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
333
334 decon_shadow_protect_win(ctx, win, false);
335
336 /* standalone update */
337 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
338}
339
340static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
341{
342 struct decon_context *ctx = crtc->ctx;
343 int i;
344
345 if (test_bit(BIT_SUSPENDED, &ctx->flags))
346 return;
347
348 for (i = ctx->first_win; i < WINDOWS_NR; i++)
349 decon_shadow_protect_win(ctx, i, false);
350
351 if (ctx->out_type == IFTYPE_I80)
352 set_bit(BIT_WIN_UPDATED, &ctx->flags);
353}
354
355static void decon_swreset(struct decon_context *ctx)
356{
357 unsigned int tries;
358
359 writel(0, ctx->addr + DECON_VIDCON0);
360 for (tries = 2000; tries; --tries) {
361 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
362 break;
363 udelay(10);
364 }
365
366 WARN(tries == 0, "failed to disable DECON\n");
367
368 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
369 for (tries = 2000; tries; --tries) {
370 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
371 break;
372 udelay(10);
373 }
374
375 WARN(tries == 0, "failed to software reset DECON\n");
376
377 if (ctx->out_type != IFTYPE_HDMI)
378 return;
379
380 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
381 decon_set_bits(ctx, DECON_CMU,
382 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
383 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
384 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
385 ctx->addr + DECON_CRCCTRL);
386 decon_setup_trigger(ctx);
387}
388
389static void decon_enable(struct exynos_drm_crtc *crtc)
390{
391 struct decon_context *ctx = crtc->ctx;
392
393 if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
394 return;
395
396 pm_runtime_get_sync(ctx->dev);
397
398 set_bit(BIT_CLKS_ENABLED, &ctx->flags);
399
400 /* if vblank was enabled status, enable it again. */
401 if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
402 decon_enable_vblank(ctx->crtc);
403
404 decon_commit(ctx->crtc);
405}
406
407static void decon_disable(struct exynos_drm_crtc *crtc)
408{
409 struct decon_context *ctx = crtc->ctx;
410 int i;
411
412 if (test_bit(BIT_SUSPENDED, &ctx->flags))
413 return;
414
415 /*
416 * We need to make sure that all windows are disabled before we
417 * suspend that connector. Otherwise we might try to scan from
418 * a destroyed buffer later.
419 */
420 for (i = ctx->first_win; i < WINDOWS_NR; i++)
421 decon_disable_plane(crtc, &ctx->planes[i]);
422
423 decon_swreset(ctx);
424
425 clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
426
427 pm_runtime_put_sync(ctx->dev);
428
429 set_bit(BIT_SUSPENDED, &ctx->flags);
430}
431
432static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
433{
434 struct decon_context *ctx = crtc->ctx;
435
436 if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
437 return;
438
439 if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
440 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
441
442 drm_crtc_handle_vblank(&ctx->crtc->base);
443}
444
445static void decon_clear_channels(struct exynos_drm_crtc *crtc)
446{
447 struct decon_context *ctx = crtc->ctx;
448 int win, i, ret;
449
450 DRM_DEBUG_KMS("%s\n", __FILE__);
451
452 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
453 ret = clk_prepare_enable(ctx->clks[i]);
454 if (ret < 0)
455 goto err;
456 }
457
458 for (win = 0; win < WINDOWS_NR; win++) {
459 decon_shadow_protect_win(ctx, win, true);
460 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
461 decon_shadow_protect_win(ctx, win, false);
462 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
463 }
464 /* TODO: wait for possible vsync */
465 msleep(50);
466
467err:
468 while (--i >= 0)
469 clk_disable_unprepare(ctx->clks[i]);
470}
471
472static struct exynos_drm_crtc_ops decon_crtc_ops = {
473 .enable = decon_enable,
474 .disable = decon_disable,
475 .enable_vblank = decon_enable_vblank,
476 .disable_vblank = decon_disable_vblank,
477 .atomic_begin = decon_atomic_begin,
478 .update_plane = decon_update_plane,
479 .disable_plane = decon_disable_plane,
480 .atomic_flush = decon_atomic_flush,
481 .te_handler = decon_te_irq_handler,
482};
483
484static int decon_bind(struct device *dev, struct device *master, void *data)
485{
486 struct decon_context *ctx = dev_get_drvdata(dev);
487 struct drm_device *drm_dev = data;
488 struct exynos_drm_private *priv = drm_dev->dev_private;
489 struct exynos_drm_plane *exynos_plane;
490 enum exynos_drm_output_type out_type;
491 unsigned int win;
492 int ret;
493
494 ctx->drm_dev = drm_dev;
495 ctx->pipe = priv->pipe++;
496
497 for (win = ctx->first_win; win < WINDOWS_NR; win++) {
498 int tmp = (win == ctx->first_win) ? 0 : win;
499
500 ctx->configs[win].pixel_formats = decon_formats;
501 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
502 ctx->configs[win].zpos = win;
503 ctx->configs[win].type = decon_win_types[tmp];
504
505 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
506 1 << ctx->pipe, &ctx->configs[win]);
507 if (ret)
508 return ret;
509 }
510
511 exynos_plane = &ctx->planes[ctx->first_win];
512 out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
513 : EXYNOS_DISPLAY_TYPE_LCD;
514 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
515 ctx->pipe, out_type,
516 &decon_crtc_ops, ctx);
517 if (IS_ERR(ctx->crtc)) {
518 ret = PTR_ERR(ctx->crtc);
519 goto err;
520 }
521
522 decon_clear_channels(ctx->crtc);
523
524 ret = drm_iommu_attach_device(drm_dev, dev);
525 if (ret)
526 goto err;
527
528 return ret;
529err:
530 priv->pipe--;
531 return ret;
532}
533
534static void decon_unbind(struct device *dev, struct device *master, void *data)
535{
536 struct decon_context *ctx = dev_get_drvdata(dev);
537
538 decon_disable(ctx->crtc);
539
540 /* detach this sub driver from iommu mapping if supported. */
541 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
542}
543
544static const struct component_ops decon_component_ops = {
545 .bind = decon_bind,
546 .unbind = decon_unbind,
547};
548
549static irqreturn_t decon_irq_handler(int irq, void *dev_id)
550{
551 struct decon_context *ctx = dev_id;
552 u32 val;
553 int win;
554
555 if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
556 goto out;
557
558 val = readl(ctx->addr + DECON_VIDINTCON1);
559 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
560
561 if (val) {
562 for (win = ctx->first_win; win < WINDOWS_NR ; win++) {
563 struct exynos_drm_plane *plane = &ctx->planes[win];
564
565 if (!plane->pending_fb)
566 continue;
567
568 exynos_drm_crtc_finish_update(ctx->crtc, plane);
569 }
570
571 /* clear */
572 writel(val, ctx->addr + DECON_VIDINTCON1);
573 }
574
575out:
576 return IRQ_HANDLED;
577}
578
579#ifdef CONFIG_PM
580static int exynos5433_decon_suspend(struct device *dev)
581{
582 struct decon_context *ctx = dev_get_drvdata(dev);
583 int i = ARRAY_SIZE(decon_clks_name);
584
585 while (--i >= 0)
586 clk_disable_unprepare(ctx->clks[i]);
587
588 return 0;
589}
590
591static int exynos5433_decon_resume(struct device *dev)
592{
593 struct decon_context *ctx = dev_get_drvdata(dev);
594 int i, ret;
595
596 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
597 ret = clk_prepare_enable(ctx->clks[i]);
598 if (ret < 0)
599 goto err;
600 }
601
602 return 0;
603
604err:
605 while (--i >= 0)
606 clk_disable_unprepare(ctx->clks[i]);
607
608 return ret;
609}
610#endif
611
612static const struct dev_pm_ops exynos5433_decon_pm_ops = {
613 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
614 NULL)
615};
616
617static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
618 {
619 .compatible = "samsung,exynos5433-decon",
620 .data = (void *)IFTYPE_RGB
621 },
622 {
623 .compatible = "samsung,exynos5433-decon-tv",
624 .data = (void *)IFTYPE_HDMI
625 },
626 {},
627};
628MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
629
630static int exynos5433_decon_probe(struct platform_device *pdev)
631{
632 const struct of_device_id *of_id;
633 struct device *dev = &pdev->dev;
634 struct decon_context *ctx;
635 struct resource *res;
636 int ret;
637 int i;
638
639 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
640 if (!ctx)
641 return -ENOMEM;
642
643 __set_bit(BIT_SUSPENDED, &ctx->flags);
644 ctx->dev = dev;
645
646 of_id = of_match_device(exynos5433_decon_driver_dt_match, &pdev->dev);
647 ctx->out_type = (enum decon_iftype)of_id->data;
648
649 if (ctx->out_type == IFTYPE_HDMI)
650 ctx->first_win = 1;
651 else if (of_get_child_by_name(dev->of_node, "i80-if-timings"))
652 ctx->out_type = IFTYPE_I80;
653
654 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
655 struct clk *clk;
656
657 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
658 if (IS_ERR(clk))
659 return PTR_ERR(clk);
660
661 ctx->clks[i] = clk;
662 }
663
664 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
665 if (!res) {
666 dev_err(dev, "cannot find IO resource\n");
667 return -ENXIO;
668 }
669
670 ctx->addr = devm_ioremap_resource(dev, res);
671 if (IS_ERR(ctx->addr)) {
672 dev_err(dev, "ioremap failed\n");
673 return PTR_ERR(ctx->addr);
674 }
675
676 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
677 (ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync");
678 if (!res) {
679 dev_err(dev, "cannot find IRQ resource\n");
680 return -ENXIO;
681 }
682
683 ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
684 "drm_decon", ctx);
685 if (ret < 0) {
686 dev_err(dev, "lcd_sys irq request failed\n");
687 return ret;
688 }
689
690 platform_set_drvdata(pdev, ctx);
691
692 pm_runtime_enable(dev);
693
694 ret = component_add(dev, &decon_component_ops);
695 if (ret)
696 goto err_disable_pm_runtime;
697
698 return 0;
699
700err_disable_pm_runtime:
701 pm_runtime_disable(dev);
702
703 return ret;
704}
705
706static int exynos5433_decon_remove(struct platform_device *pdev)
707{
708 pm_runtime_disable(&pdev->dev);
709
710 component_del(&pdev->dev, &decon_component_ops);
711
712 return 0;
713}
714
715struct platform_driver exynos5433_decon_driver = {
716 .probe = exynos5433_decon_probe,
717 .remove = exynos5433_decon_remove,
718 .driver = {
719 .name = "exynos5433-decon",
720 .pm = &exynos5433_decon_pm_ops,
721 .of_match_table = exynos5433_decon_driver_dt_match,
722 },
723};
1// SPDX-License-Identifier: GPL-2.0-only
2/* drivers/gpu/drm/exynos5433_drm_decon.c
3 *
4 * Copyright (C) 2015 Samsung Electronics Co.Ltd
5 * Authors:
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 * Hyungwon Hwang <human.hwang@samsung.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/component.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/mfd/syscon.h>
15#include <linux/of_device.h>
16#include <linux/of_gpio.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/regmap.h>
20
21#include <drm/drm_fourcc.h>
22#include <drm/drm_vblank.h>
23
24#include "exynos_drm_crtc.h"
25#include "exynos_drm_drv.h"
26#include "exynos_drm_fb.h"
27#include "exynos_drm_plane.h"
28#include "regs-decon5433.h"
29
30#define DSD_CFG_MUX 0x1004
31#define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
32
33#define WINDOWS_NR 5
34#define PRIMARY_WIN 2
35#define CURSON_WIN 4
36
37#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
38
39#define I80_HW_TRG (1 << 0)
40#define IFTYPE_HDMI (1 << 1)
41
42static const char * const decon_clks_name[] = {
43 "pclk",
44 "aclk_decon",
45 "aclk_smmu_decon0x",
46 "aclk_xiu_decon0x",
47 "pclk_smmu_decon0x",
48 "aclk_smmu_decon1x",
49 "aclk_xiu_decon1x",
50 "pclk_smmu_decon1x",
51 "sclk_decon_vclk",
52 "sclk_decon_eclk",
53};
54
55struct decon_context {
56 struct device *dev;
57 struct drm_device *drm_dev;
58 void *dma_priv;
59 struct exynos_drm_crtc *crtc;
60 struct exynos_drm_plane planes[WINDOWS_NR];
61 struct exynos_drm_plane_config configs[WINDOWS_NR];
62 void __iomem *addr;
63 struct regmap *sysreg;
64 struct clk *clks[ARRAY_SIZE(decon_clks_name)];
65 unsigned int irq;
66 unsigned int irq_vsync;
67 unsigned int irq_lcd_sys;
68 unsigned int te_irq;
69 unsigned long out_type;
70 int first_win;
71 spinlock_t vblank_lock;
72 u32 frame_id;
73};
74
75static const uint32_t decon_formats[] = {
76 DRM_FORMAT_XRGB1555,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_ARGB8888,
80};
81
82static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
83 [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
84 [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
85};
86
87static const unsigned int capabilities[WINDOWS_NR] = {
88 0,
89 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
90 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
91 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
92 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
93};
94
95static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
96 u32 val)
97{
98 val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
99 writel(val, ctx->addr + reg);
100}
101
102static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
103{
104 struct decon_context *ctx = crtc->ctx;
105 u32 val;
106
107 val = VIDINTCON0_INTEN;
108 if (crtc->i80_mode)
109 val |= VIDINTCON0_FRAMEDONE;
110 else
111 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
112
113 writel(val, ctx->addr + DECON_VIDINTCON0);
114
115 enable_irq(ctx->irq);
116 if (!(ctx->out_type & I80_HW_TRG))
117 enable_irq(ctx->te_irq);
118
119 return 0;
120}
121
122static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
123{
124 struct decon_context *ctx = crtc->ctx;
125
126 if (!(ctx->out_type & I80_HW_TRG))
127 disable_irq_nosync(ctx->te_irq);
128 disable_irq_nosync(ctx->irq);
129
130 writel(0, ctx->addr + DECON_VIDINTCON0);
131}
132
133/* return number of starts/ends of frame transmissions since reset */
134static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
135{
136 u32 frm, pfrm, status, cnt = 2;
137
138 /* To get consistent result repeat read until frame id is stable.
139 * Usually the loop will be executed once, in rare cases when the loop
140 * is executed at frame change time 2nd pass will be needed.
141 */
142 frm = readl(ctx->addr + DECON_CRFMID);
143 do {
144 status = readl(ctx->addr + DECON_VIDCON1);
145 pfrm = frm;
146 frm = readl(ctx->addr + DECON_CRFMID);
147 } while (frm != pfrm && --cnt);
148
149 /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
150 * of RGB, it should be taken into account.
151 */
152 if (!frm)
153 return 0;
154
155 switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
156 case VIDCON1_VSTATUS_VS:
157 if (!(ctx->crtc->i80_mode))
158 --frm;
159 break;
160 case VIDCON1_VSTATUS_BP:
161 --frm;
162 break;
163 case VIDCON1_I80_ACTIVE:
164 case VIDCON1_VSTATUS_AC:
165 if (end)
166 --frm;
167 break;
168 default:
169 break;
170 }
171
172 return frm;
173}
174
175static void decon_setup_trigger(struct decon_context *ctx)
176{
177 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
178 return;
179
180 if (!(ctx->out_type & I80_HW_TRG)) {
181 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
182 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
183 ctx->addr + DECON_TRIGCON);
184 return;
185 }
186
187 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
188 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
189
190 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
191 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
192 DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n");
193}
194
195static void decon_commit(struct exynos_drm_crtc *crtc)
196{
197 struct decon_context *ctx = crtc->ctx;
198 struct drm_display_mode *m = &crtc->base.mode;
199 bool interlaced = false;
200 u32 val;
201
202 if (ctx->out_type & IFTYPE_HDMI) {
203 m->crtc_hsync_start = m->crtc_hdisplay + 10;
204 m->crtc_hsync_end = m->crtc_htotal - 92;
205 m->crtc_vsync_start = m->crtc_vdisplay + 1;
206 m->crtc_vsync_end = m->crtc_vsync_start + 1;
207 if (m->flags & DRM_MODE_FLAG_INTERLACE)
208 interlaced = true;
209 }
210
211 decon_setup_trigger(ctx);
212
213 /* lcd on and use command if */
214 val = VIDOUT_LCD_ON;
215 if (interlaced)
216 val |= VIDOUT_INTERLACE_EN_F;
217 if (crtc->i80_mode) {
218 val |= VIDOUT_COMMAND_IF;
219 } else {
220 val |= VIDOUT_RGB_IF;
221 }
222
223 writel(val, ctx->addr + DECON_VIDOUTCON0);
224
225 if (interlaced)
226 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
227 VIDTCON2_HOZVAL(m->hdisplay - 1);
228 else
229 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
230 VIDTCON2_HOZVAL(m->hdisplay - 1);
231 writel(val, ctx->addr + DECON_VIDTCON2);
232
233 if (!crtc->i80_mode) {
234 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
235 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
236
237 if (interlaced)
238 vbp = vbp / 2 - 1;
239 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
240 writel(val, ctx->addr + DECON_VIDTCON00);
241
242 val = VIDTCON01_VSPW_F(
243 m->crtc_vsync_end - m->crtc_vsync_start - 1);
244 writel(val, ctx->addr + DECON_VIDTCON01);
245
246 val = VIDTCON10_HBPD_F(
247 m->crtc_htotal - m->crtc_hsync_end - 1) |
248 VIDTCON10_HFPD_F(
249 m->crtc_hsync_start - m->crtc_hdisplay - 1);
250 writel(val, ctx->addr + DECON_VIDTCON10);
251
252 val = VIDTCON11_HSPW_F(
253 m->crtc_hsync_end - m->crtc_hsync_start - 1);
254 writel(val, ctx->addr + DECON_VIDTCON11);
255 }
256
257 /* enable output and display signal */
258 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
259
260 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
261}
262
263static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win,
264 unsigned int alpha, unsigned int pixel_alpha)
265{
266 u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf);
267 u32 val = 0;
268
269 switch (pixel_alpha) {
270 case DRM_MODE_BLEND_PIXEL_NONE:
271 case DRM_MODE_BLEND_COVERAGE:
272 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A);
273 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
274 break;
275 case DRM_MODE_BLEND_PREMULTI:
276 default:
277 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
278 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0);
279 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
280 } else {
281 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE);
282 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
283 }
284 break;
285 }
286 decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val);
287}
288
289static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
290 unsigned int alpha, unsigned int pixel_alpha)
291{
292 u32 win_alpha = alpha >> 8;
293 u32 val = 0;
294
295 switch (pixel_alpha) {
296 case DRM_MODE_BLEND_PIXEL_NONE:
297 break;
298 case DRM_MODE_BLEND_COVERAGE:
299 case DRM_MODE_BLEND_PREMULTI:
300 default:
301 val |= WINCONx_ALPHA_SEL_F;
302 val |= WINCONx_BLD_PIX_F;
303 val |= WINCONx_ALPHA_MUL_F;
304 break;
305 }
306 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val);
307
308 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
309 val = VIDOSD_Wx_ALPHA_R_F(win_alpha) |
310 VIDOSD_Wx_ALPHA_G_F(win_alpha) |
311 VIDOSD_Wx_ALPHA_B_F(win_alpha);
312 decon_set_bits(ctx, DECON_VIDOSDxC(win),
313 VIDOSDxC_ALPHA0_RGB_MASK, val);
314 decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW);
315 }
316}
317
318static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
319 struct drm_framebuffer *fb)
320{
321 struct exynos_drm_plane plane = ctx->planes[win];
322 struct exynos_drm_plane_state *state =
323 to_exynos_plane_state(plane.base.state);
324 unsigned int alpha = state->base.alpha;
325 unsigned int pixel_alpha;
326 unsigned long val;
327
328 if (fb->format->has_alpha)
329 pixel_alpha = state->base.pixel_blend_mode;
330 else
331 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
332
333 val = readl(ctx->addr + DECON_WINCONx(win));
334 val &= WINCONx_ENWIN_F;
335
336 switch (fb->format->format) {
337 case DRM_FORMAT_XRGB1555:
338 val |= WINCONx_BPPMODE_16BPP_I1555;
339 val |= WINCONx_HAWSWP_F;
340 val |= WINCONx_BURSTLEN_16WORD;
341 break;
342 case DRM_FORMAT_RGB565:
343 val |= WINCONx_BPPMODE_16BPP_565;
344 val |= WINCONx_HAWSWP_F;
345 val |= WINCONx_BURSTLEN_16WORD;
346 break;
347 case DRM_FORMAT_XRGB8888:
348 val |= WINCONx_BPPMODE_24BPP_888;
349 val |= WINCONx_WSWP_F;
350 val |= WINCONx_BURSTLEN_16WORD;
351 break;
352 case DRM_FORMAT_ARGB8888:
353 default:
354 val |= WINCONx_BPPMODE_32BPP_A8888;
355 val |= WINCONx_WSWP_F;
356 val |= WINCONx_BURSTLEN_16WORD;
357 break;
358 }
359
360 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]);
361
362 /*
363 * In case of exynos, setting dma-burst to 16Word causes permanent
364 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
365 * switching which is based on plane size is not recommended as
366 * plane size varies a lot towards the end of the screen and rapid
367 * movement causes unstable DMA which results into iommu crash/tear.
368 */
369
370 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
371 val &= ~WINCONx_BURSTLEN_MASK;
372 val |= WINCONx_BURSTLEN_8WORD;
373 }
374 decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val);
375
376 if (win > 0) {
377 decon_win_set_bldmod(ctx, win, alpha, pixel_alpha);
378 decon_win_set_bldeq(ctx, win, alpha, pixel_alpha);
379 }
380}
381
382static void decon_shadow_protect(struct decon_context *ctx, bool protect)
383{
384 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
385 protect ? ~0 : 0);
386}
387
388static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
389{
390 struct decon_context *ctx = crtc->ctx;
391
392 decon_shadow_protect(ctx, true);
393}
394
395#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
396#define COORDINATE_X(x) BIT_VAL((x), 23, 12)
397#define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
398
399static void decon_update_plane(struct exynos_drm_crtc *crtc,
400 struct exynos_drm_plane *plane)
401{
402 struct exynos_drm_plane_state *state =
403 to_exynos_plane_state(plane->base.state);
404 struct decon_context *ctx = crtc->ctx;
405 struct drm_framebuffer *fb = state->base.fb;
406 unsigned int win = plane->index;
407 unsigned int cpp = fb->format->cpp[0];
408 unsigned int pitch = fb->pitches[0];
409 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
410 u32 val;
411
412 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
413 val = COORDINATE_X(state->crtc.x) |
414 COORDINATE_Y(state->crtc.y / 2);
415 writel(val, ctx->addr + DECON_VIDOSDxA(win));
416
417 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
418 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
419 writel(val, ctx->addr + DECON_VIDOSDxB(win));
420 } else {
421 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
422 writel(val, ctx->addr + DECON_VIDOSDxA(win));
423
424 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
425 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
426 writel(val, ctx->addr + DECON_VIDOSDxB(win));
427 }
428
429 val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
430 VIDOSD_Wx_ALPHA_B_F(0xff);
431 writel(val, ctx->addr + DECON_VIDOSDxC(win));
432
433 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
434 VIDOSD_Wx_ALPHA_B_F(0x0);
435 writel(val, ctx->addr + DECON_VIDOSDxD(win));
436
437 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
438
439 val = dma_addr + pitch * state->src.h;
440 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
441
442 if (!(ctx->out_type & IFTYPE_HDMI))
443 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
444 | BIT_VAL(state->crtc.w * cpp, 13, 0);
445 else
446 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
447 | BIT_VAL(state->crtc.w * cpp, 14, 0);
448 writel(val, ctx->addr + DECON_VIDW0xADD2(win));
449
450 decon_win_set_pixfmt(ctx, win, fb);
451
452 /* window enable */
453 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
454}
455
456static void decon_disable_plane(struct exynos_drm_crtc *crtc,
457 struct exynos_drm_plane *plane)
458{
459 struct decon_context *ctx = crtc->ctx;
460 unsigned int win = plane->index;
461
462 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
463}
464
465static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
466{
467 struct decon_context *ctx = crtc->ctx;
468 unsigned long flags;
469
470 spin_lock_irqsave(&ctx->vblank_lock, flags);
471
472 decon_shadow_protect(ctx, false);
473
474 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
475
476 ctx->frame_id = decon_get_frame_count(ctx, true);
477
478 exynos_crtc_handle_event(crtc);
479
480 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
481}
482
483static void decon_swreset(struct decon_context *ctx)
484{
485 unsigned long flags;
486 u32 val;
487 int ret;
488
489 writel(0, ctx->addr + DECON_VIDCON0);
490 readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
491 ~val & VIDCON0_STOP_STATUS, 12, 20000);
492
493 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
494 ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
495 ~val & VIDCON0_SWRESET, 12, 20000);
496
497 WARN(ret < 0, "failed to software reset DECON\n");
498
499 spin_lock_irqsave(&ctx->vblank_lock, flags);
500 ctx->frame_id = 0;
501 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
502
503 if (!(ctx->out_type & IFTYPE_HDMI))
504 return;
505
506 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
507 decon_set_bits(ctx, DECON_CMU,
508 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
509 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
510 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
511 ctx->addr + DECON_CRCCTRL);
512}
513
514static void decon_atomic_enable(struct exynos_drm_crtc *crtc)
515{
516 struct decon_context *ctx = crtc->ctx;
517
518 pm_runtime_get_sync(ctx->dev);
519
520 exynos_drm_pipe_clk_enable(crtc, true);
521
522 decon_swreset(ctx);
523
524 decon_commit(ctx->crtc);
525}
526
527static void decon_atomic_disable(struct exynos_drm_crtc *crtc)
528{
529 struct decon_context *ctx = crtc->ctx;
530 int i;
531
532 if (!(ctx->out_type & I80_HW_TRG))
533 synchronize_irq(ctx->te_irq);
534 synchronize_irq(ctx->irq);
535
536 /*
537 * We need to make sure that all windows are disabled before we
538 * suspend that connector. Otherwise we might try to scan from
539 * a destroyed buffer later.
540 */
541 for (i = ctx->first_win; i < WINDOWS_NR; i++)
542 decon_disable_plane(crtc, &ctx->planes[i]);
543
544 decon_swreset(ctx);
545
546 exynos_drm_pipe_clk_enable(crtc, false);
547
548 pm_runtime_put_sync(ctx->dev);
549}
550
551static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
552{
553 struct decon_context *ctx = dev_id;
554
555 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
556
557 return IRQ_HANDLED;
558}
559
560static void decon_clear_channels(struct exynos_drm_crtc *crtc)
561{
562 struct decon_context *ctx = crtc->ctx;
563 int win, i, ret;
564
565 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
566 ret = clk_prepare_enable(ctx->clks[i]);
567 if (ret < 0)
568 goto err;
569 }
570
571 decon_shadow_protect(ctx, true);
572 for (win = 0; win < WINDOWS_NR; win++)
573 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
574 decon_shadow_protect(ctx, false);
575
576 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
577
578 /* TODO: wait for possible vsync */
579 msleep(50);
580
581err:
582 while (--i >= 0)
583 clk_disable_unprepare(ctx->clks[i]);
584}
585
586static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
587 const struct drm_display_mode *mode)
588{
589 struct decon_context *ctx = crtc->ctx;
590
591 ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
592
593 if (ctx->irq)
594 return MODE_OK;
595
596 dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
597 crtc->i80_mode ? "command" : "video");
598
599 return MODE_BAD;
600}
601
602static const struct exynos_drm_crtc_ops decon_crtc_ops = {
603 .atomic_enable = decon_atomic_enable,
604 .atomic_disable = decon_atomic_disable,
605 .enable_vblank = decon_enable_vblank,
606 .disable_vblank = decon_disable_vblank,
607 .atomic_begin = decon_atomic_begin,
608 .update_plane = decon_update_plane,
609 .disable_plane = decon_disable_plane,
610 .mode_valid = decon_mode_valid,
611 .atomic_flush = decon_atomic_flush,
612};
613
614static int decon_bind(struct device *dev, struct device *master, void *data)
615{
616 struct decon_context *ctx = dev_get_drvdata(dev);
617 struct drm_device *drm_dev = data;
618 struct exynos_drm_plane *exynos_plane;
619 enum exynos_drm_output_type out_type;
620 unsigned int win;
621 int ret;
622
623 ctx->drm_dev = drm_dev;
624
625 for (win = ctx->first_win; win < WINDOWS_NR; win++) {
626 ctx->configs[win].pixel_formats = decon_formats;
627 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
628 ctx->configs[win].zpos = win - ctx->first_win;
629 ctx->configs[win].type = decon_win_types[win];
630 ctx->configs[win].capabilities = capabilities[win];
631
632 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
633 &ctx->configs[win]);
634 if (ret)
635 return ret;
636 }
637
638 exynos_plane = &ctx->planes[PRIMARY_WIN];
639 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
640 : EXYNOS_DISPLAY_TYPE_LCD;
641 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
642 out_type, &decon_crtc_ops, ctx);
643 if (IS_ERR(ctx->crtc))
644 return PTR_ERR(ctx->crtc);
645
646 decon_clear_channels(ctx->crtc);
647
648 return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
649}
650
651static void decon_unbind(struct device *dev, struct device *master, void *data)
652{
653 struct decon_context *ctx = dev_get_drvdata(dev);
654
655 decon_atomic_disable(ctx->crtc);
656
657 /* detach this sub driver from iommu mapping if supported. */
658 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
659}
660
661static const struct component_ops decon_component_ops = {
662 .bind = decon_bind,
663 .unbind = decon_unbind,
664};
665
666static void decon_handle_vblank(struct decon_context *ctx)
667{
668 u32 frm;
669
670 spin_lock(&ctx->vblank_lock);
671
672 frm = decon_get_frame_count(ctx, true);
673
674 if (frm != ctx->frame_id) {
675 /* handle only if incremented, take care of wrap-around */
676 if ((s32)(frm - ctx->frame_id) > 0)
677 drm_crtc_handle_vblank(&ctx->crtc->base);
678 ctx->frame_id = frm;
679 }
680
681 spin_unlock(&ctx->vblank_lock);
682}
683
684static irqreturn_t decon_irq_handler(int irq, void *dev_id)
685{
686 struct decon_context *ctx = dev_id;
687 u32 val;
688
689 val = readl(ctx->addr + DECON_VIDINTCON1);
690 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
691
692 if (val) {
693 writel(val, ctx->addr + DECON_VIDINTCON1);
694 if (ctx->out_type & IFTYPE_HDMI) {
695 val = readl(ctx->addr + DECON_VIDOUTCON0);
696 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
697 if (val ==
698 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
699 return IRQ_HANDLED;
700 }
701 decon_handle_vblank(ctx);
702 }
703
704 return IRQ_HANDLED;
705}
706
707#ifdef CONFIG_PM
708static int exynos5433_decon_suspend(struct device *dev)
709{
710 struct decon_context *ctx = dev_get_drvdata(dev);
711 int i = ARRAY_SIZE(decon_clks_name);
712
713 while (--i >= 0)
714 clk_disable_unprepare(ctx->clks[i]);
715
716 return 0;
717}
718
719static int exynos5433_decon_resume(struct device *dev)
720{
721 struct decon_context *ctx = dev_get_drvdata(dev);
722 int i, ret;
723
724 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
725 ret = clk_prepare_enable(ctx->clks[i]);
726 if (ret < 0)
727 goto err;
728 }
729
730 return 0;
731
732err:
733 while (--i >= 0)
734 clk_disable_unprepare(ctx->clks[i]);
735
736 return ret;
737}
738#endif
739
740static const struct dev_pm_ops exynos5433_decon_pm_ops = {
741 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
742 NULL)
743 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
744 pm_runtime_force_resume)
745};
746
747static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
748 {
749 .compatible = "samsung,exynos5433-decon",
750 .data = (void *)I80_HW_TRG
751 },
752 {
753 .compatible = "samsung,exynos5433-decon-tv",
754 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
755 },
756 {},
757};
758MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
759
760static int decon_conf_irq(struct decon_context *ctx, const char *name,
761 irq_handler_t handler, unsigned long int flags)
762{
763 struct platform_device *pdev = to_platform_device(ctx->dev);
764 int ret, irq = platform_get_irq_byname(pdev, name);
765
766 if (irq < 0) {
767 switch (irq) {
768 case -EPROBE_DEFER:
769 return irq;
770 case -ENODATA:
771 case -ENXIO:
772 return 0;
773 default:
774 dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
775 return irq;
776 }
777 }
778 irq_set_status_flags(irq, IRQ_NOAUTOEN);
779 ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx);
780 if (ret < 0) {
781 dev_err(ctx->dev, "IRQ %s request failed\n", name);
782 return ret;
783 }
784
785 return irq;
786}
787
788static int exynos5433_decon_probe(struct platform_device *pdev)
789{
790 struct device *dev = &pdev->dev;
791 struct decon_context *ctx;
792 struct resource *res;
793 int ret;
794 int i;
795
796 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
797 if (!ctx)
798 return -ENOMEM;
799
800 ctx->dev = dev;
801 ctx->out_type = (unsigned long)of_device_get_match_data(dev);
802 spin_lock_init(&ctx->vblank_lock);
803
804 if (ctx->out_type & IFTYPE_HDMI)
805 ctx->first_win = 1;
806
807 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
808 struct clk *clk;
809
810 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
811 if (IS_ERR(clk))
812 return PTR_ERR(clk);
813
814 ctx->clks[i] = clk;
815 }
816
817 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 ctx->addr = devm_ioremap_resource(dev, res);
819 if (IS_ERR(ctx->addr)) {
820 dev_err(dev, "ioremap failed\n");
821 return PTR_ERR(ctx->addr);
822 }
823
824 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
825 if (ret < 0)
826 return ret;
827 ctx->irq_vsync = ret;
828
829 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
830 if (ret < 0)
831 return ret;
832 ctx->irq_lcd_sys = ret;
833
834 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
835 IRQF_TRIGGER_RISING);
836 if (ret < 0)
837 return ret;
838 if (ret) {
839 ctx->te_irq = ret;
840 ctx->out_type &= ~I80_HW_TRG;
841 }
842
843 if (ctx->out_type & I80_HW_TRG) {
844 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
845 "samsung,disp-sysreg");
846 if (IS_ERR(ctx->sysreg)) {
847 dev_err(dev, "failed to get system register\n");
848 return PTR_ERR(ctx->sysreg);
849 }
850 }
851
852 platform_set_drvdata(pdev, ctx);
853
854 pm_runtime_enable(dev);
855
856 ret = component_add(dev, &decon_component_ops);
857 if (ret)
858 goto err_disable_pm_runtime;
859
860 return 0;
861
862err_disable_pm_runtime:
863 pm_runtime_disable(dev);
864
865 return ret;
866}
867
868static int exynos5433_decon_remove(struct platform_device *pdev)
869{
870 pm_runtime_disable(&pdev->dev);
871
872 component_del(&pdev->dev, &decon_component_ops);
873
874 return 0;
875}
876
877struct platform_driver exynos5433_decon_driver = {
878 .probe = exynos5433_decon_probe,
879 .remove = exynos5433_decon_remove,
880 .driver = {
881 .name = "exynos5433-decon",
882 .pm = &exynos5433_decon_pm_ops,
883 .of_match_table = exynos5433_decon_driver_dt_match,
884 },
885};