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1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
7#include <linux/of.h>
8#include <linux/seq_file.h>
9#include <linux/smp.h>
10#include <linux/ftrace.h>
11#include <linux/delay.h>
12#include <linux/export.h>
13
14#include <asm/apic.h>
15#include <asm/io_apic.h>
16#include <asm/irq.h>
17#include <asm/idle.h>
18#include <asm/mce.h>
19#include <asm/hw_irq.h>
20#include <asm/desc.h>
21
22#define CREATE_TRACE_POINTS
23#include <asm/trace/irq_vectors.h>
24
25DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
26EXPORT_PER_CPU_SYMBOL(irq_stat);
27
28DEFINE_PER_CPU(struct pt_regs *, irq_regs);
29EXPORT_PER_CPU_SYMBOL(irq_regs);
30
31atomic_t irq_err_count;
32
33/* Function pointer for generic interrupt vector handling */
34void (*x86_platform_ipi_callback)(void) = NULL;
35
36/*
37 * 'what should we do if we get a hw irq event on an illegal vector'.
38 * each architecture has to answer this themselves.
39 */
40void ack_bad_irq(unsigned int irq)
41{
42 if (printk_ratelimit())
43 pr_err("unexpected IRQ trap at vector %02x\n", irq);
44
45 /*
46 * Currently unexpected vectors happen only on SMP and APIC.
47 * We _must_ ack these because every local APIC has only N
48 * irq slots per priority level, and a 'hanging, unacked' IRQ
49 * holds up an irq slot - in excessive cases (when multiple
50 * unexpected vectors occur) that might lock up the APIC
51 * completely.
52 * But only ack when the APIC is enabled -AK
53 */
54 ack_APIC_irq();
55}
56
57#define irq_stats(x) (&per_cpu(irq_stat, x))
58/*
59 * /proc/interrupts printing for arch specific interrupts
60 */
61int arch_show_interrupts(struct seq_file *p, int prec)
62{
63 int j;
64
65 seq_printf(p, "%*s: ", prec, "NMI");
66 for_each_online_cpu(j)
67 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
68 seq_puts(p, " Non-maskable interrupts\n");
69#ifdef CONFIG_X86_LOCAL_APIC
70 seq_printf(p, "%*s: ", prec, "LOC");
71 for_each_online_cpu(j)
72 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
73 seq_puts(p, " Local timer interrupts\n");
74
75 seq_printf(p, "%*s: ", prec, "SPU");
76 for_each_online_cpu(j)
77 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
78 seq_puts(p, " Spurious interrupts\n");
79 seq_printf(p, "%*s: ", prec, "PMI");
80 for_each_online_cpu(j)
81 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
82 seq_puts(p, " Performance monitoring interrupts\n");
83 seq_printf(p, "%*s: ", prec, "IWI");
84 for_each_online_cpu(j)
85 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
86 seq_puts(p, " IRQ work interrupts\n");
87 seq_printf(p, "%*s: ", prec, "RTR");
88 for_each_online_cpu(j)
89 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
90 seq_puts(p, " APIC ICR read retries\n");
91#endif
92 if (x86_platform_ipi_callback) {
93 seq_printf(p, "%*s: ", prec, "PLT");
94 for_each_online_cpu(j)
95 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
96 seq_puts(p, " Platform interrupts\n");
97 }
98#ifdef CONFIG_SMP
99 seq_printf(p, "%*s: ", prec, "RES");
100 for_each_online_cpu(j)
101 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
102 seq_puts(p, " Rescheduling interrupts\n");
103 seq_printf(p, "%*s: ", prec, "CAL");
104 for_each_online_cpu(j)
105 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
106 irq_stats(j)->irq_tlb_count);
107 seq_puts(p, " Function call interrupts\n");
108 seq_printf(p, "%*s: ", prec, "TLB");
109 for_each_online_cpu(j)
110 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
111 seq_puts(p, " TLB shootdowns\n");
112#endif
113#ifdef CONFIG_X86_THERMAL_VECTOR
114 seq_printf(p, "%*s: ", prec, "TRM");
115 for_each_online_cpu(j)
116 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
117 seq_puts(p, " Thermal event interrupts\n");
118#endif
119#ifdef CONFIG_X86_MCE_THRESHOLD
120 seq_printf(p, "%*s: ", prec, "THR");
121 for_each_online_cpu(j)
122 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
123 seq_puts(p, " Threshold APIC interrupts\n");
124#endif
125#ifdef CONFIG_X86_MCE_AMD
126 seq_printf(p, "%*s: ", prec, "DFR");
127 for_each_online_cpu(j)
128 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
129 seq_puts(p, " Deferred Error APIC interrupts\n");
130#endif
131#ifdef CONFIG_X86_MCE
132 seq_printf(p, "%*s: ", prec, "MCE");
133 for_each_online_cpu(j)
134 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
135 seq_puts(p, " Machine check exceptions\n");
136 seq_printf(p, "%*s: ", prec, "MCP");
137 for_each_online_cpu(j)
138 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
139 seq_puts(p, " Machine check polls\n");
140#endif
141#if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
142 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) {
143 seq_printf(p, "%*s: ", prec, "HYP");
144 for_each_online_cpu(j)
145 seq_printf(p, "%10u ",
146 irq_stats(j)->irq_hv_callback_count);
147 seq_puts(p, " Hypervisor callback interrupts\n");
148 }
149#endif
150 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
151#if defined(CONFIG_X86_IO_APIC)
152 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
153#endif
154#ifdef CONFIG_HAVE_KVM
155 seq_printf(p, "%*s: ", prec, "PIN");
156 for_each_online_cpu(j)
157 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
158 seq_puts(p, " Posted-interrupt notification event\n");
159
160 seq_printf(p, "%*s: ", prec, "PIW");
161 for_each_online_cpu(j)
162 seq_printf(p, "%10u ",
163 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
164 seq_puts(p, " Posted-interrupt wakeup event\n");
165#endif
166 return 0;
167}
168
169/*
170 * /proc/stat helpers
171 */
172u64 arch_irq_stat_cpu(unsigned int cpu)
173{
174 u64 sum = irq_stats(cpu)->__nmi_count;
175
176#ifdef CONFIG_X86_LOCAL_APIC
177 sum += irq_stats(cpu)->apic_timer_irqs;
178 sum += irq_stats(cpu)->irq_spurious_count;
179 sum += irq_stats(cpu)->apic_perf_irqs;
180 sum += irq_stats(cpu)->apic_irq_work_irqs;
181 sum += irq_stats(cpu)->icr_read_retry_count;
182#endif
183 if (x86_platform_ipi_callback)
184 sum += irq_stats(cpu)->x86_platform_ipis;
185#ifdef CONFIG_SMP
186 sum += irq_stats(cpu)->irq_resched_count;
187 sum += irq_stats(cpu)->irq_call_count;
188#endif
189#ifdef CONFIG_X86_THERMAL_VECTOR
190 sum += irq_stats(cpu)->irq_thermal_count;
191#endif
192#ifdef CONFIG_X86_MCE_THRESHOLD
193 sum += irq_stats(cpu)->irq_threshold_count;
194#endif
195#ifdef CONFIG_X86_MCE
196 sum += per_cpu(mce_exception_count, cpu);
197 sum += per_cpu(mce_poll_count, cpu);
198#endif
199 return sum;
200}
201
202u64 arch_irq_stat(void)
203{
204 u64 sum = atomic_read(&irq_err_count);
205 return sum;
206}
207
208
209/*
210 * do_IRQ handles all normal device IRQ's (the special
211 * SMP cross-CPU interrupts have their own specific
212 * handlers).
213 */
214__visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
215{
216 struct pt_regs *old_regs = set_irq_regs(regs);
217 struct irq_desc * desc;
218 /* high bit used in ret_from_ code */
219 unsigned vector = ~regs->orig_ax;
220
221 /*
222 * NB: Unlike exception entries, IRQ entries do not reliably
223 * handle context tracking in the low-level entry code. This is
224 * because syscall entries execute briefly with IRQs on before
225 * updating context tracking state, so we can take an IRQ from
226 * kernel mode with CONTEXT_USER. The low-level entry code only
227 * updates the context if we came from user mode, so we won't
228 * switch to CONTEXT_KERNEL. We'll fix that once the syscall
229 * code is cleaned up enough that we can cleanly defer enabling
230 * IRQs.
231 */
232
233 entering_irq();
234
235 /* entering_irq() tells RCU that we're not quiescent. Check it. */
236 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
237
238 desc = __this_cpu_read(vector_irq[vector]);
239
240 if (!handle_irq(desc, regs)) {
241 ack_APIC_irq();
242
243 if (desc != VECTOR_RETRIGGERED) {
244 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
245 __func__, smp_processor_id(),
246 vector);
247 } else {
248 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
249 }
250 }
251
252 exiting_irq();
253
254 set_irq_regs(old_regs);
255 return 1;
256}
257
258/*
259 * Handler for X86_PLATFORM_IPI_VECTOR.
260 */
261void __smp_x86_platform_ipi(void)
262{
263 inc_irq_stat(x86_platform_ipis);
264
265 if (x86_platform_ipi_callback)
266 x86_platform_ipi_callback();
267}
268
269__visible void smp_x86_platform_ipi(struct pt_regs *regs)
270{
271 struct pt_regs *old_regs = set_irq_regs(regs);
272
273 entering_ack_irq();
274 __smp_x86_platform_ipi();
275 exiting_irq();
276 set_irq_regs(old_regs);
277}
278
279#ifdef CONFIG_HAVE_KVM
280static void dummy_handler(void) {}
281static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
282
283void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
284{
285 if (handler)
286 kvm_posted_intr_wakeup_handler = handler;
287 else
288 kvm_posted_intr_wakeup_handler = dummy_handler;
289}
290EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
291
292/*
293 * Handler for POSTED_INTERRUPT_VECTOR.
294 */
295__visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
296{
297 struct pt_regs *old_regs = set_irq_regs(regs);
298
299 entering_ack_irq();
300 inc_irq_stat(kvm_posted_intr_ipis);
301 exiting_irq();
302 set_irq_regs(old_regs);
303}
304
305/*
306 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
307 */
308__visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
309{
310 struct pt_regs *old_regs = set_irq_regs(regs);
311
312 entering_ack_irq();
313 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
314 kvm_posted_intr_wakeup_handler();
315 exiting_irq();
316 set_irq_regs(old_regs);
317}
318#endif
319
320__visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
321{
322 struct pt_regs *old_regs = set_irq_regs(regs);
323
324 entering_ack_irq();
325 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
326 __smp_x86_platform_ipi();
327 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
328 exiting_irq();
329 set_irq_regs(old_regs);
330}
331
332EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
333
334#ifdef CONFIG_HOTPLUG_CPU
335
336/* These two declarations are only used in check_irq_vectors_for_cpu_disable()
337 * below, which is protected by stop_machine(). Putting them on the stack
338 * results in a stack frame overflow. Dynamically allocating could result in a
339 * failure so declare these two cpumasks as global.
340 */
341static struct cpumask affinity_new, online_new;
342
343/*
344 * This cpu is going to be removed and its vectors migrated to the remaining
345 * online cpus. Check to see if there are enough vectors in the remaining cpus.
346 * This function is protected by stop_machine().
347 */
348int check_irq_vectors_for_cpu_disable(void)
349{
350 unsigned int this_cpu, vector, this_count, count;
351 struct irq_desc *desc;
352 struct irq_data *data;
353 int cpu;
354
355 this_cpu = smp_processor_id();
356 cpumask_copy(&online_new, cpu_online_mask);
357 cpumask_clear_cpu(this_cpu, &online_new);
358
359 this_count = 0;
360 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
361 desc = __this_cpu_read(vector_irq[vector]);
362 if (IS_ERR_OR_NULL(desc))
363 continue;
364 /*
365 * Protect against concurrent action removal, affinity
366 * changes etc.
367 */
368 raw_spin_lock(&desc->lock);
369 data = irq_desc_get_irq_data(desc);
370 cpumask_copy(&affinity_new,
371 irq_data_get_affinity_mask(data));
372 cpumask_clear_cpu(this_cpu, &affinity_new);
373
374 /* Do not count inactive or per-cpu irqs. */
375 if (!irq_desc_has_action(desc) || irqd_is_per_cpu(data)) {
376 raw_spin_unlock(&desc->lock);
377 continue;
378 }
379
380 raw_spin_unlock(&desc->lock);
381 /*
382 * A single irq may be mapped to multiple cpu's
383 * vector_irq[] (for example IOAPIC cluster mode). In
384 * this case we have two possibilities:
385 *
386 * 1) the resulting affinity mask is empty; that is
387 * this the down'd cpu is the last cpu in the irq's
388 * affinity mask, or
389 *
390 * 2) the resulting affinity mask is no longer a
391 * subset of the online cpus but the affinity mask is
392 * not zero; that is the down'd cpu is the last online
393 * cpu in a user set affinity mask.
394 */
395 if (cpumask_empty(&affinity_new) ||
396 !cpumask_subset(&affinity_new, &online_new))
397 this_count++;
398 }
399
400 count = 0;
401 for_each_online_cpu(cpu) {
402 if (cpu == this_cpu)
403 continue;
404 /*
405 * We scan from FIRST_EXTERNAL_VECTOR to first system
406 * vector. If the vector is marked in the used vectors
407 * bitmap or an irq is assigned to it, we don't count
408 * it as available.
409 *
410 * As this is an inaccurate snapshot anyway, we can do
411 * this w/o holding vector_lock.
412 */
413 for (vector = FIRST_EXTERNAL_VECTOR;
414 vector < first_system_vector; vector++) {
415 if (!test_bit(vector, used_vectors) &&
416 IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector]))
417 count++;
418 }
419 }
420
421 if (count < this_count) {
422 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
423 this_cpu, this_count, count);
424 return -ERANGE;
425 }
426 return 0;
427}
428
429/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
430void fixup_irqs(void)
431{
432 unsigned int irq, vector;
433 static int warned;
434 struct irq_desc *desc;
435 struct irq_data *data;
436 struct irq_chip *chip;
437 int ret;
438
439 for_each_irq_desc(irq, desc) {
440 int break_affinity = 0;
441 int set_affinity = 1;
442 const struct cpumask *affinity;
443
444 if (!desc)
445 continue;
446 if (irq == 2)
447 continue;
448
449 /* interrupt's are disabled at this point */
450 raw_spin_lock(&desc->lock);
451
452 data = irq_desc_get_irq_data(desc);
453 affinity = irq_data_get_affinity_mask(data);
454 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
455 cpumask_subset(affinity, cpu_online_mask)) {
456 raw_spin_unlock(&desc->lock);
457 continue;
458 }
459
460 /*
461 * Complete the irq move. This cpu is going down and for
462 * non intr-remapping case, we can't wait till this interrupt
463 * arrives at this cpu before completing the irq move.
464 */
465 irq_force_complete_move(desc);
466
467 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
468 break_affinity = 1;
469 affinity = cpu_online_mask;
470 }
471
472 chip = irq_data_get_irq_chip(data);
473 /*
474 * The interrupt descriptor might have been cleaned up
475 * already, but it is not yet removed from the radix tree
476 */
477 if (!chip) {
478 raw_spin_unlock(&desc->lock);
479 continue;
480 }
481
482 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
483 chip->irq_mask(data);
484
485 if (chip->irq_set_affinity) {
486 ret = chip->irq_set_affinity(data, affinity, true);
487 if (ret == -ENOSPC)
488 pr_crit("IRQ %d set affinity failed because there are no available vectors. The device assigned to this IRQ is unstable.\n", irq);
489 } else {
490 if (!(warned++))
491 set_affinity = 0;
492 }
493
494 /*
495 * We unmask if the irq was not marked masked by the
496 * core code. That respects the lazy irq disable
497 * behaviour.
498 */
499 if (!irqd_can_move_in_process_context(data) &&
500 !irqd_irq_masked(data) && chip->irq_unmask)
501 chip->irq_unmask(data);
502
503 raw_spin_unlock(&desc->lock);
504
505 if (break_affinity && set_affinity)
506 pr_notice("Broke affinity for irq %i\n", irq);
507 else if (!set_affinity)
508 pr_notice("Cannot set affinity for irq %i\n", irq);
509 }
510
511 /*
512 * We can remove mdelay() and then send spuriuous interrupts to
513 * new cpu targets for all the irqs that were handled previously by
514 * this cpu. While it works, I have seen spurious interrupt messages
515 * (nothing wrong but still...).
516 *
517 * So for now, retain mdelay(1) and check the IRR and then send those
518 * interrupts to new targets as this cpu is already offlined...
519 */
520 mdelay(1);
521
522 /*
523 * We can walk the vector array of this cpu without holding
524 * vector_lock because the cpu is already marked !online, so
525 * nothing else will touch it.
526 */
527 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
528 unsigned int irr;
529
530 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
531 continue;
532
533 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
534 if (irr & (1 << (vector % 32))) {
535 desc = __this_cpu_read(vector_irq[vector]);
536
537 raw_spin_lock(&desc->lock);
538 data = irq_desc_get_irq_data(desc);
539 chip = irq_data_get_irq_chip(data);
540 if (chip->irq_retrigger) {
541 chip->irq_retrigger(data);
542 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
543 }
544 raw_spin_unlock(&desc->lock);
545 }
546 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
547 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
548 }
549}
550#endif
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Common interrupt code for 32 and 64 bit
4 */
5#include <linux/cpu.h>
6#include <linux/interrupt.h>
7#include <linux/kernel_stat.h>
8#include <linux/of.h>
9#include <linux/seq_file.h>
10#include <linux/smp.h>
11#include <linux/ftrace.h>
12#include <linux/delay.h>
13#include <linux/export.h>
14#include <linux/irq.h>
15
16#include <asm/irq_stack.h>
17#include <asm/apic.h>
18#include <asm/io_apic.h>
19#include <asm/irq.h>
20#include <asm/mce.h>
21#include <asm/hw_irq.h>
22#include <asm/desc.h>
23#include <asm/traps.h>
24
25#define CREATE_TRACE_POINTS
26#include <asm/trace/irq_vectors.h>
27
28DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
29EXPORT_PER_CPU_SYMBOL(irq_stat);
30
31atomic_t irq_err_count;
32
33/*
34 * 'what should we do if we get a hw irq event on an illegal vector'.
35 * each architecture has to answer this themselves.
36 */
37void ack_bad_irq(unsigned int irq)
38{
39 if (printk_ratelimit())
40 pr_err("unexpected IRQ trap at vector %02x\n", irq);
41
42 /*
43 * Currently unexpected vectors happen only on SMP and APIC.
44 * We _must_ ack these because every local APIC has only N
45 * irq slots per priority level, and a 'hanging, unacked' IRQ
46 * holds up an irq slot - in excessive cases (when multiple
47 * unexpected vectors occur) that might lock up the APIC
48 * completely.
49 * But only ack when the APIC is enabled -AK
50 */
51 ack_APIC_irq();
52}
53
54#define irq_stats(x) (&per_cpu(irq_stat, x))
55/*
56 * /proc/interrupts printing for arch specific interrupts
57 */
58int arch_show_interrupts(struct seq_file *p, int prec)
59{
60 int j;
61
62 seq_printf(p, "%*s: ", prec, "NMI");
63 for_each_online_cpu(j)
64 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
65 seq_puts(p, " Non-maskable interrupts\n");
66#ifdef CONFIG_X86_LOCAL_APIC
67 seq_printf(p, "%*s: ", prec, "LOC");
68 for_each_online_cpu(j)
69 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
70 seq_puts(p, " Local timer interrupts\n");
71
72 seq_printf(p, "%*s: ", prec, "SPU");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
75 seq_puts(p, " Spurious interrupts\n");
76 seq_printf(p, "%*s: ", prec, "PMI");
77 for_each_online_cpu(j)
78 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
79 seq_puts(p, " Performance monitoring interrupts\n");
80 seq_printf(p, "%*s: ", prec, "IWI");
81 for_each_online_cpu(j)
82 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
83 seq_puts(p, " IRQ work interrupts\n");
84 seq_printf(p, "%*s: ", prec, "RTR");
85 for_each_online_cpu(j)
86 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
87 seq_puts(p, " APIC ICR read retries\n");
88 if (x86_platform_ipi_callback) {
89 seq_printf(p, "%*s: ", prec, "PLT");
90 for_each_online_cpu(j)
91 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
92 seq_puts(p, " Platform interrupts\n");
93 }
94#endif
95#ifdef CONFIG_SMP
96 seq_printf(p, "%*s: ", prec, "RES");
97 for_each_online_cpu(j)
98 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
99 seq_puts(p, " Rescheduling interrupts\n");
100 seq_printf(p, "%*s: ", prec, "CAL");
101 for_each_online_cpu(j)
102 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
103 seq_puts(p, " Function call interrupts\n");
104 seq_printf(p, "%*s: ", prec, "TLB");
105 for_each_online_cpu(j)
106 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
107 seq_puts(p, " TLB shootdowns\n");
108#endif
109#ifdef CONFIG_X86_THERMAL_VECTOR
110 seq_printf(p, "%*s: ", prec, "TRM");
111 for_each_online_cpu(j)
112 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
113 seq_puts(p, " Thermal event interrupts\n");
114#endif
115#ifdef CONFIG_X86_MCE_THRESHOLD
116 seq_printf(p, "%*s: ", prec, "THR");
117 for_each_online_cpu(j)
118 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
119 seq_puts(p, " Threshold APIC interrupts\n");
120#endif
121#ifdef CONFIG_X86_MCE_AMD
122 seq_printf(p, "%*s: ", prec, "DFR");
123 for_each_online_cpu(j)
124 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
125 seq_puts(p, " Deferred Error APIC interrupts\n");
126#endif
127#ifdef CONFIG_X86_MCE
128 seq_printf(p, "%*s: ", prec, "MCE");
129 for_each_online_cpu(j)
130 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
131 seq_puts(p, " Machine check exceptions\n");
132 seq_printf(p, "%*s: ", prec, "MCP");
133 for_each_online_cpu(j)
134 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
135 seq_puts(p, " Machine check polls\n");
136#endif
137#ifdef CONFIG_X86_HV_CALLBACK_VECTOR
138 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, system_vectors)) {
139 seq_printf(p, "%*s: ", prec, "HYP");
140 for_each_online_cpu(j)
141 seq_printf(p, "%10u ",
142 irq_stats(j)->irq_hv_callback_count);
143 seq_puts(p, " Hypervisor callback interrupts\n");
144 }
145#endif
146#if IS_ENABLED(CONFIG_HYPERV)
147 if (test_bit(HYPERV_REENLIGHTENMENT_VECTOR, system_vectors)) {
148 seq_printf(p, "%*s: ", prec, "HRE");
149 for_each_online_cpu(j)
150 seq_printf(p, "%10u ",
151 irq_stats(j)->irq_hv_reenlightenment_count);
152 seq_puts(p, " Hyper-V reenlightenment interrupts\n");
153 }
154 if (test_bit(HYPERV_STIMER0_VECTOR, system_vectors)) {
155 seq_printf(p, "%*s: ", prec, "HVS");
156 for_each_online_cpu(j)
157 seq_printf(p, "%10u ",
158 irq_stats(j)->hyperv_stimer0_count);
159 seq_puts(p, " Hyper-V stimer0 interrupts\n");
160 }
161#endif
162 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
163#if defined(CONFIG_X86_IO_APIC)
164 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
165#endif
166#ifdef CONFIG_HAVE_KVM
167 seq_printf(p, "%*s: ", prec, "PIN");
168 for_each_online_cpu(j)
169 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
170 seq_puts(p, " Posted-interrupt notification event\n");
171
172 seq_printf(p, "%*s: ", prec, "NPI");
173 for_each_online_cpu(j)
174 seq_printf(p, "%10u ",
175 irq_stats(j)->kvm_posted_intr_nested_ipis);
176 seq_puts(p, " Nested posted-interrupt event\n");
177
178 seq_printf(p, "%*s: ", prec, "PIW");
179 for_each_online_cpu(j)
180 seq_printf(p, "%10u ",
181 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
182 seq_puts(p, " Posted-interrupt wakeup event\n");
183#endif
184 return 0;
185}
186
187/*
188 * /proc/stat helpers
189 */
190u64 arch_irq_stat_cpu(unsigned int cpu)
191{
192 u64 sum = irq_stats(cpu)->__nmi_count;
193
194#ifdef CONFIG_X86_LOCAL_APIC
195 sum += irq_stats(cpu)->apic_timer_irqs;
196 sum += irq_stats(cpu)->irq_spurious_count;
197 sum += irq_stats(cpu)->apic_perf_irqs;
198 sum += irq_stats(cpu)->apic_irq_work_irqs;
199 sum += irq_stats(cpu)->icr_read_retry_count;
200 if (x86_platform_ipi_callback)
201 sum += irq_stats(cpu)->x86_platform_ipis;
202#endif
203#ifdef CONFIG_SMP
204 sum += irq_stats(cpu)->irq_resched_count;
205 sum += irq_stats(cpu)->irq_call_count;
206#endif
207#ifdef CONFIG_X86_THERMAL_VECTOR
208 sum += irq_stats(cpu)->irq_thermal_count;
209#endif
210#ifdef CONFIG_X86_MCE_THRESHOLD
211 sum += irq_stats(cpu)->irq_threshold_count;
212#endif
213#ifdef CONFIG_X86_MCE
214 sum += per_cpu(mce_exception_count, cpu);
215 sum += per_cpu(mce_poll_count, cpu);
216#endif
217 return sum;
218}
219
220u64 arch_irq_stat(void)
221{
222 u64 sum = atomic_read(&irq_err_count);
223 return sum;
224}
225
226static __always_inline void handle_irq(struct irq_desc *desc,
227 struct pt_regs *regs)
228{
229 if (IS_ENABLED(CONFIG_X86_64))
230 run_irq_on_irqstack_cond(desc->handle_irq, desc, regs);
231 else
232 __handle_irq(desc, regs);
233}
234
235/*
236 * common_interrupt() handles all normal device IRQ's (the special SMP
237 * cross-CPU interrupts have their own entry points).
238 */
239DEFINE_IDTENTRY_IRQ(common_interrupt)
240{
241 struct pt_regs *old_regs = set_irq_regs(regs);
242 struct irq_desc *desc;
243
244 /* entry code tells RCU that we're not quiescent. Check it. */
245 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
246
247 desc = __this_cpu_read(vector_irq[vector]);
248 if (likely(!IS_ERR_OR_NULL(desc))) {
249 handle_irq(desc, regs);
250 } else {
251 ack_APIC_irq();
252
253 if (desc == VECTOR_UNUSED) {
254 pr_emerg_ratelimited("%s: %d.%u No irq handler for vector\n",
255 __func__, smp_processor_id(),
256 vector);
257 } else {
258 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
259 }
260 }
261
262 set_irq_regs(old_regs);
263}
264
265#ifdef CONFIG_X86_LOCAL_APIC
266/* Function pointer for generic interrupt vector handling */
267void (*x86_platform_ipi_callback)(void) = NULL;
268/*
269 * Handler for X86_PLATFORM_IPI_VECTOR.
270 */
271DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi)
272{
273 struct pt_regs *old_regs = set_irq_regs(regs);
274
275 ack_APIC_irq();
276 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
277 inc_irq_stat(x86_platform_ipis);
278 if (x86_platform_ipi_callback)
279 x86_platform_ipi_callback();
280 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
281 set_irq_regs(old_regs);
282}
283#endif
284
285#ifdef CONFIG_HAVE_KVM
286static void dummy_handler(void) {}
287static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
288
289void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
290{
291 if (handler)
292 kvm_posted_intr_wakeup_handler = handler;
293 else
294 kvm_posted_intr_wakeup_handler = dummy_handler;
295}
296EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
297
298/*
299 * Handler for POSTED_INTERRUPT_VECTOR.
300 */
301DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi)
302{
303 ack_APIC_irq();
304 inc_irq_stat(kvm_posted_intr_ipis);
305}
306
307/*
308 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
309 */
310DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi)
311{
312 ack_APIC_irq();
313 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
314 kvm_posted_intr_wakeup_handler();
315}
316
317/*
318 * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
319 */
320DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi)
321{
322 ack_APIC_irq();
323 inc_irq_stat(kvm_posted_intr_nested_ipis);
324}
325#endif
326
327
328#ifdef CONFIG_HOTPLUG_CPU
329/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
330void fixup_irqs(void)
331{
332 unsigned int irr, vector;
333 struct irq_desc *desc;
334 struct irq_data *data;
335 struct irq_chip *chip;
336
337 irq_migrate_all_off_this_cpu();
338
339 /*
340 * We can remove mdelay() and then send spuriuous interrupts to
341 * new cpu targets for all the irqs that were handled previously by
342 * this cpu. While it works, I have seen spurious interrupt messages
343 * (nothing wrong but still...).
344 *
345 * So for now, retain mdelay(1) and check the IRR and then send those
346 * interrupts to new targets as this cpu is already offlined...
347 */
348 mdelay(1);
349
350 /*
351 * We can walk the vector array of this cpu without holding
352 * vector_lock because the cpu is already marked !online, so
353 * nothing else will touch it.
354 */
355 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
356 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
357 continue;
358
359 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
360 if (irr & (1 << (vector % 32))) {
361 desc = __this_cpu_read(vector_irq[vector]);
362
363 raw_spin_lock(&desc->lock);
364 data = irq_desc_get_irq_data(desc);
365 chip = irq_data_get_irq_chip(data);
366 if (chip->irq_retrigger) {
367 chip->irq_retrigger(data);
368 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
369 }
370 raw_spin_unlock(&desc->lock);
371 }
372 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
373 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
374 }
375}
376#endif