1#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H
  2#define DT_BINDINGS_MEMORY_TEGRA186_MC_H
  3
  4/* special clients */
  5#define TEGRA186_SID_INVALID		0x00
  6#define TEGRA186_SID_PASSTHROUGH	0x7f
  7
  8/* host1x clients */
  9#define TEGRA186_SID_HOST1X		0x01
 10#define TEGRA186_SID_CSI		0x02
 11#define TEGRA186_SID_VIC		0x03
 12#define TEGRA186_SID_VI			0x04
 13#define TEGRA186_SID_ISP		0x05
 14#define TEGRA186_SID_NVDEC		0x06
 15#define TEGRA186_SID_NVENC		0x07
 16#define TEGRA186_SID_NVJPG		0x08
 17#define TEGRA186_SID_NVDISPLAY		0x09
 18#define TEGRA186_SID_TSEC		0x0a
 19#define TEGRA186_SID_TSECB		0x0b
 20#define TEGRA186_SID_SE			0x0c
 21#define TEGRA186_SID_SE1		0x0d
 22#define TEGRA186_SID_SE2		0x0e
 23#define TEGRA186_SID_SE3		0x0f
 24
 25/* GPU clients */
 26#define TEGRA186_SID_GPU		0x10
 27
 28/* other SoC clients */
 29#define TEGRA186_SID_AFI		0x11
 30#define TEGRA186_SID_HDA		0x12
 31#define TEGRA186_SID_ETR		0x13
 32#define TEGRA186_SID_EQOS		0x14
 33#define TEGRA186_SID_UFSHC		0x15
 34#define TEGRA186_SID_AON		0x16
 35#define TEGRA186_SID_SDMMC4		0x17
 36#define TEGRA186_SID_SDMMC3		0x18
 37#define TEGRA186_SID_SDMMC2		0x19
 38#define TEGRA186_SID_SDMMC1		0x1a
 39#define TEGRA186_SID_XUSB_HOST		0x1b
 40#define TEGRA186_SID_XUSB_DEV		0x1c
 41#define TEGRA186_SID_SATA		0x1d
 42#define TEGRA186_SID_APE		0x1e
 43#define TEGRA186_SID_SCE		0x1f
 44
 45/* GPC DMA clients */
 46#define TEGRA186_SID_GPCDMA_0		0x20
 47#define TEGRA186_SID_GPCDMA_1		0x21
 48#define TEGRA186_SID_GPCDMA_2		0x22
 49#define TEGRA186_SID_GPCDMA_3		0x23
 50#define TEGRA186_SID_GPCDMA_4		0x24
 51#define TEGRA186_SID_GPCDMA_5		0x25
 52#define TEGRA186_SID_GPCDMA_6		0x26
 53#define TEGRA186_SID_GPCDMA_7		0x27
 54
 55/* APE DMA clients */
 56#define TEGRA186_SID_APE_1		0x28
 57#define TEGRA186_SID_APE_2		0x29
 58
 59/* camera RTCPU */
 60#define TEGRA186_SID_RCE		0x2a
 61
 62/* camera RTCPU on host1x address space */
 63#define TEGRA186_SID_RCE_1X		0x2b
 64
 65/* APE DMA clients */
 66#define TEGRA186_SID_APE_3		0x2c
 67
 68/* camera RTCPU running on APE */
 69#define TEGRA186_SID_APE_CAM		0x2d
 70#define TEGRA186_SID_APE_CAM_1X		0x2e
 71
 72/*
 73 * The BPMP has its SID value hardcoded in the firmware. Changing it requires
 74 * considerable effort.
 75 */
 76#define TEGRA186_SID_BPMP		0x32
 77
 78/* for SMMU tests */
 79#define TEGRA186_SID_SMMU_TEST		0x33
 80
 81/* host1x virtualization channels */
 82#define TEGRA186_SID_HOST1X_CTX0	0x38
 83#define TEGRA186_SID_HOST1X_CTX1	0x39
 84#define TEGRA186_SID_HOST1X_CTX2	0x3a
 85#define TEGRA186_SID_HOST1X_CTX3	0x3b
 86#define TEGRA186_SID_HOST1X_CTX4	0x3c
 87#define TEGRA186_SID_HOST1X_CTX5	0x3d
 88#define TEGRA186_SID_HOST1X_CTX6	0x3e
 89#define TEGRA186_SID_HOST1X_CTX7	0x3f
 90
 91/* host1x command buffers */
 92#define TEGRA186_SID_HOST1X_VM0		0x40
 93#define TEGRA186_SID_HOST1X_VM1		0x41
 94#define TEGRA186_SID_HOST1X_VM2		0x42
 95#define TEGRA186_SID_HOST1X_VM3		0x43
 96#define TEGRA186_SID_HOST1X_VM4		0x44
 97#define TEGRA186_SID_HOST1X_VM5		0x45
 98#define TEGRA186_SID_HOST1X_VM6		0x46
 99#define TEGRA186_SID_HOST1X_VM7		0x47
100
101/* SE data buffers */
102#define TEGRA186_SID_SE_VM0		0x48
103#define TEGRA186_SID_SE_VM1		0x49
104#define TEGRA186_SID_SE_VM2		0x4a
105#define TEGRA186_SID_SE_VM3		0x4b
106#define TEGRA186_SID_SE_VM4		0x4c
107#define TEGRA186_SID_SE_VM5		0x4d
108#define TEGRA186_SID_SE_VM6		0x4e
109#define TEGRA186_SID_SE_VM7		0x4f
110
111#endif