1#ifndef __DTS_MARVELL_PXA910_CLOCK_H
 2#define __DTS_MARVELL_PXA910_CLOCK_H
 3
 4/* fixed clocks and plls */
 5#define PXA910_CLK_CLK32		1
 6#define PXA910_CLK_VCTCXO		2
 7#define PXA910_CLK_PLL1			3
 8#define PXA910_CLK_PLL1_2		8
 9#define PXA910_CLK_PLL1_4		9
10#define PXA910_CLK_PLL1_8		10
11#define PXA910_CLK_PLL1_16		11
12#define PXA910_CLK_PLL1_6		12
13#define PXA910_CLK_PLL1_12		13
14#define PXA910_CLK_PLL1_24		14
15#define PXA910_CLK_PLL1_48		15
16#define PXA910_CLK_PLL1_96		16
17#define PXA910_CLK_PLL1_13		17
18#define PXA910_CLK_PLL1_13_1_5		18
19#define PXA910_CLK_PLL1_2_1_5		19
20#define PXA910_CLK_PLL1_3_16		20
21#define PXA910_CLK_PLL1_192		21
22#define PXA910_CLK_UART_PLL		27
23#define PXA910_CLK_USB_PLL		28
24
25/* apb periphrals */
26#define PXA910_CLK_TWSI0		60
27#define PXA910_CLK_TWSI1		61
28#define PXA910_CLK_TWSI2		62
29#define PXA910_CLK_TWSI3		63
30#define PXA910_CLK_GPIO			64
31#define PXA910_CLK_KPC			65
32#define PXA910_CLK_RTC			66
33#define PXA910_CLK_PWM0			67
34#define PXA910_CLK_PWM1			68
35#define PXA910_CLK_PWM2			69
36#define PXA910_CLK_PWM3			70
37#define PXA910_CLK_UART0		71
38#define PXA910_CLK_UART1		72
39#define PXA910_CLK_UART2		73
40#define PXA910_CLK_SSP0			74
41#define PXA910_CLK_SSP1			75
42#define PXA910_CLK_TIMER0		76
43#define PXA910_CLK_TIMER1		77
44
45/* axi periphrals */
46#define PXA910_CLK_DFC			100
47#define PXA910_CLK_SDH0			101
48#define PXA910_CLK_SDH1			102
49#define PXA910_CLK_SDH2			103
50#define PXA910_CLK_USB			104
51#define PXA910_CLK_SPH			105
52#define PXA910_CLK_DISP0		106
53#define PXA910_CLK_CCIC0		107
54#define PXA910_CLK_CCIC0_PHY		108
55#define PXA910_CLK_CCIC0_SPHY		109
56
57#define PXA910_NR_CLKS			200
58#endif

 1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __DTS_MARVELL_PXA910_CLOCK_H
 3#define __DTS_MARVELL_PXA910_CLOCK_H
 4
 5/* fixed clocks and plls */
 6#define PXA910_CLK_CLK32		1
 7#define PXA910_CLK_VCTCXO		2
 8#define PXA910_CLK_PLL1			3
 9#define PXA910_CLK_PLL1_2		8
10#define PXA910_CLK_PLL1_4		9
11#define PXA910_CLK_PLL1_8		10
12#define PXA910_CLK_PLL1_16		11
13#define PXA910_CLK_PLL1_6		12
14#define PXA910_CLK_PLL1_12		13
15#define PXA910_CLK_PLL1_24		14
16#define PXA910_CLK_PLL1_48		15
17#define PXA910_CLK_PLL1_96		16
18#define PXA910_CLK_PLL1_13		17
19#define PXA910_CLK_PLL1_13_1_5		18
20#define PXA910_CLK_PLL1_2_1_5		19
21#define PXA910_CLK_PLL1_3_16		20
22#define PXA910_CLK_PLL1_192		21
23#define PXA910_CLK_UART_PLL		27
24#define PXA910_CLK_USB_PLL		28
25
26/* apb periphrals */
27#define PXA910_CLK_TWSI0		60
28#define PXA910_CLK_TWSI1		61
29#define PXA910_CLK_TWSI2		62
30#define PXA910_CLK_TWSI3		63
31#define PXA910_CLK_GPIO			64
32#define PXA910_CLK_KPC			65
33#define PXA910_CLK_RTC			66
34#define PXA910_CLK_PWM0			67
35#define PXA910_CLK_PWM1			68
36#define PXA910_CLK_PWM2			69
37#define PXA910_CLK_PWM3			70
38#define PXA910_CLK_UART0		71
39#define PXA910_CLK_UART1		72
40#define PXA910_CLK_UART2		73
41#define PXA910_CLK_SSP0			74
42#define PXA910_CLK_SSP1			75
43#define PXA910_CLK_TIMER0		76
44#define PXA910_CLK_TIMER1		77
45
46/* axi periphrals */
47#define PXA910_CLK_DFC			100
48#define PXA910_CLK_SDH0			101
49#define PXA910_CLK_SDH1			102
50#define PXA910_CLK_SDH2			103
51#define PXA910_CLK_USB			104
52#define PXA910_CLK_SPH			105
53#define PXA910_CLK_DISP0		106
54#define PXA910_CLK_CCIC0		107
55#define PXA910_CLK_CCIC0_PHY		108
56#define PXA910_CLK_CCIC0_SPHY		109
57
58#define PXA910_NR_CLKS			200
59#endif