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1/*
2 * Copyright 2005-2009 MontaVista Software, Inc.
3 * Copyright 2008,2012,2015 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
20 * by Hunter Wu.
21 * Power Management support by Dave Liu <daveliu@freescale.com>,
22 * Jerry Huang <Chang-Ming.Huang@freescale.com> and
23 * Anton Vorontsov <avorontsov@ru.mvista.com>.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/types.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
31#include <linux/err.h>
32#include <linux/usb.h>
33#include <linux/usb/ehci_def.h>
34#include <linux/usb/hcd.h>
35#include <linux/usb/otg.h>
36#include <linux/platform_device.h>
37#include <linux/fsl_devices.h>
38#include <linux/of_platform.h>
39
40#include "ehci.h"
41#include "ehci-fsl.h"
42
43#define DRIVER_DESC "Freescale EHCI Host controller driver"
44#define DRV_NAME "ehci-fsl"
45
46static struct hc_driver __read_mostly fsl_ehci_hc_driver;
47
48/* configure so an HC device and id are always provided */
49/* always called with process context; sleeping is OK */
50
51/*
52 * fsl_ehci_drv_probe - initialize FSL-based HCDs
53 * @pdev: USB Host Controller being probed
54 * Context: !in_interrupt()
55 *
56 * Allocates basic resources for this USB host controller.
57 *
58 */
59static int fsl_ehci_drv_probe(struct platform_device *pdev)
60{
61 struct fsl_usb2_platform_data *pdata;
62 struct usb_hcd *hcd;
63 struct resource *res;
64 int irq;
65 int retval;
66
67 pr_debug("initializing FSL-SOC USB Controller\n");
68
69 /* Need platform data for setup */
70 pdata = dev_get_platdata(&pdev->dev);
71 if (!pdata) {
72 dev_err(&pdev->dev,
73 "No platform data for %s.\n", dev_name(&pdev->dev));
74 return -ENODEV;
75 }
76
77 /*
78 * This is a host mode driver, verify that we're supposed to be
79 * in host mode.
80 */
81 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
82 (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
83 (pdata->operating_mode == FSL_USB2_DR_OTG))) {
84 dev_err(&pdev->dev,
85 "Non Host Mode configured for %s. Wrong driver linked.\n",
86 dev_name(&pdev->dev));
87 return -ENODEV;
88 }
89
90 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
91 if (!res) {
92 dev_err(&pdev->dev,
93 "Found HC with no IRQ. Check %s setup!\n",
94 dev_name(&pdev->dev));
95 return -ENODEV;
96 }
97 irq = res->start;
98
99 hcd = usb_create_hcd(&fsl_ehci_hc_driver, &pdev->dev,
100 dev_name(&pdev->dev));
101 if (!hcd) {
102 retval = -ENOMEM;
103 goto err1;
104 }
105
106 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
107 hcd->regs = devm_ioremap_resource(&pdev->dev, res);
108 if (IS_ERR(hcd->regs)) {
109 retval = PTR_ERR(hcd->regs);
110 goto err2;
111 }
112
113 hcd->rsrc_start = res->start;
114 hcd->rsrc_len = resource_size(res);
115
116 pdata->regs = hcd->regs;
117
118 if (pdata->power_budget)
119 hcd->power_budget = pdata->power_budget;
120
121 /*
122 * do platform specific init: check the clock, grab/config pins, etc.
123 */
124 if (pdata->init && pdata->init(pdev)) {
125 retval = -ENODEV;
126 goto err2;
127 }
128
129 /* Enable USB controller, 83xx or 8536 */
130 if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
131 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
132 CONTROL_REGISTER_W1C_MASK, 0x4);
133
134 /*
135 * Enable UTMI phy and program PTS field in UTMI mode before asserting
136 * controller reset for USB Controller version 2.5
137 */
138 if (pdata->has_fsl_erratum_a007792) {
139 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
140 CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
141 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
142 }
143
144 /* Don't need to set host mode here. It will be done by tdi_reset() */
145
146 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
147 if (retval != 0)
148 goto err2;
149 device_wakeup_enable(hcd->self.controller);
150
151#ifdef CONFIG_USB_OTG
152 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
153 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
154
155 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
156 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
157 hcd, ehci, hcd->usb_phy);
158
159 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
160 retval = otg_set_host(hcd->usb_phy->otg,
161 &ehci_to_hcd(ehci)->self);
162 if (retval) {
163 usb_put_phy(hcd->usb_phy);
164 goto err2;
165 }
166 } else {
167 dev_err(&pdev->dev, "can't find phy\n");
168 retval = -ENODEV;
169 goto err2;
170 }
171 }
172#endif
173 return retval;
174
175 err2:
176 usb_put_hcd(hcd);
177 err1:
178 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
179 if (pdata->exit)
180 pdata->exit(pdev);
181 return retval;
182}
183
184static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
185 enum fsl_usb2_phy_modes phy_mode,
186 unsigned int port_offset)
187{
188 u32 portsc;
189 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
190 void __iomem *non_ehci = hcd->regs;
191 struct device *dev = hcd->self.controller;
192 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
193
194 if (pdata->controller_ver < 0) {
195 dev_warn(hcd->self.controller, "Could not get controller version\n");
196 return -ENODEV;
197 }
198
199 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
200 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
201
202 switch (phy_mode) {
203 case FSL_USB2_PHY_ULPI:
204 if (pdata->have_sysif_regs && pdata->controller_ver) {
205 /* controller version 1.6 or above */
206 clrbits32(non_ehci + FSL_SOC_USB_CTRL,
207 CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
208 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
209 CONTROL_REGISTER_W1C_MASK,
210 ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
211 }
212 portsc |= PORT_PTS_ULPI;
213 break;
214 case FSL_USB2_PHY_SERIAL:
215 portsc |= PORT_PTS_SERIAL;
216 break;
217 case FSL_USB2_PHY_UTMI_WIDE:
218 portsc |= PORT_PTS_PTW;
219 /* fall through */
220 case FSL_USB2_PHY_UTMI:
221 case FSL_USB2_PHY_UTMI_DUAL:
222 if (pdata->have_sysif_regs && pdata->controller_ver) {
223 /* controller version 1.6 or above */
224 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
225 CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
226 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
227 become stable - 10ms*/
228 }
229 /* enable UTMI PHY */
230 if (pdata->have_sysif_regs)
231 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
232 CONTROL_REGISTER_W1C_MASK,
233 CTRL_UTMI_PHY_EN);
234 portsc |= PORT_PTS_UTMI;
235 break;
236 case FSL_USB2_PHY_NONE:
237 break;
238 }
239
240 /*
241 * check PHY_CLK_VALID to determine phy clock presence before writing
242 * to portsc
243 */
244 if (pdata->check_phy_clk_valid) {
245 if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
246 PHY_CLK_VALID)) {
247 dev_warn(hcd->self.controller,
248 "USB PHY clock invalid\n");
249 return -EINVAL;
250 }
251 }
252
253 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
254
255 if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
256 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
257 CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
258
259 return 0;
260}
261
262static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
263{
264 struct usb_hcd *hcd = ehci_to_hcd(ehci);
265 struct fsl_usb2_platform_data *pdata;
266 void __iomem *non_ehci = hcd->regs;
267
268 pdata = dev_get_platdata(hcd->self.controller);
269
270 if (pdata->have_sysif_regs) {
271 /*
272 * Turn on cache snooping hardware, since some PowerPC platforms
273 * wholly rely on hardware to deal with cache coherent
274 */
275
276 /* Setup Snooping for all the 4GB space */
277 /* SNOOP1 starts from 0x0, size 2G */
278 iowrite32be(0x0 | SNOOP_SIZE_2GB,
279 non_ehci + FSL_SOC_USB_SNOOP1);
280 /* SNOOP2 starts from 0x80000000, size 2G */
281 iowrite32be(0x80000000 | SNOOP_SIZE_2GB,
282 non_ehci + FSL_SOC_USB_SNOOP2);
283 }
284
285 /* Deal with USB erratum A-005275 */
286 if (pdata->has_fsl_erratum_a005275 == 1)
287 ehci->has_fsl_hs_errata = 1;
288
289 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
290 (pdata->operating_mode == FSL_USB2_DR_OTG))
291 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
292 return -EINVAL;
293
294 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
295 unsigned int chip, rev, svr;
296
297 svr = mfspr(SPRN_SVR);
298 chip = svr >> 16;
299 rev = (svr >> 4) & 0xf;
300
301 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
302 if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
303 ehci->has_fsl_port_bug = 1;
304
305 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
306 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
307 return -EINVAL;
308
309 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
310 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
311 return -EINVAL;
312 }
313
314 if (pdata->have_sysif_regs) {
315#ifdef CONFIG_FSL_SOC_BOOKE
316 iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL);
317 iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
318#else
319 iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL);
320 iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
321#endif
322 iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL);
323 }
324
325 return 0;
326}
327
328/* called after powerup, by probe or system-pm "wakeup" */
329static int ehci_fsl_reinit(struct ehci_hcd *ehci)
330{
331 if (ehci_fsl_usb_setup(ehci))
332 return -EINVAL;
333
334 return 0;
335}
336
337/* called during probe() after chip reset completes */
338static int ehci_fsl_setup(struct usb_hcd *hcd)
339{
340 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
341 int retval;
342 struct fsl_usb2_platform_data *pdata;
343 struct device *dev;
344
345 dev = hcd->self.controller;
346 pdata = dev_get_platdata(hcd->self.controller);
347 ehci->big_endian_desc = pdata->big_endian_desc;
348 ehci->big_endian_mmio = pdata->big_endian_mmio;
349
350 /* EHCI registers start at offset 0x100 */
351 ehci->caps = hcd->regs + 0x100;
352
353#ifdef CONFIG_PPC_83xx
354 /*
355 * Deal with MPC834X that need port power to be cycled after the power
356 * fault condition is removed. Otherwise the state machine does not
357 * reflect PORTSC[CSC] correctly.
358 */
359 ehci->need_oc_pp_cycle = 1;
360#endif
361
362 hcd->has_tt = 1;
363
364 retval = ehci_setup(hcd);
365 if (retval)
366 return retval;
367
368 if (of_device_is_compatible(dev->parent->of_node,
369 "fsl,mpc5121-usb2-dr")) {
370 /*
371 * set SBUSCFG:AHBBRST so that control msgs don't
372 * fail when doing heavy PATA writes.
373 */
374 ehci_writel(ehci, SBUSCFG_INCR8,
375 hcd->regs + FSL_SOC_USB_SBUSCFG);
376 }
377
378 retval = ehci_fsl_reinit(ehci);
379 return retval;
380}
381
382struct ehci_fsl {
383 struct ehci_hcd ehci;
384
385#ifdef CONFIG_PM
386 /* Saved USB PHY settings, need to restore after deep sleep. */
387 u32 usb_ctrl;
388#endif
389};
390
391#ifdef CONFIG_PM
392
393#ifdef CONFIG_PPC_MPC512x
394static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
395{
396 struct usb_hcd *hcd = dev_get_drvdata(dev);
397 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
398 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
399 u32 tmp;
400
401#ifdef CONFIG_DYNAMIC_DEBUG
402 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
403 mode &= USBMODE_CM_MASK;
404 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
405
406 dev_dbg(dev, "suspend=%d already_suspended=%d "
407 "mode=%d usbcmd %08x\n", pdata->suspended,
408 pdata->already_suspended, mode, tmp);
409#endif
410
411 /*
412 * If the controller is already suspended, then this must be a
413 * PM suspend. Remember this fact, so that we will leave the
414 * controller suspended at PM resume time.
415 */
416 if (pdata->suspended) {
417 dev_dbg(dev, "already suspended, leaving early\n");
418 pdata->already_suspended = 1;
419 return 0;
420 }
421
422 dev_dbg(dev, "suspending...\n");
423
424 ehci->rh_state = EHCI_RH_SUSPENDED;
425 dev->power.power_state = PMSG_SUSPEND;
426
427 /* ignore non-host interrupts */
428 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
429
430 /* stop the controller */
431 tmp = ehci_readl(ehci, &ehci->regs->command);
432 tmp &= ~CMD_RUN;
433 ehci_writel(ehci, tmp, &ehci->regs->command);
434
435 /* save EHCI registers */
436 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
437 pdata->pm_command &= ~CMD_RUN;
438 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
439 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
440 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
441 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
442 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
443 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
444 pdata->pm_configured_flag =
445 ehci_readl(ehci, &ehci->regs->configured_flag);
446 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
447 pdata->pm_usbgenctrl = ehci_readl(ehci,
448 hcd->regs + FSL_SOC_USB_USBGENCTRL);
449
450 /* clear the W1C bits */
451 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
452
453 pdata->suspended = 1;
454
455 /* clear PP to cut power to the port */
456 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
457 tmp &= ~PORT_POWER;
458 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
459
460 return 0;
461}
462
463static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
464{
465 struct usb_hcd *hcd = dev_get_drvdata(dev);
466 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
467 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
468 u32 tmp;
469
470 dev_dbg(dev, "suspend=%d already_suspended=%d\n",
471 pdata->suspended, pdata->already_suspended);
472
473 /*
474 * If the controller was already suspended at suspend time,
475 * then don't resume it now.
476 */
477 if (pdata->already_suspended) {
478 dev_dbg(dev, "already suspended, leaving early\n");
479 pdata->already_suspended = 0;
480 return 0;
481 }
482
483 if (!pdata->suspended) {
484 dev_dbg(dev, "not suspended, leaving early\n");
485 return 0;
486 }
487
488 pdata->suspended = 0;
489
490 dev_dbg(dev, "resuming...\n");
491
492 /* set host mode */
493 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
494 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
495
496 ehci_writel(ehci, pdata->pm_usbgenctrl,
497 hcd->regs + FSL_SOC_USB_USBGENCTRL);
498 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
499 hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
500
501 ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
502
503 /* restore EHCI registers */
504 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
505 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
506 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
507 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
508 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
509 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
510 ehci_writel(ehci, pdata->pm_configured_flag,
511 &ehci->regs->configured_flag);
512 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
513
514 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
515 ehci->rh_state = EHCI_RH_RUNNING;
516 dev->power.power_state = PMSG_ON;
517
518 tmp = ehci_readl(ehci, &ehci->regs->command);
519 tmp |= CMD_RUN;
520 ehci_writel(ehci, tmp, &ehci->regs->command);
521
522 usb_hcd_resume_root_hub(hcd);
523
524 return 0;
525}
526#else
527static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
528{
529 return 0;
530}
531
532static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
533{
534 return 0;
535}
536#endif /* CONFIG_PPC_MPC512x */
537
538static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
539{
540 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
541
542 return container_of(ehci, struct ehci_fsl, ehci);
543}
544
545static int ehci_fsl_drv_suspend(struct device *dev)
546{
547 struct usb_hcd *hcd = dev_get_drvdata(dev);
548 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
549 void __iomem *non_ehci = hcd->regs;
550
551 if (of_device_is_compatible(dev->parent->of_node,
552 "fsl,mpc5121-usb2-dr")) {
553 return ehci_fsl_mpc512x_drv_suspend(dev);
554 }
555
556 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
557 device_may_wakeup(dev));
558 if (!fsl_deep_sleep())
559 return 0;
560
561 ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
562 return 0;
563}
564
565static int ehci_fsl_drv_resume(struct device *dev)
566{
567 struct usb_hcd *hcd = dev_get_drvdata(dev);
568 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
569 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
570 void __iomem *non_ehci = hcd->regs;
571
572 if (of_device_is_compatible(dev->parent->of_node,
573 "fsl,mpc5121-usb2-dr")) {
574 return ehci_fsl_mpc512x_drv_resume(dev);
575 }
576
577 ehci_prepare_ports_for_controller_resume(ehci);
578 if (!fsl_deep_sleep())
579 return 0;
580
581 usb_root_hub_lost_power(hcd->self.root_hub);
582
583 /* Restore USB PHY settings and enable the controller. */
584 iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
585
586 ehci_reset(ehci);
587 ehci_fsl_reinit(ehci);
588
589 return 0;
590}
591
592static int ehci_fsl_drv_restore(struct device *dev)
593{
594 struct usb_hcd *hcd = dev_get_drvdata(dev);
595
596 usb_root_hub_lost_power(hcd->self.root_hub);
597 return 0;
598}
599
600static struct dev_pm_ops ehci_fsl_pm_ops = {
601 .suspend = ehci_fsl_drv_suspend,
602 .resume = ehci_fsl_drv_resume,
603 .restore = ehci_fsl_drv_restore,
604};
605
606#define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
607#else
608#define EHCI_FSL_PM_OPS NULL
609#endif /* CONFIG_PM */
610
611#ifdef CONFIG_USB_OTG
612static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
613{
614 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
615 u32 status;
616
617 if (!port)
618 return -EINVAL;
619
620 port--;
621
622 /* start port reset before HNP protocol time out */
623 status = readl(&ehci->regs->port_status[port]);
624 if (!(status & PORT_CONNECT))
625 return -ENODEV;
626
627 /* hub_wq will finish the reset later */
628 if (ehci_is_TDI(ehci)) {
629 writel(PORT_RESET |
630 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
631 &ehci->regs->port_status[port]);
632 } else {
633 writel(PORT_RESET, &ehci->regs->port_status[port]);
634 }
635
636 return 0;
637}
638#else
639#define ehci_start_port_reset NULL
640#endif /* CONFIG_USB_OTG */
641
642static struct ehci_driver_overrides ehci_fsl_overrides __initdata = {
643 .extra_priv_size = sizeof(struct ehci_fsl),
644 .reset = ehci_fsl_setup,
645};
646
647/**
648 * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
649 * @dev: USB Host Controller being removed
650 * Context: !in_interrupt()
651 *
652 * Reverses the effect of usb_hcd_fsl_probe().
653 *
654 */
655
656static int fsl_ehci_drv_remove(struct platform_device *pdev)
657{
658 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
659 struct usb_hcd *hcd = platform_get_drvdata(pdev);
660
661 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
662 otg_set_host(hcd->usb_phy->otg, NULL);
663 usb_put_phy(hcd->usb_phy);
664 }
665
666 usb_remove_hcd(hcd);
667
668 /*
669 * do platform specific un-initialization:
670 * release iomux pins, disable clock, etc.
671 */
672 if (pdata->exit)
673 pdata->exit(pdev);
674 usb_put_hcd(hcd);
675
676 return 0;
677}
678
679static struct platform_driver ehci_fsl_driver = {
680 .probe = fsl_ehci_drv_probe,
681 .remove = fsl_ehci_drv_remove,
682 .shutdown = usb_hcd_platform_shutdown,
683 .driver = {
684 .name = "fsl-ehci",
685 .pm = EHCI_FSL_PM_OPS,
686 },
687};
688
689static int __init ehci_fsl_init(void)
690{
691 if (usb_disabled())
692 return -ENODEV;
693
694 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
695
696 ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
697
698 fsl_ehci_hc_driver.product_desc =
699 "Freescale On-Chip EHCI Host Controller";
700 fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
701
702
703 return platform_driver_register(&ehci_fsl_driver);
704}
705module_init(ehci_fsl_init);
706
707static void __exit ehci_fsl_cleanup(void)
708{
709 platform_driver_unregister(&ehci_fsl_driver);
710}
711module_exit(ehci_fsl_cleanup);
712
713MODULE_DESCRIPTION(DRIVER_DESC);
714MODULE_LICENSE("GPL");
715MODULE_ALIAS("platform:" DRV_NAME);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2005-2009 MontaVista Software, Inc.
4 * Copyright 2008,2012,2015 Freescale Semiconductor, Inc.
5 *
6 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
7 * by Hunter Wu.
8 * Power Management support by Dave Liu <daveliu@freescale.com>,
9 * Jerry Huang <Chang-Ming.Huang@freescale.com> and
10 * Anton Vorontsov <avorontsov@ru.mvista.com>.
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/err.h>
19#include <linux/usb.h>
20#include <linux/usb/ehci_def.h>
21#include <linux/usb/hcd.h>
22#include <linux/usb/otg.h>
23#include <linux/platform_device.h>
24#include <linux/fsl_devices.h>
25#include <linux/of_platform.h>
26#include <linux/io.h>
27
28#include "ehci.h"
29#include "ehci-fsl.h"
30
31#define DRIVER_DESC "Freescale EHCI Host controller driver"
32#define DRV_NAME "ehci-fsl"
33
34static struct hc_driver __read_mostly fsl_ehci_hc_driver;
35
36/* configure so an HC device and id are always provided */
37/* always called with process context; sleeping is OK */
38
39/*
40 * fsl_ehci_drv_probe - initialize FSL-based HCDs
41 * @pdev: USB Host Controller being probed
42 * Context: !in_interrupt()
43 *
44 * Allocates basic resources for this USB host controller.
45 *
46 */
47static int fsl_ehci_drv_probe(struct platform_device *pdev)
48{
49 struct fsl_usb2_platform_data *pdata;
50 struct usb_hcd *hcd;
51 struct resource *res;
52 int irq;
53 int retval;
54 u32 tmp;
55
56 pr_debug("initializing FSL-SOC USB Controller\n");
57
58 /* Need platform data for setup */
59 pdata = dev_get_platdata(&pdev->dev);
60 if (!pdata) {
61 dev_err(&pdev->dev,
62 "No platform data for %s.\n", dev_name(&pdev->dev));
63 return -ENODEV;
64 }
65
66 /*
67 * This is a host mode driver, verify that we're supposed to be
68 * in host mode.
69 */
70 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
71 (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
72 (pdata->operating_mode == FSL_USB2_DR_OTG))) {
73 dev_err(&pdev->dev,
74 "Non Host Mode configured for %s. Wrong driver linked.\n",
75 dev_name(&pdev->dev));
76 return -ENODEV;
77 }
78
79 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
80 if (!res) {
81 dev_err(&pdev->dev,
82 "Found HC with no IRQ. Check %s setup!\n",
83 dev_name(&pdev->dev));
84 return -ENODEV;
85 }
86 irq = res->start;
87
88 hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent,
89 &pdev->dev, dev_name(&pdev->dev), NULL);
90 if (!hcd) {
91 retval = -ENOMEM;
92 goto err1;
93 }
94
95 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
96 hcd->regs = devm_ioremap_resource(&pdev->dev, res);
97 if (IS_ERR(hcd->regs)) {
98 retval = PTR_ERR(hcd->regs);
99 goto err2;
100 }
101
102 hcd->rsrc_start = res->start;
103 hcd->rsrc_len = resource_size(res);
104
105 pdata->regs = hcd->regs;
106
107 if (pdata->power_budget)
108 hcd->power_budget = pdata->power_budget;
109
110 /*
111 * do platform specific init: check the clock, grab/config pins, etc.
112 */
113 if (pdata->init && pdata->init(pdev)) {
114 retval = -ENODEV;
115 goto err2;
116 }
117
118 /* Enable USB controller, 83xx or 8536 */
119 if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) {
120 tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
121 tmp &= ~CONTROL_REGISTER_W1C_MASK;
122 tmp |= 0x4;
123 iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
124 }
125
126 /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
127 if (pdata->controller_ver == FSL_USB_VER_2_5 &&
128 pdata->phy_mode == FSL_USB2_PHY_ULPI)
129 iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
130
131 /*
132 * Enable UTMI phy and program PTS field in UTMI mode before asserting
133 * controller reset for USB Controller version 2.5
134 */
135 if (pdata->has_fsl_erratum_a007792) {
136 tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
137 tmp &= ~CONTROL_REGISTER_W1C_MASK;
138 tmp |= CTRL_UTMI_PHY_EN;
139 iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
140
141 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
142 }
143
144 /* Don't need to set host mode here. It will be done by tdi_reset() */
145
146 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
147 if (retval != 0)
148 goto err2;
149 device_wakeup_enable(hcd->self.controller);
150
151#ifdef CONFIG_USB_OTG
152 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
153 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
154
155 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
156 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
157 hcd, ehci, hcd->usb_phy);
158
159 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
160 retval = otg_set_host(hcd->usb_phy->otg,
161 &ehci_to_hcd(ehci)->self);
162 if (retval) {
163 usb_put_phy(hcd->usb_phy);
164 goto err2;
165 }
166 } else {
167 dev_err(&pdev->dev, "can't find phy\n");
168 retval = -ENODEV;
169 goto err2;
170 }
171
172 hcd->skip_phy_initialization = 1;
173 }
174#endif
175 return retval;
176
177 err2:
178 usb_put_hcd(hcd);
179 err1:
180 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
181 if (pdata->exit)
182 pdata->exit(pdev);
183 return retval;
184}
185
186static bool usb_phy_clk_valid(struct usb_hcd *hcd)
187{
188 void __iomem *non_ehci = hcd->regs;
189 bool ret = true;
190
191 if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
192 ret = false;
193
194 return ret;
195}
196
197static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
198 enum fsl_usb2_phy_modes phy_mode,
199 unsigned int port_offset)
200{
201 u32 portsc, tmp;
202 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
203 void __iomem *non_ehci = hcd->regs;
204 struct device *dev = hcd->self.controller;
205 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
206
207 if (pdata->controller_ver < 0) {
208 dev_warn(hcd->self.controller, "Could not get controller version\n");
209 return -ENODEV;
210 }
211
212 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
213 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
214
215 switch (phy_mode) {
216 case FSL_USB2_PHY_ULPI:
217 if (pdata->have_sysif_regs && pdata->controller_ver) {
218 /* controller version 1.6 or above */
219 /* turn off UTMI PHY first */
220 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
221 tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
222 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
223
224 /* then turn on ULPI and enable USB controller */
225 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
226 tmp &= ~CONTROL_REGISTER_W1C_MASK;
227 tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN;
228 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
229 }
230 portsc |= PORT_PTS_ULPI;
231 break;
232 case FSL_USB2_PHY_SERIAL:
233 portsc |= PORT_PTS_SERIAL;
234 break;
235 case FSL_USB2_PHY_UTMI_WIDE:
236 portsc |= PORT_PTS_PTW;
237 /* fall through */
238 case FSL_USB2_PHY_UTMI:
239 /* Presence of this node "has_fsl_erratum_a006918"
240 * in device-tree is used to stop USB controller
241 * initialization in Linux
242 */
243 if (pdata->has_fsl_erratum_a006918) {
244 dev_warn(dev, "USB PHY clock invalid\n");
245 return -EINVAL;
246 }
247 /* fall through */
248 case FSL_USB2_PHY_UTMI_DUAL:
249 /* PHY_CLK_VALID bit is de-featured from all controller
250 * versions below 2.4 and is to be checked only for
251 * internal UTMI phy
252 */
253 if (pdata->controller_ver > FSL_USB_VER_2_4 &&
254 pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
255 dev_err(dev, "USB PHY clock invalid\n");
256 return -EINVAL;
257 }
258
259 if (pdata->have_sysif_regs && pdata->controller_ver) {
260 /* controller version 1.6 or above */
261 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
262 tmp &= ~CONTROL_REGISTER_W1C_MASK;
263 tmp |= UTMI_PHY_EN;
264 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
265
266 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
267 become stable - 10ms*/
268 }
269 /* enable UTMI PHY */
270 if (pdata->have_sysif_regs) {
271 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
272 tmp &= ~CONTROL_REGISTER_W1C_MASK;
273 tmp |= CTRL_UTMI_PHY_EN;
274 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
275 }
276 portsc |= PORT_PTS_UTMI;
277 break;
278 case FSL_USB2_PHY_NONE:
279 break;
280 }
281
282 if (pdata->have_sysif_regs &&
283 pdata->controller_ver > FSL_USB_VER_1_6 &&
284 !usb_phy_clk_valid(hcd)) {
285 dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
286 return -EINVAL;
287 }
288
289 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
290
291 if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) {
292 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
293 tmp &= ~CONTROL_REGISTER_W1C_MASK;
294 tmp |= USB_CTRL_USB_EN;
295 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
296 }
297
298 return 0;
299}
300
301static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
302{
303 struct usb_hcd *hcd = ehci_to_hcd(ehci);
304 struct fsl_usb2_platform_data *pdata;
305 void __iomem *non_ehci = hcd->regs;
306
307 pdata = dev_get_platdata(hcd->self.controller);
308
309 if (pdata->have_sysif_regs) {
310 /*
311 * Turn on cache snooping hardware, since some PowerPC platforms
312 * wholly rely on hardware to deal with cache coherent
313 */
314
315 /* Setup Snooping for all the 4GB space */
316 /* SNOOP1 starts from 0x0, size 2G */
317 iowrite32be(0x0 | SNOOP_SIZE_2GB,
318 non_ehci + FSL_SOC_USB_SNOOP1);
319 /* SNOOP2 starts from 0x80000000, size 2G */
320 iowrite32be(0x80000000 | SNOOP_SIZE_2GB,
321 non_ehci + FSL_SOC_USB_SNOOP2);
322 }
323
324 /* Deal with USB erratum A-005275 */
325 if (pdata->has_fsl_erratum_a005275 == 1)
326 ehci->has_fsl_hs_errata = 1;
327
328 if (pdata->has_fsl_erratum_a005697 == 1)
329 ehci->has_fsl_susp_errata = 1;
330
331 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
332 (pdata->operating_mode == FSL_USB2_DR_OTG))
333 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
334 return -EINVAL;
335
336 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
337
338 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
339 if (pdata->has_fsl_erratum_14 == 1)
340 ehci->has_fsl_port_bug = 1;
341
342 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
343 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
344 return -EINVAL;
345
346 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
347 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
348 return -EINVAL;
349 }
350
351 if (pdata->have_sysif_regs) {
352#ifdef CONFIG_FSL_SOC_BOOKE
353 iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL);
354 iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
355#else
356 iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL);
357 iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
358#endif
359 iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL);
360 }
361
362 return 0;
363}
364
365/* called after powerup, by probe or system-pm "wakeup" */
366static int ehci_fsl_reinit(struct ehci_hcd *ehci)
367{
368 if (ehci_fsl_usb_setup(ehci))
369 return -EINVAL;
370
371 return 0;
372}
373
374/* called during probe() after chip reset completes */
375static int ehci_fsl_setup(struct usb_hcd *hcd)
376{
377 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
378 int retval;
379 struct fsl_usb2_platform_data *pdata;
380 struct device *dev;
381
382 dev = hcd->self.controller;
383 pdata = dev_get_platdata(hcd->self.controller);
384 ehci->big_endian_desc = pdata->big_endian_desc;
385 ehci->big_endian_mmio = pdata->big_endian_mmio;
386
387 /* EHCI registers start at offset 0x100 */
388 ehci->caps = hcd->regs + 0x100;
389
390#ifdef CONFIG_PPC_83xx
391 /*
392 * Deal with MPC834X that need port power to be cycled after the power
393 * fault condition is removed. Otherwise the state machine does not
394 * reflect PORTSC[CSC] correctly.
395 */
396 ehci->need_oc_pp_cycle = 1;
397#endif
398
399 hcd->has_tt = 1;
400
401 retval = ehci_setup(hcd);
402 if (retval)
403 return retval;
404
405 if (of_device_is_compatible(dev->parent->of_node,
406 "fsl,mpc5121-usb2-dr")) {
407 /*
408 * set SBUSCFG:AHBBRST so that control msgs don't
409 * fail when doing heavy PATA writes.
410 */
411 ehci_writel(ehci, SBUSCFG_INCR8,
412 hcd->regs + FSL_SOC_USB_SBUSCFG);
413 }
414
415 retval = ehci_fsl_reinit(ehci);
416 return retval;
417}
418
419struct ehci_fsl {
420 struct ehci_hcd ehci;
421
422#ifdef CONFIG_PM
423 /* Saved USB PHY settings, need to restore after deep sleep. */
424 u32 usb_ctrl;
425#endif
426};
427
428#ifdef CONFIG_PM
429
430#ifdef CONFIG_PPC_MPC512x
431static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
432{
433 struct usb_hcd *hcd = dev_get_drvdata(dev);
434 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
435 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
436 u32 tmp;
437
438#ifdef CONFIG_DYNAMIC_DEBUG
439 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
440 mode &= USBMODE_CM_MASK;
441 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
442
443 dev_dbg(dev, "suspend=%d already_suspended=%d "
444 "mode=%d usbcmd %08x\n", pdata->suspended,
445 pdata->already_suspended, mode, tmp);
446#endif
447
448 /*
449 * If the controller is already suspended, then this must be a
450 * PM suspend. Remember this fact, so that we will leave the
451 * controller suspended at PM resume time.
452 */
453 if (pdata->suspended) {
454 dev_dbg(dev, "already suspended, leaving early\n");
455 pdata->already_suspended = 1;
456 return 0;
457 }
458
459 dev_dbg(dev, "suspending...\n");
460
461 ehci->rh_state = EHCI_RH_SUSPENDED;
462 dev->power.power_state = PMSG_SUSPEND;
463
464 /* ignore non-host interrupts */
465 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
466
467 /* stop the controller */
468 tmp = ehci_readl(ehci, &ehci->regs->command);
469 tmp &= ~CMD_RUN;
470 ehci_writel(ehci, tmp, &ehci->regs->command);
471
472 /* save EHCI registers */
473 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
474 pdata->pm_command &= ~CMD_RUN;
475 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
476 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
477 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
478 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
479 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
480 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
481 pdata->pm_configured_flag =
482 ehci_readl(ehci, &ehci->regs->configured_flag);
483 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
484 pdata->pm_usbgenctrl = ehci_readl(ehci,
485 hcd->regs + FSL_SOC_USB_USBGENCTRL);
486
487 /* clear the W1C bits */
488 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
489
490 pdata->suspended = 1;
491
492 /* clear PP to cut power to the port */
493 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
494 tmp &= ~PORT_POWER;
495 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
496
497 return 0;
498}
499
500static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
501{
502 struct usb_hcd *hcd = dev_get_drvdata(dev);
503 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
504 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
505 u32 tmp;
506
507 dev_dbg(dev, "suspend=%d already_suspended=%d\n",
508 pdata->suspended, pdata->already_suspended);
509
510 /*
511 * If the controller was already suspended at suspend time,
512 * then don't resume it now.
513 */
514 if (pdata->already_suspended) {
515 dev_dbg(dev, "already suspended, leaving early\n");
516 pdata->already_suspended = 0;
517 return 0;
518 }
519
520 if (!pdata->suspended) {
521 dev_dbg(dev, "not suspended, leaving early\n");
522 return 0;
523 }
524
525 pdata->suspended = 0;
526
527 dev_dbg(dev, "resuming...\n");
528
529 /* set host mode */
530 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
531 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
532
533 ehci_writel(ehci, pdata->pm_usbgenctrl,
534 hcd->regs + FSL_SOC_USB_USBGENCTRL);
535 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
536 hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
537
538 ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
539
540 /* restore EHCI registers */
541 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
542 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
543 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
544 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
545 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
546 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
547 ehci_writel(ehci, pdata->pm_configured_flag,
548 &ehci->regs->configured_flag);
549 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
550
551 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
552 ehci->rh_state = EHCI_RH_RUNNING;
553 dev->power.power_state = PMSG_ON;
554
555 tmp = ehci_readl(ehci, &ehci->regs->command);
556 tmp |= CMD_RUN;
557 ehci_writel(ehci, tmp, &ehci->regs->command);
558
559 usb_hcd_resume_root_hub(hcd);
560
561 return 0;
562}
563#else
564static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
565{
566 return 0;
567}
568
569static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
570{
571 return 0;
572}
573#endif /* CONFIG_PPC_MPC512x */
574
575static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
576{
577 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
578
579 return container_of(ehci, struct ehci_fsl, ehci);
580}
581
582static int ehci_fsl_drv_suspend(struct device *dev)
583{
584 struct usb_hcd *hcd = dev_get_drvdata(dev);
585 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
586 void __iomem *non_ehci = hcd->regs;
587
588 if (of_device_is_compatible(dev->parent->of_node,
589 "fsl,mpc5121-usb2-dr")) {
590 return ehci_fsl_mpc512x_drv_suspend(dev);
591 }
592
593 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
594 device_may_wakeup(dev));
595 if (!fsl_deep_sleep())
596 return 0;
597
598 ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
599 return 0;
600}
601
602static int ehci_fsl_drv_resume(struct device *dev)
603{
604 struct usb_hcd *hcd = dev_get_drvdata(dev);
605 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
606 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
607 void __iomem *non_ehci = hcd->regs;
608
609 if (of_device_is_compatible(dev->parent->of_node,
610 "fsl,mpc5121-usb2-dr")) {
611 return ehci_fsl_mpc512x_drv_resume(dev);
612 }
613
614 ehci_prepare_ports_for_controller_resume(ehci);
615 if (!fsl_deep_sleep())
616 return 0;
617
618 usb_root_hub_lost_power(hcd->self.root_hub);
619
620 /* Restore USB PHY settings and enable the controller. */
621 iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
622
623 ehci_reset(ehci);
624 ehci_fsl_reinit(ehci);
625
626 return 0;
627}
628
629static int ehci_fsl_drv_restore(struct device *dev)
630{
631 struct usb_hcd *hcd = dev_get_drvdata(dev);
632
633 usb_root_hub_lost_power(hcd->self.root_hub);
634 return 0;
635}
636
637static const struct dev_pm_ops ehci_fsl_pm_ops = {
638 .suspend = ehci_fsl_drv_suspend,
639 .resume = ehci_fsl_drv_resume,
640 .restore = ehci_fsl_drv_restore,
641};
642
643#define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
644#else
645#define EHCI_FSL_PM_OPS NULL
646#endif /* CONFIG_PM */
647
648#ifdef CONFIG_USB_OTG
649static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
650{
651 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
652 u32 status;
653
654 if (!port)
655 return -EINVAL;
656
657 port--;
658
659 /* start port reset before HNP protocol time out */
660 status = readl(&ehci->regs->port_status[port]);
661 if (!(status & PORT_CONNECT))
662 return -ENODEV;
663
664 /* hub_wq will finish the reset later */
665 if (ehci_is_TDI(ehci)) {
666 writel(PORT_RESET |
667 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
668 &ehci->regs->port_status[port]);
669 } else {
670 writel(PORT_RESET, &ehci->regs->port_status[port]);
671 }
672
673 return 0;
674}
675#else
676#define ehci_start_port_reset NULL
677#endif /* CONFIG_USB_OTG */
678
679static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = {
680 .extra_priv_size = sizeof(struct ehci_fsl),
681 .reset = ehci_fsl_setup,
682};
683
684/**
685 * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
686 * @dev: USB Host Controller being removed
687 * Context: !in_interrupt()
688 *
689 * Reverses the effect of usb_hcd_fsl_probe().
690 *
691 */
692
693static int fsl_ehci_drv_remove(struct platform_device *pdev)
694{
695 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
696 struct usb_hcd *hcd = platform_get_drvdata(pdev);
697
698 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
699 otg_set_host(hcd->usb_phy->otg, NULL);
700 usb_put_phy(hcd->usb_phy);
701 }
702
703 usb_remove_hcd(hcd);
704
705 /*
706 * do platform specific un-initialization:
707 * release iomux pins, disable clock, etc.
708 */
709 if (pdata->exit)
710 pdata->exit(pdev);
711 usb_put_hcd(hcd);
712
713 return 0;
714}
715
716static struct platform_driver ehci_fsl_driver = {
717 .probe = fsl_ehci_drv_probe,
718 .remove = fsl_ehci_drv_remove,
719 .shutdown = usb_hcd_platform_shutdown,
720 .driver = {
721 .name = "fsl-ehci",
722 .pm = EHCI_FSL_PM_OPS,
723 },
724};
725
726static int __init ehci_fsl_init(void)
727{
728 if (usb_disabled())
729 return -ENODEV;
730
731 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
732
733 ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
734
735 fsl_ehci_hc_driver.product_desc =
736 "Freescale On-Chip EHCI Host Controller";
737 fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
738
739
740 return platform_driver_register(&ehci_fsl_driver);
741}
742module_init(ehci_fsl_init);
743
744static void __exit ehci_fsl_cleanup(void)
745{
746 platform_driver_unregister(&ehci_fsl_driver);
747}
748module_exit(ehci_fsl_cleanup);
749
750MODULE_DESCRIPTION(DRIVER_DESC);
751MODULE_LICENSE("GPL");
752MODULE_ALIAS("platform:" DRV_NAME);