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1/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/version.h>
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/interrupt.h>
30#include <linux/ioport.h>
31#include <linux/io.h>
32#include <linux/list.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/of.h>
36#include <linux/acpi.h>
37#include <linux/pinctrl/consumer.h>
38
39#include <linux/usb/ch9.h>
40#include <linux/usb/gadget.h>
41#include <linux/usb/of.h>
42#include <linux/usb/otg.h>
43
44#include "platform_data.h"
45#include "core.h"
46#include "gadget.h"
47#include "io.h"
48
49#include "debug.h"
50
51/* -------------------------------------------------------------------------- */
52
53void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
54{
55 u32 reg;
56
57 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
58 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
59 reg |= DWC3_GCTL_PRTCAPDIR(mode);
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
61}
62
63/**
64 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
65 * @dwc: pointer to our context structure
66 */
67static int dwc3_core_soft_reset(struct dwc3 *dwc)
68{
69 u32 reg;
70 int retries = 1000;
71 int ret;
72
73 usb_phy_init(dwc->usb2_phy);
74 usb_phy_init(dwc->usb3_phy);
75 ret = phy_init(dwc->usb2_generic_phy);
76 if (ret < 0)
77 return ret;
78
79 ret = phy_init(dwc->usb3_generic_phy);
80 if (ret < 0) {
81 phy_exit(dwc->usb2_generic_phy);
82 return ret;
83 }
84
85 /*
86 * We're resetting only the device side because, if we're in host mode,
87 * XHCI driver will reset the host block. If dwc3 was configured for
88 * host-only mode, then we can return early.
89 */
90 if (dwc->dr_mode == USB_DR_MODE_HOST)
91 return 0;
92
93 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
94 reg |= DWC3_DCTL_CSFTRST;
95 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
96
97 do {
98 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
99 if (!(reg & DWC3_DCTL_CSFTRST))
100 return 0;
101
102 udelay(1);
103 } while (--retries);
104
105 return -ETIMEDOUT;
106}
107
108/**
109 * dwc3_soft_reset - Issue soft reset
110 * @dwc: Pointer to our controller context structure
111 */
112static int dwc3_soft_reset(struct dwc3 *dwc)
113{
114 unsigned long timeout;
115 u32 reg;
116
117 timeout = jiffies + msecs_to_jiffies(500);
118 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
119 do {
120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 if (!(reg & DWC3_DCTL_CSFTRST))
122 break;
123
124 if (time_after(jiffies, timeout)) {
125 dev_err(dwc->dev, "Reset Timed Out\n");
126 return -ETIMEDOUT;
127 }
128
129 cpu_relax();
130 } while (true);
131
132 return 0;
133}
134
135/*
136 * dwc3_frame_length_adjustment - Adjusts frame length if required
137 * @dwc3: Pointer to our controller context structure
138 * @fladj: Value of GFLADJ_30MHZ to adjust frame length
139 */
140static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
141{
142 u32 reg;
143 u32 dft;
144
145 if (dwc->revision < DWC3_REVISION_250A)
146 return;
147
148 if (fladj == 0)
149 return;
150
151 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
152 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
153 if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
154 "request value same as default, ignoring\n")) {
155 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
156 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
157 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
158 }
159}
160
161/**
162 * dwc3_free_one_event_buffer - Frees one event buffer
163 * @dwc: Pointer to our controller context structure
164 * @evt: Pointer to event buffer to be freed
165 */
166static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
167 struct dwc3_event_buffer *evt)
168{
169 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
170}
171
172/**
173 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
174 * @dwc: Pointer to our controller context structure
175 * @length: size of the event buffer
176 *
177 * Returns a pointer to the allocated event buffer structure on success
178 * otherwise ERR_PTR(errno).
179 */
180static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
181 unsigned length)
182{
183 struct dwc3_event_buffer *evt;
184
185 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
186 if (!evt)
187 return ERR_PTR(-ENOMEM);
188
189 evt->dwc = dwc;
190 evt->length = length;
191 evt->buf = dma_alloc_coherent(dwc->dev, length,
192 &evt->dma, GFP_KERNEL);
193 if (!evt->buf)
194 return ERR_PTR(-ENOMEM);
195
196 return evt;
197}
198
199/**
200 * dwc3_free_event_buffers - frees all allocated event buffers
201 * @dwc: Pointer to our controller context structure
202 */
203static void dwc3_free_event_buffers(struct dwc3 *dwc)
204{
205 struct dwc3_event_buffer *evt;
206 int i;
207
208 for (i = 0; i < dwc->num_event_buffers; i++) {
209 evt = dwc->ev_buffs[i];
210 if (evt)
211 dwc3_free_one_event_buffer(dwc, evt);
212 }
213}
214
215/**
216 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
217 * @dwc: pointer to our controller context structure
218 * @length: size of event buffer
219 *
220 * Returns 0 on success otherwise negative errno. In the error case, dwc
221 * may contain some buffers allocated but not all which were requested.
222 */
223static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
224{
225 int num;
226 int i;
227
228 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
229 dwc->num_event_buffers = num;
230
231 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
232 GFP_KERNEL);
233 if (!dwc->ev_buffs)
234 return -ENOMEM;
235
236 for (i = 0; i < num; i++) {
237 struct dwc3_event_buffer *evt;
238
239 evt = dwc3_alloc_one_event_buffer(dwc, length);
240 if (IS_ERR(evt)) {
241 dev_err(dwc->dev, "can't allocate event buffer\n");
242 return PTR_ERR(evt);
243 }
244 dwc->ev_buffs[i] = evt;
245 }
246
247 return 0;
248}
249
250/**
251 * dwc3_event_buffers_setup - setup our allocated event buffers
252 * @dwc: pointer to our controller context structure
253 *
254 * Returns 0 on success otherwise negative errno.
255 */
256static int dwc3_event_buffers_setup(struct dwc3 *dwc)
257{
258 struct dwc3_event_buffer *evt;
259 int n;
260
261 for (n = 0; n < dwc->num_event_buffers; n++) {
262 evt = dwc->ev_buffs[n];
263 dwc3_trace(trace_dwc3_core,
264 "Event buf %p dma %08llx length %d\n",
265 evt->buf, (unsigned long long) evt->dma,
266 evt->length);
267
268 evt->lpos = 0;
269
270 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
271 lower_32_bits(evt->dma));
272 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
273 upper_32_bits(evt->dma));
274 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
275 DWC3_GEVNTSIZ_SIZE(evt->length));
276 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
277 }
278
279 return 0;
280}
281
282static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
283{
284 struct dwc3_event_buffer *evt;
285 int n;
286
287 for (n = 0; n < dwc->num_event_buffers; n++) {
288 evt = dwc->ev_buffs[n];
289
290 evt->lpos = 0;
291
292 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
293 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
294 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
295 | DWC3_GEVNTSIZ_SIZE(0));
296 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
297 }
298}
299
300static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
301{
302 if (!dwc->has_hibernation)
303 return 0;
304
305 if (!dwc->nr_scratch)
306 return 0;
307
308 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
309 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
310 if (!dwc->scratchbuf)
311 return -ENOMEM;
312
313 return 0;
314}
315
316static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
317{
318 dma_addr_t scratch_addr;
319 u32 param;
320 int ret;
321
322 if (!dwc->has_hibernation)
323 return 0;
324
325 if (!dwc->nr_scratch)
326 return 0;
327
328 /* should never fall here */
329 if (!WARN_ON(dwc->scratchbuf))
330 return 0;
331
332 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
333 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
334 DMA_BIDIRECTIONAL);
335 if (dma_mapping_error(dwc->dev, scratch_addr)) {
336 dev_err(dwc->dev, "failed to map scratch buffer\n");
337 ret = -EFAULT;
338 goto err0;
339 }
340
341 dwc->scratch_addr = scratch_addr;
342
343 param = lower_32_bits(scratch_addr);
344
345 ret = dwc3_send_gadget_generic_command(dwc,
346 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
347 if (ret < 0)
348 goto err1;
349
350 param = upper_32_bits(scratch_addr);
351
352 ret = dwc3_send_gadget_generic_command(dwc,
353 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
354 if (ret < 0)
355 goto err1;
356
357 return 0;
358
359err1:
360 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
361 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
362
363err0:
364 return ret;
365}
366
367static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
368{
369 if (!dwc->has_hibernation)
370 return;
371
372 if (!dwc->nr_scratch)
373 return;
374
375 /* should never fall here */
376 if (!WARN_ON(dwc->scratchbuf))
377 return;
378
379 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
380 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
381 kfree(dwc->scratchbuf);
382}
383
384static void dwc3_core_num_eps(struct dwc3 *dwc)
385{
386 struct dwc3_hwparams *parms = &dwc->hwparams;
387
388 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
389 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
390
391 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
392 dwc->num_in_eps, dwc->num_out_eps);
393}
394
395static void dwc3_cache_hwparams(struct dwc3 *dwc)
396{
397 struct dwc3_hwparams *parms = &dwc->hwparams;
398
399 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
400 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
401 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
402 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
403 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
404 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
405 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
406 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
407 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
408}
409
410/**
411 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
412 * @dwc: Pointer to our controller context structure
413 *
414 * Returns 0 on success. The USB PHY interfaces are configured but not
415 * initialized. The PHY interfaces and the PHYs get initialized together with
416 * the core in dwc3_core_init.
417 */
418static int dwc3_phy_setup(struct dwc3 *dwc)
419{
420 u32 reg;
421 int ret;
422
423 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
424
425 /*
426 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
427 * to '0' during coreConsultant configuration. So default value
428 * will be '0' when the core is reset. Application needs to set it
429 * to '1' after the core initialization is completed.
430 */
431 if (dwc->revision > DWC3_REVISION_194A)
432 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
433
434 if (dwc->u2ss_inp3_quirk)
435 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
436
437 if (dwc->req_p1p2p3_quirk)
438 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
439
440 if (dwc->del_p1p2p3_quirk)
441 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
442
443 if (dwc->del_phy_power_chg_quirk)
444 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
445
446 if (dwc->lfps_filter_quirk)
447 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
448
449 if (dwc->rx_detect_poll_quirk)
450 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
451
452 if (dwc->tx_de_emphasis_quirk)
453 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
454
455 if (dwc->dis_u3_susphy_quirk)
456 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
457
458 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
459
460 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
461
462 /* Select the HS PHY interface */
463 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
464 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
465 if (dwc->hsphy_interface &&
466 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
467 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
468 break;
469 } else if (dwc->hsphy_interface &&
470 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
471 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
472 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
473 } else {
474 /* Relying on default value. */
475 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
476 break;
477 }
478 /* FALLTHROUGH */
479 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
480 /* Making sure the interface and PHY are operational */
481 ret = dwc3_soft_reset(dwc);
482 if (ret)
483 return ret;
484
485 udelay(1);
486
487 ret = dwc3_ulpi_init(dwc);
488 if (ret)
489 return ret;
490 /* FALLTHROUGH */
491 default:
492 break;
493 }
494
495 /*
496 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
497 * '0' during coreConsultant configuration. So default value will
498 * be '0' when the core is reset. Application needs to set it to
499 * '1' after the core initialization is completed.
500 */
501 if (dwc->revision > DWC3_REVISION_194A)
502 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
503
504 if (dwc->dis_u2_susphy_quirk)
505 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
506
507 if (dwc->dis_enblslpm_quirk)
508 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
509
510 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
511
512 return 0;
513}
514
515/**
516 * dwc3_core_init - Low-level initialization of DWC3 Core
517 * @dwc: Pointer to our controller context structure
518 *
519 * Returns 0 on success otherwise negative errno.
520 */
521static int dwc3_core_init(struct dwc3 *dwc)
522{
523 u32 hwparams4 = dwc->hwparams.hwparams4;
524 u32 reg;
525 int ret;
526
527 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
528 /* This should read as U3 followed by revision number */
529 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
530 /* Detected DWC_usb3 IP */
531 dwc->revision = reg;
532 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
533 /* Detected DWC_usb31 IP */
534 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
535 dwc->revision |= DWC3_REVISION_IS_DWC31;
536 } else {
537 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
538 ret = -ENODEV;
539 goto err0;
540 }
541
542 /*
543 * Write Linux Version Code to our GUID register so it's easy to figure
544 * out which kernel version a bug was found.
545 */
546 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
547
548 /* Handle USB2.0-only core configuration */
549 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
550 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
551 if (dwc->maximum_speed == USB_SPEED_SUPER)
552 dwc->maximum_speed = USB_SPEED_HIGH;
553 }
554
555 /* issue device SoftReset too */
556 ret = dwc3_soft_reset(dwc);
557 if (ret)
558 goto err0;
559
560 ret = dwc3_core_soft_reset(dwc);
561 if (ret)
562 goto err0;
563
564 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
565 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
566
567 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
568 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
569 /**
570 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
571 * issue which would cause xHCI compliance tests to fail.
572 *
573 * Because of that we cannot enable clock gating on such
574 * configurations.
575 *
576 * Refers to:
577 *
578 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
579 * SOF/ITP Mode Used
580 */
581 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
582 dwc->dr_mode == USB_DR_MODE_OTG) &&
583 (dwc->revision >= DWC3_REVISION_210A &&
584 dwc->revision <= DWC3_REVISION_250A))
585 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
586 else
587 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
588 break;
589 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
590 /* enable hibernation here */
591 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
592
593 /*
594 * REVISIT Enabling this bit so that host-mode hibernation
595 * will work. Device-mode hibernation is not yet implemented.
596 */
597 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
598 break;
599 default:
600 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
601 }
602
603 /* check if current dwc3 is on simulation board */
604 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
605 dwc3_trace(trace_dwc3_core,
606 "running on FPGA platform\n");
607 dwc->is_fpga = true;
608 }
609
610 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
611 "disable_scramble cannot be used on non-FPGA builds\n");
612
613 if (dwc->disable_scramble_quirk && dwc->is_fpga)
614 reg |= DWC3_GCTL_DISSCRAMBLE;
615 else
616 reg &= ~DWC3_GCTL_DISSCRAMBLE;
617
618 if (dwc->u2exit_lfps_quirk)
619 reg |= DWC3_GCTL_U2EXIT_LFPS;
620
621 /*
622 * WORKAROUND: DWC3 revisions <1.90a have a bug
623 * where the device can fail to connect at SuperSpeed
624 * and falls back to high-speed mode which causes
625 * the device to enter a Connect/Disconnect loop
626 */
627 if (dwc->revision < DWC3_REVISION_190A)
628 reg |= DWC3_GCTL_U2RSTECN;
629
630 dwc3_core_num_eps(dwc);
631
632 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
633
634 ret = dwc3_alloc_scratch_buffers(dwc);
635 if (ret)
636 goto err1;
637
638 ret = dwc3_setup_scratch_buffers(dwc);
639 if (ret)
640 goto err2;
641
642 return 0;
643
644err2:
645 dwc3_free_scratch_buffers(dwc);
646
647err1:
648 usb_phy_shutdown(dwc->usb2_phy);
649 usb_phy_shutdown(dwc->usb3_phy);
650 phy_exit(dwc->usb2_generic_phy);
651 phy_exit(dwc->usb3_generic_phy);
652
653err0:
654 return ret;
655}
656
657static void dwc3_core_exit(struct dwc3 *dwc)
658{
659 dwc3_free_scratch_buffers(dwc);
660 usb_phy_shutdown(dwc->usb2_phy);
661 usb_phy_shutdown(dwc->usb3_phy);
662 phy_exit(dwc->usb2_generic_phy);
663 phy_exit(dwc->usb3_generic_phy);
664}
665
666static int dwc3_core_get_phy(struct dwc3 *dwc)
667{
668 struct device *dev = dwc->dev;
669 struct device_node *node = dev->of_node;
670 int ret;
671
672 if (node) {
673 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
674 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
675 } else {
676 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
677 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
678 }
679
680 if (IS_ERR(dwc->usb2_phy)) {
681 ret = PTR_ERR(dwc->usb2_phy);
682 if (ret == -ENXIO || ret == -ENODEV) {
683 dwc->usb2_phy = NULL;
684 } else if (ret == -EPROBE_DEFER) {
685 return ret;
686 } else {
687 dev_err(dev, "no usb2 phy configured\n");
688 return ret;
689 }
690 }
691
692 if (IS_ERR(dwc->usb3_phy)) {
693 ret = PTR_ERR(dwc->usb3_phy);
694 if (ret == -ENXIO || ret == -ENODEV) {
695 dwc->usb3_phy = NULL;
696 } else if (ret == -EPROBE_DEFER) {
697 return ret;
698 } else {
699 dev_err(dev, "no usb3 phy configured\n");
700 return ret;
701 }
702 }
703
704 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
705 if (IS_ERR(dwc->usb2_generic_phy)) {
706 ret = PTR_ERR(dwc->usb2_generic_phy);
707 if (ret == -ENOSYS || ret == -ENODEV) {
708 dwc->usb2_generic_phy = NULL;
709 } else if (ret == -EPROBE_DEFER) {
710 return ret;
711 } else {
712 dev_err(dev, "no usb2 phy configured\n");
713 return ret;
714 }
715 }
716
717 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
718 if (IS_ERR(dwc->usb3_generic_phy)) {
719 ret = PTR_ERR(dwc->usb3_generic_phy);
720 if (ret == -ENOSYS || ret == -ENODEV) {
721 dwc->usb3_generic_phy = NULL;
722 } else if (ret == -EPROBE_DEFER) {
723 return ret;
724 } else {
725 dev_err(dev, "no usb3 phy configured\n");
726 return ret;
727 }
728 }
729
730 return 0;
731}
732
733static int dwc3_core_init_mode(struct dwc3 *dwc)
734{
735 struct device *dev = dwc->dev;
736 int ret;
737
738 switch (dwc->dr_mode) {
739 case USB_DR_MODE_PERIPHERAL:
740 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
741 ret = dwc3_gadget_init(dwc);
742 if (ret) {
743 dev_err(dev, "failed to initialize gadget\n");
744 return ret;
745 }
746 break;
747 case USB_DR_MODE_HOST:
748 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
749 ret = dwc3_host_init(dwc);
750 if (ret) {
751 dev_err(dev, "failed to initialize host\n");
752 return ret;
753 }
754 break;
755 case USB_DR_MODE_OTG:
756 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
757 ret = dwc3_host_init(dwc);
758 if (ret) {
759 dev_err(dev, "failed to initialize host\n");
760 return ret;
761 }
762
763 ret = dwc3_gadget_init(dwc);
764 if (ret) {
765 dev_err(dev, "failed to initialize gadget\n");
766 return ret;
767 }
768 break;
769 default:
770 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
771 return -EINVAL;
772 }
773
774 return 0;
775}
776
777static void dwc3_core_exit_mode(struct dwc3 *dwc)
778{
779 switch (dwc->dr_mode) {
780 case USB_DR_MODE_PERIPHERAL:
781 dwc3_gadget_exit(dwc);
782 break;
783 case USB_DR_MODE_HOST:
784 dwc3_host_exit(dwc);
785 break;
786 case USB_DR_MODE_OTG:
787 dwc3_host_exit(dwc);
788 dwc3_gadget_exit(dwc);
789 break;
790 default:
791 /* do nothing */
792 break;
793 }
794}
795
796#define DWC3_ALIGN_MASK (16 - 1)
797
798static int dwc3_probe(struct platform_device *pdev)
799{
800 struct device *dev = &pdev->dev;
801 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
802 struct resource *res;
803 struct dwc3 *dwc;
804 u8 lpm_nyet_threshold;
805 u8 tx_de_emphasis;
806 u8 hird_threshold;
807 u32 fladj = 0;
808
809 int ret;
810
811 void __iomem *regs;
812 void *mem;
813
814 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
815 if (!mem)
816 return -ENOMEM;
817
818 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
819 dwc->mem = mem;
820 dwc->dev = dev;
821
822 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
823 if (!res) {
824 dev_err(dev, "missing IRQ\n");
825 return -ENODEV;
826 }
827 dwc->xhci_resources[1].start = res->start;
828 dwc->xhci_resources[1].end = res->end;
829 dwc->xhci_resources[1].flags = res->flags;
830 dwc->xhci_resources[1].name = res->name;
831
832 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
833 if (!res) {
834 dev_err(dev, "missing memory resource\n");
835 return -ENODEV;
836 }
837
838 dwc->xhci_resources[0].start = res->start;
839 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
840 DWC3_XHCI_REGS_END;
841 dwc->xhci_resources[0].flags = res->flags;
842 dwc->xhci_resources[0].name = res->name;
843
844 res->start += DWC3_GLOBALS_REGS_START;
845
846 /*
847 * Request memory region but exclude xHCI regs,
848 * since it will be requested by the xhci-plat driver.
849 */
850 regs = devm_ioremap_resource(dev, res);
851 if (IS_ERR(regs)) {
852 ret = PTR_ERR(regs);
853 goto err0;
854 }
855
856 dwc->regs = regs;
857 dwc->regs_size = resource_size(res);
858
859 /* default to highest possible threshold */
860 lpm_nyet_threshold = 0xff;
861
862 /* default to -3.5dB de-emphasis */
863 tx_de_emphasis = 1;
864
865 /*
866 * default to assert utmi_sleep_n and use maximum allowed HIRD
867 * threshold value of 0b1100
868 */
869 hird_threshold = 12;
870
871 dwc->maximum_speed = usb_get_maximum_speed(dev);
872 dwc->dr_mode = usb_get_dr_mode(dev);
873
874 dwc->has_lpm_erratum = device_property_read_bool(dev,
875 "snps,has-lpm-erratum");
876 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
877 &lpm_nyet_threshold);
878 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
879 "snps,is-utmi-l1-suspend");
880 device_property_read_u8(dev, "snps,hird-threshold",
881 &hird_threshold);
882 dwc->usb3_lpm_capable = device_property_read_bool(dev,
883 "snps,usb3_lpm_capable");
884
885 dwc->needs_fifo_resize = device_property_read_bool(dev,
886 "tx-fifo-resize");
887
888 dwc->disable_scramble_quirk = device_property_read_bool(dev,
889 "snps,disable_scramble_quirk");
890 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
891 "snps,u2exit_lfps_quirk");
892 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
893 "snps,u2ss_inp3_quirk");
894 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
895 "snps,req_p1p2p3_quirk");
896 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
897 "snps,del_p1p2p3_quirk");
898 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
899 "snps,del_phy_power_chg_quirk");
900 dwc->lfps_filter_quirk = device_property_read_bool(dev,
901 "snps,lfps_filter_quirk");
902 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
903 "snps,rx_detect_poll_quirk");
904 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
905 "snps,dis_u3_susphy_quirk");
906 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
907 "snps,dis_u2_susphy_quirk");
908 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
909 "snps,dis_enblslpm_quirk");
910
911 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
912 "snps,tx_de_emphasis_quirk");
913 device_property_read_u8(dev, "snps,tx_de_emphasis",
914 &tx_de_emphasis);
915 device_property_read_string(dev, "snps,hsphy_interface",
916 &dwc->hsphy_interface);
917 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
918 &fladj);
919
920 if (pdata) {
921 dwc->maximum_speed = pdata->maximum_speed;
922 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
923 if (pdata->lpm_nyet_threshold)
924 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
925 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
926 if (pdata->hird_threshold)
927 hird_threshold = pdata->hird_threshold;
928
929 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
930 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
931 dwc->dr_mode = pdata->dr_mode;
932
933 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
934 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
935 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
936 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
937 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
938 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
939 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
940 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
941 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
942 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
943 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
944
945 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
946 if (pdata->tx_de_emphasis)
947 tx_de_emphasis = pdata->tx_de_emphasis;
948
949 dwc->hsphy_interface = pdata->hsphy_interface;
950 fladj = pdata->fladj_value;
951 }
952
953 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
954 dwc->tx_de_emphasis = tx_de_emphasis;
955
956 dwc->hird_threshold = hird_threshold
957 | (dwc->is_utmi_l1_suspend << 4);
958
959 platform_set_drvdata(pdev, dwc);
960 dwc3_cache_hwparams(dwc);
961
962 ret = dwc3_phy_setup(dwc);
963 if (ret)
964 goto err0;
965
966 ret = dwc3_core_get_phy(dwc);
967 if (ret)
968 goto err0;
969
970 spin_lock_init(&dwc->lock);
971
972 if (!dev->dma_mask) {
973 dev->dma_mask = dev->parent->dma_mask;
974 dev->dma_parms = dev->parent->dma_parms;
975 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
976 }
977
978 pm_runtime_enable(dev);
979 pm_runtime_get_sync(dev);
980 pm_runtime_forbid(dev);
981
982 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
983 if (ret) {
984 dev_err(dwc->dev, "failed to allocate event buffers\n");
985 ret = -ENOMEM;
986 goto err1;
987 }
988
989 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
990 dwc->dr_mode = USB_DR_MODE_HOST;
991 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
992 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
993
994 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
995 dwc->dr_mode = USB_DR_MODE_OTG;
996
997 ret = dwc3_core_init(dwc);
998 if (ret) {
999 dev_err(dev, "failed to initialize core\n");
1000 goto err1;
1001 }
1002
1003 /* Check the maximum_speed parameter */
1004 switch (dwc->maximum_speed) {
1005 case USB_SPEED_LOW:
1006 case USB_SPEED_FULL:
1007 case USB_SPEED_HIGH:
1008 case USB_SPEED_SUPER:
1009 case USB_SPEED_SUPER_PLUS:
1010 break;
1011 default:
1012 dev_err(dev, "invalid maximum_speed parameter %d\n",
1013 dwc->maximum_speed);
1014 /* fall through */
1015 case USB_SPEED_UNKNOWN:
1016 /* default to superspeed */
1017 dwc->maximum_speed = USB_SPEED_SUPER;
1018
1019 /*
1020 * default to superspeed plus if we are capable.
1021 */
1022 if (dwc3_is_usb31(dwc) &&
1023 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1024 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1025 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1026
1027 break;
1028 }
1029
1030 /* Adjust Frame Length */
1031 dwc3_frame_length_adjustment(dwc, fladj);
1032
1033 usb_phy_set_suspend(dwc->usb2_phy, 0);
1034 usb_phy_set_suspend(dwc->usb3_phy, 0);
1035 ret = phy_power_on(dwc->usb2_generic_phy);
1036 if (ret < 0)
1037 goto err2;
1038
1039 ret = phy_power_on(dwc->usb3_generic_phy);
1040 if (ret < 0)
1041 goto err3;
1042
1043 ret = dwc3_event_buffers_setup(dwc);
1044 if (ret) {
1045 dev_err(dwc->dev, "failed to setup event buffers\n");
1046 goto err4;
1047 }
1048
1049 ret = dwc3_core_init_mode(dwc);
1050 if (ret)
1051 goto err5;
1052
1053 ret = dwc3_debugfs_init(dwc);
1054 if (ret) {
1055 dev_err(dev, "failed to initialize debugfs\n");
1056 goto err6;
1057 }
1058
1059 pm_runtime_allow(dev);
1060
1061 return 0;
1062
1063err6:
1064 dwc3_core_exit_mode(dwc);
1065
1066err5:
1067 dwc3_event_buffers_cleanup(dwc);
1068
1069err4:
1070 phy_power_off(dwc->usb3_generic_phy);
1071
1072err3:
1073 phy_power_off(dwc->usb2_generic_phy);
1074
1075err2:
1076 usb_phy_set_suspend(dwc->usb2_phy, 1);
1077 usb_phy_set_suspend(dwc->usb3_phy, 1);
1078 dwc3_core_exit(dwc);
1079
1080err1:
1081 dwc3_free_event_buffers(dwc);
1082 dwc3_ulpi_exit(dwc);
1083
1084err0:
1085 /*
1086 * restore res->start back to its original value so that, in case the
1087 * probe is deferred, we don't end up getting error in request the
1088 * memory region the next time probe is called.
1089 */
1090 res->start -= DWC3_GLOBALS_REGS_START;
1091
1092 return ret;
1093}
1094
1095static int dwc3_remove(struct platform_device *pdev)
1096{
1097 struct dwc3 *dwc = platform_get_drvdata(pdev);
1098 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099
1100 /*
1101 * restore res->start back to its original value so that, in case the
1102 * probe is deferred, we don't end up getting error in request the
1103 * memory region the next time probe is called.
1104 */
1105 res->start -= DWC3_GLOBALS_REGS_START;
1106
1107 dwc3_debugfs_exit(dwc);
1108 dwc3_core_exit_mode(dwc);
1109 dwc3_event_buffers_cleanup(dwc);
1110 dwc3_free_event_buffers(dwc);
1111
1112 usb_phy_set_suspend(dwc->usb2_phy, 1);
1113 usb_phy_set_suspend(dwc->usb3_phy, 1);
1114 phy_power_off(dwc->usb2_generic_phy);
1115 phy_power_off(dwc->usb3_generic_phy);
1116
1117 dwc3_core_exit(dwc);
1118 dwc3_ulpi_exit(dwc);
1119
1120 pm_runtime_put_sync(&pdev->dev);
1121 pm_runtime_disable(&pdev->dev);
1122
1123 return 0;
1124}
1125
1126#ifdef CONFIG_PM_SLEEP
1127static int dwc3_suspend(struct device *dev)
1128{
1129 struct dwc3 *dwc = dev_get_drvdata(dev);
1130 unsigned long flags;
1131
1132 spin_lock_irqsave(&dwc->lock, flags);
1133
1134 switch (dwc->dr_mode) {
1135 case USB_DR_MODE_PERIPHERAL:
1136 case USB_DR_MODE_OTG:
1137 dwc3_gadget_suspend(dwc);
1138 /* FALLTHROUGH */
1139 case USB_DR_MODE_HOST:
1140 default:
1141 dwc3_event_buffers_cleanup(dwc);
1142 break;
1143 }
1144
1145 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1146 spin_unlock_irqrestore(&dwc->lock, flags);
1147
1148 usb_phy_shutdown(dwc->usb3_phy);
1149 usb_phy_shutdown(dwc->usb2_phy);
1150 phy_exit(dwc->usb2_generic_phy);
1151 phy_exit(dwc->usb3_generic_phy);
1152
1153 usb_phy_set_suspend(dwc->usb2_phy, 1);
1154 usb_phy_set_suspend(dwc->usb3_phy, 1);
1155 WARN_ON(phy_power_off(dwc->usb2_generic_phy) < 0);
1156 WARN_ON(phy_power_off(dwc->usb3_generic_phy) < 0);
1157
1158 pinctrl_pm_select_sleep_state(dev);
1159
1160 return 0;
1161}
1162
1163static int dwc3_resume(struct device *dev)
1164{
1165 struct dwc3 *dwc = dev_get_drvdata(dev);
1166 unsigned long flags;
1167 int ret;
1168
1169 pinctrl_pm_select_default_state(dev);
1170
1171 usb_phy_set_suspend(dwc->usb2_phy, 0);
1172 usb_phy_set_suspend(dwc->usb3_phy, 0);
1173 ret = phy_power_on(dwc->usb2_generic_phy);
1174 if (ret < 0)
1175 return ret;
1176
1177 ret = phy_power_on(dwc->usb3_generic_phy);
1178 if (ret < 0)
1179 goto err_usb2phy_power;
1180
1181 usb_phy_init(dwc->usb3_phy);
1182 usb_phy_init(dwc->usb2_phy);
1183 ret = phy_init(dwc->usb2_generic_phy);
1184 if (ret < 0)
1185 goto err_usb3phy_power;
1186
1187 ret = phy_init(dwc->usb3_generic_phy);
1188 if (ret < 0)
1189 goto err_usb2phy_init;
1190
1191 spin_lock_irqsave(&dwc->lock, flags);
1192
1193 dwc3_event_buffers_setup(dwc);
1194 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1195
1196 switch (dwc->dr_mode) {
1197 case USB_DR_MODE_PERIPHERAL:
1198 case USB_DR_MODE_OTG:
1199 dwc3_gadget_resume(dwc);
1200 /* FALLTHROUGH */
1201 case USB_DR_MODE_HOST:
1202 default:
1203 /* do nothing */
1204 break;
1205 }
1206
1207 spin_unlock_irqrestore(&dwc->lock, flags);
1208
1209 pm_runtime_disable(dev);
1210 pm_runtime_set_active(dev);
1211 pm_runtime_enable(dev);
1212
1213 return 0;
1214
1215err_usb2phy_init:
1216 phy_exit(dwc->usb2_generic_phy);
1217
1218err_usb3phy_power:
1219 phy_power_off(dwc->usb3_generic_phy);
1220
1221err_usb2phy_power:
1222 phy_power_off(dwc->usb2_generic_phy);
1223
1224 return ret;
1225}
1226
1227static const struct dev_pm_ops dwc3_dev_pm_ops = {
1228 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1229};
1230
1231#define DWC3_PM_OPS &(dwc3_dev_pm_ops)
1232#else
1233#define DWC3_PM_OPS NULL
1234#endif
1235
1236#ifdef CONFIG_OF
1237static const struct of_device_id of_dwc3_match[] = {
1238 {
1239 .compatible = "snps,dwc3"
1240 },
1241 {
1242 .compatible = "synopsys,dwc3"
1243 },
1244 { },
1245};
1246MODULE_DEVICE_TABLE(of, of_dwc3_match);
1247#endif
1248
1249#ifdef CONFIG_ACPI
1250
1251#define ACPI_ID_INTEL_BSW "808622B7"
1252
1253static const struct acpi_device_id dwc3_acpi_match[] = {
1254 { ACPI_ID_INTEL_BSW, 0 },
1255 { },
1256};
1257MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1258#endif
1259
1260static struct platform_driver dwc3_driver = {
1261 .probe = dwc3_probe,
1262 .remove = dwc3_remove,
1263 .driver = {
1264 .name = "dwc3",
1265 .of_match_table = of_match_ptr(of_dwc3_match),
1266 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1267 .pm = DWC3_PM_OPS,
1268 },
1269};
1270
1271module_platform_driver(dwc3_driver);
1272
1273MODULE_ALIAS("platform:dwc3");
1274MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1275MODULE_LICENSE("GPL v2");
1276MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1// SPDX-License-Identifier: GPL-2.0
2/**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/clk.h>
12#include <linux/version.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/of.h>
26#include <linux/acpi.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/reset.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/of.h>
33#include <linux/usb/otg.h>
34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "debug.h"
40
41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43/**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
47static int dwc3_get_dr_mode(struct dwc3 *dwc)
48{
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 dwc->revision >= DWC3_REVISION_330A)
89 mode = USB_DR_MODE_PERIPHERAL;
90 }
91
92 if (mode != dwc->dr_mode) {
93 dev_warn(dev,
94 "Configuration mismatch. dr_mode forced to %s\n",
95 mode == USB_DR_MODE_HOST ? "host" : "gadget");
96
97 dwc->dr_mode = mode;
98 }
99
100 return 0;
101}
102
103void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
104{
105 u32 reg;
106
107 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
108 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
109 reg |= DWC3_GCTL_PRTCAPDIR(mode);
110 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
111
112 dwc->current_dr_role = mode;
113}
114
115static void __dwc3_set_mode(struct work_struct *work)
116{
117 struct dwc3 *dwc = work_to_dwc(work);
118 unsigned long flags;
119 int ret;
120
121 if (dwc->dr_mode != USB_DR_MODE_OTG)
122 return;
123
124 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
125 dwc3_otg_update(dwc, 0);
126
127 if (!dwc->desired_dr_role)
128 return;
129
130 if (dwc->desired_dr_role == dwc->current_dr_role)
131 return;
132
133 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
134 return;
135
136 switch (dwc->current_dr_role) {
137 case DWC3_GCTL_PRTCAP_HOST:
138 dwc3_host_exit(dwc);
139 break;
140 case DWC3_GCTL_PRTCAP_DEVICE:
141 dwc3_gadget_exit(dwc);
142 dwc3_event_buffers_cleanup(dwc);
143 break;
144 case DWC3_GCTL_PRTCAP_OTG:
145 dwc3_otg_exit(dwc);
146 spin_lock_irqsave(&dwc->lock, flags);
147 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
148 spin_unlock_irqrestore(&dwc->lock, flags);
149 dwc3_otg_update(dwc, 1);
150 break;
151 default:
152 break;
153 }
154
155 spin_lock_irqsave(&dwc->lock, flags);
156
157 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
158
159 spin_unlock_irqrestore(&dwc->lock, flags);
160
161 switch (dwc->desired_dr_role) {
162 case DWC3_GCTL_PRTCAP_HOST:
163 ret = dwc3_host_init(dwc);
164 if (ret) {
165 dev_err(dwc->dev, "failed to initialize host\n");
166 } else {
167 if (dwc->usb2_phy)
168 otg_set_vbus(dwc->usb2_phy->otg, true);
169 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
170 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
171 }
172 break;
173 case DWC3_GCTL_PRTCAP_DEVICE:
174 dwc3_event_buffers_setup(dwc);
175
176 if (dwc->usb2_phy)
177 otg_set_vbus(dwc->usb2_phy->otg, false);
178 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
179 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
180
181 ret = dwc3_gadget_init(dwc);
182 if (ret)
183 dev_err(dwc->dev, "failed to initialize peripheral\n");
184 break;
185 case DWC3_GCTL_PRTCAP_OTG:
186 dwc3_otg_init(dwc);
187 dwc3_otg_update(dwc, 0);
188 break;
189 default:
190 break;
191 }
192
193}
194
195void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
196{
197 unsigned long flags;
198
199 spin_lock_irqsave(&dwc->lock, flags);
200 dwc->desired_dr_role = mode;
201 spin_unlock_irqrestore(&dwc->lock, flags);
202
203 queue_work(system_freezable_wq, &dwc->drd_work);
204}
205
206u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
207{
208 struct dwc3 *dwc = dep->dwc;
209 u32 reg;
210
211 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
212 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
213 DWC3_GDBGFIFOSPACE_TYPE(type));
214
215 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
216
217 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
218}
219
220/**
221 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
222 * @dwc: pointer to our context structure
223 */
224static int dwc3_core_soft_reset(struct dwc3 *dwc)
225{
226 u32 reg;
227 int retries = 1000;
228 int ret;
229
230 usb_phy_init(dwc->usb2_phy);
231 usb_phy_init(dwc->usb3_phy);
232 ret = phy_init(dwc->usb2_generic_phy);
233 if (ret < 0)
234 return ret;
235
236 ret = phy_init(dwc->usb3_generic_phy);
237 if (ret < 0) {
238 phy_exit(dwc->usb2_generic_phy);
239 return ret;
240 }
241
242 /*
243 * We're resetting only the device side because, if we're in host mode,
244 * XHCI driver will reset the host block. If dwc3 was configured for
245 * host-only mode, then we can return early.
246 */
247 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
248 return 0;
249
250 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
251 reg |= DWC3_DCTL_CSFTRST;
252 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
253
254 /*
255 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
256 * is cleared only after all the clocks are synchronized. This can
257 * take a little more than 50ms. Set the polling rate at 20ms
258 * for 10 times instead.
259 */
260 if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A)
261 retries = 10;
262
263 do {
264 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
265 if (!(reg & DWC3_DCTL_CSFTRST))
266 goto done;
267
268 if (dwc3_is_usb31(dwc) &&
269 dwc->revision >= DWC3_USB31_REVISION_190A)
270 msleep(20);
271 else
272 udelay(1);
273 } while (--retries);
274
275 phy_exit(dwc->usb3_generic_phy);
276 phy_exit(dwc->usb2_generic_phy);
277
278 return -ETIMEDOUT;
279
280done:
281 /*
282 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
283 * is cleared, we must wait at least 50ms before accessing the PHY
284 * domain (synchronization delay).
285 */
286 if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A)
287 msleep(50);
288
289 return 0;
290}
291
292static const struct clk_bulk_data dwc3_core_clks[] = {
293 { .id = "ref" },
294 { .id = "bus_early" },
295 { .id = "suspend" },
296};
297
298/*
299 * dwc3_frame_length_adjustment - Adjusts frame length if required
300 * @dwc3: Pointer to our controller context structure
301 */
302static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
303{
304 u32 reg;
305 u32 dft;
306
307 if (dwc->revision < DWC3_REVISION_250A)
308 return;
309
310 if (dwc->fladj == 0)
311 return;
312
313 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
314 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
315 if (dft != dwc->fladj) {
316 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
317 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
318 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
319 }
320}
321
322/**
323 * dwc3_free_one_event_buffer - Frees one event buffer
324 * @dwc: Pointer to our controller context structure
325 * @evt: Pointer to event buffer to be freed
326 */
327static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
328 struct dwc3_event_buffer *evt)
329{
330 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
331}
332
333/**
334 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
335 * @dwc: Pointer to our controller context structure
336 * @length: size of the event buffer
337 *
338 * Returns a pointer to the allocated event buffer structure on success
339 * otherwise ERR_PTR(errno).
340 */
341static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
342 unsigned length)
343{
344 struct dwc3_event_buffer *evt;
345
346 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
347 if (!evt)
348 return ERR_PTR(-ENOMEM);
349
350 evt->dwc = dwc;
351 evt->length = length;
352 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
353 if (!evt->cache)
354 return ERR_PTR(-ENOMEM);
355
356 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
357 &evt->dma, GFP_KERNEL);
358 if (!evt->buf)
359 return ERR_PTR(-ENOMEM);
360
361 return evt;
362}
363
364/**
365 * dwc3_free_event_buffers - frees all allocated event buffers
366 * @dwc: Pointer to our controller context structure
367 */
368static void dwc3_free_event_buffers(struct dwc3 *dwc)
369{
370 struct dwc3_event_buffer *evt;
371
372 evt = dwc->ev_buf;
373 if (evt)
374 dwc3_free_one_event_buffer(dwc, evt);
375}
376
377/**
378 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
379 * @dwc: pointer to our controller context structure
380 * @length: size of event buffer
381 *
382 * Returns 0 on success otherwise negative errno. In the error case, dwc
383 * may contain some buffers allocated but not all which were requested.
384 */
385static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
386{
387 struct dwc3_event_buffer *evt;
388
389 evt = dwc3_alloc_one_event_buffer(dwc, length);
390 if (IS_ERR(evt)) {
391 dev_err(dwc->dev, "can't allocate event buffer\n");
392 return PTR_ERR(evt);
393 }
394 dwc->ev_buf = evt;
395
396 return 0;
397}
398
399/**
400 * dwc3_event_buffers_setup - setup our allocated event buffers
401 * @dwc: pointer to our controller context structure
402 *
403 * Returns 0 on success otherwise negative errno.
404 */
405int dwc3_event_buffers_setup(struct dwc3 *dwc)
406{
407 struct dwc3_event_buffer *evt;
408
409 evt = dwc->ev_buf;
410 evt->lpos = 0;
411 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
412 lower_32_bits(evt->dma));
413 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
414 upper_32_bits(evt->dma));
415 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
416 DWC3_GEVNTSIZ_SIZE(evt->length));
417 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
418
419 return 0;
420}
421
422void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
423{
424 struct dwc3_event_buffer *evt;
425
426 evt = dwc->ev_buf;
427
428 evt->lpos = 0;
429
430 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
431 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
432 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
433 | DWC3_GEVNTSIZ_SIZE(0));
434 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
435}
436
437static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
438{
439 if (!dwc->has_hibernation)
440 return 0;
441
442 if (!dwc->nr_scratch)
443 return 0;
444
445 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
446 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
447 if (!dwc->scratchbuf)
448 return -ENOMEM;
449
450 return 0;
451}
452
453static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
454{
455 dma_addr_t scratch_addr;
456 u32 param;
457 int ret;
458
459 if (!dwc->has_hibernation)
460 return 0;
461
462 if (!dwc->nr_scratch)
463 return 0;
464
465 /* should never fall here */
466 if (!WARN_ON(dwc->scratchbuf))
467 return 0;
468
469 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
470 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
471 DMA_BIDIRECTIONAL);
472 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
473 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
474 ret = -EFAULT;
475 goto err0;
476 }
477
478 dwc->scratch_addr = scratch_addr;
479
480 param = lower_32_bits(scratch_addr);
481
482 ret = dwc3_send_gadget_generic_command(dwc,
483 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
484 if (ret < 0)
485 goto err1;
486
487 param = upper_32_bits(scratch_addr);
488
489 ret = dwc3_send_gadget_generic_command(dwc,
490 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
491 if (ret < 0)
492 goto err1;
493
494 return 0;
495
496err1:
497 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
498 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
499
500err0:
501 return ret;
502}
503
504static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
505{
506 if (!dwc->has_hibernation)
507 return;
508
509 if (!dwc->nr_scratch)
510 return;
511
512 /* should never fall here */
513 if (!WARN_ON(dwc->scratchbuf))
514 return;
515
516 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
517 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
518 kfree(dwc->scratchbuf);
519}
520
521static void dwc3_core_num_eps(struct dwc3 *dwc)
522{
523 struct dwc3_hwparams *parms = &dwc->hwparams;
524
525 dwc->num_eps = DWC3_NUM_EPS(parms);
526}
527
528static void dwc3_cache_hwparams(struct dwc3 *dwc)
529{
530 struct dwc3_hwparams *parms = &dwc->hwparams;
531
532 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
533 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
534 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
535 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
536 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
537 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
538 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
539 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
540 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
541}
542
543static int dwc3_core_ulpi_init(struct dwc3 *dwc)
544{
545 int intf;
546 int ret = 0;
547
548 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
549
550 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
551 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
552 dwc->hsphy_interface &&
553 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
554 ret = dwc3_ulpi_init(dwc);
555
556 return ret;
557}
558
559/**
560 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
561 * @dwc: Pointer to our controller context structure
562 *
563 * Returns 0 on success. The USB PHY interfaces are configured but not
564 * initialized. The PHY interfaces and the PHYs get initialized together with
565 * the core in dwc3_core_init.
566 */
567static int dwc3_phy_setup(struct dwc3 *dwc)
568{
569 u32 reg;
570
571 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
572
573 /*
574 * Make sure UX_EXIT_PX is cleared as that causes issues with some
575 * PHYs. Also, this bit is not supposed to be used in normal operation.
576 */
577 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
578
579 /*
580 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
581 * to '0' during coreConsultant configuration. So default value
582 * will be '0' when the core is reset. Application needs to set it
583 * to '1' after the core initialization is completed.
584 */
585 if (dwc->revision > DWC3_REVISION_194A)
586 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
587
588 if (dwc->u2ss_inp3_quirk)
589 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
590
591 if (dwc->dis_rxdet_inp3_quirk)
592 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
593
594 if (dwc->req_p1p2p3_quirk)
595 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
596
597 if (dwc->del_p1p2p3_quirk)
598 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
599
600 if (dwc->del_phy_power_chg_quirk)
601 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
602
603 if (dwc->lfps_filter_quirk)
604 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
605
606 if (dwc->rx_detect_poll_quirk)
607 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
608
609 if (dwc->tx_de_emphasis_quirk)
610 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
611
612 if (dwc->dis_u3_susphy_quirk)
613 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
614
615 if (dwc->dis_del_phy_power_chg_quirk)
616 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
617
618 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
619
620 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
621
622 /* Select the HS PHY interface */
623 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
624 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
625 if (dwc->hsphy_interface &&
626 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
627 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
628 break;
629 } else if (dwc->hsphy_interface &&
630 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
631 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
632 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
633 } else {
634 /* Relying on default value. */
635 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
636 break;
637 }
638 /* FALLTHROUGH */
639 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
640 /* FALLTHROUGH */
641 default:
642 break;
643 }
644
645 switch (dwc->hsphy_mode) {
646 case USBPHY_INTERFACE_MODE_UTMI:
647 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
648 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
649 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
650 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
651 break;
652 case USBPHY_INTERFACE_MODE_UTMIW:
653 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
654 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
655 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
656 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
657 break;
658 default:
659 break;
660 }
661
662 /*
663 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
664 * '0' during coreConsultant configuration. So default value will
665 * be '0' when the core is reset. Application needs to set it to
666 * '1' after the core initialization is completed.
667 */
668 if (dwc->revision > DWC3_REVISION_194A)
669 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
670
671 if (dwc->dis_u2_susphy_quirk)
672 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
673
674 if (dwc->dis_enblslpm_quirk)
675 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
676 else
677 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
678
679 if (dwc->dis_u2_freeclk_exists_quirk)
680 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
681
682 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
683
684 return 0;
685}
686
687static void dwc3_core_exit(struct dwc3 *dwc)
688{
689 dwc3_event_buffers_cleanup(dwc);
690
691 usb_phy_shutdown(dwc->usb2_phy);
692 usb_phy_shutdown(dwc->usb3_phy);
693 phy_exit(dwc->usb2_generic_phy);
694 phy_exit(dwc->usb3_generic_phy);
695
696 usb_phy_set_suspend(dwc->usb2_phy, 1);
697 usb_phy_set_suspend(dwc->usb3_phy, 1);
698 phy_power_off(dwc->usb2_generic_phy);
699 phy_power_off(dwc->usb3_generic_phy);
700 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
701 reset_control_assert(dwc->reset);
702}
703
704static bool dwc3_core_is_valid(struct dwc3 *dwc)
705{
706 u32 reg;
707
708 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
709
710 /* This should read as U3 followed by revision number */
711 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
712 /* Detected DWC_usb3 IP */
713 dwc->revision = reg;
714 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
715 /* Detected DWC_usb31 IP */
716 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
717 dwc->revision |= DWC3_REVISION_IS_DWC31;
718 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
719 } else {
720 return false;
721 }
722
723 return true;
724}
725
726static void dwc3_core_setup_global_control(struct dwc3 *dwc)
727{
728 u32 hwparams4 = dwc->hwparams.hwparams4;
729 u32 reg;
730
731 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
732 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
733
734 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
735 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
736 /**
737 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
738 * issue which would cause xHCI compliance tests to fail.
739 *
740 * Because of that we cannot enable clock gating on such
741 * configurations.
742 *
743 * Refers to:
744 *
745 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
746 * SOF/ITP Mode Used
747 */
748 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
749 dwc->dr_mode == USB_DR_MODE_OTG) &&
750 (dwc->revision >= DWC3_REVISION_210A &&
751 dwc->revision <= DWC3_REVISION_250A))
752 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
753 else
754 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
755 break;
756 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
757 /* enable hibernation here */
758 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
759
760 /*
761 * REVISIT Enabling this bit so that host-mode hibernation
762 * will work. Device-mode hibernation is not yet implemented.
763 */
764 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
765 break;
766 default:
767 /* nothing */
768 break;
769 }
770
771 /* check if current dwc3 is on simulation board */
772 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
773 dev_info(dwc->dev, "Running with FPGA optimizations\n");
774 dwc->is_fpga = true;
775 }
776
777 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
778 "disable_scramble cannot be used on non-FPGA builds\n");
779
780 if (dwc->disable_scramble_quirk && dwc->is_fpga)
781 reg |= DWC3_GCTL_DISSCRAMBLE;
782 else
783 reg &= ~DWC3_GCTL_DISSCRAMBLE;
784
785 if (dwc->u2exit_lfps_quirk)
786 reg |= DWC3_GCTL_U2EXIT_LFPS;
787
788 /*
789 * WORKAROUND: DWC3 revisions <1.90a have a bug
790 * where the device can fail to connect at SuperSpeed
791 * and falls back to high-speed mode which causes
792 * the device to enter a Connect/Disconnect loop
793 */
794 if (dwc->revision < DWC3_REVISION_190A)
795 reg |= DWC3_GCTL_U2RSTECN;
796
797 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
798}
799
800static int dwc3_core_get_phy(struct dwc3 *dwc);
801static int dwc3_core_ulpi_init(struct dwc3 *dwc);
802
803/* set global incr burst type configuration registers */
804static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
805{
806 struct device *dev = dwc->dev;
807 /* incrx_mode : for INCR burst type. */
808 bool incrx_mode;
809 /* incrx_size : for size of INCRX burst. */
810 u32 incrx_size;
811 u32 *vals;
812 u32 cfg;
813 int ntype;
814 int ret;
815 int i;
816
817 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
818
819 /*
820 * Handle property "snps,incr-burst-type-adjustment".
821 * Get the number of value from this property:
822 * result <= 0, means this property is not supported.
823 * result = 1, means INCRx burst mode supported.
824 * result > 1, means undefined length burst mode supported.
825 */
826 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
827 if (ntype <= 0)
828 return;
829
830 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
831 if (!vals) {
832 dev_err(dev, "Error to get memory\n");
833 return;
834 }
835
836 /* Get INCR burst type, and parse it */
837 ret = device_property_read_u32_array(dev,
838 "snps,incr-burst-type-adjustment", vals, ntype);
839 if (ret) {
840 kfree(vals);
841 dev_err(dev, "Error to get property\n");
842 return;
843 }
844
845 incrx_size = *vals;
846
847 if (ntype > 1) {
848 /* INCRX (undefined length) burst mode */
849 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
850 for (i = 1; i < ntype; i++) {
851 if (vals[i] > incrx_size)
852 incrx_size = vals[i];
853 }
854 } else {
855 /* INCRX burst mode */
856 incrx_mode = INCRX_BURST_MODE;
857 }
858
859 kfree(vals);
860
861 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
862 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
863 if (incrx_mode)
864 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
865 switch (incrx_size) {
866 case 256:
867 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
868 break;
869 case 128:
870 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
871 break;
872 case 64:
873 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
874 break;
875 case 32:
876 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
877 break;
878 case 16:
879 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
880 break;
881 case 8:
882 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
883 break;
884 case 4:
885 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
886 break;
887 case 1:
888 break;
889 default:
890 dev_err(dev, "Invalid property\n");
891 break;
892 }
893
894 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
895}
896
897/**
898 * dwc3_core_init - Low-level initialization of DWC3 Core
899 * @dwc: Pointer to our controller context structure
900 *
901 * Returns 0 on success otherwise negative errno.
902 */
903static int dwc3_core_init(struct dwc3 *dwc)
904{
905 u32 reg;
906 int ret;
907
908 /*
909 * Write Linux Version Code to our GUID register so it's easy to figure
910 * out which kernel version a bug was found.
911 */
912 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
913
914 /* Handle USB2.0-only core configuration */
915 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
916 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
917 if (dwc->maximum_speed == USB_SPEED_SUPER)
918 dwc->maximum_speed = USB_SPEED_HIGH;
919 }
920
921 ret = dwc3_phy_setup(dwc);
922 if (ret)
923 goto err0;
924
925 if (!dwc->ulpi_ready) {
926 ret = dwc3_core_ulpi_init(dwc);
927 if (ret)
928 goto err0;
929 dwc->ulpi_ready = true;
930 }
931
932 if (!dwc->phys_ready) {
933 ret = dwc3_core_get_phy(dwc);
934 if (ret)
935 goto err0a;
936 dwc->phys_ready = true;
937 }
938
939 ret = dwc3_core_soft_reset(dwc);
940 if (ret)
941 goto err0a;
942
943 dwc3_core_setup_global_control(dwc);
944 dwc3_core_num_eps(dwc);
945
946 ret = dwc3_setup_scratch_buffers(dwc);
947 if (ret)
948 goto err1;
949
950 /* Adjust Frame Length */
951 dwc3_frame_length_adjustment(dwc);
952
953 dwc3_set_incr_burst_type(dwc);
954
955 usb_phy_set_suspend(dwc->usb2_phy, 0);
956 usb_phy_set_suspend(dwc->usb3_phy, 0);
957 ret = phy_power_on(dwc->usb2_generic_phy);
958 if (ret < 0)
959 goto err2;
960
961 ret = phy_power_on(dwc->usb3_generic_phy);
962 if (ret < 0)
963 goto err3;
964
965 ret = dwc3_event_buffers_setup(dwc);
966 if (ret) {
967 dev_err(dwc->dev, "failed to setup event buffers\n");
968 goto err4;
969 }
970
971 /*
972 * ENDXFER polling is available on version 3.10a and later of
973 * the DWC_usb3 controller. It is NOT available in the
974 * DWC_usb31 controller.
975 */
976 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
977 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
978 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
979 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
980 }
981
982 if (dwc->revision >= DWC3_REVISION_250A) {
983 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
984
985 /*
986 * Enable hardware control of sending remote wakeup
987 * in HS when the device is in the L1 state.
988 */
989 if (dwc->revision >= DWC3_REVISION_290A)
990 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
991
992 if (dwc->dis_tx_ipgap_linecheck_quirk)
993 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
994
995 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
996 }
997
998 if (dwc->dr_mode == USB_DR_MODE_HOST ||
999 dwc->dr_mode == USB_DR_MODE_OTG) {
1000 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1001
1002 /*
1003 * Enable Auto retry Feature to make the controller operating in
1004 * Host mode on seeing transaction errors(CRC errors or internal
1005 * overrun scenerios) on IN transfers to reply to the device
1006 * with a non-terminating retry ACK (i.e, an ACK transcation
1007 * packet with Retry=1 & Nump != 0)
1008 */
1009 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1010
1011 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1012 }
1013
1014 /*
1015 * Must config both number of packets and max burst settings to enable
1016 * RX and/or TX threshold.
1017 */
1018 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1019 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1020 u8 rx_maxburst = dwc->rx_max_burst_prd;
1021 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1022 u8 tx_maxburst = dwc->tx_max_burst_prd;
1023
1024 if (rx_thr_num && rx_maxburst) {
1025 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1026 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1027
1028 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1029 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1030
1031 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1032 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1033
1034 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1035 }
1036
1037 if (tx_thr_num && tx_maxburst) {
1038 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1039 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1040
1041 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1042 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1043
1044 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1045 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1046
1047 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1048 }
1049 }
1050
1051 return 0;
1052
1053err4:
1054 phy_power_off(dwc->usb3_generic_phy);
1055
1056err3:
1057 phy_power_off(dwc->usb2_generic_phy);
1058
1059err2:
1060 usb_phy_set_suspend(dwc->usb2_phy, 1);
1061 usb_phy_set_suspend(dwc->usb3_phy, 1);
1062
1063err1:
1064 usb_phy_shutdown(dwc->usb2_phy);
1065 usb_phy_shutdown(dwc->usb3_phy);
1066 phy_exit(dwc->usb2_generic_phy);
1067 phy_exit(dwc->usb3_generic_phy);
1068
1069err0a:
1070 dwc3_ulpi_exit(dwc);
1071
1072err0:
1073 return ret;
1074}
1075
1076static int dwc3_core_get_phy(struct dwc3 *dwc)
1077{
1078 struct device *dev = dwc->dev;
1079 struct device_node *node = dev->of_node;
1080 int ret;
1081
1082 if (node) {
1083 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1084 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1085 } else {
1086 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1087 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1088 }
1089
1090 if (IS_ERR(dwc->usb2_phy)) {
1091 ret = PTR_ERR(dwc->usb2_phy);
1092 if (ret == -ENXIO || ret == -ENODEV) {
1093 dwc->usb2_phy = NULL;
1094 } else if (ret == -EPROBE_DEFER) {
1095 return ret;
1096 } else {
1097 dev_err(dev, "no usb2 phy configured\n");
1098 return ret;
1099 }
1100 }
1101
1102 if (IS_ERR(dwc->usb3_phy)) {
1103 ret = PTR_ERR(dwc->usb3_phy);
1104 if (ret == -ENXIO || ret == -ENODEV) {
1105 dwc->usb3_phy = NULL;
1106 } else if (ret == -EPROBE_DEFER) {
1107 return ret;
1108 } else {
1109 dev_err(dev, "no usb3 phy configured\n");
1110 return ret;
1111 }
1112 }
1113
1114 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1115 if (IS_ERR(dwc->usb2_generic_phy)) {
1116 ret = PTR_ERR(dwc->usb2_generic_phy);
1117 if (ret == -ENOSYS || ret == -ENODEV) {
1118 dwc->usb2_generic_phy = NULL;
1119 } else if (ret == -EPROBE_DEFER) {
1120 return ret;
1121 } else {
1122 dev_err(dev, "no usb2 phy configured\n");
1123 return ret;
1124 }
1125 }
1126
1127 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1128 if (IS_ERR(dwc->usb3_generic_phy)) {
1129 ret = PTR_ERR(dwc->usb3_generic_phy);
1130 if (ret == -ENOSYS || ret == -ENODEV) {
1131 dwc->usb3_generic_phy = NULL;
1132 } else if (ret == -EPROBE_DEFER) {
1133 return ret;
1134 } else {
1135 dev_err(dev, "no usb3 phy configured\n");
1136 return ret;
1137 }
1138 }
1139
1140 return 0;
1141}
1142
1143static int dwc3_core_init_mode(struct dwc3 *dwc)
1144{
1145 struct device *dev = dwc->dev;
1146 int ret;
1147
1148 switch (dwc->dr_mode) {
1149 case USB_DR_MODE_PERIPHERAL:
1150 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1151
1152 if (dwc->usb2_phy)
1153 otg_set_vbus(dwc->usb2_phy->otg, false);
1154 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1155 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1156
1157 ret = dwc3_gadget_init(dwc);
1158 if (ret) {
1159 if (ret != -EPROBE_DEFER)
1160 dev_err(dev, "failed to initialize gadget\n");
1161 return ret;
1162 }
1163 break;
1164 case USB_DR_MODE_HOST:
1165 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1166
1167 if (dwc->usb2_phy)
1168 otg_set_vbus(dwc->usb2_phy->otg, true);
1169 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1170 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1171
1172 ret = dwc3_host_init(dwc);
1173 if (ret) {
1174 if (ret != -EPROBE_DEFER)
1175 dev_err(dev, "failed to initialize host\n");
1176 return ret;
1177 }
1178 break;
1179 case USB_DR_MODE_OTG:
1180 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1181 ret = dwc3_drd_init(dwc);
1182 if (ret) {
1183 if (ret != -EPROBE_DEFER)
1184 dev_err(dev, "failed to initialize dual-role\n");
1185 return ret;
1186 }
1187 break;
1188 default:
1189 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1190 return -EINVAL;
1191 }
1192
1193 return 0;
1194}
1195
1196static void dwc3_core_exit_mode(struct dwc3 *dwc)
1197{
1198 switch (dwc->dr_mode) {
1199 case USB_DR_MODE_PERIPHERAL:
1200 dwc3_gadget_exit(dwc);
1201 break;
1202 case USB_DR_MODE_HOST:
1203 dwc3_host_exit(dwc);
1204 break;
1205 case USB_DR_MODE_OTG:
1206 dwc3_drd_exit(dwc);
1207 break;
1208 default:
1209 /* do nothing */
1210 break;
1211 }
1212}
1213
1214static void dwc3_get_properties(struct dwc3 *dwc)
1215{
1216 struct device *dev = dwc->dev;
1217 u8 lpm_nyet_threshold;
1218 u8 tx_de_emphasis;
1219 u8 hird_threshold;
1220 u8 rx_thr_num_pkt_prd;
1221 u8 rx_max_burst_prd;
1222 u8 tx_thr_num_pkt_prd;
1223 u8 tx_max_burst_prd;
1224
1225 /* default to highest possible threshold */
1226 lpm_nyet_threshold = 0xf;
1227
1228 /* default to -3.5dB de-emphasis */
1229 tx_de_emphasis = 1;
1230
1231 /*
1232 * default to assert utmi_sleep_n and use maximum allowed HIRD
1233 * threshold value of 0b1100
1234 */
1235 hird_threshold = 12;
1236
1237 dwc->maximum_speed = usb_get_maximum_speed(dev);
1238 dwc->dr_mode = usb_get_dr_mode(dev);
1239 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1240
1241 dwc->sysdev_is_parent = device_property_read_bool(dev,
1242 "linux,sysdev_is_parent");
1243 if (dwc->sysdev_is_parent)
1244 dwc->sysdev = dwc->dev->parent;
1245 else
1246 dwc->sysdev = dwc->dev;
1247
1248 dwc->has_lpm_erratum = device_property_read_bool(dev,
1249 "snps,has-lpm-erratum");
1250 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1251 &lpm_nyet_threshold);
1252 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1253 "snps,is-utmi-l1-suspend");
1254 device_property_read_u8(dev, "snps,hird-threshold",
1255 &hird_threshold);
1256 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1257 "snps,dis-start-transfer-quirk");
1258 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1259 "snps,usb3_lpm_capable");
1260 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1261 "snps,usb2-lpm-disable");
1262 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1263 &rx_thr_num_pkt_prd);
1264 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1265 &rx_max_burst_prd);
1266 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1267 &tx_thr_num_pkt_prd);
1268 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1269 &tx_max_burst_prd);
1270
1271 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1272 "snps,disable_scramble_quirk");
1273 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1274 "snps,u2exit_lfps_quirk");
1275 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1276 "snps,u2ss_inp3_quirk");
1277 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1278 "snps,req_p1p2p3_quirk");
1279 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1280 "snps,del_p1p2p3_quirk");
1281 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1282 "snps,del_phy_power_chg_quirk");
1283 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1284 "snps,lfps_filter_quirk");
1285 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1286 "snps,rx_detect_poll_quirk");
1287 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1288 "snps,dis_u3_susphy_quirk");
1289 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1290 "snps,dis_u2_susphy_quirk");
1291 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1292 "snps,dis_enblslpm_quirk");
1293 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1294 "snps,dis-u1-entry-quirk");
1295 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1296 "snps,dis-u2-entry-quirk");
1297 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1298 "snps,dis_rxdet_inp3_quirk");
1299 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1300 "snps,dis-u2-freeclk-exists-quirk");
1301 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1302 "snps,dis-del-phy-power-chg-quirk");
1303 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1304 "snps,dis-tx-ipgap-linecheck-quirk");
1305
1306 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1307 "snps,tx_de_emphasis_quirk");
1308 device_property_read_u8(dev, "snps,tx_de_emphasis",
1309 &tx_de_emphasis);
1310 device_property_read_string(dev, "snps,hsphy_interface",
1311 &dwc->hsphy_interface);
1312 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1313 &dwc->fladj);
1314
1315 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1316 "snps,dis_metastability_quirk");
1317
1318 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1319 dwc->tx_de_emphasis = tx_de_emphasis;
1320
1321 dwc->hird_threshold = hird_threshold;
1322
1323 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1324 dwc->rx_max_burst_prd = rx_max_burst_prd;
1325
1326 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1327 dwc->tx_max_burst_prd = tx_max_burst_prd;
1328
1329 dwc->imod_interval = 0;
1330}
1331
1332/* check whether the core supports IMOD */
1333bool dwc3_has_imod(struct dwc3 *dwc)
1334{
1335 return ((dwc3_is_usb3(dwc) &&
1336 dwc->revision >= DWC3_REVISION_300A) ||
1337 (dwc3_is_usb31(dwc) &&
1338 dwc->revision >= DWC3_USB31_REVISION_120A));
1339}
1340
1341static void dwc3_check_params(struct dwc3 *dwc)
1342{
1343 struct device *dev = dwc->dev;
1344
1345 /* Check for proper value of imod_interval */
1346 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1347 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1348 dwc->imod_interval = 0;
1349 }
1350
1351 /*
1352 * Workaround for STAR 9000961433 which affects only version
1353 * 3.00a of the DWC_usb3 core. This prevents the controller
1354 * interrupt from being masked while handling events. IMOD
1355 * allows us to work around this issue. Enable it for the
1356 * affected version.
1357 */
1358 if (!dwc->imod_interval &&
1359 (dwc->revision == DWC3_REVISION_300A))
1360 dwc->imod_interval = 1;
1361
1362 /* Check the maximum_speed parameter */
1363 switch (dwc->maximum_speed) {
1364 case USB_SPEED_LOW:
1365 case USB_SPEED_FULL:
1366 case USB_SPEED_HIGH:
1367 case USB_SPEED_SUPER:
1368 case USB_SPEED_SUPER_PLUS:
1369 break;
1370 default:
1371 dev_err(dev, "invalid maximum_speed parameter %d\n",
1372 dwc->maximum_speed);
1373 /* fall through */
1374 case USB_SPEED_UNKNOWN:
1375 /* default to superspeed */
1376 dwc->maximum_speed = USB_SPEED_SUPER;
1377
1378 /*
1379 * default to superspeed plus if we are capable.
1380 */
1381 if (dwc3_is_usb31(dwc) &&
1382 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1383 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1384 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1385
1386 break;
1387 }
1388}
1389
1390static int dwc3_probe(struct platform_device *pdev)
1391{
1392 struct device *dev = &pdev->dev;
1393 struct resource *res, dwc_res;
1394 struct dwc3 *dwc;
1395
1396 int ret;
1397
1398 void __iomem *regs;
1399
1400 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1401 if (!dwc)
1402 return -ENOMEM;
1403
1404 dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1405 GFP_KERNEL);
1406 if (!dwc->clks)
1407 return -ENOMEM;
1408
1409 dwc->dev = dev;
1410
1411 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1412 if (!res) {
1413 dev_err(dev, "missing memory resource\n");
1414 return -ENODEV;
1415 }
1416
1417 dwc->xhci_resources[0].start = res->start;
1418 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1419 DWC3_XHCI_REGS_END;
1420 dwc->xhci_resources[0].flags = res->flags;
1421 dwc->xhci_resources[0].name = res->name;
1422
1423 /*
1424 * Request memory region but exclude xHCI regs,
1425 * since it will be requested by the xhci-plat driver.
1426 */
1427 dwc_res = *res;
1428 dwc_res.start += DWC3_GLOBALS_REGS_START;
1429
1430 regs = devm_ioremap_resource(dev, &dwc_res);
1431 if (IS_ERR(regs))
1432 return PTR_ERR(regs);
1433
1434 dwc->regs = regs;
1435 dwc->regs_size = resource_size(&dwc_res);
1436
1437 dwc3_get_properties(dwc);
1438
1439 dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1440 if (IS_ERR(dwc->reset))
1441 return PTR_ERR(dwc->reset);
1442
1443 if (dev->of_node) {
1444 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1445
1446 ret = devm_clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1447 if (ret == -EPROBE_DEFER)
1448 return ret;
1449 /*
1450 * Clocks are optional, but new DT platforms should support all
1451 * clocks as required by the DT-binding.
1452 */
1453 if (ret)
1454 dwc->num_clks = 0;
1455 }
1456
1457 ret = reset_control_deassert(dwc->reset);
1458 if (ret)
1459 return ret;
1460
1461 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1462 if (ret)
1463 goto assert_reset;
1464
1465 if (!dwc3_core_is_valid(dwc)) {
1466 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1467 ret = -ENODEV;
1468 goto disable_clks;
1469 }
1470
1471 platform_set_drvdata(pdev, dwc);
1472 dwc3_cache_hwparams(dwc);
1473
1474 spin_lock_init(&dwc->lock);
1475
1476 pm_runtime_set_active(dev);
1477 pm_runtime_use_autosuspend(dev);
1478 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1479 pm_runtime_enable(dev);
1480 ret = pm_runtime_get_sync(dev);
1481 if (ret < 0)
1482 goto err1;
1483
1484 pm_runtime_forbid(dev);
1485
1486 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1487 if (ret) {
1488 dev_err(dwc->dev, "failed to allocate event buffers\n");
1489 ret = -ENOMEM;
1490 goto err2;
1491 }
1492
1493 ret = dwc3_get_dr_mode(dwc);
1494 if (ret)
1495 goto err3;
1496
1497 ret = dwc3_alloc_scratch_buffers(dwc);
1498 if (ret)
1499 goto err3;
1500
1501 ret = dwc3_core_init(dwc);
1502 if (ret) {
1503 if (ret != -EPROBE_DEFER)
1504 dev_err(dev, "failed to initialize core: %d\n", ret);
1505 goto err4;
1506 }
1507
1508 dwc3_check_params(dwc);
1509
1510 ret = dwc3_core_init_mode(dwc);
1511 if (ret)
1512 goto err5;
1513
1514 dwc3_debugfs_init(dwc);
1515 pm_runtime_put(dev);
1516
1517 return 0;
1518
1519err5:
1520 dwc3_event_buffers_cleanup(dwc);
1521 dwc3_ulpi_exit(dwc);
1522
1523err4:
1524 dwc3_free_scratch_buffers(dwc);
1525
1526err3:
1527 dwc3_free_event_buffers(dwc);
1528
1529err2:
1530 pm_runtime_allow(&pdev->dev);
1531
1532err1:
1533 pm_runtime_put_sync(&pdev->dev);
1534 pm_runtime_disable(&pdev->dev);
1535
1536disable_clks:
1537 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1538assert_reset:
1539 reset_control_assert(dwc->reset);
1540
1541 return ret;
1542}
1543
1544static int dwc3_remove(struct platform_device *pdev)
1545{
1546 struct dwc3 *dwc = platform_get_drvdata(pdev);
1547
1548 pm_runtime_get_sync(&pdev->dev);
1549
1550 dwc3_debugfs_exit(dwc);
1551 dwc3_core_exit_mode(dwc);
1552
1553 dwc3_core_exit(dwc);
1554 dwc3_ulpi_exit(dwc);
1555
1556 pm_runtime_put_sync(&pdev->dev);
1557 pm_runtime_allow(&pdev->dev);
1558 pm_runtime_disable(&pdev->dev);
1559
1560 dwc3_free_event_buffers(dwc);
1561 dwc3_free_scratch_buffers(dwc);
1562
1563 return 0;
1564}
1565
1566#ifdef CONFIG_PM
1567static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1568{
1569 int ret;
1570
1571 ret = reset_control_deassert(dwc->reset);
1572 if (ret)
1573 return ret;
1574
1575 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1576 if (ret)
1577 goto assert_reset;
1578
1579 ret = dwc3_core_init(dwc);
1580 if (ret)
1581 goto disable_clks;
1582
1583 return 0;
1584
1585disable_clks:
1586 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1587assert_reset:
1588 reset_control_assert(dwc->reset);
1589
1590 return ret;
1591}
1592
1593static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1594{
1595 unsigned long flags;
1596 u32 reg;
1597
1598 switch (dwc->current_dr_role) {
1599 case DWC3_GCTL_PRTCAP_DEVICE:
1600 spin_lock_irqsave(&dwc->lock, flags);
1601 dwc3_gadget_suspend(dwc);
1602 spin_unlock_irqrestore(&dwc->lock, flags);
1603 synchronize_irq(dwc->irq_gadget);
1604 dwc3_core_exit(dwc);
1605 break;
1606 case DWC3_GCTL_PRTCAP_HOST:
1607 if (!PMSG_IS_AUTO(msg)) {
1608 dwc3_core_exit(dwc);
1609 break;
1610 }
1611
1612 /* Let controller to suspend HSPHY before PHY driver suspends */
1613 if (dwc->dis_u2_susphy_quirk ||
1614 dwc->dis_enblslpm_quirk) {
1615 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1616 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1617 DWC3_GUSB2PHYCFG_SUSPHY;
1618 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1619
1620 /* Give some time for USB2 PHY to suspend */
1621 usleep_range(5000, 6000);
1622 }
1623
1624 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1625 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1626 break;
1627 case DWC3_GCTL_PRTCAP_OTG:
1628 /* do nothing during runtime_suspend */
1629 if (PMSG_IS_AUTO(msg))
1630 break;
1631
1632 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1633 spin_lock_irqsave(&dwc->lock, flags);
1634 dwc3_gadget_suspend(dwc);
1635 spin_unlock_irqrestore(&dwc->lock, flags);
1636 synchronize_irq(dwc->irq_gadget);
1637 }
1638
1639 dwc3_otg_exit(dwc);
1640 dwc3_core_exit(dwc);
1641 break;
1642 default:
1643 /* do nothing */
1644 break;
1645 }
1646
1647 return 0;
1648}
1649
1650static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1651{
1652 unsigned long flags;
1653 int ret;
1654 u32 reg;
1655
1656 switch (dwc->current_dr_role) {
1657 case DWC3_GCTL_PRTCAP_DEVICE:
1658 ret = dwc3_core_init_for_resume(dwc);
1659 if (ret)
1660 return ret;
1661
1662 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1663 spin_lock_irqsave(&dwc->lock, flags);
1664 dwc3_gadget_resume(dwc);
1665 spin_unlock_irqrestore(&dwc->lock, flags);
1666 break;
1667 case DWC3_GCTL_PRTCAP_HOST:
1668 if (!PMSG_IS_AUTO(msg)) {
1669 ret = dwc3_core_init_for_resume(dwc);
1670 if (ret)
1671 return ret;
1672 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1673 break;
1674 }
1675 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1676 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1677 if (dwc->dis_u2_susphy_quirk)
1678 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1679
1680 if (dwc->dis_enblslpm_quirk)
1681 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1682
1683 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1684
1685 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1686 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1687 break;
1688 case DWC3_GCTL_PRTCAP_OTG:
1689 /* nothing to do on runtime_resume */
1690 if (PMSG_IS_AUTO(msg))
1691 break;
1692
1693 ret = dwc3_core_init(dwc);
1694 if (ret)
1695 return ret;
1696
1697 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1698
1699 dwc3_otg_init(dwc);
1700 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1701 dwc3_otg_host_init(dwc);
1702 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1703 spin_lock_irqsave(&dwc->lock, flags);
1704 dwc3_gadget_resume(dwc);
1705 spin_unlock_irqrestore(&dwc->lock, flags);
1706 }
1707
1708 break;
1709 default:
1710 /* do nothing */
1711 break;
1712 }
1713
1714 return 0;
1715}
1716
1717static int dwc3_runtime_checks(struct dwc3 *dwc)
1718{
1719 switch (dwc->current_dr_role) {
1720 case DWC3_GCTL_PRTCAP_DEVICE:
1721 if (dwc->connected)
1722 return -EBUSY;
1723 break;
1724 case DWC3_GCTL_PRTCAP_HOST:
1725 default:
1726 /* do nothing */
1727 break;
1728 }
1729
1730 return 0;
1731}
1732
1733static int dwc3_runtime_suspend(struct device *dev)
1734{
1735 struct dwc3 *dwc = dev_get_drvdata(dev);
1736 int ret;
1737
1738 if (dwc3_runtime_checks(dwc))
1739 return -EBUSY;
1740
1741 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1742 if (ret)
1743 return ret;
1744
1745 device_init_wakeup(dev, true);
1746
1747 return 0;
1748}
1749
1750static int dwc3_runtime_resume(struct device *dev)
1751{
1752 struct dwc3 *dwc = dev_get_drvdata(dev);
1753 int ret;
1754
1755 device_init_wakeup(dev, false);
1756
1757 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1758 if (ret)
1759 return ret;
1760
1761 switch (dwc->current_dr_role) {
1762 case DWC3_GCTL_PRTCAP_DEVICE:
1763 dwc3_gadget_process_pending_events(dwc);
1764 break;
1765 case DWC3_GCTL_PRTCAP_HOST:
1766 default:
1767 /* do nothing */
1768 break;
1769 }
1770
1771 pm_runtime_mark_last_busy(dev);
1772
1773 return 0;
1774}
1775
1776static int dwc3_runtime_idle(struct device *dev)
1777{
1778 struct dwc3 *dwc = dev_get_drvdata(dev);
1779
1780 switch (dwc->current_dr_role) {
1781 case DWC3_GCTL_PRTCAP_DEVICE:
1782 if (dwc3_runtime_checks(dwc))
1783 return -EBUSY;
1784 break;
1785 case DWC3_GCTL_PRTCAP_HOST:
1786 default:
1787 /* do nothing */
1788 break;
1789 }
1790
1791 pm_runtime_mark_last_busy(dev);
1792 pm_runtime_autosuspend(dev);
1793
1794 return 0;
1795}
1796#endif /* CONFIG_PM */
1797
1798#ifdef CONFIG_PM_SLEEP
1799static int dwc3_suspend(struct device *dev)
1800{
1801 struct dwc3 *dwc = dev_get_drvdata(dev);
1802 int ret;
1803
1804 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1805 if (ret)
1806 return ret;
1807
1808 pinctrl_pm_select_sleep_state(dev);
1809
1810 return 0;
1811}
1812
1813static int dwc3_resume(struct device *dev)
1814{
1815 struct dwc3 *dwc = dev_get_drvdata(dev);
1816 int ret;
1817
1818 pinctrl_pm_select_default_state(dev);
1819
1820 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1821 if (ret)
1822 return ret;
1823
1824 pm_runtime_disable(dev);
1825 pm_runtime_set_active(dev);
1826 pm_runtime_enable(dev);
1827
1828 return 0;
1829}
1830#endif /* CONFIG_PM_SLEEP */
1831
1832static const struct dev_pm_ops dwc3_dev_pm_ops = {
1833 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1834 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1835 dwc3_runtime_idle)
1836};
1837
1838#ifdef CONFIG_OF
1839static const struct of_device_id of_dwc3_match[] = {
1840 {
1841 .compatible = "snps,dwc3"
1842 },
1843 {
1844 .compatible = "synopsys,dwc3"
1845 },
1846 { },
1847};
1848MODULE_DEVICE_TABLE(of, of_dwc3_match);
1849#endif
1850
1851#ifdef CONFIG_ACPI
1852
1853#define ACPI_ID_INTEL_BSW "808622B7"
1854
1855static const struct acpi_device_id dwc3_acpi_match[] = {
1856 { ACPI_ID_INTEL_BSW, 0 },
1857 { },
1858};
1859MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1860#endif
1861
1862static struct platform_driver dwc3_driver = {
1863 .probe = dwc3_probe,
1864 .remove = dwc3_remove,
1865 .driver = {
1866 .name = "dwc3",
1867 .of_match_table = of_match_ptr(of_dwc3_match),
1868 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1869 .pm = &dwc3_dev_pm_ops,
1870 },
1871};
1872
1873module_platform_driver(dwc3_driver);
1874
1875MODULE_ALIAS("platform:dwc3");
1876MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1877MODULE_LICENSE("GPL v2");
1878MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");