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1/*
2 *
3 * Includes for cdc-acm.c
4 *
5 * Mainly take from usbnet's cdc-ether part
6 *
7 */
8
9/*
10 * CMSPAR, some architectures can't have space and mark parity.
11 */
12
13#ifndef CMSPAR
14#define CMSPAR 0
15#endif
16
17/*
18 * Major and minor numbers.
19 */
20
21#define ACM_TTY_MAJOR 166
22#define ACM_TTY_MINORS 256
23
24/*
25 * Requests.
26 */
27
28#define USB_RT_ACM (USB_TYPE_CLASS | USB_RECIP_INTERFACE)
29
30/*
31 * Output control lines.
32 */
33
34#define ACM_CTRL_DTR 0x01
35#define ACM_CTRL_RTS 0x02
36
37/*
38 * Input control lines and line errors.
39 */
40
41#define ACM_CTRL_DCD 0x01
42#define ACM_CTRL_DSR 0x02
43#define ACM_CTRL_BRK 0x04
44#define ACM_CTRL_RI 0x08
45
46#define ACM_CTRL_FRAMING 0x10
47#define ACM_CTRL_PARITY 0x20
48#define ACM_CTRL_OVERRUN 0x40
49
50/*
51 * Internal driver structures.
52 */
53
54/*
55 * The only reason to have several buffers is to accommodate assumptions
56 * in line disciplines. They ask for empty space amount, receive our URB size,
57 * and proceed to issue several 1-character writes, assuming they will fit.
58 * The very first write takes a complete URB. Fortunately, this only happens
59 * when processing onlcr, so we only need 2 buffers. These values must be
60 * powers of 2.
61 */
62#define ACM_NW 16
63#define ACM_NR 16
64
65struct acm_wb {
66 unsigned char *buf;
67 dma_addr_t dmah;
68 int len;
69 int use;
70 struct urb *urb;
71 struct acm *instance;
72};
73
74struct acm_rb {
75 int size;
76 unsigned char *base;
77 dma_addr_t dma;
78 int index;
79 struct acm *instance;
80};
81
82struct acm {
83 struct usb_device *dev; /* the corresponding usb device */
84 struct usb_interface *control; /* control interface */
85 struct usb_interface *data; /* data interface */
86 struct tty_port port; /* our tty port data */
87 struct urb *ctrlurb; /* urbs */
88 u8 *ctrl_buffer; /* buffers of urbs */
89 dma_addr_t ctrl_dma; /* dma handles of buffers */
90 u8 *country_codes; /* country codes from device */
91 unsigned int country_code_size; /* size of this buffer */
92 unsigned int country_rel_date; /* release date of version */
93 struct acm_wb wb[ACM_NW];
94 unsigned long read_urbs_free;
95 struct urb *read_urbs[ACM_NR];
96 struct acm_rb read_buffers[ACM_NR];
97 struct acm_wb *putbuffer; /* for acm_tty_put_char() */
98 int rx_buflimit;
99 int rx_endpoint;
100 spinlock_t read_lock;
101 int write_used; /* number of non-empty write buffers */
102 int transmitting;
103 spinlock_t write_lock;
104 struct mutex mutex;
105 bool disconnected;
106 struct usb_cdc_line_coding line; /* bits, stop, parity */
107 struct work_struct work; /* work queue entry for line discipline waking up */
108 unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */
109 unsigned int ctrlout; /* output control lines (DTR, RTS) */
110 struct async_icount iocount; /* counters for control line changes */
111 struct async_icount oldcount; /* for comparison of counter */
112 wait_queue_head_t wioctl; /* for ioctl */
113 unsigned int writesize; /* max packet size for the output bulk endpoint */
114 unsigned int readsize,ctrlsize; /* buffer sizes for freeing */
115 unsigned int minor; /* acm minor number */
116 unsigned char clocal; /* termios CLOCAL */
117 unsigned int ctrl_caps; /* control capabilities from the class specific header */
118 unsigned int susp_count; /* number of suspended interfaces */
119 unsigned int combined_interfaces:1; /* control and data collapsed */
120 unsigned int is_int_ep:1; /* interrupt endpoints contrary to spec used */
121 unsigned int throttled:1; /* actually throttled */
122 unsigned int throttle_req:1; /* throttle requested */
123 u8 bInterval;
124 struct usb_anchor delayed; /* writes queued for a device about to be woken */
125 unsigned long quirks;
126};
127
128#define CDC_DATA_INTERFACE_TYPE 0x0a
129
130/* constants describing various quirks and errors */
131#define NO_UNION_NORMAL BIT(0)
132#define SINGLE_RX_URB BIT(1)
133#define NO_CAP_LINE BIT(2)
134#define NO_DATA_INTERFACE BIT(4)
135#define IGNORE_DEVICE BIT(5)
136#define QUIRK_CONTROL_LINE_STATE BIT(6)
137#define CLEAR_HALT_CONDITIONS BIT(7)
138#define SEND_ZERO_PACKET BIT(8)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 *
4 * Includes for cdc-acm.c
5 *
6 * Mainly take from usbnet's cdc-ether part
7 *
8 */
9
10/*
11 * CMSPAR, some architectures can't have space and mark parity.
12 */
13
14#ifndef CMSPAR
15#define CMSPAR 0
16#endif
17
18/*
19 * Major and minor numbers.
20 */
21
22#define ACM_TTY_MAJOR 166
23#define ACM_TTY_MINORS 256
24
25/*
26 * Requests.
27 */
28
29#define USB_RT_ACM (USB_TYPE_CLASS | USB_RECIP_INTERFACE)
30
31/*
32 * Output control lines.
33 */
34
35#define ACM_CTRL_DTR 0x01
36#define ACM_CTRL_RTS 0x02
37
38/*
39 * Input control lines and line errors.
40 */
41
42#define ACM_CTRL_DCD 0x01
43#define ACM_CTRL_DSR 0x02
44#define ACM_CTRL_BRK 0x04
45#define ACM_CTRL_RI 0x08
46
47#define ACM_CTRL_FRAMING 0x10
48#define ACM_CTRL_PARITY 0x20
49#define ACM_CTRL_OVERRUN 0x40
50
51/*
52 * Internal driver structures.
53 */
54
55/*
56 * The only reason to have several buffers is to accommodate assumptions
57 * in line disciplines. They ask for empty space amount, receive our URB size,
58 * and proceed to issue several 1-character writes, assuming they will fit.
59 * The very first write takes a complete URB. Fortunately, this only happens
60 * when processing onlcr, so we only need 2 buffers. These values must be
61 * powers of 2.
62 */
63#define ACM_NW 16
64#define ACM_NR 16
65
66struct acm_wb {
67 unsigned char *buf;
68 dma_addr_t dmah;
69 int len;
70 int use;
71 struct urb *urb;
72 struct acm *instance;
73};
74
75struct acm_rb {
76 int size;
77 unsigned char *base;
78 dma_addr_t dma;
79 int index;
80 struct acm *instance;
81};
82
83struct acm {
84 struct usb_device *dev; /* the corresponding usb device */
85 struct usb_interface *control; /* control interface */
86 struct usb_interface *data; /* data interface */
87 unsigned in, out; /* i/o pipes */
88 struct tty_port port; /* our tty port data */
89 struct urb *ctrlurb; /* urbs */
90 u8 *ctrl_buffer; /* buffers of urbs */
91 dma_addr_t ctrl_dma; /* dma handles of buffers */
92 u8 *country_codes; /* country codes from device */
93 unsigned int country_code_size; /* size of this buffer */
94 unsigned int country_rel_date; /* release date of version */
95 struct acm_wb wb[ACM_NW];
96 unsigned long read_urbs_free;
97 struct urb *read_urbs[ACM_NR];
98 struct acm_rb read_buffers[ACM_NR];
99 int rx_buflimit;
100 spinlock_t read_lock;
101 u8 *notification_buffer; /* to reassemble fragmented notifications */
102 unsigned int nb_index;
103 unsigned int nb_size;
104 int transmitting;
105 spinlock_t write_lock;
106 struct mutex mutex;
107 bool disconnected;
108 unsigned long flags;
109# define EVENT_TTY_WAKEUP 0
110# define EVENT_RX_STALL 1
111# define ACM_THROTTLED 2
112 struct usb_cdc_line_coding line; /* bits, stop, parity */
113 struct work_struct work; /* work queue entry for line discipline waking up */
114 unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */
115 unsigned int ctrlout; /* output control lines (DTR, RTS) */
116 struct async_icount iocount; /* counters for control line changes */
117 struct async_icount oldcount; /* for comparison of counter */
118 wait_queue_head_t wioctl; /* for ioctl */
119 unsigned int writesize; /* max packet size for the output bulk endpoint */
120 unsigned int readsize,ctrlsize; /* buffer sizes for freeing */
121 unsigned int minor; /* acm minor number */
122 unsigned char clocal; /* termios CLOCAL */
123 unsigned int ctrl_caps; /* control capabilities from the class specific header */
124 unsigned int susp_count; /* number of suspended interfaces */
125 unsigned int combined_interfaces:1; /* control and data collapsed */
126 u8 bInterval;
127 struct usb_anchor delayed; /* writes queued for a device about to be woken */
128 unsigned long quirks;
129};
130
131#define CDC_DATA_INTERFACE_TYPE 0x0a
132
133/* constants describing various quirks and errors */
134#define NO_UNION_NORMAL BIT(0)
135#define SINGLE_RX_URB BIT(1)
136#define NO_CAP_LINE BIT(2)
137#define NO_DATA_INTERFACE BIT(4)
138#define IGNORE_DEVICE BIT(5)
139#define QUIRK_CONTROL_LINE_STATE BIT(6)
140#define CLEAR_HALT_CONDITIONS BIT(7)
141#define SEND_ZERO_PACKET BIT(8)
142#define DISABLE_ECHO BIT(9)