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1/*
2 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
3 *
4 * Copyright (C) 2015 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 */
19
20#include <linux/delay.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/platform_device.h>
26#include <linux/rtc.h>
27
28/* RTC Registers */
29#define RTC_SET_TM_WR 0x00
30#define RTC_SET_TM_RD 0x04
31#define RTC_CALIB_WR 0x08
32#define RTC_CALIB_RD 0x0C
33#define RTC_CUR_TM 0x10
34#define RTC_CUR_TICK 0x14
35#define RTC_ALRM 0x18
36#define RTC_INT_STS 0x20
37#define RTC_INT_MASK 0x24
38#define RTC_INT_EN 0x28
39#define RTC_INT_DIS 0x2C
40#define RTC_CTRL 0x40
41
42#define RTC_FR_EN BIT(20)
43#define RTC_FR_DATSHIFT 16
44#define RTC_TICK_MASK 0xFFFF
45#define RTC_INT_SEC BIT(0)
46#define RTC_INT_ALRM BIT(1)
47#define RTC_OSC_EN BIT(24)
48
49#define RTC_CALIB_DEF 0x198233
50#define RTC_CALIB_MASK 0x1FFFFF
51#define RTC_SEC_MAX_VAL 0xFFFFFFFF
52
53struct xlnx_rtc_dev {
54 struct rtc_device *rtc;
55 void __iomem *reg_base;
56 int alarm_irq;
57 int sec_irq;
58};
59
60static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
61{
62 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
63 unsigned long new_time;
64
65 new_time = rtc_tm_to_time64(tm);
66
67 if (new_time > RTC_SEC_MAX_VAL)
68 return -EINVAL;
69
70 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
71
72 return 0;
73}
74
75static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
76{
77 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
78
79 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);
80
81 return rtc_valid_tm(tm);
82}
83
84static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
85{
86 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
87
88 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
89 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
90
91 return 0;
92}
93
94static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
95{
96 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
97
98 if (enabled)
99 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
100 else
101 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
102
103 return 0;
104}
105
106static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
107{
108 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
109 unsigned long alarm_time;
110
111 alarm_time = rtc_tm_to_time64(&alrm->time);
112
113 if (alarm_time > RTC_SEC_MAX_VAL)
114 return -EINVAL;
115
116 writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
117
118 xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
119
120 return 0;
121}
122
123static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev, u32 calibval)
124{
125 /*
126 * Based on crystal freq of 33.330 KHz
127 * set the seconds counter and enable, set fractions counter
128 * to default value suggested as per design spec
129 * to correct RTC delay in frequency over period of time.
130 */
131 calibval &= RTC_CALIB_MASK;
132 writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
133}
134
135static const struct rtc_class_ops xlnx_rtc_ops = {
136 .set_time = xlnx_rtc_set_time,
137 .read_time = xlnx_rtc_read_time,
138 .read_alarm = xlnx_rtc_read_alarm,
139 .set_alarm = xlnx_rtc_set_alarm,
140 .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
141};
142
143static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
144{
145 struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
146 unsigned int status;
147
148 status = readl(xrtcdev->reg_base + RTC_INT_STS);
149 /* Check if interrupt asserted */
150 if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
151 return IRQ_NONE;
152
153 /* Clear interrupt */
154 writel(status, xrtcdev->reg_base + RTC_INT_STS);
155
156 if (status & RTC_INT_SEC)
157 rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_UF);
158 if (status & RTC_INT_ALRM)
159 rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
160
161 return IRQ_HANDLED;
162}
163
164static int xlnx_rtc_probe(struct platform_device *pdev)
165{
166 struct xlnx_rtc_dev *xrtcdev;
167 struct resource *res;
168 int ret;
169 unsigned int calibvalue;
170
171 xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
172 if (!xrtcdev)
173 return -ENOMEM;
174
175 platform_set_drvdata(pdev, xrtcdev);
176
177 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
178
179 xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res);
180 if (IS_ERR(xrtcdev->reg_base))
181 return PTR_ERR(xrtcdev->reg_base);
182
183 xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
184 if (xrtcdev->alarm_irq < 0) {
185 dev_err(&pdev->dev, "no irq resource\n");
186 return xrtcdev->alarm_irq;
187 }
188 ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
189 xlnx_rtc_interrupt, 0,
190 dev_name(&pdev->dev), xrtcdev);
191 if (ret) {
192 dev_err(&pdev->dev, "request irq failed\n");
193 return ret;
194 }
195
196 xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
197 if (xrtcdev->sec_irq < 0) {
198 dev_err(&pdev->dev, "no irq resource\n");
199 return xrtcdev->sec_irq;
200 }
201 ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
202 xlnx_rtc_interrupt, 0,
203 dev_name(&pdev->dev), xrtcdev);
204 if (ret) {
205 dev_err(&pdev->dev, "request irq failed\n");
206 return ret;
207 }
208
209 ret = of_property_read_u32(pdev->dev.of_node, "calibration",
210 &calibvalue);
211 if (ret)
212 calibvalue = RTC_CALIB_DEF;
213
214 xlnx_init_rtc(xrtcdev, calibvalue);
215
216 device_init_wakeup(&pdev->dev, 1);
217
218 xrtcdev->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
219 &xlnx_rtc_ops, THIS_MODULE);
220 return PTR_ERR_OR_ZERO(xrtcdev->rtc);
221}
222
223static int xlnx_rtc_remove(struct platform_device *pdev)
224{
225 xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
226 device_init_wakeup(&pdev->dev, 0);
227
228 return 0;
229}
230
231static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
232{
233 struct platform_device *pdev = to_platform_device(dev);
234 struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);
235
236 if (device_may_wakeup(&pdev->dev))
237 enable_irq_wake(xrtcdev->alarm_irq);
238 else
239 xlnx_rtc_alarm_irq_enable(dev, 0);
240
241 return 0;
242}
243
244static int __maybe_unused xlnx_rtc_resume(struct device *dev)
245{
246 struct platform_device *pdev = to_platform_device(dev);
247 struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);
248
249 if (device_may_wakeup(&pdev->dev))
250 disable_irq_wake(xrtcdev->alarm_irq);
251 else
252 xlnx_rtc_alarm_irq_enable(dev, 1);
253
254 return 0;
255}
256
257static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
258
259static const struct of_device_id xlnx_rtc_of_match[] = {
260 {.compatible = "xlnx,zynqmp-rtc" },
261 { }
262};
263MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
264
265static struct platform_driver xlnx_rtc_driver = {
266 .probe = xlnx_rtc_probe,
267 .remove = xlnx_rtc_remove,
268 .driver = {
269 .name = KBUILD_MODNAME,
270 .pm = &xlnx_rtc_pm_ops,
271 .of_match_table = xlnx_rtc_of_match,
272 },
273};
274
275module_platform_driver(xlnx_rtc_driver);
276
277MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
278MODULE_AUTHOR("Xilinx Inc.");
279MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
4 *
5 * Copyright (C) 2015 Xilinx, Inc.
6 *
7 */
8
9#include <linux/delay.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/rtc.h>
16
17/* RTC Registers */
18#define RTC_SET_TM_WR 0x00
19#define RTC_SET_TM_RD 0x04
20#define RTC_CALIB_WR 0x08
21#define RTC_CALIB_RD 0x0C
22#define RTC_CUR_TM 0x10
23#define RTC_CUR_TICK 0x14
24#define RTC_ALRM 0x18
25#define RTC_INT_STS 0x20
26#define RTC_INT_MASK 0x24
27#define RTC_INT_EN 0x28
28#define RTC_INT_DIS 0x2C
29#define RTC_CTRL 0x40
30
31#define RTC_FR_EN BIT(20)
32#define RTC_FR_DATSHIFT 16
33#define RTC_TICK_MASK 0xFFFF
34#define RTC_INT_SEC BIT(0)
35#define RTC_INT_ALRM BIT(1)
36#define RTC_OSC_EN BIT(24)
37#define RTC_BATT_EN BIT(31)
38
39#define RTC_CALIB_DEF 0x198233
40#define RTC_CALIB_MASK 0x1FFFFF
41
42struct xlnx_rtc_dev {
43 struct rtc_device *rtc;
44 void __iomem *reg_base;
45 int alarm_irq;
46 int sec_irq;
47 int calibval;
48};
49
50static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
51{
52 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
53 unsigned long new_time;
54
55 /*
56 * The value written will be updated after 1 sec into the
57 * seconds read register, so we need to program time +1 sec
58 * to get the correct time on read.
59 */
60 new_time = rtc_tm_to_time64(tm) + 1;
61
62 /*
63 * Writing into calibration register will clear the Tick Counter and
64 * force the next second to be signaled exactly in 1 second period
65 */
66 xrtcdev->calibval &= RTC_CALIB_MASK;
67 writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
68
69 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
70
71 /*
72 * Clear the rtc interrupt status register after setting the
73 * time. During a read_time function, the code should read the
74 * RTC_INT_STATUS register and if bit 0 is still 0, it means
75 * that one second has not elapsed yet since RTC was set and
76 * the current time should be read from SET_TIME_READ register;
77 * otherwise, CURRENT_TIME register is read to report the time
78 */
79 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
80
81 return 0;
82}
83
84static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
85{
86 u32 status;
87 unsigned long read_time;
88 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
89
90 status = readl(xrtcdev->reg_base + RTC_INT_STS);
91
92 if (status & RTC_INT_SEC) {
93 /*
94 * RTC has updated the CURRENT_TIME with the time written into
95 * SET_TIME_WRITE register.
96 */
97 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);
98 } else {
99 /*
100 * Time written in SET_TIME_WRITE has not yet updated into
101 * the seconds read register, so read the time from the
102 * SET_TIME_WRITE instead of CURRENT_TIME register.
103 * Since we add +1 sec while writing, we need to -1 sec while
104 * reading.
105 */
106 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
107 rtc_time64_to_tm(read_time, tm);
108 }
109
110 return 0;
111}
112
113static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
114{
115 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
116
117 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
118 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
119
120 return 0;
121}
122
123static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
124{
125 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
126
127 if (enabled)
128 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
129 else
130 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
131
132 return 0;
133}
134
135static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
136{
137 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
138 unsigned long alarm_time;
139
140 alarm_time = rtc_tm_to_time64(&alrm->time);
141
142 writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
143
144 xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
145
146 return 0;
147}
148
149static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
150{
151 u32 rtc_ctrl;
152
153 /* Enable RTC switch to battery when VCC_PSAUX is not available */
154 rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
155 rtc_ctrl |= RTC_BATT_EN;
156 writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
157
158 /*
159 * Based on crystal freq of 33.330 KHz
160 * set the seconds counter and enable, set fractions counter
161 * to default value suggested as per design spec
162 * to correct RTC delay in frequency over period of time.
163 */
164 xrtcdev->calibval &= RTC_CALIB_MASK;
165 writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
166}
167
168static const struct rtc_class_ops xlnx_rtc_ops = {
169 .set_time = xlnx_rtc_set_time,
170 .read_time = xlnx_rtc_read_time,
171 .read_alarm = xlnx_rtc_read_alarm,
172 .set_alarm = xlnx_rtc_set_alarm,
173 .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
174};
175
176static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
177{
178 struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
179 unsigned int status;
180
181 status = readl(xrtcdev->reg_base + RTC_INT_STS);
182 /* Check if interrupt asserted */
183 if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
184 return IRQ_NONE;
185
186 /* Clear RTC_INT_ALRM interrupt only */
187 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
188
189 if (status & RTC_INT_ALRM)
190 rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
191
192 return IRQ_HANDLED;
193}
194
195static int xlnx_rtc_probe(struct platform_device *pdev)
196{
197 struct xlnx_rtc_dev *xrtcdev;
198 struct resource *res;
199 int ret;
200
201 xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
202 if (!xrtcdev)
203 return -ENOMEM;
204
205 platform_set_drvdata(pdev, xrtcdev);
206
207 xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
208 if (IS_ERR(xrtcdev->rtc))
209 return PTR_ERR(xrtcdev->rtc);
210
211 xrtcdev->rtc->ops = &xlnx_rtc_ops;
212 xrtcdev->rtc->range_max = U32_MAX;
213
214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
215
216 xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res);
217 if (IS_ERR(xrtcdev->reg_base))
218 return PTR_ERR(xrtcdev->reg_base);
219
220 xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
221 if (xrtcdev->alarm_irq < 0)
222 return xrtcdev->alarm_irq;
223 ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
224 xlnx_rtc_interrupt, 0,
225 dev_name(&pdev->dev), xrtcdev);
226 if (ret) {
227 dev_err(&pdev->dev, "request irq failed\n");
228 return ret;
229 }
230
231 xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
232 if (xrtcdev->sec_irq < 0)
233 return xrtcdev->sec_irq;
234 ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
235 xlnx_rtc_interrupt, 0,
236 dev_name(&pdev->dev), xrtcdev);
237 if (ret) {
238 dev_err(&pdev->dev, "request irq failed\n");
239 return ret;
240 }
241
242 ret = of_property_read_u32(pdev->dev.of_node, "calibration",
243 &xrtcdev->calibval);
244 if (ret)
245 xrtcdev->calibval = RTC_CALIB_DEF;
246
247 xlnx_init_rtc(xrtcdev);
248
249 device_init_wakeup(&pdev->dev, 1);
250
251 return rtc_register_device(xrtcdev->rtc);
252}
253
254static int xlnx_rtc_remove(struct platform_device *pdev)
255{
256 xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
257 device_init_wakeup(&pdev->dev, 0);
258
259 return 0;
260}
261
262static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
263{
264 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
265
266 if (device_may_wakeup(dev))
267 enable_irq_wake(xrtcdev->alarm_irq);
268 else
269 xlnx_rtc_alarm_irq_enable(dev, 0);
270
271 return 0;
272}
273
274static int __maybe_unused xlnx_rtc_resume(struct device *dev)
275{
276 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
277
278 if (device_may_wakeup(dev))
279 disable_irq_wake(xrtcdev->alarm_irq);
280 else
281 xlnx_rtc_alarm_irq_enable(dev, 1);
282
283 return 0;
284}
285
286static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
287
288static const struct of_device_id xlnx_rtc_of_match[] = {
289 {.compatible = "xlnx,zynqmp-rtc" },
290 { }
291};
292MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
293
294static struct platform_driver xlnx_rtc_driver = {
295 .probe = xlnx_rtc_probe,
296 .remove = xlnx_rtc_remove,
297 .driver = {
298 .name = KBUILD_MODNAME,
299 .pm = &xlnx_rtc_pm_ops,
300 .of_match_table = xlnx_rtc_of_match,
301 },
302};
303
304module_platform_driver(xlnx_rtc_driver);
305
306MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
307MODULE_AUTHOR("Xilinx Inc.");
308MODULE_LICENSE("GPL v2");