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1/*
2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
3 *
4 * (C) Copyright 2008-2010,2015 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 *
12 * SCU running in ARC processor communicates with other entity running in IA
13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
18 */
19#include <linux/delay.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/pm.h>
24#include <linux/pci.h>
25#include <linux/interrupt.h>
26#include <linux/sfi.h>
27#include <asm/intel-mid.h>
28#include <asm/intel_scu_ipc.h>
29
30/* IPC defines the following message types */
31#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
32#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
33#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
34#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
35#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
36
37/* Command id associated with message IPCMSG_PCNTRL */
38#define IPC_CMD_PCNTRL_W 0 /* Register write */
39#define IPC_CMD_PCNTRL_R 1 /* Register read */
40#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
41
42/*
43 * IPC register summary
44 *
45 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
46 * To read or write information to the SCU, driver writes to IPC-1 memory
47 * mapped registers. The following is the IPC mechanism
48 *
49 * 1. IA core cDMI interface claims this transaction and converts it to a
50 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
51 *
52 * 2. South Complex cDMI block receives this message and writes it to
53 * the IPC-1 register block, causing an interrupt to the SCU
54 *
55 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
56 * message handler is called within firmware.
57 */
58
59#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
60#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
61#define IPC_IOC 0x100 /* IPC command register IOC bit */
62
63#define PCI_DEVICE_ID_LINCROFT 0x082a
64#define PCI_DEVICE_ID_PENWELL 0x080e
65#define PCI_DEVICE_ID_CLOVERVIEW 0x08ea
66#define PCI_DEVICE_ID_TANGIER 0x11a0
67
68/* intel scu ipc driver data */
69struct intel_scu_ipc_pdata_t {
70 u32 i2c_base;
71 u32 i2c_len;
72 u8 irq_mode;
73};
74
75static struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
76 .i2c_base = 0xff12b000,
77 .i2c_len = 0x10,
78 .irq_mode = 0,
79};
80
81/* Penwell and Cloverview */
82static struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
83 .i2c_base = 0xff12b000,
84 .i2c_len = 0x10,
85 .irq_mode = 1,
86};
87
88static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
89 .i2c_base = 0xff00d000,
90 .i2c_len = 0x10,
91 .irq_mode = 0,
92};
93
94struct intel_scu_ipc_dev {
95 struct device *dev;
96 void __iomem *ipc_base;
97 void __iomem *i2c_base;
98 struct completion cmd_complete;
99 u8 irq_mode;
100};
101
102static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
103
104/*
105 * IPC Read Buffer (Read Only):
106 * 16 byte buffer for receiving data from SCU, if IPC command
107 * processing results in response data
108 */
109#define IPC_READ_BUFFER 0x90
110
111#define IPC_I2C_CNTRL_ADDR 0
112#define I2C_DATA_ADDR 0x04
113
114static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
115
116/*
117 * Send ipc command
118 * Command Register (Write Only):
119 * A write to this register results in an interrupt to the SCU core processor
120 * Format:
121 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
122 */
123static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
124{
125 if (scu->irq_mode) {
126 reinit_completion(&scu->cmd_complete);
127 writel(cmd | IPC_IOC, scu->ipc_base);
128 }
129 writel(cmd, scu->ipc_base);
130}
131
132/*
133 * Write ipc data
134 * IPC Write Buffer (Write Only):
135 * 16-byte buffer for sending data associated with IPC command to
136 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
137 */
138static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
139{
140 writel(data, scu->ipc_base + 0x80 + offset);
141}
142
143/*
144 * Status Register (Read Only):
145 * Driver will read this register to get the ready/busy status of the IPC
146 * block and error status of the IPC command that was just processed by SCU
147 * Format:
148 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
149 */
150static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
151{
152 return __raw_readl(scu->ipc_base + 0x04);
153}
154
155/* Read ipc byte data */
156static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
157{
158 return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
159}
160
161/* Read ipc u32 data */
162static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
163{
164 return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
165}
166
167/* Wait till scu status is busy */
168static inline int busy_loop(struct intel_scu_ipc_dev *scu)
169{
170 u32 status = ipc_read_status(scu);
171 u32 loop_count = 100000;
172
173 /* break if scu doesn't reset busy bit after huge retry */
174 while ((status & BIT(0)) && --loop_count) {
175 udelay(1); /* scu processing time is in few u secods */
176 status = ipc_read_status(scu);
177 }
178
179 if (status & BIT(0)) {
180 dev_err(scu->dev, "IPC timed out");
181 return -ETIMEDOUT;
182 }
183
184 if (status & BIT(1))
185 return -EIO;
186
187 return 0;
188}
189
190/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
191static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
192{
193 int status;
194
195 if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
196 dev_err(scu->dev, "IPC timed out\n");
197 return -ETIMEDOUT;
198 }
199
200 status = ipc_read_status(scu);
201 if (status & BIT(1))
202 return -EIO;
203
204 return 0;
205}
206
207static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
208{
209 return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
210}
211
212/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
213static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
214{
215 struct intel_scu_ipc_dev *scu = &ipcdev;
216 int nc;
217 u32 offset = 0;
218 int err;
219 u8 cbuf[IPC_WWBUF_SIZE];
220 u32 *wbuf = (u32 *)&cbuf;
221
222 memset(cbuf, 0, sizeof(cbuf));
223
224 mutex_lock(&ipclock);
225
226 if (scu->dev == NULL) {
227 mutex_unlock(&ipclock);
228 return -ENODEV;
229 }
230
231 for (nc = 0; nc < count; nc++, offset += 2) {
232 cbuf[offset] = addr[nc];
233 cbuf[offset + 1] = addr[nc] >> 8;
234 }
235
236 if (id == IPC_CMD_PCNTRL_R) {
237 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
238 ipc_data_writel(scu, wbuf[nc], offset);
239 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
240 } else if (id == IPC_CMD_PCNTRL_W) {
241 for (nc = 0; nc < count; nc++, offset += 1)
242 cbuf[offset] = data[nc];
243 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
244 ipc_data_writel(scu, wbuf[nc], offset);
245 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
246 } else if (id == IPC_CMD_PCNTRL_M) {
247 cbuf[offset] = data[0];
248 cbuf[offset + 1] = data[1];
249 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
250 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
251 }
252
253 err = intel_scu_ipc_check_status(scu);
254 if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
255 /* Workaround: values are read as 0 without memcpy_fromio */
256 memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
257 for (nc = 0; nc < count; nc++)
258 data[nc] = ipc_data_readb(scu, nc);
259 }
260 mutex_unlock(&ipclock);
261 return err;
262}
263
264/**
265 * intel_scu_ipc_ioread8 - read a word via the SCU
266 * @addr: register on SCU
267 * @data: return pointer for read byte
268 *
269 * Read a single register. Returns 0 on success or an error code. All
270 * locking between SCU accesses is handled for the caller.
271 *
272 * This function may sleep.
273 */
274int intel_scu_ipc_ioread8(u16 addr, u8 *data)
275{
276 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
277}
278EXPORT_SYMBOL(intel_scu_ipc_ioread8);
279
280/**
281 * intel_scu_ipc_ioread16 - read a word via the SCU
282 * @addr: register on SCU
283 * @data: return pointer for read word
284 *
285 * Read a register pair. Returns 0 on success or an error code. All
286 * locking between SCU accesses is handled for the caller.
287 *
288 * This function may sleep.
289 */
290int intel_scu_ipc_ioread16(u16 addr, u16 *data)
291{
292 u16 x[2] = {addr, addr + 1};
293 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
294}
295EXPORT_SYMBOL(intel_scu_ipc_ioread16);
296
297/**
298 * intel_scu_ipc_ioread32 - read a dword via the SCU
299 * @addr: register on SCU
300 * @data: return pointer for read dword
301 *
302 * Read four registers. Returns 0 on success or an error code. All
303 * locking between SCU accesses is handled for the caller.
304 *
305 * This function may sleep.
306 */
307int intel_scu_ipc_ioread32(u16 addr, u32 *data)
308{
309 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
310 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
311}
312EXPORT_SYMBOL(intel_scu_ipc_ioread32);
313
314/**
315 * intel_scu_ipc_iowrite8 - write a byte via the SCU
316 * @addr: register on SCU
317 * @data: byte to write
318 *
319 * Write a single register. Returns 0 on success or an error code. All
320 * locking between SCU accesses is handled for the caller.
321 *
322 * This function may sleep.
323 */
324int intel_scu_ipc_iowrite8(u16 addr, u8 data)
325{
326 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
327}
328EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
329
330/**
331 * intel_scu_ipc_iowrite16 - write a word via the SCU
332 * @addr: register on SCU
333 * @data: word to write
334 *
335 * Write two registers. Returns 0 on success or an error code. All
336 * locking between SCU accesses is handled for the caller.
337 *
338 * This function may sleep.
339 */
340int intel_scu_ipc_iowrite16(u16 addr, u16 data)
341{
342 u16 x[2] = {addr, addr + 1};
343 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
344}
345EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
346
347/**
348 * intel_scu_ipc_iowrite32 - write a dword via the SCU
349 * @addr: register on SCU
350 * @data: dword to write
351 *
352 * Write four registers. Returns 0 on success or an error code. All
353 * locking between SCU accesses is handled for the caller.
354 *
355 * This function may sleep.
356 */
357int intel_scu_ipc_iowrite32(u16 addr, u32 data)
358{
359 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
360 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
361}
362EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
363
364/**
365 * intel_scu_ipc_readvv - read a set of registers
366 * @addr: register list
367 * @data: bytes to return
368 * @len: length of array
369 *
370 * Read registers. Returns 0 on success or an error code. All
371 * locking between SCU accesses is handled for the caller.
372 *
373 * The largest array length permitted by the hardware is 5 items.
374 *
375 * This function may sleep.
376 */
377int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
378{
379 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
380}
381EXPORT_SYMBOL(intel_scu_ipc_readv);
382
383/**
384 * intel_scu_ipc_writev - write a set of registers
385 * @addr: register list
386 * @data: bytes to write
387 * @len: length of array
388 *
389 * Write registers. Returns 0 on success or an error code. All
390 * locking between SCU accesses is handled for the caller.
391 *
392 * The largest array length permitted by the hardware is 5 items.
393 *
394 * This function may sleep.
395 *
396 */
397int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
398{
399 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
400}
401EXPORT_SYMBOL(intel_scu_ipc_writev);
402
403/**
404 * intel_scu_ipc_update_register - r/m/w a register
405 * @addr: register address
406 * @bits: bits to update
407 * @mask: mask of bits to update
408 *
409 * Read-modify-write power control unit register. The first data argument
410 * must be register value and second is mask value
411 * mask is a bitmap that indicates which bits to update.
412 * 0 = masked. Don't modify this bit, 1 = modify this bit.
413 * returns 0 on success or an error code.
414 *
415 * This function may sleep. Locking between SCU accesses is handled
416 * for the caller.
417 */
418int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
419{
420 u8 data[2] = { bits, mask };
421 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
422}
423EXPORT_SYMBOL(intel_scu_ipc_update_register);
424
425/**
426 * intel_scu_ipc_simple_command - send a simple command
427 * @cmd: command
428 * @sub: sub type
429 *
430 * Issue a simple command to the SCU. Do not use this interface if
431 * you must then access data as any data values may be overwritten
432 * by another SCU access by the time this function returns.
433 *
434 * This function may sleep. Locking for SCU accesses is handled for
435 * the caller.
436 */
437int intel_scu_ipc_simple_command(int cmd, int sub)
438{
439 struct intel_scu_ipc_dev *scu = &ipcdev;
440 int err;
441
442 mutex_lock(&ipclock);
443 if (scu->dev == NULL) {
444 mutex_unlock(&ipclock);
445 return -ENODEV;
446 }
447 ipc_command(scu, sub << 12 | cmd);
448 err = intel_scu_ipc_check_status(scu);
449 mutex_unlock(&ipclock);
450 return err;
451}
452EXPORT_SYMBOL(intel_scu_ipc_simple_command);
453
454/**
455 * intel_scu_ipc_command - command with data
456 * @cmd: command
457 * @sub: sub type
458 * @in: input data
459 * @inlen: input length in dwords
460 * @out: output data
461 * @outlein: output length in dwords
462 *
463 * Issue a command to the SCU which involves data transfers. Do the
464 * data copies under the lock but leave it for the caller to interpret
465 */
466int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
467 u32 *out, int outlen)
468{
469 struct intel_scu_ipc_dev *scu = &ipcdev;
470 int i, err;
471
472 mutex_lock(&ipclock);
473 if (scu->dev == NULL) {
474 mutex_unlock(&ipclock);
475 return -ENODEV;
476 }
477
478 for (i = 0; i < inlen; i++)
479 ipc_data_writel(scu, *in++, 4 * i);
480
481 ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
482 err = intel_scu_ipc_check_status(scu);
483
484 if (!err) {
485 for (i = 0; i < outlen; i++)
486 *out++ = ipc_data_readl(scu, 4 * i);
487 }
488
489 mutex_unlock(&ipclock);
490 return err;
491}
492EXPORT_SYMBOL(intel_scu_ipc_command);
493
494/* I2C commands */
495#define IPC_I2C_WRITE 1 /* I2C Write command */
496#define IPC_I2C_READ 2 /* I2C Read command */
497
498/**
499 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
500 * @addr: I2C address + command bits
501 * @data: data to read/write
502 *
503 * Perform an an I2C read/write operation via the SCU. All locking is
504 * handled for the caller. This function may sleep.
505 *
506 * Returns an error code or 0 on success.
507 *
508 * This has to be in the IPC driver for the locking.
509 */
510int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
511{
512 struct intel_scu_ipc_dev *scu = &ipcdev;
513 u32 cmd = 0;
514
515 mutex_lock(&ipclock);
516 if (scu->dev == NULL) {
517 mutex_unlock(&ipclock);
518 return -ENODEV;
519 }
520 cmd = (addr >> 24) & 0xFF;
521 if (cmd == IPC_I2C_READ) {
522 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
523 /* Write not getting updated without delay */
524 mdelay(1);
525 *data = readl(scu->i2c_base + I2C_DATA_ADDR);
526 } else if (cmd == IPC_I2C_WRITE) {
527 writel(*data, scu->i2c_base + I2C_DATA_ADDR);
528 mdelay(1);
529 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
530 } else {
531 dev_err(scu->dev,
532 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
533
534 mutex_unlock(&ipclock);
535 return -EIO;
536 }
537 mutex_unlock(&ipclock);
538 return 0;
539}
540EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
541
542/*
543 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
544 * When ioc bit is set to 1, caller api must wait for interrupt handler called
545 * which in turn unlocks the caller api. Currently this is not used
546 *
547 * This is edge triggered so we need take no action to clear anything
548 */
549static irqreturn_t ioc(int irq, void *dev_id)
550{
551 struct intel_scu_ipc_dev *scu = dev_id;
552
553 if (scu->irq_mode)
554 complete(&scu->cmd_complete);
555
556 return IRQ_HANDLED;
557}
558
559/**
560 * ipc_probe - probe an Intel SCU IPC
561 * @pdev: the PCI device matching
562 * @id: entry in the match table
563 *
564 * Enable and install an intel SCU IPC. This appears in the PCI space
565 * but uses some hard coded addresses as well.
566 */
567static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
568{
569 int platform; /* Platform type */
570 int err;
571 struct intel_scu_ipc_dev *scu = &ipcdev;
572 struct intel_scu_ipc_pdata_t *pdata;
573
574 platform = intel_mid_identify_cpu();
575 if (platform == 0)
576 return -ENODEV;
577
578 if (scu->dev) /* We support only one SCU */
579 return -EBUSY;
580
581 pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
582
583 scu->dev = &pdev->dev;
584 scu->irq_mode = pdata->irq_mode;
585
586 err = pcim_enable_device(pdev);
587 if (err)
588 return err;
589
590 err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
591 if (err)
592 return err;
593
594 init_completion(&scu->cmd_complete);
595
596 err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc",
597 scu);
598 if (err)
599 return err;
600
601 scu->ipc_base = pcim_iomap_table(pdev)[0];
602
603 scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
604 if (!scu->i2c_base)
605 return -ENOMEM;
606
607 intel_scu_devices_create();
608
609 pci_set_drvdata(pdev, scu);
610 return 0;
611}
612
613static const struct pci_device_id pci_ids[] = {
614 {
615 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_LINCROFT),
616 (kernel_ulong_t)&intel_scu_ipc_lincroft_pdata,
617 }, {
618 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL),
619 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
620 }, {
621 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CLOVERVIEW),
622 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
623 }, {
624 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER),
625 (kernel_ulong_t)&intel_scu_ipc_tangier_pdata,
626 }, {
627 0,
628 }
629};
630
631static struct pci_driver ipc_driver = {
632 .driver = {
633 .suppress_bind_attrs = true,
634 },
635 .name = "intel_scu_ipc",
636 .id_table = pci_ids,
637 .probe = ipc_probe,
638};
639builtin_pci_driver(ipc_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the Intel SCU IPC mechanism
4 *
5 * (C) Copyright 2008-2010,2015 Intel Corporation
6 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 *
8 * SCU running in ARC processor communicates with other entity running in IA
9 * core through IPC mechanism which in turn messaging between IA core ad SCU.
10 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
11 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
12 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
13 * along with other APIs.
14 */
15
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/pci.h>
22#include <linux/pm.h>
23#include <linux/sfi.h>
24
25#include <asm/intel-mid.h>
26#include <asm/intel_scu_ipc.h>
27
28/* IPC defines the following message types */
29#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
30#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
31#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
32#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
33#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
34
35/* Command id associated with message IPCMSG_PCNTRL */
36#define IPC_CMD_PCNTRL_W 0 /* Register write */
37#define IPC_CMD_PCNTRL_R 1 /* Register read */
38#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
39
40/*
41 * IPC register summary
42 *
43 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
44 * To read or write information to the SCU, driver writes to IPC-1 memory
45 * mapped registers. The following is the IPC mechanism
46 *
47 * 1. IA core cDMI interface claims this transaction and converts it to a
48 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
49 *
50 * 2. South Complex cDMI block receives this message and writes it to
51 * the IPC-1 register block, causing an interrupt to the SCU
52 *
53 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
54 * message handler is called within firmware.
55 */
56
57#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
58#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
59#define IPC_IOC 0x100 /* IPC command register IOC bit */
60
61#define PCI_DEVICE_ID_LINCROFT 0x082a
62#define PCI_DEVICE_ID_PENWELL 0x080e
63#define PCI_DEVICE_ID_CLOVERVIEW 0x08ea
64#define PCI_DEVICE_ID_TANGIER 0x11a0
65
66/* intel scu ipc driver data */
67struct intel_scu_ipc_pdata_t {
68 u32 i2c_base;
69 u32 i2c_len;
70 u8 irq_mode;
71};
72
73static const struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
74 .i2c_base = 0xff12b000,
75 .i2c_len = 0x10,
76 .irq_mode = 0,
77};
78
79/* Penwell and Cloverview */
80static const struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
81 .i2c_base = 0xff12b000,
82 .i2c_len = 0x10,
83 .irq_mode = 1,
84};
85
86static const struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
87 .i2c_base = 0xff00d000,
88 .i2c_len = 0x10,
89 .irq_mode = 0,
90};
91
92struct intel_scu_ipc_dev {
93 struct device *dev;
94 void __iomem *ipc_base;
95 void __iomem *i2c_base;
96 struct completion cmd_complete;
97 u8 irq_mode;
98};
99
100static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
101
102/*
103 * IPC Read Buffer (Read Only):
104 * 16 byte buffer for receiving data from SCU, if IPC command
105 * processing results in response data
106 */
107#define IPC_READ_BUFFER 0x90
108
109#define IPC_I2C_CNTRL_ADDR 0
110#define I2C_DATA_ADDR 0x04
111
112static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
113
114/*
115 * Send ipc command
116 * Command Register (Write Only):
117 * A write to this register results in an interrupt to the SCU core processor
118 * Format:
119 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
120 */
121static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
122{
123 if (scu->irq_mode) {
124 reinit_completion(&scu->cmd_complete);
125 writel(cmd | IPC_IOC, scu->ipc_base);
126 }
127 writel(cmd, scu->ipc_base);
128}
129
130/*
131 * Write ipc data
132 * IPC Write Buffer (Write Only):
133 * 16-byte buffer for sending data associated with IPC command to
134 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
135 */
136static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
137{
138 writel(data, scu->ipc_base + 0x80 + offset);
139}
140
141/*
142 * Status Register (Read Only):
143 * Driver will read this register to get the ready/busy status of the IPC
144 * block and error status of the IPC command that was just processed by SCU
145 * Format:
146 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
147 */
148static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
149{
150 return __raw_readl(scu->ipc_base + 0x04);
151}
152
153/* Read ipc byte data */
154static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
155{
156 return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
157}
158
159/* Read ipc u32 data */
160static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
161{
162 return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
163}
164
165/* Wait till scu status is busy */
166static inline int busy_loop(struct intel_scu_ipc_dev *scu)
167{
168 u32 status = ipc_read_status(scu);
169 u32 loop_count = 100000;
170
171 /* break if scu doesn't reset busy bit after huge retry */
172 while ((status & BIT(0)) && --loop_count) {
173 udelay(1); /* scu processing time is in few u secods */
174 status = ipc_read_status(scu);
175 }
176
177 if (status & BIT(0)) {
178 dev_err(scu->dev, "IPC timed out");
179 return -ETIMEDOUT;
180 }
181
182 if (status & BIT(1))
183 return -EIO;
184
185 return 0;
186}
187
188/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
189static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
190{
191 int status;
192
193 if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
194 dev_err(scu->dev, "IPC timed out\n");
195 return -ETIMEDOUT;
196 }
197
198 status = ipc_read_status(scu);
199 if (status & BIT(1))
200 return -EIO;
201
202 return 0;
203}
204
205static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
206{
207 return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
208}
209
210/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
211static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
212{
213 struct intel_scu_ipc_dev *scu = &ipcdev;
214 int nc;
215 u32 offset = 0;
216 int err;
217 u8 cbuf[IPC_WWBUF_SIZE];
218 u32 *wbuf = (u32 *)&cbuf;
219
220 memset(cbuf, 0, sizeof(cbuf));
221
222 mutex_lock(&ipclock);
223
224 if (scu->dev == NULL) {
225 mutex_unlock(&ipclock);
226 return -ENODEV;
227 }
228
229 for (nc = 0; nc < count; nc++, offset += 2) {
230 cbuf[offset] = addr[nc];
231 cbuf[offset + 1] = addr[nc] >> 8;
232 }
233
234 if (id == IPC_CMD_PCNTRL_R) {
235 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
236 ipc_data_writel(scu, wbuf[nc], offset);
237 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
238 } else if (id == IPC_CMD_PCNTRL_W) {
239 for (nc = 0; nc < count; nc++, offset += 1)
240 cbuf[offset] = data[nc];
241 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
242 ipc_data_writel(scu, wbuf[nc], offset);
243 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
244 } else if (id == IPC_CMD_PCNTRL_M) {
245 cbuf[offset] = data[0];
246 cbuf[offset + 1] = data[1];
247 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
248 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
249 }
250
251 err = intel_scu_ipc_check_status(scu);
252 if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
253 /* Workaround: values are read as 0 without memcpy_fromio */
254 memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
255 for (nc = 0; nc < count; nc++)
256 data[nc] = ipc_data_readb(scu, nc);
257 }
258 mutex_unlock(&ipclock);
259 return err;
260}
261
262/**
263 * intel_scu_ipc_ioread8 - read a word via the SCU
264 * @addr: register on SCU
265 * @data: return pointer for read byte
266 *
267 * Read a single register. Returns 0 on success or an error code. All
268 * locking between SCU accesses is handled for the caller.
269 *
270 * This function may sleep.
271 */
272int intel_scu_ipc_ioread8(u16 addr, u8 *data)
273{
274 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
275}
276EXPORT_SYMBOL(intel_scu_ipc_ioread8);
277
278/**
279 * intel_scu_ipc_ioread16 - read a word via the SCU
280 * @addr: register on SCU
281 * @data: return pointer for read word
282 *
283 * Read a register pair. Returns 0 on success or an error code. All
284 * locking between SCU accesses is handled for the caller.
285 *
286 * This function may sleep.
287 */
288int intel_scu_ipc_ioread16(u16 addr, u16 *data)
289{
290 u16 x[2] = {addr, addr + 1};
291 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
292}
293EXPORT_SYMBOL(intel_scu_ipc_ioread16);
294
295/**
296 * intel_scu_ipc_ioread32 - read a dword via the SCU
297 * @addr: register on SCU
298 * @data: return pointer for read dword
299 *
300 * Read four registers. Returns 0 on success or an error code. All
301 * locking between SCU accesses is handled for the caller.
302 *
303 * This function may sleep.
304 */
305int intel_scu_ipc_ioread32(u16 addr, u32 *data)
306{
307 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
308 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
309}
310EXPORT_SYMBOL(intel_scu_ipc_ioread32);
311
312/**
313 * intel_scu_ipc_iowrite8 - write a byte via the SCU
314 * @addr: register on SCU
315 * @data: byte to write
316 *
317 * Write a single register. Returns 0 on success or an error code. All
318 * locking between SCU accesses is handled for the caller.
319 *
320 * This function may sleep.
321 */
322int intel_scu_ipc_iowrite8(u16 addr, u8 data)
323{
324 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
325}
326EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
327
328/**
329 * intel_scu_ipc_iowrite16 - write a word via the SCU
330 * @addr: register on SCU
331 * @data: word to write
332 *
333 * Write two registers. Returns 0 on success or an error code. All
334 * locking between SCU accesses is handled for the caller.
335 *
336 * This function may sleep.
337 */
338int intel_scu_ipc_iowrite16(u16 addr, u16 data)
339{
340 u16 x[2] = {addr, addr + 1};
341 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
342}
343EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
344
345/**
346 * intel_scu_ipc_iowrite32 - write a dword via the SCU
347 * @addr: register on SCU
348 * @data: dword to write
349 *
350 * Write four registers. Returns 0 on success or an error code. All
351 * locking between SCU accesses is handled for the caller.
352 *
353 * This function may sleep.
354 */
355int intel_scu_ipc_iowrite32(u16 addr, u32 data)
356{
357 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
358 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
359}
360EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
361
362/**
363 * intel_scu_ipc_readvv - read a set of registers
364 * @addr: register list
365 * @data: bytes to return
366 * @len: length of array
367 *
368 * Read registers. Returns 0 on success or an error code. All
369 * locking between SCU accesses is handled for the caller.
370 *
371 * The largest array length permitted by the hardware is 5 items.
372 *
373 * This function may sleep.
374 */
375int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
376{
377 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
378}
379EXPORT_SYMBOL(intel_scu_ipc_readv);
380
381/**
382 * intel_scu_ipc_writev - write a set of registers
383 * @addr: register list
384 * @data: bytes to write
385 * @len: length of array
386 *
387 * Write registers. Returns 0 on success or an error code. All
388 * locking between SCU accesses is handled for the caller.
389 *
390 * The largest array length permitted by the hardware is 5 items.
391 *
392 * This function may sleep.
393 *
394 */
395int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
396{
397 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
398}
399EXPORT_SYMBOL(intel_scu_ipc_writev);
400
401/**
402 * intel_scu_ipc_update_register - r/m/w a register
403 * @addr: register address
404 * @bits: bits to update
405 * @mask: mask of bits to update
406 *
407 * Read-modify-write power control unit register. The first data argument
408 * must be register value and second is mask value
409 * mask is a bitmap that indicates which bits to update.
410 * 0 = masked. Don't modify this bit, 1 = modify this bit.
411 * returns 0 on success or an error code.
412 *
413 * This function may sleep. Locking between SCU accesses is handled
414 * for the caller.
415 */
416int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
417{
418 u8 data[2] = { bits, mask };
419 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
420}
421EXPORT_SYMBOL(intel_scu_ipc_update_register);
422
423/**
424 * intel_scu_ipc_simple_command - send a simple command
425 * @cmd: command
426 * @sub: sub type
427 *
428 * Issue a simple command to the SCU. Do not use this interface if
429 * you must then access data as any data values may be overwritten
430 * by another SCU access by the time this function returns.
431 *
432 * This function may sleep. Locking for SCU accesses is handled for
433 * the caller.
434 */
435int intel_scu_ipc_simple_command(int cmd, int sub)
436{
437 struct intel_scu_ipc_dev *scu = &ipcdev;
438 int err;
439
440 mutex_lock(&ipclock);
441 if (scu->dev == NULL) {
442 mutex_unlock(&ipclock);
443 return -ENODEV;
444 }
445 ipc_command(scu, sub << 12 | cmd);
446 err = intel_scu_ipc_check_status(scu);
447 mutex_unlock(&ipclock);
448 return err;
449}
450EXPORT_SYMBOL(intel_scu_ipc_simple_command);
451
452/**
453 * intel_scu_ipc_command - command with data
454 * @cmd: command
455 * @sub: sub type
456 * @in: input data
457 * @inlen: input length in dwords
458 * @out: output data
459 * @outlein: output length in dwords
460 *
461 * Issue a command to the SCU which involves data transfers. Do the
462 * data copies under the lock but leave it for the caller to interpret
463 */
464int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
465 u32 *out, int outlen)
466{
467 struct intel_scu_ipc_dev *scu = &ipcdev;
468 int i, err;
469
470 mutex_lock(&ipclock);
471 if (scu->dev == NULL) {
472 mutex_unlock(&ipclock);
473 return -ENODEV;
474 }
475
476 for (i = 0; i < inlen; i++)
477 ipc_data_writel(scu, *in++, 4 * i);
478
479 ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
480 err = intel_scu_ipc_check_status(scu);
481
482 if (!err) {
483 for (i = 0; i < outlen; i++)
484 *out++ = ipc_data_readl(scu, 4 * i);
485 }
486
487 mutex_unlock(&ipclock);
488 return err;
489}
490EXPORT_SYMBOL(intel_scu_ipc_command);
491
492#define IPC_SPTR 0x08
493#define IPC_DPTR 0x0C
494
495/**
496 * intel_scu_ipc_raw_command() - IPC command with data and pointers
497 * @cmd: IPC command code.
498 * @sub: IPC command sub type.
499 * @in: input data of this IPC command.
500 * @inlen: input data length in dwords.
501 * @out: output data of this IPC command.
502 * @outlen: output data length in dwords.
503 * @sptr: data writing to SPTR register.
504 * @dptr: data writing to DPTR register.
505 *
506 * Send an IPC command to SCU with input/output data and source/dest pointers.
507 *
508 * Return: an IPC error code or 0 on success.
509 */
510int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,
511 u32 *out, int outlen, u32 dptr, u32 sptr)
512{
513 struct intel_scu_ipc_dev *scu = &ipcdev;
514 int inbuflen = DIV_ROUND_UP(inlen, 4);
515 u32 inbuf[4];
516 int i, err;
517
518 /* Up to 16 bytes */
519 if (inbuflen > 4)
520 return -EINVAL;
521
522 mutex_lock(&ipclock);
523 if (scu->dev == NULL) {
524 mutex_unlock(&ipclock);
525 return -ENODEV;
526 }
527
528 writel(dptr, scu->ipc_base + IPC_DPTR);
529 writel(sptr, scu->ipc_base + IPC_SPTR);
530
531 /*
532 * SRAM controller doesn't support 8-bit writes, it only
533 * supports 32-bit writes, so we have to copy input data into
534 * the temporary buffer, and SCU FW will use the inlen to
535 * determine the actual input data length in the temporary
536 * buffer.
537 */
538 memcpy(inbuf, in, inlen);
539
540 for (i = 0; i < inbuflen; i++)
541 ipc_data_writel(scu, inbuf[i], 4 * i);
542
543 ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
544 err = intel_scu_ipc_check_status(scu);
545 if (!err) {
546 for (i = 0; i < outlen; i++)
547 *out++ = ipc_data_readl(scu, 4 * i);
548 }
549
550 mutex_unlock(&ipclock);
551 return err;
552}
553EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);
554
555/* I2C commands */
556#define IPC_I2C_WRITE 1 /* I2C Write command */
557#define IPC_I2C_READ 2 /* I2C Read command */
558
559/**
560 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
561 * @addr: I2C address + command bits
562 * @data: data to read/write
563 *
564 * Perform an an I2C read/write operation via the SCU. All locking is
565 * handled for the caller. This function may sleep.
566 *
567 * Returns an error code or 0 on success.
568 *
569 * This has to be in the IPC driver for the locking.
570 */
571int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
572{
573 struct intel_scu_ipc_dev *scu = &ipcdev;
574 u32 cmd = 0;
575
576 mutex_lock(&ipclock);
577 if (scu->dev == NULL) {
578 mutex_unlock(&ipclock);
579 return -ENODEV;
580 }
581 cmd = (addr >> 24) & 0xFF;
582 if (cmd == IPC_I2C_READ) {
583 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
584 /* Write not getting updated without delay */
585 usleep_range(1000, 2000);
586 *data = readl(scu->i2c_base + I2C_DATA_ADDR);
587 } else if (cmd == IPC_I2C_WRITE) {
588 writel(*data, scu->i2c_base + I2C_DATA_ADDR);
589 usleep_range(1000, 2000);
590 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
591 } else {
592 dev_err(scu->dev,
593 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
594
595 mutex_unlock(&ipclock);
596 return -EIO;
597 }
598 mutex_unlock(&ipclock);
599 return 0;
600}
601EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
602
603/*
604 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
605 * When ioc bit is set to 1, caller api must wait for interrupt handler called
606 * which in turn unlocks the caller api. Currently this is not used
607 *
608 * This is edge triggered so we need take no action to clear anything
609 */
610static irqreturn_t ioc(int irq, void *dev_id)
611{
612 struct intel_scu_ipc_dev *scu = dev_id;
613
614 if (scu->irq_mode)
615 complete(&scu->cmd_complete);
616
617 return IRQ_HANDLED;
618}
619
620/**
621 * ipc_probe - probe an Intel SCU IPC
622 * @pdev: the PCI device matching
623 * @id: entry in the match table
624 *
625 * Enable and install an intel SCU IPC. This appears in the PCI space
626 * but uses some hard coded addresses as well.
627 */
628static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
629{
630 int err;
631 struct intel_scu_ipc_dev *scu = &ipcdev;
632 struct intel_scu_ipc_pdata_t *pdata;
633
634 if (scu->dev) /* We support only one SCU */
635 return -EBUSY;
636
637 pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
638 if (!pdata)
639 return -ENODEV;
640
641 scu->irq_mode = pdata->irq_mode;
642
643 err = pcim_enable_device(pdev);
644 if (err)
645 return err;
646
647 err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
648 if (err)
649 return err;
650
651 init_completion(&scu->cmd_complete);
652
653 scu->ipc_base = pcim_iomap_table(pdev)[0];
654
655 scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
656 if (!scu->i2c_base)
657 return -ENOMEM;
658
659 err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc",
660 scu);
661 if (err)
662 return err;
663
664 /* Assign device at last */
665 scu->dev = &pdev->dev;
666
667 intel_scu_devices_create();
668
669 pci_set_drvdata(pdev, scu);
670 return 0;
671}
672
673#define SCU_DEVICE(id, pdata) {PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&pdata}
674
675static const struct pci_device_id pci_ids[] = {
676 SCU_DEVICE(PCI_DEVICE_ID_LINCROFT, intel_scu_ipc_lincroft_pdata),
677 SCU_DEVICE(PCI_DEVICE_ID_PENWELL, intel_scu_ipc_penwell_pdata),
678 SCU_DEVICE(PCI_DEVICE_ID_CLOVERVIEW, intel_scu_ipc_penwell_pdata),
679 SCU_DEVICE(PCI_DEVICE_ID_TANGIER, intel_scu_ipc_tangier_pdata),
680 {}
681};
682
683static struct pci_driver ipc_driver = {
684 .driver = {
685 .suppress_bind_attrs = true,
686 },
687 .name = "intel_scu_ipc",
688 .id_table = pci_ids,
689 .probe = ipc_probe,
690};
691builtin_pci_driver(ipc_driver);