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1/*
2 * Tegra host1x Register Offsets for Tegra20 and Tegra30
3 *
4 * Copyright (c) 2010-2013 NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef __HOST1X_HOST1X01_HARDWARE_H
20#define __HOST1X_HOST1X01_HARDWARE_H
21
22#include <linux/types.h>
23#include <linux/bitops.h>
24
25#include "hw_host1x01_channel.h"
26#include "hw_host1x01_sync.h"
27#include "hw_host1x01_uclass.h"
28
29static inline u32 host1x_class_host_wait_syncpt(
30 unsigned indx, unsigned threshold)
31{
32 return host1x_uclass_wait_syncpt_indx_f(indx)
33 | host1x_uclass_wait_syncpt_thresh_f(threshold);
34}
35
36static inline u32 host1x_class_host_load_syncpt_base(
37 unsigned indx, unsigned threshold)
38{
39 return host1x_uclass_load_syncpt_base_base_indx_f(indx)
40 | host1x_uclass_load_syncpt_base_value_f(threshold);
41}
42
43static inline u32 host1x_class_host_wait_syncpt_base(
44 unsigned indx, unsigned base_indx, unsigned offset)
45{
46 return host1x_uclass_wait_syncpt_base_indx_f(indx)
47 | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
48 | host1x_uclass_wait_syncpt_base_offset_f(offset);
49}
50
51static inline u32 host1x_class_host_incr_syncpt_base(
52 unsigned base_indx, unsigned offset)
53{
54 return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
55 | host1x_uclass_incr_syncpt_base_offset_f(offset);
56}
57
58static inline u32 host1x_class_host_incr_syncpt(
59 unsigned cond, unsigned indx)
60{
61 return host1x_uclass_incr_syncpt_cond_f(cond)
62 | host1x_uclass_incr_syncpt_indx_f(indx);
63}
64
65static inline u32 host1x_class_host_indoff_reg_write(
66 unsigned mod_id, unsigned offset, bool auto_inc)
67{
68 u32 v = host1x_uclass_indoff_indbe_f(0xf)
69 | host1x_uclass_indoff_indmodid_f(mod_id)
70 | host1x_uclass_indoff_indroffset_f(offset);
71 if (auto_inc)
72 v |= host1x_uclass_indoff_autoinc_f(1);
73 return v;
74}
75
76static inline u32 host1x_class_host_indoff_reg_read(
77 unsigned mod_id, unsigned offset, bool auto_inc)
78{
79 u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
80 | host1x_uclass_indoff_indroffset_f(offset)
81 | host1x_uclass_indoff_rwn_read_v();
82 if (auto_inc)
83 v |= host1x_uclass_indoff_autoinc_f(1);
84 return v;
85}
86
87
88/* cdma opcodes */
89static inline u32 host1x_opcode_setclass(
90 unsigned class_id, unsigned offset, unsigned mask)
91{
92 return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
93}
94
95static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
96{
97 return (1 << 28) | (offset << 16) | count;
98}
99
100static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
101{
102 return (2 << 28) | (offset << 16) | count;
103}
104
105static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
106{
107 return (3 << 28) | (offset << 16) | mask;
108}
109
110static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
111{
112 return (4 << 28) | (offset << 16) | value;
113}
114
115static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
116{
117 return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
118 host1x_class_host_incr_syncpt(cond, indx));
119}
120
121static inline u32 host1x_opcode_restart(unsigned address)
122{
123 return (5 << 28) | (address >> 4);
124}
125
126static inline u32 host1x_opcode_gather(unsigned count)
127{
128 return (6 << 28) | count;
129}
130
131static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
132{
133 return (6 << 28) | (offset << 16) | BIT(15) | count;
134}
135
136static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
137{
138 return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
139}
140
141#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
142
143#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Tegra host1x Register Offsets for Tegra20 and Tegra30
4 *
5 * Copyright (c) 2010-2013 NVIDIA Corporation.
6 */
7
8#ifndef __HOST1X_HOST1X01_HARDWARE_H
9#define __HOST1X_HOST1X01_HARDWARE_H
10
11#include <linux/types.h>
12#include <linux/bitops.h>
13
14#include "hw_host1x01_channel.h"
15#include "hw_host1x01_sync.h"
16#include "hw_host1x01_uclass.h"
17
18static inline u32 host1x_class_host_wait_syncpt(
19 unsigned indx, unsigned threshold)
20{
21 return host1x_uclass_wait_syncpt_indx_f(indx)
22 | host1x_uclass_wait_syncpt_thresh_f(threshold);
23}
24
25static inline u32 host1x_class_host_load_syncpt_base(
26 unsigned indx, unsigned threshold)
27{
28 return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29 | host1x_uclass_load_syncpt_base_value_f(threshold);
30}
31
32static inline u32 host1x_class_host_wait_syncpt_base(
33 unsigned indx, unsigned base_indx, unsigned offset)
34{
35 return host1x_uclass_wait_syncpt_base_indx_f(indx)
36 | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37 | host1x_uclass_wait_syncpt_base_offset_f(offset);
38}
39
40static inline u32 host1x_class_host_incr_syncpt_base(
41 unsigned base_indx, unsigned offset)
42{
43 return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44 | host1x_uclass_incr_syncpt_base_offset_f(offset);
45}
46
47static inline u32 host1x_class_host_incr_syncpt(
48 unsigned cond, unsigned indx)
49{
50 return host1x_uclass_incr_syncpt_cond_f(cond)
51 | host1x_uclass_incr_syncpt_indx_f(indx);
52}
53
54static inline u32 host1x_class_host_indoff_reg_write(
55 unsigned mod_id, unsigned offset, bool auto_inc)
56{
57 u32 v = host1x_uclass_indoff_indbe_f(0xf)
58 | host1x_uclass_indoff_indmodid_f(mod_id)
59 | host1x_uclass_indoff_indroffset_f(offset);
60 if (auto_inc)
61 v |= host1x_uclass_indoff_autoinc_f(1);
62 return v;
63}
64
65static inline u32 host1x_class_host_indoff_reg_read(
66 unsigned mod_id, unsigned offset, bool auto_inc)
67{
68 u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69 | host1x_uclass_indoff_indroffset_f(offset)
70 | host1x_uclass_indoff_rwn_read_v();
71 if (auto_inc)
72 v |= host1x_uclass_indoff_autoinc_f(1);
73 return v;
74}
75
76
77/* cdma opcodes */
78static inline u32 host1x_opcode_setclass(
79 unsigned class_id, unsigned offset, unsigned mask)
80{
81 return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
82}
83
84static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
85{
86 return (1 << 28) | (offset << 16) | count;
87}
88
89static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
90{
91 return (2 << 28) | (offset << 16) | count;
92}
93
94static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
95{
96 return (3 << 28) | (offset << 16) | mask;
97}
98
99static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
100{
101 return (4 << 28) | (offset << 16) | value;
102}
103
104static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
105{
106 return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
107 host1x_class_host_incr_syncpt(cond, indx));
108}
109
110static inline u32 host1x_opcode_restart(unsigned address)
111{
112 return (5 << 28) | (address >> 4);
113}
114
115static inline u32 host1x_opcode_gather(unsigned count)
116{
117 return (6 << 28) | count;
118}
119
120static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
121{
122 return (6 << 28) | (offset << 16) | BIT(15) | count;
123}
124
125static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
126{
127 return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
128}
129
130#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
131
132#endif