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1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Authors:
6 * Dave Airlie
7 * Alon Levy
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 */
27
28#include <drm/drmP.h>
29#include "virtgpu_drv.h"
30#include <drm/virtgpu_drm.h>
31#include "ttm/ttm_execbuf_util.h"
32
33static void convert_to_hw_box(struct virtio_gpu_box *dst,
34 const struct drm_virtgpu_3d_box *src)
35{
36 dst->x = cpu_to_le32(src->x);
37 dst->y = cpu_to_le32(src->y);
38 dst->z = cpu_to_le32(src->z);
39 dst->w = cpu_to_le32(src->w);
40 dst->h = cpu_to_le32(src->h);
41 dst->d = cpu_to_le32(src->d);
42}
43
44static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
45 struct drm_file *file_priv)
46{
47 struct virtio_gpu_device *vgdev = dev->dev_private;
48 struct drm_virtgpu_map *virtio_gpu_map = data;
49
50 return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev,
51 virtio_gpu_map->handle,
52 &virtio_gpu_map->offset);
53}
54
55static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
56 struct list_head *head)
57{
58 struct ttm_validate_buffer *buf;
59 struct ttm_buffer_object *bo;
60 struct virtio_gpu_object *qobj;
61 int ret;
62
63 ret = ttm_eu_reserve_buffers(ticket, head, true, NULL);
64 if (ret != 0)
65 return ret;
66
67 list_for_each_entry(buf, head, head) {
68 bo = buf->bo;
69 qobj = container_of(bo, struct virtio_gpu_object, tbo);
70 ret = ttm_bo_validate(bo, &qobj->placement, false, false);
71 if (ret) {
72 ttm_eu_backoff_reservation(ticket, head);
73 return ret;
74 }
75 }
76 return 0;
77}
78
79static void virtio_gpu_unref_list(struct list_head *head)
80{
81 struct ttm_validate_buffer *buf;
82 struct ttm_buffer_object *bo;
83 struct virtio_gpu_object *qobj;
84 list_for_each_entry(buf, head, head) {
85 bo = buf->bo;
86 qobj = container_of(bo, struct virtio_gpu_object, tbo);
87
88 drm_gem_object_unreference_unlocked(&qobj->gem_base);
89 }
90}
91
92static int virtio_gpu_execbuffer(struct drm_device *dev,
93 struct drm_virtgpu_execbuffer *exbuf,
94 struct drm_file *drm_file)
95{
96 struct virtio_gpu_device *vgdev = dev->dev_private;
97 struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv;
98 struct drm_gem_object *gobj;
99 struct virtio_gpu_fence *fence;
100 struct virtio_gpu_object *qobj;
101 int ret;
102 uint32_t *bo_handles = NULL;
103 void __user *user_bo_handles = NULL;
104 struct list_head validate_list;
105 struct ttm_validate_buffer *buflist = NULL;
106 int i;
107 struct ww_acquire_ctx ticket;
108 void *buf;
109
110 if (vgdev->has_virgl_3d == false)
111 return -ENOSYS;
112
113 INIT_LIST_HEAD(&validate_list);
114 if (exbuf->num_bo_handles) {
115
116 bo_handles = drm_malloc_ab(exbuf->num_bo_handles,
117 sizeof(uint32_t));
118 buflist = drm_calloc_large(exbuf->num_bo_handles,
119 sizeof(struct ttm_validate_buffer));
120 if (!bo_handles || !buflist) {
121 drm_free_large(bo_handles);
122 drm_free_large(buflist);
123 return -ENOMEM;
124 }
125
126 user_bo_handles = (void __user *)(uintptr_t)exbuf->bo_handles;
127 if (copy_from_user(bo_handles, user_bo_handles,
128 exbuf->num_bo_handles * sizeof(uint32_t))) {
129 ret = -EFAULT;
130 drm_free_large(bo_handles);
131 drm_free_large(buflist);
132 return ret;
133 }
134
135 for (i = 0; i < exbuf->num_bo_handles; i++) {
136 gobj = drm_gem_object_lookup(dev,
137 drm_file, bo_handles[i]);
138 if (!gobj) {
139 drm_free_large(bo_handles);
140 drm_free_large(buflist);
141 return -ENOENT;
142 }
143
144 qobj = gem_to_virtio_gpu_obj(gobj);
145 buflist[i].bo = &qobj->tbo;
146
147 list_add(&buflist[i].head, &validate_list);
148 }
149 drm_free_large(bo_handles);
150 }
151
152 ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
153 if (ret)
154 goto out_free;
155
156 buf = kmalloc(exbuf->size, GFP_KERNEL);
157 if (!buf) {
158 ret = -ENOMEM;
159 goto out_unresv;
160 }
161 if (copy_from_user(buf, (void __user *)(uintptr_t)exbuf->command,
162 exbuf->size)) {
163 kfree(buf);
164 ret = -EFAULT;
165 goto out_unresv;
166 }
167 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
168 vfpriv->ctx_id, &fence);
169
170 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
171
172 /* fence the command bo */
173 virtio_gpu_unref_list(&validate_list);
174 drm_free_large(buflist);
175 fence_put(&fence->f);
176 return 0;
177
178out_unresv:
179 ttm_eu_backoff_reservation(&ticket, &validate_list);
180out_free:
181 virtio_gpu_unref_list(&validate_list);
182 drm_free_large(buflist);
183 return ret;
184}
185
186/*
187 * Usage of execbuffer:
188 * Relocations need to take into account the full VIRTIO_GPUDrawable size.
189 * However, the command as passed from user space must *not* contain the initial
190 * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
191 */
192static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
193 struct drm_file *file_priv)
194{
195 struct drm_virtgpu_execbuffer *execbuffer = data;
196 return virtio_gpu_execbuffer(dev, execbuffer, file_priv);
197}
198
199
200static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
201 struct drm_file *file_priv)
202{
203 struct virtio_gpu_device *vgdev = dev->dev_private;
204 struct drm_virtgpu_getparam *param = data;
205 int value;
206
207 switch (param->param) {
208 case VIRTGPU_PARAM_3D_FEATURES:
209 value = vgdev->has_virgl_3d == true ? 1 : 0;
210 break;
211 default:
212 return -EINVAL;
213 }
214 if (copy_to_user((void __user *)(unsigned long)param->value,
215 &value, sizeof(int))) {
216 return -EFAULT;
217 }
218 return 0;
219}
220
221static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
222 struct drm_file *file_priv)
223{
224 struct virtio_gpu_device *vgdev = dev->dev_private;
225 struct drm_virtgpu_resource_create *rc = data;
226 int ret;
227 uint32_t res_id;
228 struct virtio_gpu_object *qobj;
229 struct drm_gem_object *obj;
230 uint32_t handle = 0;
231 uint32_t size;
232 struct list_head validate_list;
233 struct ttm_validate_buffer mainbuf;
234 struct virtio_gpu_fence *fence = NULL;
235 struct ww_acquire_ctx ticket;
236 struct virtio_gpu_resource_create_3d rc_3d;
237
238 if (vgdev->has_virgl_3d == false) {
239 if (rc->depth > 1)
240 return -EINVAL;
241 if (rc->nr_samples > 1)
242 return -EINVAL;
243 if (rc->last_level > 1)
244 return -EINVAL;
245 if (rc->target != 2)
246 return -EINVAL;
247 if (rc->array_size > 1)
248 return -EINVAL;
249 }
250
251 INIT_LIST_HEAD(&validate_list);
252 memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
253
254 virtio_gpu_resource_id_get(vgdev, &res_id);
255
256 size = rc->size;
257
258 /* allocate a single page size object */
259 if (size == 0)
260 size = PAGE_SIZE;
261
262 qobj = virtio_gpu_alloc_object(dev, size, false, false);
263 if (IS_ERR(qobj)) {
264 ret = PTR_ERR(qobj);
265 goto fail_id;
266 }
267 obj = &qobj->gem_base;
268
269 if (!vgdev->has_virgl_3d) {
270 virtio_gpu_cmd_create_resource(vgdev, res_id, rc->format,
271 rc->width, rc->height);
272
273 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, NULL);
274 } else {
275 /* use a gem reference since unref list undoes them */
276 drm_gem_object_reference(&qobj->gem_base);
277 mainbuf.bo = &qobj->tbo;
278 list_add(&mainbuf.head, &validate_list);
279
280 ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
281 if (ret) {
282 DRM_DEBUG("failed to validate\n");
283 goto fail_unref;
284 }
285
286 rc_3d.resource_id = cpu_to_le32(res_id);
287 rc_3d.target = cpu_to_le32(rc->target);
288 rc_3d.format = cpu_to_le32(rc->format);
289 rc_3d.bind = cpu_to_le32(rc->bind);
290 rc_3d.width = cpu_to_le32(rc->width);
291 rc_3d.height = cpu_to_le32(rc->height);
292 rc_3d.depth = cpu_to_le32(rc->depth);
293 rc_3d.array_size = cpu_to_le32(rc->array_size);
294 rc_3d.last_level = cpu_to_le32(rc->last_level);
295 rc_3d.nr_samples = cpu_to_le32(rc->nr_samples);
296 rc_3d.flags = cpu_to_le32(rc->flags);
297
298 virtio_gpu_cmd_resource_create_3d(vgdev, &rc_3d, NULL);
299 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, &fence);
300 if (ret) {
301 ttm_eu_backoff_reservation(&ticket, &validate_list);
302 goto fail_unref;
303 }
304 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
305 }
306
307 qobj->hw_res_handle = res_id;
308
309 ret = drm_gem_handle_create(file_priv, obj, &handle);
310 if (ret) {
311
312 drm_gem_object_release(obj);
313 if (vgdev->has_virgl_3d) {
314 virtio_gpu_unref_list(&validate_list);
315 fence_put(&fence->f);
316 }
317 return ret;
318 }
319 drm_gem_object_unreference_unlocked(obj);
320
321 rc->res_handle = res_id; /* similiar to a VM address */
322 rc->bo_handle = handle;
323
324 if (vgdev->has_virgl_3d) {
325 virtio_gpu_unref_list(&validate_list);
326 fence_put(&fence->f);
327 }
328 return 0;
329fail_unref:
330 if (vgdev->has_virgl_3d) {
331 virtio_gpu_unref_list(&validate_list);
332 fence_put(&fence->f);
333 }
334//fail_obj:
335// drm_gem_object_handle_unreference_unlocked(obj);
336fail_id:
337 virtio_gpu_resource_id_put(vgdev, res_id);
338 return ret;
339}
340
341static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
342 struct drm_file *file_priv)
343{
344 struct drm_virtgpu_resource_info *ri = data;
345 struct drm_gem_object *gobj = NULL;
346 struct virtio_gpu_object *qobj = NULL;
347
348 gobj = drm_gem_object_lookup(dev, file_priv, ri->bo_handle);
349 if (gobj == NULL)
350 return -ENOENT;
351
352 qobj = gem_to_virtio_gpu_obj(gobj);
353
354 ri->size = qobj->gem_base.size;
355 ri->res_handle = qobj->hw_res_handle;
356 drm_gem_object_unreference_unlocked(gobj);
357 return 0;
358}
359
360static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
361 void *data,
362 struct drm_file *file)
363{
364 struct virtio_gpu_device *vgdev = dev->dev_private;
365 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
366 struct drm_virtgpu_3d_transfer_from_host *args = data;
367 struct drm_gem_object *gobj = NULL;
368 struct virtio_gpu_object *qobj = NULL;
369 struct virtio_gpu_fence *fence;
370 int ret;
371 u32 offset = args->offset;
372 struct virtio_gpu_box box;
373
374 if (vgdev->has_virgl_3d == false)
375 return -ENOSYS;
376
377 gobj = drm_gem_object_lookup(dev, file, args->bo_handle);
378 if (gobj == NULL)
379 return -ENOENT;
380
381 qobj = gem_to_virtio_gpu_obj(gobj);
382
383 ret = virtio_gpu_object_reserve(qobj, false);
384 if (ret)
385 goto out;
386
387 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement,
388 true, false);
389 if (unlikely(ret))
390 goto out_unres;
391
392 convert_to_hw_box(&box, &args->box);
393 virtio_gpu_cmd_transfer_from_host_3d
394 (vgdev, qobj->hw_res_handle,
395 vfpriv->ctx_id, offset, args->level,
396 &box, &fence);
397 reservation_object_add_excl_fence(qobj->tbo.resv,
398 &fence->f);
399
400 fence_put(&fence->f);
401out_unres:
402 virtio_gpu_object_unreserve(qobj);
403out:
404 drm_gem_object_unreference_unlocked(gobj);
405 return ret;
406}
407
408static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
409 struct drm_file *file)
410{
411 struct virtio_gpu_device *vgdev = dev->dev_private;
412 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
413 struct drm_virtgpu_3d_transfer_to_host *args = data;
414 struct drm_gem_object *gobj = NULL;
415 struct virtio_gpu_object *qobj = NULL;
416 struct virtio_gpu_fence *fence;
417 struct virtio_gpu_box box;
418 int ret;
419 u32 offset = args->offset;
420
421 gobj = drm_gem_object_lookup(dev, file, args->bo_handle);
422 if (gobj == NULL)
423 return -ENOENT;
424
425 qobj = gem_to_virtio_gpu_obj(gobj);
426
427 ret = virtio_gpu_object_reserve(qobj, false);
428 if (ret)
429 goto out;
430
431 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement,
432 true, false);
433 if (unlikely(ret))
434 goto out_unres;
435
436 convert_to_hw_box(&box, &args->box);
437 if (!vgdev->has_virgl_3d) {
438 virtio_gpu_cmd_transfer_to_host_2d
439 (vgdev, qobj->hw_res_handle, offset,
440 box.w, box.h, box.x, box.y, NULL);
441 } else {
442 virtio_gpu_cmd_transfer_to_host_3d
443 (vgdev, qobj->hw_res_handle,
444 vfpriv ? vfpriv->ctx_id : 0, offset,
445 args->level, &box, &fence);
446 reservation_object_add_excl_fence(qobj->tbo.resv,
447 &fence->f);
448 fence_put(&fence->f);
449 }
450
451out_unres:
452 virtio_gpu_object_unreserve(qobj);
453out:
454 drm_gem_object_unreference_unlocked(gobj);
455 return ret;
456}
457
458static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
459 struct drm_file *file)
460{
461 struct drm_virtgpu_3d_wait *args = data;
462 struct drm_gem_object *gobj = NULL;
463 struct virtio_gpu_object *qobj = NULL;
464 int ret;
465 bool nowait = false;
466
467 gobj = drm_gem_object_lookup(dev, file, args->handle);
468 if (gobj == NULL)
469 return -ENOENT;
470
471 qobj = gem_to_virtio_gpu_obj(gobj);
472
473 if (args->flags & VIRTGPU_WAIT_NOWAIT)
474 nowait = true;
475 ret = virtio_gpu_object_wait(qobj, nowait);
476
477 drm_gem_object_unreference_unlocked(gobj);
478 return ret;
479}
480
481static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
482 void *data, struct drm_file *file)
483{
484 struct virtio_gpu_device *vgdev = dev->dev_private;
485 struct drm_virtgpu_get_caps *args = data;
486 int size;
487 int i;
488 int found_valid = -1;
489 int ret;
490 struct virtio_gpu_drv_cap_cache *cache_ent;
491 void *ptr;
492 if (vgdev->num_capsets == 0)
493 return -ENOSYS;
494
495 spin_lock(&vgdev->display_info_lock);
496 for (i = 0; i < vgdev->num_capsets; i++) {
497 if (vgdev->capsets[i].id == args->cap_set_id) {
498 if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
499 found_valid = i;
500 break;
501 }
502 }
503 }
504
505 if (found_valid == -1) {
506 spin_unlock(&vgdev->display_info_lock);
507 return -EINVAL;
508 }
509
510 size = vgdev->capsets[found_valid].max_size;
511 if (args->size > size) {
512 spin_unlock(&vgdev->display_info_lock);
513 return -EINVAL;
514 }
515
516 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
517 if (cache_ent->id == args->cap_set_id &&
518 cache_ent->version == args->cap_set_ver) {
519 ptr = cache_ent->caps_cache;
520 spin_unlock(&vgdev->display_info_lock);
521 goto copy_exit;
522 }
523 }
524 spin_unlock(&vgdev->display_info_lock);
525
526 /* not in cache - need to talk to hw */
527 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
528 &cache_ent);
529
530 ret = wait_event_timeout(vgdev->resp_wq,
531 atomic_read(&cache_ent->is_valid), 5 * HZ);
532
533 ptr = cache_ent->caps_cache;
534
535copy_exit:
536 if (copy_to_user((void __user *)(unsigned long)args->addr, ptr, size))
537 return -EFAULT;
538
539 return 0;
540}
541
542struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
543 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
544 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
545
546 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
547 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
548
549 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
550 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
551
552 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
553 virtio_gpu_resource_create_ioctl,
554 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
555
556 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
557 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
558
559 /* make transfer async to the main ring? - no sure, can we
560 thread these in the underlying GL */
561 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
562 virtio_gpu_transfer_from_host_ioctl,
563 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
564 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
565 virtio_gpu_transfer_to_host_ioctl,
566 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
567
568 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
569 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
570
571 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
572 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
573};
1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Authors:
6 * Dave Airlie
7 * Alon Levy
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 */
27
28#include <linux/file.h>
29#include <linux/sync_file.h>
30
31#include <drm/drm_file.h>
32#include <drm/ttm/ttm_execbuf_util.h>
33#include <drm/virtgpu_drm.h>
34
35#include "virtgpu_drv.h"
36
37static void convert_to_hw_box(struct virtio_gpu_box *dst,
38 const struct drm_virtgpu_3d_box *src)
39{
40 dst->x = cpu_to_le32(src->x);
41 dst->y = cpu_to_le32(src->y);
42 dst->z = cpu_to_le32(src->z);
43 dst->w = cpu_to_le32(src->w);
44 dst->h = cpu_to_le32(src->h);
45 dst->d = cpu_to_le32(src->d);
46}
47
48static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
49 struct drm_file *file_priv)
50{
51 struct virtio_gpu_device *vgdev = dev->dev_private;
52 struct drm_virtgpu_map *virtio_gpu_map = data;
53
54 return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev,
55 virtio_gpu_map->handle,
56 &virtio_gpu_map->offset);
57}
58
59int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
60 struct list_head *head)
61{
62 struct ttm_operation_ctx ctx = { false, false };
63 struct ttm_validate_buffer *buf;
64 struct ttm_buffer_object *bo;
65 struct virtio_gpu_object *qobj;
66 int ret;
67
68 ret = ttm_eu_reserve_buffers(ticket, head, true, NULL, true);
69 if (ret != 0)
70 return ret;
71
72 list_for_each_entry(buf, head, head) {
73 bo = buf->bo;
74 qobj = container_of(bo, struct virtio_gpu_object, tbo);
75 ret = ttm_bo_validate(bo, &qobj->placement, &ctx);
76 if (ret) {
77 ttm_eu_backoff_reservation(ticket, head);
78 return ret;
79 }
80 }
81 return 0;
82}
83
84void virtio_gpu_unref_list(struct list_head *head)
85{
86 struct ttm_validate_buffer *buf;
87 struct ttm_buffer_object *bo;
88 struct virtio_gpu_object *qobj;
89
90 list_for_each_entry(buf, head, head) {
91 bo = buf->bo;
92 qobj = container_of(bo, struct virtio_gpu_object, tbo);
93
94 drm_gem_object_put_unlocked(&qobj->gem_base);
95 }
96}
97
98/*
99 * Usage of execbuffer:
100 * Relocations need to take into account the full VIRTIO_GPUDrawable size.
101 * However, the command as passed from user space must *not* contain the initial
102 * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
103 */
104static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
105 struct drm_file *drm_file)
106{
107 struct drm_virtgpu_execbuffer *exbuf = data;
108 struct virtio_gpu_device *vgdev = dev->dev_private;
109 struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv;
110 struct drm_gem_object *gobj;
111 struct virtio_gpu_fence *out_fence;
112 struct virtio_gpu_object *qobj;
113 int ret;
114 uint32_t *bo_handles = NULL;
115 void __user *user_bo_handles = NULL;
116 struct list_head validate_list;
117 struct ttm_validate_buffer *buflist = NULL;
118 int i;
119 struct ww_acquire_ctx ticket;
120 struct sync_file *sync_file;
121 int in_fence_fd = exbuf->fence_fd;
122 int out_fence_fd = -1;
123 void *buf;
124
125 if (vgdev->has_virgl_3d == false)
126 return -ENOSYS;
127
128 if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS))
129 return -EINVAL;
130
131 exbuf->fence_fd = -1;
132
133 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
134 struct dma_fence *in_fence;
135
136 in_fence = sync_file_get_fence(in_fence_fd);
137
138 if (!in_fence)
139 return -EINVAL;
140
141 /*
142 * Wait if the fence is from a foreign context, or if the fence
143 * array contains any fence from a foreign context.
144 */
145 ret = 0;
146 if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context))
147 ret = dma_fence_wait(in_fence, true);
148
149 dma_fence_put(in_fence);
150 if (ret)
151 return ret;
152 }
153
154 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
155 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
156 if (out_fence_fd < 0)
157 return out_fence_fd;
158 }
159
160 INIT_LIST_HEAD(&validate_list);
161 if (exbuf->num_bo_handles) {
162
163 bo_handles = kvmalloc_array(exbuf->num_bo_handles,
164 sizeof(uint32_t), GFP_KERNEL);
165 buflist = kvmalloc_array(exbuf->num_bo_handles,
166 sizeof(struct ttm_validate_buffer),
167 GFP_KERNEL | __GFP_ZERO);
168 if (!bo_handles || !buflist) {
169 ret = -ENOMEM;
170 goto out_unused_fd;
171 }
172
173 user_bo_handles = u64_to_user_ptr(exbuf->bo_handles);
174 if (copy_from_user(bo_handles, user_bo_handles,
175 exbuf->num_bo_handles * sizeof(uint32_t))) {
176 ret = -EFAULT;
177 goto out_unused_fd;
178 }
179
180 for (i = 0; i < exbuf->num_bo_handles; i++) {
181 gobj = drm_gem_object_lookup(drm_file, bo_handles[i]);
182 if (!gobj) {
183 ret = -ENOENT;
184 goto out_unused_fd;
185 }
186
187 qobj = gem_to_virtio_gpu_obj(gobj);
188 buflist[i].bo = &qobj->tbo;
189
190 list_add(&buflist[i].head, &validate_list);
191 }
192 kvfree(bo_handles);
193 bo_handles = NULL;
194 }
195
196 ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
197 if (ret)
198 goto out_free;
199
200 buf = memdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
201 if (IS_ERR(buf)) {
202 ret = PTR_ERR(buf);
203 goto out_unresv;
204 }
205
206 out_fence = virtio_gpu_fence_alloc(vgdev);
207 if(!out_fence) {
208 ret = -ENOMEM;
209 goto out_memdup;
210 }
211
212 if (out_fence_fd >= 0) {
213 sync_file = sync_file_create(&out_fence->f);
214 if (!sync_file) {
215 dma_fence_put(&out_fence->f);
216 ret = -ENOMEM;
217 goto out_memdup;
218 }
219
220 exbuf->fence_fd = out_fence_fd;
221 fd_install(out_fence_fd, sync_file->file);
222 }
223
224 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
225 vfpriv->ctx_id, out_fence);
226
227 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &out_fence->f);
228
229 /* fence the command bo */
230 virtio_gpu_unref_list(&validate_list);
231 kvfree(buflist);
232 return 0;
233
234out_memdup:
235 kfree(buf);
236out_unresv:
237 ttm_eu_backoff_reservation(&ticket, &validate_list);
238out_free:
239 virtio_gpu_unref_list(&validate_list);
240out_unused_fd:
241 kvfree(bo_handles);
242 kvfree(buflist);
243
244 if (out_fence_fd >= 0)
245 put_unused_fd(out_fence_fd);
246
247 return ret;
248}
249
250static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
251 struct drm_file *file_priv)
252{
253 struct virtio_gpu_device *vgdev = dev->dev_private;
254 struct drm_virtgpu_getparam *param = data;
255 int value;
256
257 switch (param->param) {
258 case VIRTGPU_PARAM_3D_FEATURES:
259 value = vgdev->has_virgl_3d == true ? 1 : 0;
260 break;
261 case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
262 value = 1;
263 break;
264 default:
265 return -EINVAL;
266 }
267 if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
268 return -EFAULT;
269
270 return 0;
271}
272
273static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
274 struct drm_file *file_priv)
275{
276 struct virtio_gpu_device *vgdev = dev->dev_private;
277 struct drm_virtgpu_resource_create *rc = data;
278 struct virtio_gpu_fence *fence;
279 int ret;
280 struct virtio_gpu_object *qobj;
281 struct drm_gem_object *obj;
282 uint32_t handle = 0;
283 struct virtio_gpu_object_params params = { 0 };
284
285 if (vgdev->has_virgl_3d == false) {
286 if (rc->depth > 1)
287 return -EINVAL;
288 if (rc->nr_samples > 1)
289 return -EINVAL;
290 if (rc->last_level > 1)
291 return -EINVAL;
292 if (rc->target != 2)
293 return -EINVAL;
294 if (rc->array_size > 1)
295 return -EINVAL;
296 }
297
298 params.format = rc->format;
299 params.width = rc->width;
300 params.height = rc->height;
301 params.size = rc->size;
302 if (vgdev->has_virgl_3d) {
303 params.virgl = true;
304 params.target = rc->target;
305 params.bind = rc->bind;
306 params.depth = rc->depth;
307 params.array_size = rc->array_size;
308 params.last_level = rc->last_level;
309 params.nr_samples = rc->nr_samples;
310 params.flags = rc->flags;
311 }
312 /* allocate a single page size object */
313 if (params.size == 0)
314 params.size = PAGE_SIZE;
315
316 fence = virtio_gpu_fence_alloc(vgdev);
317 if (!fence)
318 return -ENOMEM;
319 qobj = virtio_gpu_alloc_object(dev, ¶ms, fence);
320 dma_fence_put(&fence->f);
321 if (IS_ERR(qobj))
322 return PTR_ERR(qobj);
323 obj = &qobj->gem_base;
324
325 ret = drm_gem_handle_create(file_priv, obj, &handle);
326 if (ret) {
327 drm_gem_object_release(obj);
328 return ret;
329 }
330 drm_gem_object_put_unlocked(obj);
331
332 rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
333 rc->bo_handle = handle;
334 return 0;
335}
336
337static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
338 struct drm_file *file_priv)
339{
340 struct drm_virtgpu_resource_info *ri = data;
341 struct drm_gem_object *gobj = NULL;
342 struct virtio_gpu_object *qobj = NULL;
343
344 gobj = drm_gem_object_lookup(file_priv, ri->bo_handle);
345 if (gobj == NULL)
346 return -ENOENT;
347
348 qobj = gem_to_virtio_gpu_obj(gobj);
349
350 ri->size = qobj->gem_base.size;
351 ri->res_handle = qobj->hw_res_handle;
352 drm_gem_object_put_unlocked(gobj);
353 return 0;
354}
355
356static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
357 void *data,
358 struct drm_file *file)
359{
360 struct virtio_gpu_device *vgdev = dev->dev_private;
361 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
362 struct drm_virtgpu_3d_transfer_from_host *args = data;
363 struct ttm_operation_ctx ctx = { true, false };
364 struct drm_gem_object *gobj = NULL;
365 struct virtio_gpu_object *qobj = NULL;
366 struct virtio_gpu_fence *fence;
367 int ret;
368 u32 offset = args->offset;
369 struct virtio_gpu_box box;
370
371 if (vgdev->has_virgl_3d == false)
372 return -ENOSYS;
373
374 gobj = drm_gem_object_lookup(file, args->bo_handle);
375 if (gobj == NULL)
376 return -ENOENT;
377
378 qobj = gem_to_virtio_gpu_obj(gobj);
379
380 ret = virtio_gpu_object_reserve(qobj, false);
381 if (ret)
382 goto out;
383
384 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
385 if (unlikely(ret))
386 goto out_unres;
387
388 convert_to_hw_box(&box, &args->box);
389
390 fence = virtio_gpu_fence_alloc(vgdev);
391 if (!fence) {
392 ret = -ENOMEM;
393 goto out_unres;
394 }
395 virtio_gpu_cmd_transfer_from_host_3d
396 (vgdev, qobj->hw_res_handle,
397 vfpriv->ctx_id, offset, args->level,
398 &box, fence);
399 dma_resv_add_excl_fence(qobj->tbo.base.resv,
400 &fence->f);
401
402 dma_fence_put(&fence->f);
403out_unres:
404 virtio_gpu_object_unreserve(qobj);
405out:
406 drm_gem_object_put_unlocked(gobj);
407 return ret;
408}
409
410static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
411 struct drm_file *file)
412{
413 struct virtio_gpu_device *vgdev = dev->dev_private;
414 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
415 struct drm_virtgpu_3d_transfer_to_host *args = data;
416 struct ttm_operation_ctx ctx = { true, false };
417 struct drm_gem_object *gobj = NULL;
418 struct virtio_gpu_object *qobj = NULL;
419 struct virtio_gpu_fence *fence;
420 struct virtio_gpu_box box;
421 int ret;
422 u32 offset = args->offset;
423
424 gobj = drm_gem_object_lookup(file, args->bo_handle);
425 if (gobj == NULL)
426 return -ENOENT;
427
428 qobj = gem_to_virtio_gpu_obj(gobj);
429
430 ret = virtio_gpu_object_reserve(qobj, false);
431 if (ret)
432 goto out;
433
434 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
435 if (unlikely(ret))
436 goto out_unres;
437
438 convert_to_hw_box(&box, &args->box);
439 if (!vgdev->has_virgl_3d) {
440 virtio_gpu_cmd_transfer_to_host_2d
441 (vgdev, qobj, offset,
442 box.w, box.h, box.x, box.y, NULL);
443 } else {
444 fence = virtio_gpu_fence_alloc(vgdev);
445 if (!fence) {
446 ret = -ENOMEM;
447 goto out_unres;
448 }
449 virtio_gpu_cmd_transfer_to_host_3d
450 (vgdev, qobj,
451 vfpriv ? vfpriv->ctx_id : 0, offset,
452 args->level, &box, fence);
453 dma_resv_add_excl_fence(qobj->tbo.base.resv,
454 &fence->f);
455 dma_fence_put(&fence->f);
456 }
457
458out_unres:
459 virtio_gpu_object_unreserve(qobj);
460out:
461 drm_gem_object_put_unlocked(gobj);
462 return ret;
463}
464
465static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
466 struct drm_file *file)
467{
468 struct drm_virtgpu_3d_wait *args = data;
469 struct drm_gem_object *gobj = NULL;
470 struct virtio_gpu_object *qobj = NULL;
471 int ret;
472 bool nowait = false;
473
474 gobj = drm_gem_object_lookup(file, args->handle);
475 if (gobj == NULL)
476 return -ENOENT;
477
478 qobj = gem_to_virtio_gpu_obj(gobj);
479
480 if (args->flags & VIRTGPU_WAIT_NOWAIT)
481 nowait = true;
482 ret = virtio_gpu_object_wait(qobj, nowait);
483
484 drm_gem_object_put_unlocked(gobj);
485 return ret;
486}
487
488static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
489 void *data, struct drm_file *file)
490{
491 struct virtio_gpu_device *vgdev = dev->dev_private;
492 struct drm_virtgpu_get_caps *args = data;
493 unsigned size, host_caps_size;
494 int i;
495 int found_valid = -1;
496 int ret;
497 struct virtio_gpu_drv_cap_cache *cache_ent;
498 void *ptr;
499
500 if (vgdev->num_capsets == 0)
501 return -ENOSYS;
502
503 /* don't allow userspace to pass 0 */
504 if (args->size == 0)
505 return -EINVAL;
506
507 spin_lock(&vgdev->display_info_lock);
508 for (i = 0; i < vgdev->num_capsets; i++) {
509 if (vgdev->capsets[i].id == args->cap_set_id) {
510 if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
511 found_valid = i;
512 break;
513 }
514 }
515 }
516
517 if (found_valid == -1) {
518 spin_unlock(&vgdev->display_info_lock);
519 return -EINVAL;
520 }
521
522 host_caps_size = vgdev->capsets[found_valid].max_size;
523 /* only copy to user the minimum of the host caps size or the guest caps size */
524 size = min(args->size, host_caps_size);
525
526 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
527 if (cache_ent->id == args->cap_set_id &&
528 cache_ent->version == args->cap_set_ver) {
529 spin_unlock(&vgdev->display_info_lock);
530 goto copy_exit;
531 }
532 }
533 spin_unlock(&vgdev->display_info_lock);
534
535 /* not in cache - need to talk to hw */
536 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
537 &cache_ent);
538
539copy_exit:
540 ret = wait_event_timeout(vgdev->resp_wq,
541 atomic_read(&cache_ent->is_valid), 5 * HZ);
542 if (!ret)
543 return -EBUSY;
544
545 /* is_valid check must proceed before copy of the cache entry. */
546 smp_rmb();
547
548 ptr = cache_ent->caps_cache;
549
550 if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
551 return -EFAULT;
552
553 return 0;
554}
555
556struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
557 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
558 DRM_RENDER_ALLOW),
559
560 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
561 DRM_RENDER_ALLOW),
562
563 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
564 DRM_RENDER_ALLOW),
565
566 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
567 virtio_gpu_resource_create_ioctl,
568 DRM_RENDER_ALLOW),
569
570 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
571 DRM_RENDER_ALLOW),
572
573 /* make transfer async to the main ring? - no sure, can we
574 * thread these in the underlying GL
575 */
576 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
577 virtio_gpu_transfer_from_host_ioctl,
578 DRM_RENDER_ALLOW),
579 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
580 virtio_gpu_transfer_to_host_ioctl,
581 DRM_RENDER_ALLOW),
582
583 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
584 DRM_RENDER_ALLOW),
585
586 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
587 DRM_RENDER_ALLOW),
588};