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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24 *
25 */
26
27#include <drm/drmP.h>
28#include <drm/drm_crtc.h>
29#include <drm/drm_edid.h>
30#include <drm/i915_drm.h>
31#include <drm/drm_panel.h>
32#include <linux/slab.h>
33#include <video/mipi_display.h>
34#include <asm/intel-mid.h>
35#include <video/mipi_display.h>
36#include "i915_drv.h"
37#include "intel_drv.h"
38#include "intel_dsi.h"
39
40struct vbt_panel {
41 struct drm_panel panel;
42 struct intel_dsi *intel_dsi;
43};
44
45static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
46{
47 return container_of(panel, struct vbt_panel, panel);
48}
49
50#define MIPI_TRANSFER_MODE_SHIFT 0
51#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
52#define MIPI_PORT_SHIFT 3
53
54#define PREPARE_CNT_MAX 0x3F
55#define EXIT_ZERO_CNT_MAX 0x3F
56#define CLK_ZERO_CNT_MAX 0xFF
57#define TRAIL_CNT_MAX 0x1F
58
59#define NS_KHZ_RATIO 1000000
60
61#define GPI0_NC_0_HV_DDI0_HPD 0x4130
62#define GPIO_NC_0_HV_DDI0_PAD 0x4138
63#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
64#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
65#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
66#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
67#define GPIO_NC_3_PANEL0_VDDEN 0x4140
68#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
69#define GPIO_NC_4_PANEL0_BLKEN 0x4150
70#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
71#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
72#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
73#define GPIO_NC_6_PCONF0 0x4180
74#define GPIO_NC_6_PAD 0x4188
75#define GPIO_NC_7_PCONF0 0x4190
76#define GPIO_NC_7_PAD 0x4198
77#define GPIO_NC_8_PCONF0 0x4170
78#define GPIO_NC_8_PAD 0x4178
79#define GPIO_NC_9_PCONF0 0x4100
80#define GPIO_NC_9_PAD 0x4108
81#define GPIO_NC_10_PCONF0 0x40E0
82#define GPIO_NC_10_PAD 0x40E8
83#define GPIO_NC_11_PCONF0 0x40F0
84#define GPIO_NC_11_PAD 0x40F8
85
86struct gpio_table {
87 u16 function_reg;
88 u16 pad_reg;
89 u8 init;
90};
91
92static struct gpio_table gtable[] = {
93 { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
94 { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
95 { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
96 { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
97 { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
98 { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
99 { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
100 { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
101 { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
102 { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
103 { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
104 { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
105};
106
107static inline enum port intel_dsi_seq_port_to_port(u8 port)
108{
109 return port ? PORT_C : PORT_A;
110}
111
112static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
113 const u8 *data)
114{
115 struct mipi_dsi_device *dsi_device;
116 u8 type, flags, seq_port;
117 u16 len;
118 enum port port;
119
120 flags = *data++;
121 type = *data++;
122
123 len = *((u16 *) data);
124 data += 2;
125
126 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
127
128 /* For DSI single link on Port A & C, the seq_port value which is
129 * parsed from Sequence Block#53 of VBT has been set to 0
130 * Now, read/write of packets for the DSI single link on Port A and
131 * Port C will based on the DVO port from VBT block 2.
132 */
133 if (intel_dsi->ports == (1 << PORT_C))
134 port = PORT_C;
135 else
136 port = intel_dsi_seq_port_to_port(seq_port);
137
138 dsi_device = intel_dsi->dsi_hosts[port]->device;
139 if (!dsi_device) {
140 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
141 goto out;
142 }
143
144 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
145 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
146 else
147 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
148
149 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
150
151 switch (type) {
152 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
153 mipi_dsi_generic_write(dsi_device, NULL, 0);
154 break;
155 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
156 mipi_dsi_generic_write(dsi_device, data, 1);
157 break;
158 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
159 mipi_dsi_generic_write(dsi_device, data, 2);
160 break;
161 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
162 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
163 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
164 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
165 break;
166 case MIPI_DSI_GENERIC_LONG_WRITE:
167 mipi_dsi_generic_write(dsi_device, data, len);
168 break;
169 case MIPI_DSI_DCS_SHORT_WRITE:
170 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
171 break;
172 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
173 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
174 break;
175 case MIPI_DSI_DCS_READ:
176 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
177 break;
178 case MIPI_DSI_DCS_LONG_WRITE:
179 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
180 break;
181 }
182
183out:
184 data += len;
185
186 return data;
187}
188
189static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
190{
191 u32 delay = *((const u32 *) data);
192
193 usleep_range(delay, delay + 10);
194 data += 4;
195
196 return data;
197}
198
199static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
200{
201 u8 gpio, action;
202 u16 function, pad;
203 u32 val;
204 struct drm_device *dev = intel_dsi->base.base.dev;
205 struct drm_i915_private *dev_priv = dev->dev_private;
206
207 if (dev_priv->vbt.dsi.seq_version >= 3)
208 data++;
209
210 gpio = *data++;
211
212 /* pull up/down */
213 action = *data++ & 1;
214
215 if (gpio >= ARRAY_SIZE(gtable)) {
216 DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
217 goto out;
218 }
219
220 if (!IS_VALLEYVIEW(dev_priv)) {
221 DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
222 goto out;
223 }
224
225 if (dev_priv->vbt.dsi.seq_version >= 3) {
226 DRM_DEBUG_KMS("GPIO element v3 not supported\n");
227 goto out;
228 }
229
230 function = gtable[gpio].function_reg;
231 pad = gtable[gpio].pad_reg;
232
233 mutex_lock(&dev_priv->sb_lock);
234 if (!gtable[gpio].init) {
235 /* program the function */
236 /* FIXME: remove constant below */
237 vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
238 0x2000CC00);
239 gtable[gpio].init = 1;
240 }
241
242 val = 0x4 | action;
243
244 /* pull up/down */
245 vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
246 mutex_unlock(&dev_priv->sb_lock);
247
248out:
249 return data;
250}
251
252static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
253{
254 return data + *(data + 6) + 7;
255}
256
257typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
258 const u8 *data);
259static const fn_mipi_elem_exec exec_elem[] = {
260 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
261 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
262 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
263 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip,
264};
265
266/*
267 * MIPI Sequence from VBT #53 parsing logic
268 * We have already separated each seqence during bios parsing
269 * Following is generic execution function for any sequence
270 */
271
272static const char * const seq_name[] = {
273 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
274 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
275 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
276 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
277 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
278 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
279 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
280 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
281 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
282 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
283 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
284};
285
286static const char *sequence_name(enum mipi_seq seq_id)
287{
288 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
289 return seq_name[seq_id];
290 else
291 return "(unknown)";
292}
293
294static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id)
295{
296 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
297 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
298 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
299 const u8 *data;
300 fn_mipi_elem_exec mipi_elem_exec;
301
302 if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
303 return;
304
305 data = dev_priv->vbt.dsi.sequence[seq_id];
306 if (!data) {
307 DRM_DEBUG_KMS("MIPI sequence %d - %s not available\n",
308 seq_id, sequence_name(seq_id));
309 return;
310 }
311
312 WARN_ON(*data != seq_id);
313
314 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
315 seq_id, sequence_name(seq_id));
316
317 /* Skip Sequence Byte. */
318 data++;
319
320 /* Skip Size of Sequence. */
321 if (dev_priv->vbt.dsi.seq_version >= 3)
322 data += 4;
323
324 while (1) {
325 u8 operation_byte = *data++;
326 u8 operation_size = 0;
327
328 if (operation_byte == MIPI_SEQ_ELEM_END)
329 break;
330
331 if (operation_byte < ARRAY_SIZE(exec_elem))
332 mipi_elem_exec = exec_elem[operation_byte];
333 else
334 mipi_elem_exec = NULL;
335
336 /* Size of Operation. */
337 if (dev_priv->vbt.dsi.seq_version >= 3)
338 operation_size = *data++;
339
340 if (mipi_elem_exec) {
341 data = mipi_elem_exec(intel_dsi, data);
342 } else if (operation_size) {
343 /* We have size, skip. */
344 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
345 operation_byte);
346 data += operation_size;
347 } else {
348 /* No size, can't skip without parsing. */
349 DRM_ERROR("Unsupported MIPI operation byte %u\n",
350 operation_byte);
351 return;
352 }
353 }
354}
355
356static int vbt_panel_prepare(struct drm_panel *panel)
357{
358 generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
359 generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
360
361 return 0;
362}
363
364static int vbt_panel_unprepare(struct drm_panel *panel)
365{
366 generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
367
368 return 0;
369}
370
371static int vbt_panel_enable(struct drm_panel *panel)
372{
373 generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_ON);
374
375 return 0;
376}
377
378static int vbt_panel_disable(struct drm_panel *panel)
379{
380 generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_OFF);
381
382 return 0;
383}
384
385static int vbt_panel_get_modes(struct drm_panel *panel)
386{
387 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
388 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
389 struct drm_device *dev = intel_dsi->base.base.dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 struct drm_display_mode *mode;
392
393 if (!panel->connector)
394 return 0;
395
396 mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
397 if (!mode)
398 return 0;
399
400 mode->type |= DRM_MODE_TYPE_PREFERRED;
401
402 drm_mode_probed_add(panel->connector, mode);
403
404 return 1;
405}
406
407static const struct drm_panel_funcs vbt_panel_funcs = {
408 .disable = vbt_panel_disable,
409 .unprepare = vbt_panel_unprepare,
410 .prepare = vbt_panel_prepare,
411 .enable = vbt_panel_enable,
412 .get_modes = vbt_panel_get_modes,
413};
414
415struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
416{
417 struct drm_device *dev = intel_dsi->base.base.dev;
418 struct drm_i915_private *dev_priv = dev->dev_private;
419 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
420 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
421 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
422 struct vbt_panel *vbt_panel;
423 u32 bits_per_pixel = 24;
424 u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
425 u32 ui_num, ui_den;
426 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
427 u32 ths_prepare_ns, tclk_trail_ns;
428 u32 tclk_prepare_clkzero, ths_prepare_hszero;
429 u32 lp_to_hs_switch, hs_to_lp_switch;
430 u32 pclk, computed_ddr;
431 u16 burst_mode_ratio;
432 enum port port;
433
434 DRM_DEBUG_KMS("\n");
435
436 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
437 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
438 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
439 intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
440 intel_dsi->dual_link = mipi_config->dual_link;
441 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
442
443 bits_per_pixel = dsi_pixel_format_bpp(intel_dsi->pixel_format);
444
445 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
446 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
447 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
448 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
449 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
450 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
451 intel_dsi->init_count = mipi_config->master_init_timer;
452 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
453 intel_dsi->video_frmt_cfg_bits =
454 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
455
456 pclk = mode->clock;
457
458 /* In dual link mode each port needs half of pixel clock */
459 if (intel_dsi->dual_link) {
460 pclk = pclk / 2;
461
462 /* we can enable pixel_overlap if needed by panel. In this
463 * case we need to increase the pixelclock for extra pixels
464 */
465 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
466 pclk += DIV_ROUND_UP(mode->vtotal *
467 intel_dsi->pixel_overlap *
468 60, 1000);
469 }
470 }
471
472 /* Burst Mode Ratio
473 * Target ddr frequency from VBT / non burst ddr freq
474 * multiply by 100 to preserve remainder
475 */
476 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
477 if (mipi_config->target_burst_mode_freq) {
478 computed_ddr =
479 (pclk * bits_per_pixel) / intel_dsi->lane_count;
480
481 if (mipi_config->target_burst_mode_freq <
482 computed_ddr) {
483 DRM_ERROR("Burst mode freq is less than computed\n");
484 return NULL;
485 }
486
487 burst_mode_ratio = DIV_ROUND_UP(
488 mipi_config->target_burst_mode_freq * 100,
489 computed_ddr);
490
491 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
492 } else {
493 DRM_ERROR("Burst mode target is not set\n");
494 return NULL;
495 }
496 } else
497 burst_mode_ratio = 100;
498
499 intel_dsi->burst_mode_ratio = burst_mode_ratio;
500 intel_dsi->pclk = pclk;
501
502 bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
503
504 switch (intel_dsi->escape_clk_div) {
505 case 0:
506 tlpx_ns = 50;
507 break;
508 case 1:
509 tlpx_ns = 100;
510 break;
511
512 case 2:
513 tlpx_ns = 200;
514 break;
515 default:
516 tlpx_ns = 50;
517 break;
518 }
519
520 switch (intel_dsi->lane_count) {
521 case 1:
522 case 2:
523 extra_byte_count = 2;
524 break;
525 case 3:
526 extra_byte_count = 4;
527 break;
528 case 4:
529 default:
530 extra_byte_count = 3;
531 break;
532 }
533
534 /*
535 * ui(s) = 1/f [f in hz]
536 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
537 */
538
539 /* in Kbps */
540 ui_num = NS_KHZ_RATIO;
541 ui_den = bitrate;
542
543 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
544 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
545
546 /*
547 * B060
548 * LP byte clock = TLPX/ (8UI)
549 */
550 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
551
552 /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
553 *
554 * Since txddrclkhs_i is 2xUI, all the count values programmed in
555 * DPHY param register are divided by 2
556 *
557 * prepare count
558 */
559 ths_prepare_ns = max(mipi_config->ths_prepare,
560 mipi_config->tclk_prepare);
561 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
562
563 /* exit zero count */
564 exit_zero_cnt = DIV_ROUND_UP(
565 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
566 ui_num * 2
567 );
568
569 /*
570 * Exit zero is unified val ths_zero and ths_exit
571 * minimum value for ths_exit = 110ns
572 * min (exit_zero_cnt * 2) = 110/UI
573 * exit_zero_cnt = 55/UI
574 */
575 if (exit_zero_cnt < (55 * ui_den / ui_num))
576 if ((55 * ui_den) % ui_num)
577 exit_zero_cnt += 1;
578
579 /* clk zero count */
580 clk_zero_cnt = DIV_ROUND_UP(
581 (tclk_prepare_clkzero - ths_prepare_ns)
582 * ui_den, 2 * ui_num);
583
584 /* trail count */
585 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
586 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
587
588 if (prepare_cnt > PREPARE_CNT_MAX ||
589 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
590 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
591 trail_cnt > TRAIL_CNT_MAX)
592 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
593
594 if (prepare_cnt > PREPARE_CNT_MAX)
595 prepare_cnt = PREPARE_CNT_MAX;
596
597 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
598 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
599
600 if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
601 clk_zero_cnt = CLK_ZERO_CNT_MAX;
602
603 if (trail_cnt > TRAIL_CNT_MAX)
604 trail_cnt = TRAIL_CNT_MAX;
605
606 /* B080 */
607 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
608 clk_zero_cnt << 8 | prepare_cnt;
609
610 /*
611 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
612 * + 10UI + Extra Byte Count
613 *
614 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
615 * Extra Byte Count is calculated according to number of lanes.
616 * High Low Switch Count is the Max of LP to HS and
617 * HS to LP switch count
618 *
619 */
620 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
621
622 /* B044 */
623 /* FIXME:
624 * The comment above does not match with the code */
625 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
626 exit_zero_cnt * 2 + 10, 8);
627
628 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
629
630 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
631 intel_dsi->hs_to_lp_count += extra_byte_count;
632
633 /* B088 */
634 /* LP -> HS for clock lanes
635 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
636 * extra byte count
637 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
638 * 2(in UI) + extra byte count
639 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
640 * 8 + extra byte count
641 */
642 intel_dsi->clk_lp_to_hs_count =
643 DIV_ROUND_UP(
644 4 * tlpx_ui + prepare_cnt * 2 +
645 clk_zero_cnt * 2,
646 8);
647
648 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
649
650 /* HS->LP for Clock Lanes
651 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
652 * Extra byte count
653 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
654 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
655 * Extra byte count
656 */
657 intel_dsi->clk_hs_to_lp_count =
658 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
659 8);
660 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
661
662 DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
663 DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
664 "disabled" : "enabled");
665 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
666 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
667 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
668 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
669 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
670 else
671 DRM_DEBUG_KMS("Dual link: NONE\n");
672 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
673 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
674 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
675 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
676 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
677 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
678 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
679 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
680 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
681 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
682 DRM_DEBUG_KMS("BTA %s\n",
683 intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
684 "disabled" : "enabled");
685
686 /* delays in VBT are in unit of 100us, so need to convert
687 * here in ms
688 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
689 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
690 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
691 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
692 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
693 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
694
695 /* This is cheating a bit with the cleanup. */
696 vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL);
697 if (!vbt_panel)
698 return NULL;
699
700 vbt_panel->intel_dsi = intel_dsi;
701 drm_panel_init(&vbt_panel->panel);
702 vbt_panel->panel.funcs = &vbt_panel_funcs;
703 drm_panel_add(&vbt_panel->panel);
704
705 /* a regular driver would get the device in probe */
706 for_each_dsi_port(port, intel_dsi->ports) {
707 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
708 }
709
710 return &vbt_panel->panel;
711}