1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2019 Intel Corporation
  4 */
  5
  6#ifndef __I915_IRQ_H__
  7#define __I915_IRQ_H__
  8
  9#include <linux/ktime.h>
 10#include <linux/types.h>
 11
 12#include "display/intel_display.h"
 13#include "i915_reg.h"
 14
 15struct drm_crtc;
 16struct drm_device;
 17struct drm_display_mode;
 18struct drm_i915_private;
 19struct intel_crtc;
 20struct intel_crtc;
 21struct intel_gt;
 22struct intel_guc;
 23struct intel_uncore;
 24
 25void gen11_rps_irq_handler(struct intel_gt *gt, u32 pm_iir);
 26void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 27
 28void intel_irq_init(struct drm_i915_private *dev_priv);
 29void intel_irq_fini(struct drm_i915_private *dev_priv);
 30int intel_irq_install(struct drm_i915_private *dev_priv);
 31void intel_irq_uninstall(struct drm_i915_private *dev_priv);
 32
 33u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 34			      enum pipe pipe);
 35void
 36i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 37		     u32 status_mask);
 38
 39void
 40i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 41		      u32 status_mask);
 42
 43void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
 44void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
 45
 46void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 47				   u32 mask,
 48				   u32 bits);
 49void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 50			    u32 interrupt_mask,
 51			    u32 enabled_irq_mask);
 52static inline void
 53ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
 54{
 55	ilk_update_display_irq(dev_priv, bits, bits);
 56}
 57static inline void
 58ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
 59{
 60	ilk_update_display_irq(dev_priv, bits, 0);
 61}
 62void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 63			 enum pipe pipe,
 64			 u32 interrupt_mask,
 65			 u32 enabled_irq_mask);
 66static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
 67				       enum pipe pipe, u32 bits)
 68{
 69	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
 70}
 71static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
 72					enum pipe pipe, u32 bits)
 73{
 74	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
 75}
 76void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 77				  u32 interrupt_mask,
 78				  u32 enabled_irq_mask);
 79static inline void
 80ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
 81{
 82	ibx_display_interrupt_update(dev_priv, bits, bits);
 83}
 84static inline void
 85ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
 86{
 87	ibx_display_interrupt_update(dev_priv, bits, 0);
 88}
 89
 90void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
 91void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
 92void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
 93void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
 94void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
 95void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
 96void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
 97u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
 98
 99void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
100void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
101bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
102void intel_synchronize_irq(struct drm_i915_private *i915);
103
104int intel_get_crtc_scanline(struct intel_crtc *crtc);
105void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
106				     u8 pipe_mask);
107void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
108				     u8 pipe_mask);
109void gen9_reset_guc_interrupts(struct intel_guc *guc);
110void gen9_enable_guc_interrupts(struct intel_guc *guc);
111void gen9_disable_guc_interrupts(struct intel_guc *guc);
112void gen11_reset_guc_interrupts(struct intel_guc *guc);
113void gen11_enable_guc_interrupts(struct intel_guc *guc);
114void gen11_disable_guc_interrupts(struct intel_guc *guc);
115
116bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
117			      bool in_vblank_irq, int *vpos, int *hpos,
118			      ktime_t *stime, ktime_t *etime,
119			      const struct drm_display_mode *mode);
120
121u32 i915_get_vblank_counter(struct drm_crtc *crtc);
122u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
123
124int i8xx_enable_vblank(struct drm_crtc *crtc);
125int i945gm_enable_vblank(struct drm_crtc *crtc);
126int i965_enable_vblank(struct drm_crtc *crtc);
127int ilk_enable_vblank(struct drm_crtc *crtc);
128int bdw_enable_vblank(struct drm_crtc *crtc);
129void i8xx_disable_vblank(struct drm_crtc *crtc);
130void i945gm_disable_vblank(struct drm_crtc *crtc);
131void i965_disable_vblank(struct drm_crtc *crtc);
132void ilk_disable_vblank(struct drm_crtc *crtc);
133void bdw_disable_vblank(struct drm_crtc *crtc);
134
135void gen2_irq_reset(struct intel_uncore *uncore);
136void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
137		    i915_reg_t iir, i915_reg_t ier);
138
139void gen2_irq_init(struct intel_uncore *uncore,
140		   u32 imr_val, u32 ier_val);
141void gen3_irq_init(struct intel_uncore *uncore,
142		   i915_reg_t imr, u32 imr_val,
143		   i915_reg_t ier, u32 ier_val,
144		   i915_reg_t iir);
145
146#define GEN8_IRQ_RESET_NDX(uncore, type, which) \
147({ \
148	unsigned int which_ = which; \
149	gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
150		       GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
151})
152
153#define GEN3_IRQ_RESET(uncore, type) \
154	gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
155
156#define GEN2_IRQ_RESET(uncore) \
157	gen2_irq_reset(uncore)
158
159#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
160({ \
161	unsigned int which_ = which; \
162	gen3_irq_init((uncore), \
163		      GEN8_##type##_IMR(which_), imr_val, \
164		      GEN8_##type##_IER(which_), ier_val, \
165		      GEN8_##type##_IIR(which_)); \
166})
167
168#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
169	gen3_irq_init((uncore), \
170		      type##IMR, imr_val, \
171		      type##IER, ier_val, \
172		      type##IIR)
173
174#define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
175	gen2_irq_init((uncore), imr_val, ier_val)
176
177#endif /* __I915_IRQ_H__ */