Loading...
Note: File does not exist in v5.4.
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24#include <linux/firmware.h>
25#include <linux/circ_buf.h>
26#include "i915_drv.h"
27#include "intel_guc.h"
28
29/**
30 * DOC: GuC-based command submission
31 *
32 * i915_guc_client:
33 * We use the term client to avoid confusion with contexts. A i915_guc_client is
34 * equivalent to GuC object guc_context_desc. This context descriptor is
35 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
36 * and workqueue for it. Also the process descriptor (guc_process_desc), which
37 * is mapped to client space. So the client can write Work Item then ring the
38 * doorbell.
39 *
40 * To simplify the implementation, we allocate one gem object that contains all
41 * pages for doorbell, process descriptor and workqueue.
42 *
43 * The Scratch registers:
44 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
45 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
46 * triggers an interrupt on the GuC via another register write (0xC4C8).
47 * Firmware writes a success/fail code back to the action register after
48 * processes the request. The kernel driver polls waiting for this update and
49 * then proceeds.
50 * See host2guc_action()
51 *
52 * Doorbells:
53 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
54 * mapped into process space.
55 *
56 * Work Items:
57 * There are several types of work items that the host may place into a
58 * workqueue, each with its own requirements and limitations. Currently only
59 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
60 * represents in-order queue. The kernel driver packs ring tail pointer and an
61 * ELSP context descriptor dword into Work Item.
62 * See guc_add_workqueue_item()
63 *
64 */
65
66/*
67 * Read GuC command/status register (SOFT_SCRATCH_0)
68 * Return true if it contains a response rather than a command
69 */
70static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
71 u32 *status)
72{
73 u32 val = I915_READ(SOFT_SCRATCH(0));
74 *status = val;
75 return GUC2HOST_IS_RESPONSE(val);
76}
77
78static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
79{
80 struct drm_i915_private *dev_priv = guc_to_i915(guc);
81 u32 status;
82 int i;
83 int ret;
84
85 if (WARN_ON(len < 1 || len > 15))
86 return -EINVAL;
87
88 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
89
90 dev_priv->guc.action_count += 1;
91 dev_priv->guc.action_cmd = data[0];
92
93 for (i = 0; i < len; i++)
94 I915_WRITE(SOFT_SCRATCH(i), data[i]);
95
96 POSTING_READ(SOFT_SCRATCH(i - 1));
97
98 I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
99
100 /* No HOST2GUC command should take longer than 10ms */
101 ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10);
102 if (status != GUC2HOST_STATUS_SUCCESS) {
103 /*
104 * Either the GuC explicitly returned an error (which
105 * we convert to -EIO here) or no response at all was
106 * received within the timeout limit (-ETIMEDOUT)
107 */
108 if (ret != -ETIMEDOUT)
109 ret = -EIO;
110
111 DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
112 "status=0x%08X response=0x%08X\n",
113 data[0], ret, status,
114 I915_READ(SOFT_SCRATCH(15)));
115
116 dev_priv->guc.action_fail += 1;
117 dev_priv->guc.action_err = ret;
118 }
119 dev_priv->guc.action_status = status;
120
121 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
122
123 return ret;
124}
125
126/*
127 * Tell the GuC to allocate or deallocate a specific doorbell
128 */
129
130static int host2guc_allocate_doorbell(struct intel_guc *guc,
131 struct i915_guc_client *client)
132{
133 u32 data[2];
134
135 data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
136 data[1] = client->ctx_index;
137
138 return host2guc_action(guc, data, 2);
139}
140
141static int host2guc_release_doorbell(struct intel_guc *guc,
142 struct i915_guc_client *client)
143{
144 u32 data[2];
145
146 data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
147 data[1] = client->ctx_index;
148
149 return host2guc_action(guc, data, 2);
150}
151
152static int host2guc_sample_forcewake(struct intel_guc *guc,
153 struct i915_guc_client *client)
154{
155 struct drm_i915_private *dev_priv = guc_to_i915(guc);
156 struct drm_device *dev = dev_priv->dev;
157 u32 data[2];
158
159 data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
160 /* WaRsDisableCoarsePowerGating:skl,bxt */
161 if (!intel_enable_rc6(dev) ||
162 NEEDS_WaRsDisableCoarsePowerGating(dev))
163 data[1] = 0;
164 else
165 /* bit 0 and 1 are for Render and Media domain separately */
166 data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
167
168 return host2guc_action(guc, data, ARRAY_SIZE(data));
169}
170
171/*
172 * Initialise, update, or clear doorbell data shared with the GuC
173 *
174 * These functions modify shared data and so need access to the mapped
175 * client object which contains the page being used for the doorbell
176 */
177
178static void guc_init_doorbell(struct intel_guc *guc,
179 struct i915_guc_client *client)
180{
181 struct guc_doorbell_info *doorbell;
182 void *base;
183
184 base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
185 doorbell = base + client->doorbell_offset;
186
187 doorbell->db_status = 1;
188 doorbell->cookie = 0;
189
190 kunmap_atomic(base);
191}
192
193static int guc_ring_doorbell(struct i915_guc_client *gc)
194{
195 struct guc_process_desc *desc;
196 union guc_doorbell_qw db_cmp, db_exc, db_ret;
197 union guc_doorbell_qw *db;
198 void *base;
199 int attempt = 2, ret = -EAGAIN;
200
201 base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
202 desc = base + gc->proc_desc_offset;
203
204 /* Update the tail so it is visible to GuC */
205 desc->tail = gc->wq_tail;
206
207 /* current cookie */
208 db_cmp.db_status = GUC_DOORBELL_ENABLED;
209 db_cmp.cookie = gc->cookie;
210
211 /* cookie to be updated */
212 db_exc.db_status = GUC_DOORBELL_ENABLED;
213 db_exc.cookie = gc->cookie + 1;
214 if (db_exc.cookie == 0)
215 db_exc.cookie = 1;
216
217 /* pointer of current doorbell cacheline */
218 db = base + gc->doorbell_offset;
219
220 while (attempt--) {
221 /* lets ring the doorbell */
222 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
223 db_cmp.value_qw, db_exc.value_qw);
224
225 /* if the exchange was successfully executed */
226 if (db_ret.value_qw == db_cmp.value_qw) {
227 /* db was successfully rung */
228 gc->cookie = db_exc.cookie;
229 ret = 0;
230 break;
231 }
232
233 /* XXX: doorbell was lost and need to acquire it again */
234 if (db_ret.db_status == GUC_DOORBELL_DISABLED)
235 break;
236
237 DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n",
238 db_cmp.cookie, db_ret.cookie);
239
240 /* update the cookie to newly read cookie from GuC */
241 db_cmp.cookie = db_ret.cookie;
242 db_exc.cookie = db_ret.cookie + 1;
243 if (db_exc.cookie == 0)
244 db_exc.cookie = 1;
245 }
246
247 /* Finally, update the cached copy of the GuC's WQ head */
248 gc->wq_head = desc->head;
249
250 kunmap_atomic(base);
251 return ret;
252}
253
254static void guc_disable_doorbell(struct intel_guc *guc,
255 struct i915_guc_client *client)
256{
257 struct drm_i915_private *dev_priv = guc_to_i915(guc);
258 struct guc_doorbell_info *doorbell;
259 void *base;
260 i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id);
261 int value;
262
263 base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
264 doorbell = base + client->doorbell_offset;
265
266 doorbell->db_status = 0;
267
268 kunmap_atomic(base);
269
270 I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID);
271
272 value = I915_READ(drbreg);
273 WARN_ON((value & GEN8_DRB_VALID) != 0);
274
275 I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0);
276 I915_WRITE(drbreg, 0);
277
278 /* XXX: wait for any interrupts */
279 /* XXX: wait for workqueue to drain */
280}
281
282/*
283 * Select, assign and relase doorbell cachelines
284 *
285 * These functions track which doorbell cachelines are in use.
286 * The data they manipulate is protected by the host2guc lock.
287 */
288
289static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
290{
291 const uint32_t cacheline_size = cache_line_size();
292 uint32_t offset;
293
294 /* Doorbell uses a single cache line within a page */
295 offset = offset_in_page(guc->db_cacheline);
296
297 /* Moving to next cache line to reduce contention */
298 guc->db_cacheline += cacheline_size;
299
300 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
301 offset, guc->db_cacheline, cacheline_size);
302
303 return offset;
304}
305
306static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority)
307{
308 /*
309 * The bitmap is split into two halves; the first half is used for
310 * normal priority contexts, the second half for high-priority ones.
311 * Note that logically higher priorities are numerically less than
312 * normal ones, so the test below means "is it high-priority?"
313 */
314 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
315 const uint16_t half = GUC_MAX_DOORBELLS / 2;
316 const uint16_t start = hi_pri ? half : 0;
317 const uint16_t end = start + half;
318 uint16_t id;
319
320 id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
321 if (id == end)
322 id = GUC_INVALID_DOORBELL_ID;
323 else
324 bitmap_set(guc->doorbell_bitmap, id, 1);
325
326 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
327 hi_pri ? "high" : "normal", id);
328
329 return id;
330}
331
332static void release_doorbell(struct intel_guc *guc, uint16_t id)
333{
334 bitmap_clear(guc->doorbell_bitmap, id, 1);
335}
336
337/*
338 * Initialise the process descriptor shared with the GuC firmware.
339 */
340static void guc_init_proc_desc(struct intel_guc *guc,
341 struct i915_guc_client *client)
342{
343 struct guc_process_desc *desc;
344 void *base;
345
346 base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
347 desc = base + client->proc_desc_offset;
348
349 memset(desc, 0, sizeof(*desc));
350
351 /*
352 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
353 * space for ring3 clients (set them as in mmap_ioctl) or kernel
354 * space for kernel clients (map on demand instead? May make debug
355 * easier to have it mapped).
356 */
357 desc->wq_base_addr = 0;
358 desc->db_base_addr = 0;
359
360 desc->context_id = client->ctx_index;
361 desc->wq_size_bytes = client->wq_size;
362 desc->wq_status = WQ_STATUS_ACTIVE;
363 desc->priority = client->priority;
364
365 kunmap_atomic(base);
366}
367
368/*
369 * Initialise/clear the context descriptor shared with the GuC firmware.
370 *
371 * This descriptor tells the GuC where (in GGTT space) to find the important
372 * data structures relating to this client (doorbell, process descriptor,
373 * write queue, etc).
374 */
375
376static void guc_init_ctx_desc(struct intel_guc *guc,
377 struct i915_guc_client *client)
378{
379 struct drm_i915_private *dev_priv = guc_to_i915(guc);
380 struct intel_engine_cs *ring;
381 struct intel_context *ctx = client->owner;
382 struct guc_context_desc desc;
383 struct sg_table *sg;
384 int i;
385
386 memset(&desc, 0, sizeof(desc));
387
388 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
389 desc.context_id = client->ctx_index;
390 desc.priority = client->priority;
391 desc.db_id = client->doorbell_id;
392
393 for_each_ring(ring, dev_priv, i) {
394 struct guc_execlist_context *lrc = &desc.lrc[ring->guc_id];
395 struct drm_i915_gem_object *obj;
396 uint64_t ctx_desc;
397
398 /* TODO: We have a design issue to be solved here. Only when we
399 * receive the first batch, we know which engine is used by the
400 * user. But here GuC expects the lrc and ring to be pinned. It
401 * is not an issue for default context, which is the only one
402 * for now who owns a GuC client. But for future owner of GuC
403 * client, need to make sure lrc is pinned prior to enter here.
404 */
405 obj = ctx->engine[i].state;
406 if (!obj)
407 break; /* XXX: continue? */
408
409 ctx_desc = intel_lr_context_descriptor(ctx, ring);
410 lrc->context_desc = (u32)ctx_desc;
411
412 /* The state page is after PPHWSP */
413 lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) +
414 LRC_STATE_PN * PAGE_SIZE;
415 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
416 (ring->guc_id << GUC_ELC_ENGINE_OFFSET);
417
418 obj = ctx->engine[i].ringbuf->obj;
419
420 lrc->ring_begin = i915_gem_obj_ggtt_offset(obj);
421 lrc->ring_end = lrc->ring_begin + obj->base.size - 1;
422 lrc->ring_next_free_location = lrc->ring_begin;
423 lrc->ring_current_tail_pointer_value = 0;
424
425 desc.engines_used |= (1 << ring->guc_id);
426 }
427
428 WARN_ON(desc.engines_used == 0);
429
430 /*
431 * The CPU address is only needed at certain points, so kmap_atomic on
432 * demand instead of storing it in the ctx descriptor.
433 * XXX: May make debug easier to have it mapped
434 */
435 desc.db_trigger_cpu = 0;
436 desc.db_trigger_uk = client->doorbell_offset +
437 i915_gem_obj_ggtt_offset(client->client_obj);
438 desc.db_trigger_phy = client->doorbell_offset +
439 sg_dma_address(client->client_obj->pages->sgl);
440
441 desc.process_desc = client->proc_desc_offset +
442 i915_gem_obj_ggtt_offset(client->client_obj);
443
444 desc.wq_addr = client->wq_offset +
445 i915_gem_obj_ggtt_offset(client->client_obj);
446
447 desc.wq_size = client->wq_size;
448
449 /*
450 * XXX: Take LRCs from an existing intel_context if this is not an
451 * IsKMDCreatedContext client
452 */
453 desc.desc_private = (uintptr_t)client;
454
455 /* Pool context is pinned already */
456 sg = guc->ctx_pool_obj->pages;
457 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
458 sizeof(desc) * client->ctx_index);
459}
460
461static void guc_fini_ctx_desc(struct intel_guc *guc,
462 struct i915_guc_client *client)
463{
464 struct guc_context_desc desc;
465 struct sg_table *sg;
466
467 memset(&desc, 0, sizeof(desc));
468
469 sg = guc->ctx_pool_obj->pages;
470 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
471 sizeof(desc) * client->ctx_index);
472}
473
474int i915_guc_wq_check_space(struct i915_guc_client *gc)
475{
476 struct guc_process_desc *desc;
477 void *base;
478 u32 size = sizeof(struct guc_wq_item);
479 int ret = -ETIMEDOUT, timeout_counter = 200;
480
481 if (!gc)
482 return 0;
483
484 /* Quickly return if wq space is available since last time we cache the
485 * head position. */
486 if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size)
487 return 0;
488
489 base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
490 desc = base + gc->proc_desc_offset;
491
492 while (timeout_counter-- > 0) {
493 gc->wq_head = desc->head;
494
495 if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) {
496 ret = 0;
497 break;
498 }
499
500 if (timeout_counter)
501 usleep_range(1000, 2000);
502 };
503
504 kunmap_atomic(base);
505
506 return ret;
507}
508
509static int guc_add_workqueue_item(struct i915_guc_client *gc,
510 struct drm_i915_gem_request *rq)
511{
512 struct guc_wq_item *wqi;
513 void *base;
514 u32 tail, wq_len, wq_off, space;
515
516 space = CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size);
517 if (WARN_ON(space < sizeof(struct guc_wq_item)))
518 return -ENOSPC; /* shouldn't happen */
519
520 /* postincrement WQ tail for next time */
521 wq_off = gc->wq_tail;
522 gc->wq_tail += sizeof(struct guc_wq_item);
523 gc->wq_tail &= gc->wq_size - 1;
524
525 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
526 * should not have the case where structure wqi is across page, neither
527 * wrapped to the beginning. This simplifies the implementation below.
528 *
529 * XXX: if not the case, we need save data to a temp wqi and copy it to
530 * workqueue buffer dw by dw.
531 */
532 WARN_ON(sizeof(struct guc_wq_item) != 16);
533 WARN_ON(wq_off & 3);
534
535 /* wq starts from the page after doorbell / process_desc */
536 base = kmap_atomic(i915_gem_object_get_page(gc->client_obj,
537 (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT));
538 wq_off &= PAGE_SIZE - 1;
539 wqi = (struct guc_wq_item *)((char *)base + wq_off);
540
541 /* len does not include the header */
542 wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1;
543 wqi->header = WQ_TYPE_INORDER |
544 (wq_len << WQ_LEN_SHIFT) |
545 (rq->ring->guc_id << WQ_TARGET_SHIFT) |
546 WQ_NO_WCFLUSH_WAIT;
547
548 /* The GuC wants only the low-order word of the context descriptor */
549 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, rq->ring);
550
551 /* The GuC firmware wants the tail index in QWords, not bytes */
552 tail = rq->ringbuf->tail >> 3;
553 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
554 wqi->fence_id = 0; /*XXX: what fence to be here */
555
556 kunmap_atomic(base);
557
558 return 0;
559}
560
561/**
562 * i915_guc_submit() - Submit commands through GuC
563 * @client: the guc client where commands will go through
564 * @rq: request associated with the commands
565 *
566 * Return: 0 if succeed
567 */
568int i915_guc_submit(struct i915_guc_client *client,
569 struct drm_i915_gem_request *rq)
570{
571 struct intel_guc *guc = client->guc;
572 unsigned int engine_id = rq->ring->guc_id;
573 int q_ret, b_ret;
574
575 q_ret = guc_add_workqueue_item(client, rq);
576 if (q_ret == 0)
577 b_ret = guc_ring_doorbell(client);
578
579 client->submissions[engine_id] += 1;
580 if (q_ret) {
581 client->q_fail += 1;
582 client->retcode = q_ret;
583 } else if (b_ret) {
584 client->b_fail += 1;
585 client->retcode = q_ret = b_ret;
586 } else {
587 client->retcode = 0;
588 }
589 guc->submissions[engine_id] += 1;
590 guc->last_seqno[engine_id] = rq->seqno;
591
592 return q_ret;
593}
594
595/*
596 * Everything below here is concerned with setup & teardown, and is
597 * therefore not part of the somewhat time-critical batch-submission
598 * path of i915_guc_submit() above.
599 */
600
601/**
602 * gem_allocate_guc_obj() - Allocate gem object for GuC usage
603 * @dev: drm device
604 * @size: size of object
605 *
606 * This is a wrapper to create a gem obj. In order to use it inside GuC, the
607 * object needs to be pinned lifetime. Also we must pin it to gtt space other
608 * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC.
609 *
610 * Return: A drm_i915_gem_object if successful, otherwise NULL.
611 */
612static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
613 u32 size)
614{
615 struct drm_i915_private *dev_priv = dev->dev_private;
616 struct drm_i915_gem_object *obj;
617
618 obj = i915_gem_alloc_object(dev, size);
619 if (!obj)
620 return NULL;
621
622 if (i915_gem_object_get_pages(obj)) {
623 drm_gem_object_unreference(&obj->base);
624 return NULL;
625 }
626
627 if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
628 PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) {
629 drm_gem_object_unreference(&obj->base);
630 return NULL;
631 }
632
633 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
634 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
635
636 return obj;
637}
638
639/**
640 * gem_release_guc_obj() - Release gem object allocated for GuC usage
641 * @obj: gem obj to be released
642 */
643static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
644{
645 if (!obj)
646 return;
647
648 if (i915_gem_obj_is_pinned(obj))
649 i915_gem_object_ggtt_unpin(obj);
650
651 drm_gem_object_unreference(&obj->base);
652}
653
654static void guc_client_free(struct drm_device *dev,
655 struct i915_guc_client *client)
656{
657 struct drm_i915_private *dev_priv = dev->dev_private;
658 struct intel_guc *guc = &dev_priv->guc;
659
660 if (!client)
661 return;
662
663 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) {
664 /*
665 * First disable the doorbell, then tell the GuC we've
666 * finished with it, finally deallocate it in our bitmap
667 */
668 guc_disable_doorbell(guc, client);
669 host2guc_release_doorbell(guc, client);
670 release_doorbell(guc, client->doorbell_id);
671 }
672
673 /*
674 * XXX: wait for any outstanding submissions before freeing memory.
675 * Be sure to drop any locks
676 */
677
678 gem_release_guc_obj(client->client_obj);
679
680 if (client->ctx_index != GUC_INVALID_CTX_ID) {
681 guc_fini_ctx_desc(guc, client);
682 ida_simple_remove(&guc->ctx_ids, client->ctx_index);
683 }
684
685 kfree(client);
686}
687
688/**
689 * guc_client_alloc() - Allocate an i915_guc_client
690 * @dev: drm device
691 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
692 * The kernel client to replace ExecList submission is created with
693 * NORMAL priority. Priority of a client for scheduler can be HIGH,
694 * while a preemption context can use CRITICAL.
695 * @ctx: the context that owns the client (we use the default render
696 * context)
697 *
698 * Return: An i915_guc_client object if success.
699 */
700static struct i915_guc_client *guc_client_alloc(struct drm_device *dev,
701 uint32_t priority,
702 struct intel_context *ctx)
703{
704 struct i915_guc_client *client;
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 struct intel_guc *guc = &dev_priv->guc;
707 struct drm_i915_gem_object *obj;
708
709 client = kzalloc(sizeof(*client), GFP_KERNEL);
710 if (!client)
711 return NULL;
712
713 client->doorbell_id = GUC_INVALID_DOORBELL_ID;
714 client->priority = priority;
715 client->owner = ctx;
716 client->guc = guc;
717
718 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
719 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
720 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
721 client->ctx_index = GUC_INVALID_CTX_ID;
722 goto err;
723 }
724
725 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
726 obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE);
727 if (!obj)
728 goto err;
729
730 client->client_obj = obj;
731 client->wq_offset = GUC_DB_SIZE;
732 client->wq_size = GUC_WQ_SIZE;
733
734 client->doorbell_offset = select_doorbell_cacheline(guc);
735
736 /*
737 * Since the doorbell only requires a single cacheline, we can save
738 * space by putting the application process descriptor in the same
739 * page. Use the half of the page that doesn't include the doorbell.
740 */
741 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
742 client->proc_desc_offset = 0;
743 else
744 client->proc_desc_offset = (GUC_DB_SIZE / 2);
745
746 client->doorbell_id = assign_doorbell(guc, client->priority);
747 if (client->doorbell_id == GUC_INVALID_DOORBELL_ID)
748 /* XXX: evict a doorbell instead */
749 goto err;
750
751 guc_init_proc_desc(guc, client);
752 guc_init_ctx_desc(guc, client);
753 guc_init_doorbell(guc, client);
754
755 /* XXX: Any cache flushes needed? General domain mgmt calls? */
756
757 if (host2guc_allocate_doorbell(guc, client))
758 goto err;
759
760 DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n",
761 priority, client, client->ctx_index, client->doorbell_id);
762
763 return client;
764
765err:
766 DRM_ERROR("FAILED to create priority %u GuC client!\n", priority);
767
768 guc_client_free(dev, client);
769 return NULL;
770}
771
772static void guc_create_log(struct intel_guc *guc)
773{
774 struct drm_i915_private *dev_priv = guc_to_i915(guc);
775 struct drm_i915_gem_object *obj;
776 unsigned long offset;
777 uint32_t size, flags;
778
779 if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN)
780 return;
781
782 if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
783 i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
784
785 /* The first page is to save log buffer state. Allocate one
786 * extra page for others in case for overlap */
787 size = (1 + GUC_LOG_DPC_PAGES + 1 +
788 GUC_LOG_ISR_PAGES + 1 +
789 GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
790
791 obj = guc->log_obj;
792 if (!obj) {
793 obj = gem_allocate_guc_obj(dev_priv->dev, size);
794 if (!obj) {
795 /* logging will be off */
796 i915.guc_log_level = -1;
797 return;
798 }
799
800 guc->log_obj = obj;
801 }
802
803 /* each allocated unit is a page */
804 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
805 (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
806 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
807 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
808
809 offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */
810 guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
811}
812
813static void init_guc_policies(struct guc_policies *policies)
814{
815 struct guc_policy *policy;
816 u32 p, i;
817
818 policies->dpc_promote_time = 500000;
819 policies->max_num_work_items = POLICY_MAX_NUM_WI;
820
821 for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
822 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
823 policy = &policies->policy[p][i];
824
825 policy->execution_quantum = 1000000;
826 policy->preemption_time = 500000;
827 policy->fault_time = 250000;
828 policy->policy_flags = 0;
829 }
830 }
831
832 policies->is_valid = 1;
833}
834
835static void guc_create_ads(struct intel_guc *guc)
836{
837 struct drm_i915_private *dev_priv = guc_to_i915(guc);
838 struct drm_i915_gem_object *obj;
839 struct guc_ads *ads;
840 struct guc_policies *policies;
841 struct guc_mmio_reg_state *reg_state;
842 struct intel_engine_cs *ring;
843 struct page *page;
844 u32 size, i;
845
846 /* The ads obj includes the struct itself and buffers passed to GuC */
847 size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
848 sizeof(struct guc_mmio_reg_state) +
849 GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
850
851 obj = guc->ads_obj;
852 if (!obj) {
853 obj = gem_allocate_guc_obj(dev_priv->dev, PAGE_ALIGN(size));
854 if (!obj)
855 return;
856
857 guc->ads_obj = obj;
858 }
859
860 page = i915_gem_object_get_page(obj, 0);
861 ads = kmap(page);
862
863 /*
864 * The GuC requires a "Golden Context" when it reinitialises
865 * engines after a reset. Here we use the Render ring default
866 * context, which must already exist and be pinned in the GGTT,
867 * so its address won't change after we've told the GuC where
868 * to find it.
869 */
870 ring = &dev_priv->ring[RCS];
871 ads->golden_context_lrca = ring->status_page.gfx_addr;
872
873 for_each_ring(ring, dev_priv, i)
874 ads->eng_state_size[ring->guc_id] = intel_lr_context_size(ring);
875
876 /* GuC scheduling policies */
877 policies = (void *)ads + sizeof(struct guc_ads);
878 init_guc_policies(policies);
879
880 ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) +
881 sizeof(struct guc_ads);
882
883 /* MMIO reg state */
884 reg_state = (void *)policies + sizeof(struct guc_policies);
885
886 for_each_ring(ring, dev_priv, i) {
887 reg_state->mmio_white_list[ring->guc_id].mmio_start =
888 ring->mmio_base + GUC_MMIO_WHITE_LIST_START;
889
890 /* Nothing to be saved or restored for now. */
891 reg_state->mmio_white_list[ring->guc_id].count = 0;
892 }
893
894 ads->reg_state_addr = ads->scheduler_policies +
895 sizeof(struct guc_policies);
896
897 ads->reg_state_buffer = ads->reg_state_addr +
898 sizeof(struct guc_mmio_reg_state);
899
900 kunmap(page);
901}
902
903/*
904 * Set up the memory resources to be shared with the GuC. At this point,
905 * we require just one object that can be mapped through the GGTT.
906 */
907int i915_guc_submission_init(struct drm_device *dev)
908{
909 struct drm_i915_private *dev_priv = dev->dev_private;
910 const size_t ctxsize = sizeof(struct guc_context_desc);
911 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
912 const size_t gemsize = round_up(poolsize, PAGE_SIZE);
913 struct intel_guc *guc = &dev_priv->guc;
914
915 if (!i915.enable_guc_submission)
916 return 0; /* not enabled */
917
918 if (guc->ctx_pool_obj)
919 return 0; /* already allocated */
920
921 guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize);
922 if (!guc->ctx_pool_obj)
923 return -ENOMEM;
924
925 ida_init(&guc->ctx_ids);
926
927 guc_create_log(guc);
928
929 guc_create_ads(guc);
930
931 return 0;
932}
933
934int i915_guc_submission_enable(struct drm_device *dev)
935{
936 struct drm_i915_private *dev_priv = dev->dev_private;
937 struct intel_guc *guc = &dev_priv->guc;
938 struct intel_context *ctx = dev_priv->kernel_context;
939 struct i915_guc_client *client;
940
941 /* client for execbuf submission */
942 client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx);
943 if (!client) {
944 DRM_ERROR("Failed to create execbuf guc_client\n");
945 return -ENOMEM;
946 }
947
948 guc->execbuf_client = client;
949
950 host2guc_sample_forcewake(guc, client);
951
952 return 0;
953}
954
955void i915_guc_submission_disable(struct drm_device *dev)
956{
957 struct drm_i915_private *dev_priv = dev->dev_private;
958 struct intel_guc *guc = &dev_priv->guc;
959
960 guc_client_free(dev, guc->execbuf_client);
961 guc->execbuf_client = NULL;
962}
963
964void i915_guc_submission_fini(struct drm_device *dev)
965{
966 struct drm_i915_private *dev_priv = dev->dev_private;
967 struct intel_guc *guc = &dev_priv->guc;
968
969 gem_release_guc_obj(dev_priv->guc.ads_obj);
970 guc->ads_obj = NULL;
971
972 gem_release_guc_obj(dev_priv->guc.log_obj);
973 guc->log_obj = NULL;
974
975 if (guc->ctx_pool_obj)
976 ida_destroy(&guc->ctx_ids);
977 gem_release_guc_obj(guc->ctx_pool_obj);
978 guc->ctx_pool_obj = NULL;
979}
980
981/**
982 * intel_guc_suspend() - notify GuC entering suspend state
983 * @dev: drm device
984 */
985int intel_guc_suspend(struct drm_device *dev)
986{
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 struct intel_guc *guc = &dev_priv->guc;
989 struct intel_context *ctx;
990 u32 data[3];
991
992 if (!i915.enable_guc_submission)
993 return 0;
994
995 ctx = dev_priv->kernel_context;
996
997 data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
998 /* any value greater than GUC_POWER_D0 */
999 data[1] = GUC_POWER_D1;
1000 /* first page is shared data with GuC */
1001 data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
1002
1003 return host2guc_action(guc, data, ARRAY_SIZE(data));
1004}
1005
1006
1007/**
1008 * intel_guc_resume() - notify GuC resuming from suspend state
1009 * @dev: drm device
1010 */
1011int intel_guc_resume(struct drm_device *dev)
1012{
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 struct intel_guc *guc = &dev_priv->guc;
1015 struct intel_context *ctx;
1016 u32 data[3];
1017
1018 if (!i915.enable_guc_submission)
1019 return 0;
1020
1021 ctx = dev_priv->kernel_context;
1022
1023 data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
1024 data[1] = GUC_POWER_D0;
1025 /* first page is shared data with GuC */
1026 data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
1027
1028 return host2guc_action(guc, data, ARRAY_SIZE(data));
1029}