1/*
 2 * SPDX-License-Identifier: MIT
 3 *
 4 * Copyright © 2019 Intel Corporation
 5 */
 6
 7#ifndef __INTEL_SSEU_H__
 8#define __INTEL_SSEU_H__
 9
10#include <linux/types.h>
11#include <linux/kernel.h>
12
13struct drm_i915_private;
14
15#define GEN_MAX_SLICES		(6) /* CNL upper bound */
16#define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
17#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
18
19struct sseu_dev_info {
20	u8 slice_mask;
21	u8 subslice_mask[GEN_MAX_SLICES];
22	u16 eu_total;
23	u8 eu_per_subslice;
24	u8 min_eu_in_pool;
25	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
26	u8 subslice_7eu[3];
27	u8 has_slice_pg:1;
28	u8 has_subslice_pg:1;
29	u8 has_eu_pg:1;
30
31	/* Topology fields */
32	u8 max_slices;
33	u8 max_subslices;
34	u8 max_eus_per_subslice;
35
36	/* We don't have more than 8 eus per subslice at the moment and as we
37	 * store eus enabled using bits, no need to multiply by eus per
38	 * subslice.
39	 */
40	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
41};
42
43/*
44 * Powergating configuration for a particular (context,engine).
45 */
46struct intel_sseu {
47	u8 slice_mask;
48	u8 subslice_mask;
49	u8 min_eus_per_subslice;
50	u8 max_eus_per_subslice;
51};
52
53static inline struct intel_sseu
54intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
55{
56	struct intel_sseu value = {
57		.slice_mask = sseu->slice_mask,
58		.subslice_mask = sseu->subslice_mask[0],
59		.min_eus_per_subslice = sseu->max_eus_per_subslice,
60		.max_eus_per_subslice = sseu->max_eus_per_subslice,
61	};
62
63	return value;
64}
65
66unsigned int
67intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
68
69unsigned int
70intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
71
72u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
73			 const struct intel_sseu *req_sseu);
74
75#endif /* __INTEL_SSEU_H__ */