1/*
  2 * Copyright © 2014 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 * Authors:
 24 *    Mika Kuoppala <mika.kuoppala@intel.com>
 25 *
 26 */
 27
 28#include "i915_drv.h"
 29#include "intel_renderstate.h"
 30
 31struct intel_renderstate {
 32	const struct intel_renderstate_rodata *rodata;
 33	struct drm_i915_gem_object *obj;
 34	struct i915_vma *vma;
 35	u32 batch_offset;
 36	u32 batch_size;
 37	u32 aux_offset;
 38	u32 aux_size;
 39};
 40
 41static const struct intel_renderstate_rodata *
 42render_state_get_rodata(const struct intel_engine_cs *engine)
 43{
 44	if (engine->class != RENDER_CLASS)
 45		return NULL;
 46
 47	switch (INTEL_GEN(engine->i915)) {
 48	case 6:
 49		return &gen6_null_state;
 50	case 7:
 51		return &gen7_null_state;
 52	case 8:
 53		return &gen8_null_state;
 54	case 9:
 55		return &gen9_null_state;
 56	}
 57
 58	return NULL;
 59}
 60
 61/*
 62 * Macro to add commands to auxiliary batch.
 63 * This macro only checks for page overflow before inserting the commands,
 64 * this is sufficient as the null state generator makes the final batch
 65 * with two passes to build command and state separately. At this point
 66 * the size of both are known and it compacts them by relocating the state
 67 * right after the commands taking care of alignment so we should sufficient
 68 * space below them for adding new commands.
 69 */
 70#define OUT_BATCH(batch, i, val)				\
 71	do {							\
 72		if ((i) >= PAGE_SIZE / sizeof(u32))		\
 73			goto err;				\
 74		(batch)[(i)++] = (val);				\
 75	} while(0)
 76
 77static int render_state_setup(struct intel_renderstate *so,
 78			      struct drm_i915_private *i915)
 79{
 80	const struct intel_renderstate_rodata *rodata = so->rodata;
 81	unsigned int i = 0, reloc_index = 0;
 82	unsigned int needs_clflush;
 83	u32 *d;
 84	int ret;
 85
 86	ret = i915_gem_object_prepare_write(so->obj, &needs_clflush);
 87	if (ret)
 88		return ret;
 89
 90	d = kmap_atomic(i915_gem_object_get_dirty_page(so->obj, 0));
 91
 92	while (i < rodata->batch_items) {
 93		u32 s = rodata->batch[i];
 94
 95		if (i * 4  == rodata->reloc[reloc_index]) {
 96			u64 r = s + so->vma->node.start;
 97			s = lower_32_bits(r);
 98			if (HAS_64BIT_RELOC(i915)) {
 99				if (i + 1 >= rodata->batch_items ||
100				    rodata->batch[i + 1] != 0)
101					goto err;
102
103				d[i++] = s;
104				s = upper_32_bits(r);
105			}
106
107			reloc_index++;
108		}
109
110		d[i++] = s;
111	}
112
113	if (rodata->reloc[reloc_index] != -1) {
114		DRM_ERROR("only %d relocs resolved\n", reloc_index);
115		goto err;
116	}
117
118	so->batch_offset = i915_ggtt_offset(so->vma);
119	so->batch_size = rodata->batch_items * sizeof(u32);
120
121	while (i % CACHELINE_DWORDS)
122		OUT_BATCH(d, i, MI_NOOP);
123
124	so->aux_offset = i * sizeof(u32);
125
126	if (HAS_POOLED_EU(i915)) {
127		/*
128		 * We always program 3x6 pool config but depending upon which
129		 * subslice is disabled HW drops down to appropriate config
130		 * shown below.
131		 *
132		 * In the below table 2x6 config always refers to
133		 * fused-down version, native 2x6 is not available and can
134		 * be ignored
135		 *
136		 * SNo  subslices config                eu pool configuration
137		 * -----------------------------------------------------------
138		 * 1    3 subslices enabled (3x6)  -    0x00777000  (9+9)
139		 * 2    ss0 disabled (2x6)         -    0x00777000  (3+9)
140		 * 3    ss1 disabled (2x6)         -    0x00770000  (6+6)
141		 * 4    ss2 disabled (2x6)         -    0x00007000  (9+3)
142		 */
143		u32 eu_pool_config = 0x00777000;
144
145		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
146		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
147		OUT_BATCH(d, i, eu_pool_config);
148		OUT_BATCH(d, i, 0);
149		OUT_BATCH(d, i, 0);
150		OUT_BATCH(d, i, 0);
151	}
152
153	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
154	so->aux_size = i * sizeof(u32) - so->aux_offset;
155	so->aux_offset += so->batch_offset;
156	/*
157	 * Since we are sending length, we need to strictly conform to
158	 * all requirements. For Gen2 this must be a multiple of 8.
159	 */
160	so->aux_size = ALIGN(so->aux_size, 8);
161
162	if (needs_clflush)
163		drm_clflush_virt_range(d, i * sizeof(u32));
164	kunmap_atomic(d);
165
166	ret = 0;
167out:
168	i915_gem_object_finish_access(so->obj);
169	return ret;
170
171err:
172	kunmap_atomic(d);
173	ret = -EINVAL;
174	goto out;
175}
176
177#undef OUT_BATCH
178
179int intel_renderstate_emit(struct i915_request *rq)
180{
181	struct intel_engine_cs *engine = rq->engine;
182	struct intel_renderstate so = {}; /* keep the compiler happy */
183	int err;
184
185	so.rodata = render_state_get_rodata(engine);
186	if (!so.rodata)
187		return 0;
188
189	if (so.rodata->batch_items * 4 > PAGE_SIZE)
190		return -EINVAL;
191
192	so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
193	if (IS_ERR(so.obj))
194		return PTR_ERR(so.obj);
195
196	so.vma = i915_vma_instance(so.obj, &engine->gt->ggtt->vm, NULL);
197	if (IS_ERR(so.vma)) {
198		err = PTR_ERR(so.vma);
199		goto err_obj;
200	}
201
202	err = i915_vma_pin(so.vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
203	if (err)
204		goto err_vma;
205
206	err = render_state_setup(&so, rq->i915);
207	if (err)
208		goto err_unpin;
209
210	err = engine->emit_bb_start(rq,
211				    so.batch_offset, so.batch_size,
212				    I915_DISPATCH_SECURE);
213	if (err)
214		goto err_unpin;
215
216	if (so.aux_size > 8) {
217		err = engine->emit_bb_start(rq,
218					    so.aux_offset, so.aux_size,
219					    I915_DISPATCH_SECURE);
220		if (err)
221			goto err_unpin;
222	}
223
224	i915_vma_lock(so.vma);
225	err = i915_request_await_object(rq, so.vma->obj, false);
226	if (err == 0)
227		err = i915_vma_move_to_active(so.vma, rq, 0);
228	i915_vma_unlock(so.vma);
229err_unpin:
230	i915_vma_unpin(so.vma);
231err_vma:
232	i915_vma_close(so.vma);
233err_obj:
234	i915_gem_object_put(so.obj);
235	return err;
236}