1/*
   2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3 * Copyright © 2006-2009 Intel Corporation
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice (including the next
  13 * paragraph) shall be included in all copies or substantial portions of the
  14 * Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22 * DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors:
  25 *	Eric Anholt <eric@anholt.net>
  26 *	Jesse Barnes <jesse.barnes@intel.com>
  27 */
  28
  29#include <linux/delay.h>
  30#include <linux/hdmi.h>
  31#include <linux/i2c.h>
  32#include <linux/slab.h>
  33
  34#include <drm/drm_atomic_helper.h>
  35#include <drm/drm_crtc.h>
  36#include <drm/drm_edid.h>
  37#include <drm/drm_hdcp.h>
  38#include <drm/drm_scdc_helper.h>
  39#include <drm/i915_drm.h>
  40#include <drm/intel_lpe_audio.h>
  41
  42#include "i915_debugfs.h"
  43#include "i915_drv.h"
  44#include "intel_atomic.h"
  45#include "intel_audio.h"
  46#include "intel_connector.h"
  47#include "intel_ddi.h"
  48#include "intel_display_types.h"
  49#include "intel_dp.h"
  50#include "intel_dpio_phy.h"
  51#include "intel_fifo_underrun.h"
  52#include "intel_gmbus.h"
  53#include "intel_hdcp.h"
  54#include "intel_hdmi.h"
  55#include "intel_hotplug.h"
  56#include "intel_lspcon.h"
  57#include "intel_panel.h"
  58#include "intel_sdvo.h"
  59#include "intel_sideband.h"
  60
  61static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  62{
  63	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  64}
  65
  66static void
  67assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  68{
  69	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  70	struct drm_i915_private *dev_priv = to_i915(dev);
  71	u32 enabled_bits;
  72
  73	enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  74
  75	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  76	     "HDMI port enabled, expecting disabled\n");
  77}
  78
  79static void
  80assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  81				     enum transcoder cpu_transcoder)
  82{
  83	WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  84	     TRANS_DDI_FUNC_ENABLE,
  85	     "HDMI transcoder function enabled, expecting disabled\n");
  86}
  87
  88struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  89{
  90	struct intel_digital_port *intel_dig_port =
  91		container_of(encoder, struct intel_digital_port, base.base);
  92	return &intel_dig_port->hdmi;
  93}
  94
  95static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  96{
  97	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  98}
  99
 100static u32 g4x_infoframe_index(unsigned int type)
 101{
 102	switch (type) {
 103	case HDMI_PACKET_TYPE_GAMUT_METADATA:
 104		return VIDEO_DIP_SELECT_GAMUT;
 105	case HDMI_INFOFRAME_TYPE_AVI:
 106		return VIDEO_DIP_SELECT_AVI;
 107	case HDMI_INFOFRAME_TYPE_SPD:
 108		return VIDEO_DIP_SELECT_SPD;
 109	case HDMI_INFOFRAME_TYPE_VENDOR:
 110		return VIDEO_DIP_SELECT_VENDOR;
 111	default:
 112		MISSING_CASE(type);
 113		return 0;
 114	}
 115}
 116
 117static u32 g4x_infoframe_enable(unsigned int type)
 118{
 119	switch (type) {
 120	case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 121		return VIDEO_DIP_ENABLE_GCP;
 122	case HDMI_PACKET_TYPE_GAMUT_METADATA:
 123		return VIDEO_DIP_ENABLE_GAMUT;
 124	case DP_SDP_VSC:
 125		return 0;
 126	case HDMI_INFOFRAME_TYPE_AVI:
 127		return VIDEO_DIP_ENABLE_AVI;
 128	case HDMI_INFOFRAME_TYPE_SPD:
 129		return VIDEO_DIP_ENABLE_SPD;
 130	case HDMI_INFOFRAME_TYPE_VENDOR:
 131		return VIDEO_DIP_ENABLE_VENDOR;
 132	case HDMI_INFOFRAME_TYPE_DRM:
 133		return 0;
 134	default:
 135		MISSING_CASE(type);
 136		return 0;
 137	}
 138}
 139
 140static u32 hsw_infoframe_enable(unsigned int type)
 141{
 142	switch (type) {
 143	case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 144		return VIDEO_DIP_ENABLE_GCP_HSW;
 145	case HDMI_PACKET_TYPE_GAMUT_METADATA:
 146		return VIDEO_DIP_ENABLE_GMP_HSW;
 147	case DP_SDP_VSC:
 148		return VIDEO_DIP_ENABLE_VSC_HSW;
 149	case DP_SDP_PPS:
 150		return VDIP_ENABLE_PPS;
 151	case HDMI_INFOFRAME_TYPE_AVI:
 152		return VIDEO_DIP_ENABLE_AVI_HSW;
 153	case HDMI_INFOFRAME_TYPE_SPD:
 154		return VIDEO_DIP_ENABLE_SPD_HSW;
 155	case HDMI_INFOFRAME_TYPE_VENDOR:
 156		return VIDEO_DIP_ENABLE_VS_HSW;
 157	case HDMI_INFOFRAME_TYPE_DRM:
 158		return VIDEO_DIP_ENABLE_DRM_GLK;
 159	default:
 160		MISSING_CASE(type);
 161		return 0;
 162	}
 163}
 164
 165static i915_reg_t
 166hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 167		 enum transcoder cpu_transcoder,
 168		 unsigned int type,
 169		 int i)
 170{
 171	switch (type) {
 172	case HDMI_PACKET_TYPE_GAMUT_METADATA:
 173		return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 174	case DP_SDP_VSC:
 175		return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 176	case DP_SDP_PPS:
 177		return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 178	case HDMI_INFOFRAME_TYPE_AVI:
 179		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 180	case HDMI_INFOFRAME_TYPE_SPD:
 181		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 182	case HDMI_INFOFRAME_TYPE_VENDOR:
 183		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 184	case HDMI_INFOFRAME_TYPE_DRM:
 185		return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 186	default:
 187		MISSING_CASE(type);
 188		return INVALID_MMIO_REG;
 189	}
 190}
 191
 192static int hsw_dip_data_size(unsigned int type)
 193{
 194	switch (type) {
 195	case DP_SDP_VSC:
 196		return VIDEO_DIP_VSC_DATA_SIZE;
 197	case DP_SDP_PPS:
 198		return VIDEO_DIP_PPS_DATA_SIZE;
 199	default:
 200		return VIDEO_DIP_DATA_SIZE;
 201	}
 202}
 203
 204static void g4x_write_infoframe(struct intel_encoder *encoder,
 205				const struct intel_crtc_state *crtc_state,
 206				unsigned int type,
 207				const void *frame, ssize_t len)
 208{
 209	const u32 *data = frame;
 210	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 211	u32 val = I915_READ(VIDEO_DIP_CTL);
 212	int i;
 213
 214	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 215
 216	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 217	val |= g4x_infoframe_index(type);
 218
 219	val &= ~g4x_infoframe_enable(type);
 220
 221	I915_WRITE(VIDEO_DIP_CTL, val);
 222
 223	for (i = 0; i < len; i += 4) {
 224		I915_WRITE(VIDEO_DIP_DATA, *data);
 225		data++;
 226	}
 227	/* Write every possible data byte to force correct ECC calculation. */
 228	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 229		I915_WRITE(VIDEO_DIP_DATA, 0);
 230
 231	val |= g4x_infoframe_enable(type);
 232	val &= ~VIDEO_DIP_FREQ_MASK;
 233	val |= VIDEO_DIP_FREQ_VSYNC;
 234
 235	I915_WRITE(VIDEO_DIP_CTL, val);
 236	POSTING_READ(VIDEO_DIP_CTL);
 237}
 238
 239static void g4x_read_infoframe(struct intel_encoder *encoder,
 240			       const struct intel_crtc_state *crtc_state,
 241			       unsigned int type,
 242			       void *frame, ssize_t len)
 243{
 244	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 245	u32 val, *data = frame;
 246	int i;
 247
 248	val = I915_READ(VIDEO_DIP_CTL);
 249
 250	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 251	val |= g4x_infoframe_index(type);
 252
 253	I915_WRITE(VIDEO_DIP_CTL, val);
 254
 255	for (i = 0; i < len; i += 4)
 256		*data++ = I915_READ(VIDEO_DIP_DATA);
 257}
 258
 259static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 260				  const struct intel_crtc_state *pipe_config)
 261{
 262	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263	u32 val = I915_READ(VIDEO_DIP_CTL);
 264
 265	if ((val & VIDEO_DIP_ENABLE) == 0)
 266		return 0;
 267
 268	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 269		return 0;
 270
 271	return val & (VIDEO_DIP_ENABLE_AVI |
 272		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 273}
 274
 275static void ibx_write_infoframe(struct intel_encoder *encoder,
 276				const struct intel_crtc_state *crtc_state,
 277				unsigned int type,
 278				const void *frame, ssize_t len)
 279{
 280	const u32 *data = frame;
 281	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 282	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 283	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 284	u32 val = I915_READ(reg);
 285	int i;
 286
 287	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 288
 289	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 290	val |= g4x_infoframe_index(type);
 291
 292	val &= ~g4x_infoframe_enable(type);
 293
 294	I915_WRITE(reg, val);
 295
 296	for (i = 0; i < len; i += 4) {
 297		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 298		data++;
 299	}
 300	/* Write every possible data byte to force correct ECC calculation. */
 301	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 302		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 303
 304	val |= g4x_infoframe_enable(type);
 305	val &= ~VIDEO_DIP_FREQ_MASK;
 306	val |= VIDEO_DIP_FREQ_VSYNC;
 307
 308	I915_WRITE(reg, val);
 309	POSTING_READ(reg);
 310}
 311
 312static void ibx_read_infoframe(struct intel_encoder *encoder,
 313			       const struct intel_crtc_state *crtc_state,
 314			       unsigned int type,
 315			       void *frame, ssize_t len)
 316{
 317	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 318	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 319	u32 val, *data = frame;
 320	int i;
 321
 322	val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 323
 324	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 325	val |= g4x_infoframe_index(type);
 326
 327	I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 328
 329	for (i = 0; i < len; i += 4)
 330		*data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 331}
 332
 333static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 334				  const struct intel_crtc_state *pipe_config)
 335{
 336	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 337	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 338	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 339	u32 val = I915_READ(reg);
 340
 341	if ((val & VIDEO_DIP_ENABLE) == 0)
 342		return 0;
 343
 344	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 345		return 0;
 346
 347	return val & (VIDEO_DIP_ENABLE_AVI |
 348		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 349		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 350}
 351
 352static void cpt_write_infoframe(struct intel_encoder *encoder,
 353				const struct intel_crtc_state *crtc_state,
 354				unsigned int type,
 355				const void *frame, ssize_t len)
 356{
 357	const u32 *data = frame;
 358	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 359	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 360	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 361	u32 val = I915_READ(reg);
 362	int i;
 363
 364	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 365
 366	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 367	val |= g4x_infoframe_index(type);
 368
 369	/* The DIP control register spec says that we need to update the AVI
 370	 * infoframe without clearing its enable bit */
 371	if (type != HDMI_INFOFRAME_TYPE_AVI)
 372		val &= ~g4x_infoframe_enable(type);
 373
 374	I915_WRITE(reg, val);
 375
 376	for (i = 0; i < len; i += 4) {
 377		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 378		data++;
 379	}
 380	/* Write every possible data byte to force correct ECC calculation. */
 381	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 382		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 383
 384	val |= g4x_infoframe_enable(type);
 385	val &= ~VIDEO_DIP_FREQ_MASK;
 386	val |= VIDEO_DIP_FREQ_VSYNC;
 387
 388	I915_WRITE(reg, val);
 389	POSTING_READ(reg);
 390}
 391
 392static void cpt_read_infoframe(struct intel_encoder *encoder,
 393			       const struct intel_crtc_state *crtc_state,
 394			       unsigned int type,
 395			       void *frame, ssize_t len)
 396{
 397	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 398	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 399	u32 val, *data = frame;
 400	int i;
 401
 402	val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 403
 404	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 405	val |= g4x_infoframe_index(type);
 406
 407	I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 408
 409	for (i = 0; i < len; i += 4)
 410		*data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 411}
 412
 413static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 414				  const struct intel_crtc_state *pipe_config)
 415{
 416	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 417	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 418	u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 419
 420	if ((val & VIDEO_DIP_ENABLE) == 0)
 421		return 0;
 422
 423	return val & (VIDEO_DIP_ENABLE_AVI |
 424		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 425		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 426}
 427
 428static void vlv_write_infoframe(struct intel_encoder *encoder,
 429				const struct intel_crtc_state *crtc_state,
 430				unsigned int type,
 431				const void *frame, ssize_t len)
 432{
 433	const u32 *data = frame;
 434	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 435	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 436	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 437	u32 val = I915_READ(reg);
 438	int i;
 439
 440	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 441
 442	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 443	val |= g4x_infoframe_index(type);
 444
 445	val &= ~g4x_infoframe_enable(type);
 446
 447	I915_WRITE(reg, val);
 448
 449	for (i = 0; i < len; i += 4) {
 450		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 451		data++;
 452	}
 453	/* Write every possible data byte to force correct ECC calculation. */
 454	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 455		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 456
 457	val |= g4x_infoframe_enable(type);
 458	val &= ~VIDEO_DIP_FREQ_MASK;
 459	val |= VIDEO_DIP_FREQ_VSYNC;
 460
 461	I915_WRITE(reg, val);
 462	POSTING_READ(reg);
 463}
 464
 465static void vlv_read_infoframe(struct intel_encoder *encoder,
 466			       const struct intel_crtc_state *crtc_state,
 467			       unsigned int type,
 468			       void *frame, ssize_t len)
 469{
 470	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 471	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 472	u32 val, *data = frame;
 473	int i;
 474
 475	val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
 476
 477	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 478	val |= g4x_infoframe_index(type);
 479
 480	I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 481
 482	for (i = 0; i < len; i += 4)
 483		*data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
 484}
 485
 486static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 487				  const struct intel_crtc_state *pipe_config)
 488{
 489	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 490	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 491	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 492
 493	if ((val & VIDEO_DIP_ENABLE) == 0)
 494		return 0;
 495
 496	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 497		return 0;
 498
 499	return val & (VIDEO_DIP_ENABLE_AVI |
 500		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 501		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 502}
 503
 504static void hsw_write_infoframe(struct intel_encoder *encoder,
 505				const struct intel_crtc_state *crtc_state,
 506				unsigned int type,
 507				const void *frame, ssize_t len)
 508{
 509	const u32 *data = frame;
 510	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 511	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 512	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 513	int data_size;
 514	int i;
 515	u32 val = I915_READ(ctl_reg);
 516
 517	data_size = hsw_dip_data_size(type);
 518
 519	val &= ~hsw_infoframe_enable(type);
 520	I915_WRITE(ctl_reg, val);
 521
 522	for (i = 0; i < len; i += 4) {
 523		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 524					    type, i >> 2), *data);
 525		data++;
 526	}
 527	/* Write every possible data byte to force correct ECC calculation. */
 528	for (; i < data_size; i += 4)
 529		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 530					    type, i >> 2), 0);
 531
 532	val |= hsw_infoframe_enable(type);
 533	I915_WRITE(ctl_reg, val);
 534	POSTING_READ(ctl_reg);
 535}
 536
 537static void hsw_read_infoframe(struct intel_encoder *encoder,
 538			       const struct intel_crtc_state *crtc_state,
 539			       unsigned int type,
 540			       void *frame, ssize_t len)
 541{
 542	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 543	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 544	u32 val, *data = frame;
 545	int i;
 546
 547	val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
 548
 549	for (i = 0; i < len; i += 4)
 550		*data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 551						     type, i >> 2));
 552}
 553
 554static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 555				  const struct intel_crtc_state *pipe_config)
 556{
 557	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 558	u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 559	u32 mask;
 560
 561	mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 562		VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 563		VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 564
 565	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 566		mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 567
 568	return val & mask;
 569}
 570
 571static const u8 infoframe_type_to_idx[] = {
 572	HDMI_PACKET_TYPE_GENERAL_CONTROL,
 573	HDMI_PACKET_TYPE_GAMUT_METADATA,
 574	DP_SDP_VSC,
 575	HDMI_INFOFRAME_TYPE_AVI,
 576	HDMI_INFOFRAME_TYPE_SPD,
 577	HDMI_INFOFRAME_TYPE_VENDOR,
 578	HDMI_INFOFRAME_TYPE_DRM,
 579};
 580
 581u32 intel_hdmi_infoframe_enable(unsigned int type)
 582{
 583	int i;
 584
 585	for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 586		if (infoframe_type_to_idx[i] == type)
 587			return BIT(i);
 588	}
 589
 590	return 0;
 591}
 592
 593u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 594				  const struct intel_crtc_state *crtc_state)
 595{
 596	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 597	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 598	u32 val, ret = 0;
 599	int i;
 600
 601	val = dig_port->infoframes_enabled(encoder, crtc_state);
 602
 603	/* map from hardware bits to dip idx */
 604	for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 605		unsigned int type = infoframe_type_to_idx[i];
 606
 607		if (HAS_DDI(dev_priv)) {
 608			if (val & hsw_infoframe_enable(type))
 609				ret |= BIT(i);
 610		} else {
 611			if (val & g4x_infoframe_enable(type))
 612				ret |= BIT(i);
 613		}
 614	}
 615
 616	return ret;
 617}
 618
 619/*
 620 * The data we write to the DIP data buffer registers is 1 byte bigger than the
 621 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 622 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 623 * used for both technologies.
 624 *
 625 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 626 * DW1:       DB3       | DB2 | DB1 | DB0
 627 * DW2:       DB7       | DB6 | DB5 | DB4
 628 * DW3: ...
 629 *
 630 * (HB is Header Byte, DB is Data Byte)
 631 *
 632 * The hdmi pack() functions don't know about that hardware specific hole so we
 633 * trick them by giving an offset into the buffer and moving back the header
 634 * bytes by one.
 635 */
 636static void intel_write_infoframe(struct intel_encoder *encoder,
 637				  const struct intel_crtc_state *crtc_state,
 638				  enum hdmi_infoframe_type type,
 639				  const union hdmi_infoframe *frame)
 640{
 641	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 642	u8 buffer[VIDEO_DIP_DATA_SIZE];
 643	ssize_t len;
 644
 645	if ((crtc_state->infoframes.enable &
 646	     intel_hdmi_infoframe_enable(type)) == 0)
 647		return;
 648
 649	if (WARN_ON(frame->any.type != type))
 650		return;
 651
 652	/* see comment above for the reason for this offset */
 653	len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 654	if (WARN_ON(len < 0))
 655		return;
 656
 657	/* Insert the 'hole' (see big comment above) at position 3 */
 658	memmove(&buffer[0], &buffer[1], 3);
 659	buffer[3] = 0;
 660	len++;
 661
 662	intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 663}
 664
 665void intel_read_infoframe(struct intel_encoder *encoder,
 666			  const struct intel_crtc_state *crtc_state,
 667			  enum hdmi_infoframe_type type,
 668			  union hdmi_infoframe *frame)
 669{
 670	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 671	u8 buffer[VIDEO_DIP_DATA_SIZE];
 672	int ret;
 673
 674	if ((crtc_state->infoframes.enable &
 675	     intel_hdmi_infoframe_enable(type)) == 0)
 676		return;
 677
 678	intel_dig_port->read_infoframe(encoder, crtc_state,
 679				       type, buffer, sizeof(buffer));
 680
 681	/* Fill the 'hole' (see big comment above) at position 3 */
 682	memmove(&buffer[1], &buffer[0], 3);
 683
 684	/* see comment above for the reason for this offset */
 685	ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 686	if (ret) {
 687		DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
 688		return;
 689	}
 690
 691	if (frame->any.type != type)
 692		DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 693			      frame->any.type, type);
 694}
 695
 696static bool
 697intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 698				 struct intel_crtc_state *crtc_state,
 699				 struct drm_connector_state *conn_state)
 700{
 701	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 702	const struct drm_display_mode *adjusted_mode =
 703		&crtc_state->base.adjusted_mode;
 704	struct drm_connector *connector = conn_state->connector;
 705	int ret;
 706
 707	if (!crtc_state->has_infoframe)
 708		return true;
 709
 710	crtc_state->infoframes.enable |=
 711		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 712
 713	ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 714						       adjusted_mode);
 715	if (ret)
 716		return false;
 717
 718	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 719		frame->colorspace = HDMI_COLORSPACE_YUV420;
 720	else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 721		frame->colorspace = HDMI_COLORSPACE_YUV444;
 722	else
 723		frame->colorspace = HDMI_COLORSPACE_RGB;
 724
 725	drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
 726
 727	drm_hdmi_avi_infoframe_quant_range(frame, connector,
 728					   adjusted_mode,
 729					   crtc_state->limited_color_range ?
 730					   HDMI_QUANTIZATION_RANGE_LIMITED :
 731					   HDMI_QUANTIZATION_RANGE_FULL);
 732
 733	drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 734
 735	/* TODO: handle pixel repetition for YCBCR420 outputs */
 736
 737	ret = hdmi_avi_infoframe_check(frame);
 738	if (WARN_ON(ret))
 739		return false;
 740
 741	return true;
 742}
 743
 744static bool
 745intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 746				 struct intel_crtc_state *crtc_state,
 747				 struct drm_connector_state *conn_state)
 748{
 749	struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 750	int ret;
 751
 752	if (!crtc_state->has_infoframe)
 753		return true;
 754
 755	crtc_state->infoframes.enable |=
 756		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 757
 758	ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 759	if (WARN_ON(ret))
 760		return false;
 761
 762	frame->sdi = HDMI_SPD_SDI_PC;
 763
 764	ret = hdmi_spd_infoframe_check(frame);
 765	if (WARN_ON(ret))
 766		return false;
 767
 768	return true;
 769}
 770
 771static bool
 772intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 773				  struct intel_crtc_state *crtc_state,
 774				  struct drm_connector_state *conn_state)
 775{
 776	struct hdmi_vendor_infoframe *frame =
 777		&crtc_state->infoframes.hdmi.vendor.hdmi;
 778	const struct drm_display_info *info =
 779		&conn_state->connector->display_info;
 780	int ret;
 781
 782	if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 783		return true;
 784
 785	crtc_state->infoframes.enable |=
 786		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 787
 788	ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 789							  conn_state->connector,
 790							  &crtc_state->base.adjusted_mode);
 791	if (WARN_ON(ret))
 792		return false;
 793
 794	ret = hdmi_vendor_infoframe_check(frame);
 795	if (WARN_ON(ret))
 796		return false;
 797
 798	return true;
 799}
 800
 801static bool
 802intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 803				 struct intel_crtc_state *crtc_state,
 804				 struct drm_connector_state *conn_state)
 805{
 806	struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 807	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 808	int ret;
 809
 810	if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
 811		return true;
 812
 813	if (!crtc_state->has_infoframe)
 814		return true;
 815
 816	if (!conn_state->hdr_output_metadata)
 817		return true;
 818
 819	crtc_state->infoframes.enable |=
 820		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 821
 822	ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 823	if (ret < 0) {
 824		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
 825		return false;
 826	}
 827
 828	ret = hdmi_drm_infoframe_check(frame);
 829	if (WARN_ON(ret))
 830		return false;
 831
 832	return true;
 833}
 834
 835static void g4x_set_infoframes(struct intel_encoder *encoder,
 836			       bool enable,
 837			       const struct intel_crtc_state *crtc_state,
 838			       const struct drm_connector_state *conn_state)
 839{
 840	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 841	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 842	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 843	i915_reg_t reg = VIDEO_DIP_CTL;
 844	u32 val = I915_READ(reg);
 845	u32 port = VIDEO_DIP_PORT(encoder->port);
 846
 847	assert_hdmi_port_disabled(intel_hdmi);
 848
 849	/* If the registers were not initialized yet, they might be zeroes,
 850	 * which means we're selecting the AVI DIP and we're setting its
 851	 * frequency to once. This seems to really confuse the HW and make
 852	 * things stop working (the register spec says the AVI always needs to
 853	 * be sent every VSync). So here we avoid writing to the register more
 854	 * than we need and also explicitly select the AVI DIP and explicitly
 855	 * set its frequency to every VSync. Avoiding to write it twice seems to
 856	 * be enough to solve the problem, but being defensive shouldn't hurt us
 857	 * either. */
 858	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 859
 860	if (!enable) {
 861		if (!(val & VIDEO_DIP_ENABLE))
 862			return;
 863		if (port != (val & VIDEO_DIP_PORT_MASK)) {
 864			DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 865				      (val & VIDEO_DIP_PORT_MASK) >> 29);
 866			return;
 867		}
 868		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 869			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 870		I915_WRITE(reg, val);
 871		POSTING_READ(reg);
 872		return;
 873	}
 874
 875	if (port != (val & VIDEO_DIP_PORT_MASK)) {
 876		if (val & VIDEO_DIP_ENABLE) {
 877			DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 878				      (val & VIDEO_DIP_PORT_MASK) >> 29);
 879			return;
 880		}
 881		val &= ~VIDEO_DIP_PORT_MASK;
 882		val |= port;
 883	}
 884
 885	val |= VIDEO_DIP_ENABLE;
 886	val &= ~(VIDEO_DIP_ENABLE_AVI |
 887		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 888
 889	I915_WRITE(reg, val);
 890	POSTING_READ(reg);
 891
 892	intel_write_infoframe(encoder, crtc_state,
 893			      HDMI_INFOFRAME_TYPE_AVI,
 894			      &crtc_state->infoframes.avi);
 895	intel_write_infoframe(encoder, crtc_state,
 896			      HDMI_INFOFRAME_TYPE_SPD,
 897			      &crtc_state->infoframes.spd);
 898	intel_write_infoframe(encoder, crtc_state,
 899			      HDMI_INFOFRAME_TYPE_VENDOR,
 900			      &crtc_state->infoframes.hdmi);
 901}
 902
 903/*
 904 * Determine if default_phase=1 can be indicated in the GCP infoframe.
 905 *
 906 * From HDMI specification 1.4a:
 907 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 908 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 909 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 910 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 911 *   phase of 0
 912 */
 913static bool gcp_default_phase_possible(int pipe_bpp,
 914				       const struct drm_display_mode *mode)
 915{
 916	unsigned int pixels_per_group;
 917
 918	switch (pipe_bpp) {
 919	case 30:
 920		/* 4 pixels in 5 clocks */
 921		pixels_per_group = 4;
 922		break;
 923	case 36:
 924		/* 2 pixels in 3 clocks */
 925		pixels_per_group = 2;
 926		break;
 927	case 48:
 928		/* 1 pixel in 2 clocks */
 929		pixels_per_group = 1;
 930		break;
 931	default:
 932		/* phase information not relevant for 8bpc */
 933		return false;
 934	}
 935
 936	return mode->crtc_hdisplay % pixels_per_group == 0 &&
 937		mode->crtc_htotal % pixels_per_group == 0 &&
 938		mode->crtc_hblank_start % pixels_per_group == 0 &&
 939		mode->crtc_hblank_end % pixels_per_group == 0 &&
 940		mode->crtc_hsync_start % pixels_per_group == 0 &&
 941		mode->crtc_hsync_end % pixels_per_group == 0 &&
 942		((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 943		 mode->crtc_htotal/2 % pixels_per_group == 0);
 944}
 945
 946static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 947					 const struct intel_crtc_state *crtc_state,
 948					 const struct drm_connector_state *conn_state)
 949{
 950	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 951	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 952	i915_reg_t reg;
 953
 954	if ((crtc_state->infoframes.enable &
 955	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 956		return false;
 957
 958	if (HAS_DDI(dev_priv))
 959		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 960	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 961		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 962	else if (HAS_PCH_SPLIT(dev_priv))
 963		reg = TVIDEO_DIP_GCP(crtc->pipe);
 964	else
 965		return false;
 966
 967	I915_WRITE(reg, crtc_state->infoframes.gcp);
 968
 969	return true;
 970}
 971
 972void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 973				   struct intel_crtc_state *crtc_state)
 974{
 975	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 976	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 977	i915_reg_t reg;
 978
 979	if ((crtc_state->infoframes.enable &
 980	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 981		return;
 982
 983	if (HAS_DDI(dev_priv))
 984		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 985	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 986		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 987	else if (HAS_PCH_SPLIT(dev_priv))
 988		reg = TVIDEO_DIP_GCP(crtc->pipe);
 989	else
 990		return;
 991
 992	crtc_state->infoframes.gcp = I915_READ(reg);
 993}
 994
 995static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
 996					     struct intel_crtc_state *crtc_state,
 997					     struct drm_connector_state *conn_state)
 998{
 999	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1000
1001	if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1002		return;
1003
1004	crtc_state->infoframes.enable |=
1005		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1006
1007	/* Indicate color indication for deep color mode */
1008	if (crtc_state->pipe_bpp > 24)
1009		crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1010
1011	/* Enable default_phase whenever the display mode is suitably aligned */
1012	if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1013				       &crtc_state->base.adjusted_mode))
1014		crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1015}
1016
1017static void ibx_set_infoframes(struct intel_encoder *encoder,
1018			       bool enable,
1019			       const struct intel_crtc_state *crtc_state,
1020			       const struct drm_connector_state *conn_state)
1021{
1022	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1023	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1024	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1025	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1026	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1027	u32 val = I915_READ(reg);
1028	u32 port = VIDEO_DIP_PORT(encoder->port);
1029
1030	assert_hdmi_port_disabled(intel_hdmi);
1031
1032	/* See the big comment in g4x_set_infoframes() */
1033	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1034
1035	if (!enable) {
1036		if (!(val & VIDEO_DIP_ENABLE))
1037			return;
1038		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1039			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1040			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1041		I915_WRITE(reg, val);
1042		POSTING_READ(reg);
1043		return;
1044	}
1045
1046	if (port != (val & VIDEO_DIP_PORT_MASK)) {
1047		WARN(val & VIDEO_DIP_ENABLE,
1048		     "DIP already enabled on port %c\n",
1049		     (val & VIDEO_DIP_PORT_MASK) >> 29);
1050		val &= ~VIDEO_DIP_PORT_MASK;
1051		val |= port;
1052	}
1053
1054	val |= VIDEO_DIP_ENABLE;
1055	val &= ~(VIDEO_DIP_ENABLE_AVI |
1056		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1057		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1058
1059	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1060		val |= VIDEO_DIP_ENABLE_GCP;
1061
1062	I915_WRITE(reg, val);
1063	POSTING_READ(reg);
1064
1065	intel_write_infoframe(encoder, crtc_state,
1066			      HDMI_INFOFRAME_TYPE_AVI,
1067			      &crtc_state->infoframes.avi);
1068	intel_write_infoframe(encoder, crtc_state,
1069			      HDMI_INFOFRAME_TYPE_SPD,
1070			      &crtc_state->infoframes.spd);
1071	intel_write_infoframe(encoder, crtc_state,
1072			      HDMI_INFOFRAME_TYPE_VENDOR,
1073			      &crtc_state->infoframes.hdmi);
1074}
1075
1076static void cpt_set_infoframes(struct intel_encoder *encoder,
1077			       bool enable,
1078			       const struct intel_crtc_state *crtc_state,
1079			       const struct drm_connector_state *conn_state)
1080{
1081	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1082	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1083	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1084	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1085	u32 val = I915_READ(reg);
1086
1087	assert_hdmi_port_disabled(intel_hdmi);
1088
1089	/* See the big comment in g4x_set_infoframes() */
1090	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1091
1092	if (!enable) {
1093		if (!(val & VIDEO_DIP_ENABLE))
1094			return;
1095		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1096			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1097			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1098		I915_WRITE(reg, val);
1099		POSTING_READ(reg);
1100		return;
1101	}
1102
1103	/* Set both together, unset both together: see the spec. */
1104	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1105	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1106		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1107
1108	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1109		val |= VIDEO_DIP_ENABLE_GCP;
1110
1111	I915_WRITE(reg, val);
1112	POSTING_READ(reg);
1113
1114	intel_write_infoframe(encoder, crtc_state,
1115			      HDMI_INFOFRAME_TYPE_AVI,
1116			      &crtc_state->infoframes.avi);
1117	intel_write_infoframe(encoder, crtc_state,
1118			      HDMI_INFOFRAME_TYPE_SPD,
1119			      &crtc_state->infoframes.spd);
1120	intel_write_infoframe(encoder, crtc_state,
1121			      HDMI_INFOFRAME_TYPE_VENDOR,
1122			      &crtc_state->infoframes.hdmi);
1123}
1124
1125static void vlv_set_infoframes(struct intel_encoder *encoder,
1126			       bool enable,
1127			       const struct intel_crtc_state *crtc_state,
1128			       const struct drm_connector_state *conn_state)
1129{
1130	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1131	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1132	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1133	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1134	u32 val = I915_READ(reg);
1135	u32 port = VIDEO_DIP_PORT(encoder->port);
1136
1137	assert_hdmi_port_disabled(intel_hdmi);
1138
1139	/* See the big comment in g4x_set_infoframes() */
1140	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1141
1142	if (!enable) {
1143		if (!(val & VIDEO_DIP_ENABLE))
1144			return;
1145		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1146			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1147			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1148		I915_WRITE(reg, val);
1149		POSTING_READ(reg);
1150		return;
1151	}
1152
1153	if (port != (val & VIDEO_DIP_PORT_MASK)) {
1154		WARN(val & VIDEO_DIP_ENABLE,
1155		     "DIP already enabled on port %c\n",
1156		     (val & VIDEO_DIP_PORT_MASK) >> 29);
1157		val &= ~VIDEO_DIP_PORT_MASK;
1158		val |= port;
1159	}
1160
1161	val |= VIDEO_DIP_ENABLE;
1162	val &= ~(VIDEO_DIP_ENABLE_AVI |
1163		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1164		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1165
1166	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1167		val |= VIDEO_DIP_ENABLE_GCP;
1168
1169	I915_WRITE(reg, val);
1170	POSTING_READ(reg);
1171
1172	intel_write_infoframe(encoder, crtc_state,
1173			      HDMI_INFOFRAME_TYPE_AVI,
1174			      &crtc_state->infoframes.avi);
1175	intel_write_infoframe(encoder, crtc_state,
1176			      HDMI_INFOFRAME_TYPE_SPD,
1177			      &crtc_state->infoframes.spd);
1178	intel_write_infoframe(encoder, crtc_state,
1179			      HDMI_INFOFRAME_TYPE_VENDOR,
1180			      &crtc_state->infoframes.hdmi);
1181}
1182
1183static void hsw_set_infoframes(struct intel_encoder *encoder,
1184			       bool enable,
1185			       const struct intel_crtc_state *crtc_state,
1186			       const struct drm_connector_state *conn_state)
1187{
1188	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1189	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1190	u32 val = I915_READ(reg);
1191
1192	assert_hdmi_transcoder_func_disabled(dev_priv,
1193					     crtc_state->cpu_transcoder);
1194
1195	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1196		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1197		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1198		 VIDEO_DIP_ENABLE_DRM_GLK);
1199
1200	if (!enable) {
1201		I915_WRITE(reg, val);
1202		POSTING_READ(reg);
1203		return;
1204	}
1205
1206	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1207		val |= VIDEO_DIP_ENABLE_GCP_HSW;
1208
1209	I915_WRITE(reg, val);
1210	POSTING_READ(reg);
1211
1212	intel_write_infoframe(encoder, crtc_state,
1213			      HDMI_INFOFRAME_TYPE_AVI,
1214			      &crtc_state->infoframes.avi);
1215	intel_write_infoframe(encoder, crtc_state,
1216			      HDMI_INFOFRAME_TYPE_SPD,
1217			      &crtc_state->infoframes.spd);
1218	intel_write_infoframe(encoder, crtc_state,
1219			      HDMI_INFOFRAME_TYPE_VENDOR,
1220			      &crtc_state->infoframes.hdmi);
1221	intel_write_infoframe(encoder, crtc_state,
1222			      HDMI_INFOFRAME_TYPE_DRM,
1223			      &crtc_state->infoframes.drm);
1224}
1225
1226void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1227{
1228	struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1229	struct i2c_adapter *adapter =
1230		intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1231
1232	if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1233		return;
1234
1235	DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1236		      enable ? "Enabling" : "Disabling");
1237
1238	drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1239					 adapter, enable);
1240}
1241
1242static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1243				unsigned int offset, void *buffer, size_t size)
1244{
1245	struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1246	struct drm_i915_private *dev_priv =
1247		intel_dig_port->base.base.dev->dev_private;
1248	struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1249							      hdmi->ddc_bus);
1250	int ret;
1251	u8 start = offset & 0xff;
1252	struct i2c_msg msgs[] = {
1253		{
1254			.addr = DRM_HDCP_DDC_ADDR,
1255			.flags = 0,
1256			.len = 1,
1257			.buf = &start,
1258		},
1259		{
1260			.addr = DRM_HDCP_DDC_ADDR,
1261			.flags = I2C_M_RD,
1262			.len = size,
1263			.buf = buffer
1264		}
1265	};
1266	ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1267	if (ret == ARRAY_SIZE(msgs))
1268		return 0;
1269	return ret >= 0 ? -EIO : ret;
1270}
1271
1272static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1273				 unsigned int offset, void *buffer, size_t size)
1274{
1275	struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1276	struct drm_i915_private *dev_priv =
1277		intel_dig_port->base.base.dev->dev_private;
1278	struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1279							      hdmi->ddc_bus);
1280	int ret;
1281	u8 *write_buf;
1282	struct i2c_msg msg;
1283
1284	write_buf = kzalloc(size + 1, GFP_KERNEL);
1285	if (!write_buf)
1286		return -ENOMEM;
1287
1288	write_buf[0] = offset & 0xff;
1289	memcpy(&write_buf[1], buffer, size);
1290
1291	msg.addr = DRM_HDCP_DDC_ADDR;
1292	msg.flags = 0,
1293	msg.len = size + 1,
1294	msg.buf = write_buf;
1295
1296	ret = i2c_transfer(adapter, &msg, 1);
1297	if (ret == 1)
1298		ret = 0;
1299	else if (ret >= 0)
1300		ret = -EIO;
1301
1302	kfree(write_buf);
1303	return ret;
1304}
1305
1306static
1307int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1308				  u8 *an)
1309{
1310	struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1311	struct drm_i915_private *dev_priv =
1312		intel_dig_port->base.base.dev->dev_private;
1313	struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1314							      hdmi->ddc_bus);
1315	int ret;
1316
1317	ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1318				    DRM_HDCP_AN_LEN);
1319	if (ret) {
1320		DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1321		return ret;
1322	}
1323
1324	ret = intel_gmbus_output_aksv(adapter);
1325	if (ret < 0) {
1326		DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1327		return ret;
1328	}
1329	return 0;
1330}
1331
1332static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1333				     u8 *bksv)
1334{
1335	int ret;
1336	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1337				   DRM_HDCP_KSV_LEN);
1338	if (ret)
1339		DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1340	return ret;
1341}
1342
1343static
1344int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1345				 u8 *bstatus)
1346{
1347	int ret;
1348	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1349				   bstatus, DRM_HDCP_BSTATUS_LEN);
1350	if (ret)
1351		DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1352	return ret;
1353}
1354
1355static
1356int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1357				     bool *repeater_present)
1358{
1359	int ret;
1360	u8 val;
1361
1362	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1363	if (ret) {
1364		DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1365		return ret;
1366	}
1367	*repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1368	return 0;
1369}
1370
1371static
1372int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1373				  u8 *ri_prime)
1374{
1375	int ret;
1376	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1377				   ri_prime, DRM_HDCP_RI_LEN);
1378	if (ret)
1379		DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1380	return ret;
1381}
1382
1383static
1384int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1385				   bool *ksv_ready)
1386{
1387	int ret;
1388	u8 val;
1389
1390	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1391	if (ret) {
1392		DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1393		return ret;
1394	}
1395	*ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1396	return 0;
1397}
1398
1399static
1400int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1401				  int num_downstream, u8 *ksv_fifo)
1402{
1403	int ret;
1404	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1405				   ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1406	if (ret) {
1407		DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1408		return ret;
1409	}
1410	return 0;
1411}
1412
1413static
1414int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1415				      int i, u32 *part)
1416{
1417	int ret;
1418
1419	if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1420		return -EINVAL;
1421
1422	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1423				   part, DRM_HDCP_V_PRIME_PART_LEN);
1424	if (ret)
1425		DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1426	return ret;
1427}
1428
1429static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1430{
1431	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1432	struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1433	struct drm_crtc *crtc = connector->base.state->crtc;
1434	struct intel_crtc *intel_crtc = container_of(crtc,
1435						     struct intel_crtc, base);
1436	u32 scanline;
1437	int ret;
1438
1439	for (;;) {
1440		scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1441		if (scanline > 100 && scanline < 200)
1442			break;
1443		usleep_range(25, 50);
1444	}
1445
1446	ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1447	if (ret) {
1448		DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1449		return ret;
1450	}
1451	ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1452	if (ret) {
1453		DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1454		return ret;
1455	}
1456
1457	return 0;
1458}
1459
1460static
1461int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1462				      bool enable)
1463{
1464	struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1465	struct intel_connector *connector = hdmi->attached_connector;
1466	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1467	int ret;
1468
1469	if (!enable)
1470		usleep_range(6, 60); /* Bspec says >= 6us */
1471
1472	ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1473	if (ret) {
1474		DRM_ERROR("%s HDCP signalling failed (%d)\n",
1475			  enable ? "Enable" : "Disable", ret);
1476		return ret;
1477	}
1478
1479	/*
1480	 * WA: To fix incorrect positioning of the window of
1481	 * opportunity and enc_en signalling in KABYLAKE.
1482	 */
1483	if (IS_KABYLAKE(dev_priv) && enable)
1484		return kbl_repositioning_enc_en_signal(connector);
1485
1486	return 0;
1487}
1488
1489static
1490bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1491{
1492	struct drm_i915_private *dev_priv =
1493		intel_dig_port->base.base.dev->dev_private;
1494	enum port port = intel_dig_port->base.port;
1495	int ret;
1496	union {
1497		u32 reg;
1498		u8 shim[DRM_HDCP_RI_LEN];
1499	} ri;
1500
1501	ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1502	if (ret)
1503		return false;
1504
1505	I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1506
1507	/* Wait for Ri prime match */
1508	if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1509		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1510		DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1511			  I915_READ(PORT_HDCP_STATUS(port)));
1512		return false;
1513	}
1514	return true;
1515}
1516
1517struct hdcp2_hdmi_msg_data {
1518	u8 msg_id;
1519	u32 timeout;
1520	u32 timeout2;
1521};
1522
1523static const struct hdcp2_hdmi_msg_data hdcp2_msg_data[] = {
1524	{ HDCP_2_2_AKE_INIT, 0, 0 },
1525	{ HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
1526	{ HDCP_2_2_AKE_NO_STORED_KM, 0, 0 },
1527	{ HDCP_2_2_AKE_STORED_KM, 0, 0 },
1528	{ HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1529	  HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
1530	{ HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
1531	{ HDCP_2_2_LC_INIT, 0, 0 },
1532	{ HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0 },
1533	{ HDCP_2_2_SKE_SEND_EKS, 0, 0 },
1534	{ HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
1535	{ HDCP_2_2_REP_SEND_ACK, 0, 0 },
1536	{ HDCP_2_2_REP_STREAM_MANAGE, 0, 0 },
1537	{ HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
1538};
1539
1540static
1541int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1542				    u8 *rx_status)
1543{
1544	return intel_hdmi_hdcp_read(intel_dig_port,
1545				    HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1546				    rx_status,
1547				    HDCP_2_2_HDMI_RXSTATUS_LEN);
1548}
1549
1550static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1551{
1552	int i;
1553
1554	for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1555		if (hdcp2_msg_data[i].msg_id == msg_id &&
1556		    (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1557			return hdcp2_msg_data[i].timeout;
1558		else if (hdcp2_msg_data[i].msg_id == msg_id)
1559			return hdcp2_msg_data[i].timeout2;
1560
1561	return -EINVAL;
1562}
1563
1564static inline
1565int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1566				  u8 msg_id, bool *msg_ready,
1567				  ssize_t *msg_sz)
1568{
1569	u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1570	int ret;
1571
1572	ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1573	if (ret < 0) {
1574		DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1575		return ret;
1576	}
1577
1578	*msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1579		  rx_status[0]);
1580
1581	if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1582		*msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1583			     *msg_sz);
1584	else
1585		*msg_ready = *msg_sz;
1586
1587	return 0;
1588}
1589
1590static ssize_t
1591intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1592			      u8 msg_id, bool paired)
1593{
1594	bool msg_ready = false;
1595	int timeout, ret;
1596	ssize_t msg_sz = 0;
1597
1598	timeout = get_hdcp2_msg_timeout(msg_id, paired);
1599	if (timeout < 0)
1600		return timeout;
1601
1602	ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1603							     msg_id, &msg_ready,
1604							     &msg_sz),
1605			 !ret && msg_ready && msg_sz, timeout * 1000,
1606			 1000, 5 * 1000);
1607	if (ret)
1608		DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1609			      msg_id, ret, timeout);
1610
1611	return ret ? ret : msg_sz;
1612}
1613
1614static
1615int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1616			       void *buf, size_t size)
1617{
1618	unsigned int offset;
1619
1620	offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1621	return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1622}
1623
1624static
1625int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1626			      u8 msg_id, void *buf, size_t size)
1627{
1628	struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1629	struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1630	unsigned int offset;
1631	ssize_t ret;
1632
1633	ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1634					    hdcp->is_paired);
1635	if (ret < 0)
1636		return ret;
1637
1638	/*
1639	 * Available msg size should be equal to or lesser than the
1640	 * available buffer.
1641	 */
1642	if (ret > size) {
1643		DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1644			      ret, size);
1645		return -1;
1646	}
1647
1648	offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1649	ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1650	if (ret)
1651		DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1652
1653	return ret;
1654}
1655
1656static
1657int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1658{
1659	u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1660	int ret;
1661
1662	ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1663	if (ret)
1664		return ret;
1665
1666	/*
1667	 * Re-auth request and Link Integrity Failures are represented by
1668	 * same bit. i.e reauth_req.
1669	 */
1670	if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1671		ret = HDCP_REAUTH_REQUEST;
1672	else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1673		ret = HDCP_TOPOLOGY_CHANGE;
1674
1675	return ret;
1676}
1677
1678static
1679int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1680			     bool *capable)
1681{
1682	u8 hdcp2_version;
1683	int ret;
1684
1685	*capable = false;
1686	ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1687				   &hdcp2_version, sizeof(hdcp2_version));
1688	if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1689		*capable = true;
1690
1691	return ret;
1692}
1693
1694static inline
1695enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1696{
1697	return HDCP_PROTOCOL_HDMI;
1698}
1699
1700static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1701	.write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1702	.read_bksv = intel_hdmi_hdcp_read_bksv,
1703	.read_bstatus = intel_hdmi_hdcp_read_bstatus,
1704	.repeater_present = intel_hdmi_hdcp_repeater_present,
1705	.read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1706	.read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1707	.read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1708	.read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1709	.toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1710	.check_link = intel_hdmi_hdcp_check_link,
1711	.write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1712	.read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1713	.check_2_2_link	= intel_hdmi_hdcp2_check_link,
1714	.hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1715	.protocol = HDCP_PROTOCOL_HDMI,
1716};
1717
1718static void intel_hdmi_prepare(struct intel_encoder *encoder,
1719			       const struct intel_crtc_state *crtc_state)
1720{
1721	struct drm_device *dev = encoder->base.dev;
1722	struct drm_i915_private *dev_priv = to_i915(dev);
1723	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1724	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1725	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1726	u32 hdmi_val;
1727
1728	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1729
1730	hdmi_val = SDVO_ENCODING_HDMI;
1731	if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1732		hdmi_val |= HDMI_COLOR_RANGE_16_235;
1733	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1734		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1735	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1736		hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1737
1738	if (crtc_state->pipe_bpp > 24)
1739		hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1740	else
1741		hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1742
1743	if (crtc_state->has_hdmi_sink)
1744		hdmi_val |= HDMI_MODE_SELECT_HDMI;
1745
1746	if (HAS_PCH_CPT(dev_priv))
1747		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1748	else if (IS_CHERRYVIEW(dev_priv))
1749		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1750	else
1751		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1752
1753	I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1754	POSTING_READ(intel_hdmi->hdmi_reg);
1755}
1756
1757static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1758				    enum pipe *pipe)
1759{
1760	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1761	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1762	intel_wakeref_t wakeref;
1763	bool ret;
1764
1765	wakeref = intel_display_power_get_if_enabled(dev_priv,
1766						     encoder->power_domain);
1767	if (!wakeref)
1768		return false;
1769
1770	ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1771
1772	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1773
1774	return ret;
1775}
1776
1777static void intel_hdmi_get_config(struct intel_encoder *encoder,
1778				  struct intel_crtc_state *pipe_config)
1779{
1780	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1781	struct drm_device *dev = encoder->base.dev;
1782	struct drm_i915_private *dev_priv = to_i915(dev);
1783	u32 tmp, flags = 0;
1784	int dotclock;
1785
1786	pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1787
1788	tmp = I915_READ(intel_hdmi->hdmi_reg);
1789
1790	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1791		flags |= DRM_MODE_FLAG_PHSYNC;
1792	else
1793		flags |= DRM_MODE_FLAG_NHSYNC;
1794
1795	if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1796		flags |= DRM_MODE_FLAG_PVSYNC;
1797	else
1798		flags |= DRM_MODE_FLAG_NVSYNC;
1799
1800	if (tmp & HDMI_MODE_SELECT_HDMI)
1801		pipe_config->has_hdmi_sink = true;
1802
1803	pipe_config->infoframes.enable |=
1804		intel_hdmi_infoframes_enabled(encoder, pipe_config);
1805
1806	if (pipe_config->infoframes.enable)
1807		pipe_config->has_infoframe = true;
1808
1809	if (tmp & HDMI_AUDIO_ENABLE)
1810		pipe_config->has_audio = true;
1811
1812	if (!HAS_PCH_SPLIT(dev_priv) &&
1813	    tmp & HDMI_COLOR_RANGE_16_235)
1814		pipe_config->limited_color_range = true;
1815
1816	pipe_config->base.adjusted_mode.flags |= flags;
1817
1818	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1819		dotclock = pipe_config->port_clock * 2 / 3;
1820	else
1821		dotclock = pipe_config->port_clock;
1822
1823	if (pipe_config->pixel_multiplier)
1824		dotclock /= pipe_config->pixel_multiplier;
1825
1826	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1827
1828	pipe_config->lane_count = 4;
1829
1830	intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1831
1832	intel_read_infoframe(encoder, pipe_config,
1833			     HDMI_INFOFRAME_TYPE_AVI,
1834			     &pipe_config->infoframes.avi);
1835	intel_read_infoframe(encoder, pipe_config,
1836			     HDMI_INFOFRAME_TYPE_SPD,
1837			     &pipe_config->infoframes.spd);
1838	intel_read_infoframe(encoder, pipe_config,
1839			     HDMI_INFOFRAME_TYPE_VENDOR,
1840			     &pipe_config->infoframes.hdmi);
1841}
1842
1843static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1844				    const struct intel_crtc_state *pipe_config,
1845				    const struct drm_connector_state *conn_state)
1846{
1847	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1848
1849	WARN_ON(!pipe_config->has_hdmi_sink);
1850	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1851			 pipe_name(crtc->pipe));
1852	intel_audio_codec_enable(encoder, pipe_config, conn_state);
1853}
1854
1855static void g4x_enable_hdmi(struct intel_encoder *encoder,
1856			    const struct intel_crtc_state *pipe_config,
1857			    const struct drm_connector_state *conn_state)
1858{
1859	struct drm_device *dev = encoder->base.dev;
1860	struct drm_i915_private *dev_priv = to_i915(dev);
1861	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1862	u32 temp;
1863
1864	temp = I915_READ(intel_hdmi->hdmi_reg);
1865
1866	temp |= SDVO_ENABLE;
1867	if (pipe_config->has_audio)
1868		temp |= HDMI_AUDIO_ENABLE;
1869
1870	I915_WRITE(intel_hdmi->hdmi_reg, temp);
1871	POSTING_READ(intel_hdmi->hdmi_reg);
1872
1873	if (pipe_config->has_audio)
1874		intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1875}
1876
1877static void ibx_enable_hdmi(struct intel_encoder *encoder,
1878			    const struct intel_crtc_state *pipe_config,
1879			    const struct drm_connector_state *conn_state)
1880{
1881	struct drm_device *dev = encoder->base.dev;
1882	struct drm_i915_private *dev_priv = to_i915(dev);
1883	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1884	u32 temp;
1885
1886	temp = I915_READ(intel_hdmi->hdmi_reg);
1887
1888	temp |= SDVO_ENABLE;
1889	if (pipe_config->has_audio)
1890		temp |= HDMI_AUDIO_ENABLE;
1891
1892	/*
1893	 * HW workaround, need to write this twice for issue
1894	 * that may result in first write getting masked.
1895	 */
1896	I915_WRITE(intel_hdmi->hdmi_reg, temp);
1897	POSTING_READ(intel_hdmi->hdmi_reg);
1898	I915_WRITE(intel_hdmi->hdmi_reg, temp);
1899	POSTING_READ(intel_hdmi->hdmi_reg);
1900
1901	/*
1902	 * HW workaround, need to toggle enable bit off and on
1903	 * for 12bpc with pixel repeat.
1904	 *
1905	 * FIXME: BSpec says this should be done at the end of
1906	 * of the modeset sequence, so not sure if this isn't too soon.
1907	 */
1908	if (pipe_config->pipe_bpp > 24 &&
1909	    pipe_config->pixel_multiplier > 1) {
1910		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1911		POSTING_READ(intel_hdmi->hdmi_reg);
1912
1913		/*
1914		 * HW workaround, need to write this twice for issue
1915		 * that may result in first write getting masked.
1916		 */
1917		I915_WRITE(intel_hdmi->hdmi_reg, temp);
1918		POSTING_READ(intel_hdmi->hdmi_reg);
1919		I915_WRITE(intel_hdmi->hdmi_reg, temp);
1920		POSTING_READ(intel_hdmi->hdmi_reg);
1921	}
1922
1923	if (pipe_config->has_audio)
1924		intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1925}
1926
1927static void cpt_enable_hdmi(struct intel_encoder *encoder,
1928			    const struct intel_crtc_state *pipe_config,
1929			    const struct drm_connector_state *conn_state)
1930{
1931	struct drm_device *dev = encoder->base.dev;
1932	struct drm_i915_private *dev_priv = to_i915(dev);
1933	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1934	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1935	enum pipe pipe = crtc->pipe;
1936	u32 temp;
1937
1938	temp = I915_READ(intel_hdmi->hdmi_reg);
1939
1940	temp |= SDVO_ENABLE;
1941	if (pipe_config->has_audio)
1942		temp |= HDMI_AUDIO_ENABLE;
1943
1944	/*
1945	 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1946	 *
1947	 * The procedure for 12bpc is as follows:
1948	 * 1. disable HDMI clock gating
1949	 * 2. enable HDMI with 8bpc
1950	 * 3. enable HDMI with 12bpc
1951	 * 4. enable HDMI clock gating
1952	 */
1953
1954	if (pipe_config->pipe_bpp > 24) {
1955		I915_WRITE(TRANS_CHICKEN1(pipe),
1956			   I915_READ(TRANS_CHICKEN1(pipe)) |
1957			   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1958
1959		temp &= ~SDVO_COLOR_FORMAT_MASK;
1960		temp |= SDVO_COLOR_FORMAT_8bpc;
1961	}
1962
1963	I915_WRITE(intel_hdmi->hdmi_reg, temp);
1964	POSTING_READ(intel_hdmi->hdmi_reg);
1965
1966	if (pipe_config->pipe_bpp > 24) {
1967		temp &= ~SDVO_COLOR_FORMAT_MASK;
1968		temp |= HDMI_COLOR_FORMAT_12bpc;
1969
1970		I915_WRITE(intel_hdmi->hdmi_reg, temp);
1971		POSTING_READ(intel_hdmi->hdmi_reg);
1972
1973		I915_WRITE(TRANS_CHICKEN1(pipe),
1974			   I915_READ(TRANS_CHICKEN1(pipe)) &
1975			   ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1976	}
1977
1978	if (pipe_config->has_audio)
1979		intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1980}
1981
1982static void vlv_enable_hdmi(struct intel_encoder *encoder,
1983			    const struct intel_crtc_state *pipe_config,
1984			    const struct drm_connector_state *conn_state)
1985{
1986}
1987
1988static void intel_disable_hdmi(struct intel_encoder *encoder,
1989			       const struct intel_crtc_state *old_crtc_state,
1990			       const struct drm_connector_state *old_conn_state)
1991{
1992	struct drm_device *dev = encoder->base.dev;
1993	struct drm_i915_private *dev_priv = to_i915(dev);
1994	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1995	struct intel_digital_port *intel_dig_port =
1996		hdmi_to_dig_port(intel_hdmi);
1997	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1998	u32 temp;
1999
2000	temp = I915_READ(intel_hdmi->hdmi_reg);
2001
2002	temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2003	I915_WRITE(intel_hdmi->hdmi_reg, temp);
2004	POSTING_READ(intel_hdmi->hdmi_reg);
2005
2006	/*
2007	 * HW workaround for IBX, we need to move the port
2008	 * to transcoder A after disabling it to allow the
2009	 * matching DP port to be enabled on transcoder A.
2010	 */
2011	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2012		/*
2013		 * We get CPU/PCH FIFO underruns on the other pipe when
2014		 * doing the workaround. Sweep them under the rug.
2015		 */
2016		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2017		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2018
2019		temp &= ~SDVO_PIPE_SEL_MASK;
2020		temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2021		/*
2022		 * HW workaround, need to write this twice for issue
2023		 * that may result in first write getting masked.
2024		 */
2025		I915_WRITE(intel_hdmi->hdmi_reg, temp);
2026		POSTING_READ(intel_hdmi->hdmi_reg);
2027		I915_WRITE(intel_hdmi->hdmi_reg, temp);
2028		POSTING_READ(intel_hdmi->hdmi_reg);
2029
2030		temp &= ~SDVO_ENABLE;
2031		I915_WRITE(intel_hdmi->hdmi_reg, temp);
2032		POSTING_READ(intel_hdmi->hdmi_reg);
2033
2034		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2035		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2036		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2037	}
2038
2039	intel_dig_port->set_infoframes(encoder,
2040				       false,
2041				       old_crtc_state, old_conn_state);
2042
2043	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2044}
2045
2046static void g4x_disable_hdmi(struct intel_encoder *encoder,
2047			     const struct intel_crtc_state *old_crtc_state,
2048			     const struct drm_connector_state *old_conn_state)
2049{
2050	if (old_crtc_state->has_audio)
2051		intel_audio_codec_disable(encoder,
2052					  old_crtc_state, old_conn_state);
2053
2054	intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2055}
2056
2057static void pch_disable_hdmi(struct intel_encoder *encoder,
2058			     const struct intel_crtc_state *old_crtc_state,
2059			     const struct drm_connector_state *old_conn_state)
2060{
2061	if (old_crtc_state->has_audio)
2062		intel_audio_codec_disable(encoder,
2063					  old_crtc_state, old_conn_state);
2064}
2065
2066static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2067				  const struct intel_crtc_state *old_crtc_state,
2068				  const struct drm_connector_state *old_conn_state)
2069{
2070	intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2071}
2072
2073static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2074{
2075	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2076	const struct ddi_vbt_port_info *info =
2077		&dev_priv->vbt.ddi_port_info[encoder->port];
2078	int max_tmds_clock;
2079
2080	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2081		max_tmds_clock = 594000;
2082	else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2083		max_tmds_clock = 300000;
2084	else if (INTEL_GEN(dev_priv) >= 5)
2085		max_tmds_clock = 225000;
2086	else
2087		max_tmds_clock = 165000;
2088
2089	if (info->max_tmds_clock)
2090		max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2091
2092	return max_tmds_clock;
2093}
2094
2095static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2096				 bool respect_downstream_limits,
2097				 bool force_dvi)
2098{
2099	struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2100	int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2101
2102	if (respect_downstream_limits) {
2103		struct intel_connector *connector = hdmi->attached_connector;
2104		const struct drm_display_info *info = &connector->base.display_info;
2105
2106		if (hdmi->dp_dual_mode.max_tmds_clock)
2107			max_tmds_clock = min(max_tmds_clock,
2108					     hdmi->dp_dual_mode.max_tmds_clock);
2109
2110		if (info->max_tmds_clock)
2111			max_tmds_clock = min(max_tmds_clock,
2112					     info->max_tmds_clock);
2113		else if (!hdmi->has_hdmi_sink || force_dvi)
2114			max_tmds_clock = min(max_tmds_clock, 165000);
2115	}
2116
2117	return max_tmds_clock;
2118}
2119
2120static enum drm_mode_status
2121hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2122		      int clock, bool respect_downstream_limits,
2123		      bool force_dvi)
2124{
2125	struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2126
2127	if (clock < 25000)
2128		return MODE_CLOCK_LOW;
2129	if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2130		return MODE_CLOCK_HIGH;
2131
2132	/* BXT DPLL can't generate 223-240 MHz */
2133	if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2134		return MODE_CLOCK_RANGE;
2135
2136	/* CHV DPLL can't generate 216-240 MHz */
2137	if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2138		return MODE_CLOCK_RANGE;
2139
2140	return MODE_OK;
2141}
2142
2143static enum drm_mode_status
2144intel_hdmi_mode_valid(struct drm_connector *connector,
2145		      struct drm_display_mode *mode)
2146{
2147	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2148	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2149	struct drm_i915_private *dev_priv = to_i915(dev);
2150	enum drm_mode_status status;
2151	int clock;
2152	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2153	bool force_dvi =
2154		READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2155
2156	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2157		return MODE_NO_DBLESCAN;
2158
2159	clock = mode->clock;
2160
2161	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2162		clock *= 2;
2163
2164	if (clock > max_dotclk)
2165		return MODE_CLOCK_HIGH;
2166
2167	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2168		clock *= 2;
2169
2170	if (drm_mode_is_420_only(&connector->display_info, mode))
2171		clock /= 2;
2172
2173	/* check if we can do 8bpc */
2174	status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2175
2176	if (hdmi->has_hdmi_sink && !force_dvi) {
2177		/* if we can't do 8bpc we may still be able to do 12bpc */
2178		if (status != MODE_OK && !HAS_GMCH(dev_priv))
2179			status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2180						       true, force_dvi);
2181
2182		/* if we can't do 8,12bpc we may still be able to do 10bpc */
2183		if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2184			status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2185						       true, force_dvi);
2186	}
2187
2188	return status;
2189}
2190
2191static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2192				     int bpc)
2193{
2194	struct drm_i915_private *dev_priv =
2195		to_i915(crtc_state->base.crtc->dev);
2196	struct drm_atomic_state *state = crtc_state->base.state;
2197	struct drm_connector_state *connector_state;
2198	struct drm_connector *connector;
2199	const struct drm_display_mode *adjusted_mode =
2200		&crtc_state->base.adjusted_mode;
2201	int i;
2202
2203	if (HAS_GMCH(dev_priv))
2204		return false;
2205
2206	if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2207		return false;
2208
2209	if (crtc_state->pipe_bpp < bpc * 3)
2210		return false;
2211
2212	if (!crtc_state->has_hdmi_sink)
2213		return false;
2214
2215	/*
2216	 * HDMI deep color affects the clocks, so it's only possible
2217	 * when not cloning with other encoder types.
2218	 */
2219	if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2220		return false;
2221
2222	for_each_new_connector_in_state(state, connector, connector_state, i) {
2223		const struct drm_display_info *info = &connector->display_info;
2224
2225		if (connector_state->crtc != crtc_state->base.crtc)
2226			continue;
2227
2228		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2229			const struct drm_hdmi_info *hdmi = &info->hdmi;
2230
2231			if (bpc == 12 && !(hdmi->y420_dc_modes &
2232					   DRM_EDID_YCBCR420_DC_36))
2233				return false;
2234			else if (bpc == 10 && !(hdmi->y420_dc_modes &
2235						DRM_EDID_YCBCR420_DC_30))
2236				return false;
2237		} else {
2238			if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2239					   DRM_EDID_HDMI_DC_36))
2240				return false;
2241			else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2242						DRM_EDID_HDMI_DC_30))
2243				return false;
2244		}
2245	}
2246
2247	/* Display WA #1139: glk */
2248	if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2249	    adjusted_mode->htotal > 5460)
2250		return false;
2251
2252	/* Display Wa_1405510057:icl */
2253	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2254	    bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2255	    (adjusted_mode->crtc_hblank_end -
2256	     adjusted_mode->crtc_hblank_start) % 8 == 2)
2257		return false;
2258
2259	return true;
2260}
2261
2262static bool
2263intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2264			   struct intel_crtc_state *config,
2265			   int *clock_12bpc, int *clock_10bpc,
2266			   int *clock_8bpc)
2267{
2268	struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2269
2270	if (!connector->ycbcr_420_allowed) {
2271		DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2272		return false;
2273	}
2274
2275	/* YCBCR420 TMDS rate requirement is half the pixel clock */
2276	config->port_clock /= 2;
2277	*clock_12bpc /= 2;
2278	*clock_10bpc /= 2;
2279	*clock_8bpc /= 2;
2280	config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2281
2282	/* YCBCR 420 output conversion needs a scaler */
2283	if (skl_update_scaler_crtc(config)) {
2284		DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2285		return false;
2286	}
2287
2288	intel_pch_panel_fitting(intel_crtc, config,
2289				DRM_MODE_SCALE_FULLSCREEN);
2290
2291	return true;
2292}
2293
2294int intel_hdmi_compute_config(struct intel_encoder *encoder,
2295			      struct intel_crtc_state *pipe_config,
2296			      struct drm_connector_state *conn_state)
2297{
2298	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2299	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2300	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2301	struct drm_connector *connector = conn_state->connector;
2302	struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2303	struct intel_digital_connector_state *intel_conn_state =
2304		to_intel_digital_connector_state(conn_state);
2305	int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
2306	int clock_10bpc = clock_8bpc * 5 / 4;
2307	int clock_12bpc = clock_8bpc * 3 / 2;
2308	int desired_bpp;
2309	bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2310
2311	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2312		return -EINVAL;
2313
2314	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2315	pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2316
2317	if (pipe_config->has_hdmi_sink)
2318		pipe_config->has_infoframe = true;
2319
2320	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2321		/* See CEA-861-E - 5.1 Default Encoding Parameters */
2322		pipe_config->limited_color_range =
2323			pipe_config->has_hdmi_sink &&
2324			drm_default_rgb_quant_range(adjusted_mode) ==
2325			HDMI_QUANTIZATION_RANGE_LIMITED;
2326	} else {
2327		pipe_config->limited_color_range =
2328			intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2329	}
2330
2331	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
2332		pipe_config->pixel_multiplier = 2;
2333		clock_8bpc *= 2;
2334		clock_10bpc *= 2;
2335		clock_12bpc *= 2;
2336	}
2337
2338	if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2339		if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
2340						&clock_12bpc, &clock_10bpc,
2341						&clock_8bpc)) {
2342			DRM_ERROR("Can't support YCBCR420 output\n");
2343			return -EINVAL;
2344		}
2345	}
2346
2347	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2348		pipe_config->has_pch_encoder = true;
2349
2350	if (pipe_config->has_hdmi_sink) {
2351		if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2352			pipe_config->has_audio = intel_hdmi->has_audio;
2353		else
2354			pipe_config->has_audio =
2355				intel_conn_state->force_audio == HDMI_AUDIO_ON;
2356	}
2357
2358	/*
2359	 * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
2360	 * to check that the higher clock still fits within limits.
2361	 */
2362	if (hdmi_deep_color_possible(pipe_config, 12) &&
2363	    hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
2364				  true, force_dvi) == MODE_OK) {
2365		DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
2366		desired_bpp = 12*3;
2367
2368		/* Need to adjust the port link by 1.5x for 12bpc. */
2369		pipe_config->port_clock = clock_12bpc;
2370	} else if (hdmi_deep_color_possible(pipe_config, 10) &&
2371		   hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
2372					 true, force_dvi) == MODE_OK) {
2373		DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
2374		desired_bpp = 10 * 3;
2375
2376		/* Need to adjust the port link by 1.25x for 10bpc. */
2377		pipe_config->port_clock = clock_10bpc;
2378	} else {
2379		DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
2380		desired_bpp = 8*3;
2381
2382		pipe_config->port_clock = clock_8bpc;
2383	}
2384
2385	if (!pipe_config->bw_constrained) {
2386		DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
2387		pipe_config->pipe_bpp = desired_bpp;
2388	}
2389
2390	if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
2391				  false, force_dvi) != MODE_OK) {
2392		DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
2393		return -EINVAL;
2394	}
2395
2396	/* Set user selected PAR to incoming mode's member */
2397	adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2398
2399	pipe_config->lane_count = 4;
2400
2401	if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2402					   IS_GEMINILAKE(dev_priv))) {
2403		if (scdc->scrambling.low_rates)
2404			pipe_config->hdmi_scrambling = true;
2405
2406		if (pipe_config->port_clock > 340000) {
2407			pipe_config->hdmi_scrambling = true;
2408			pipe_config->hdmi_high_tmds_clock_ratio = true;
2409		}
2410	}
2411
2412	intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2413
2414	if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2415		DRM_DEBUG_KMS("bad AVI infoframe\n");
2416		return -EINVAL;
2417	}
2418
2419	if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2420		DRM_DEBUG_KMS("bad SPD infoframe\n");
2421		return -EINVAL;
2422	}
2423
2424	if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2425		DRM_DEBUG_KMS("bad HDMI infoframe\n");
2426		return -EINVAL;
2427	}
2428
2429	if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2430		DRM_DEBUG_KMS("bad DRM infoframe\n");
2431		return -EINVAL;
2432	}
2433
2434	return 0;
2435}
2436
2437static void
2438intel_hdmi_unset_edid(struct drm_connector *connector)
2439{
2440	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2441
2442	intel_hdmi->has_hdmi_sink = false;
2443	intel_hdmi->has_audio = false;
2444
2445	intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2446	intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2447
2448	kfree(to_intel_connector(connector)->detect_edid);
2449	to_intel_connector(connector)->detect_edid = NULL;
2450}
2451
2452static void
2453intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2454{
2455	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2456	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2457	enum port port = hdmi_to_dig_port(hdmi)->base.port;
2458	struct i2c_adapter *adapter =
2459		intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2460	enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2461
2462	/*
2463	 * Type 1 DVI adaptors are not required to implement any
2464	 * registers, so we can't always detect their presence.
2465	 * Ideally we should be able to check the state of the
2466	 * CONFIG1 pin, but no such luck on our hardware.
2467	 *
2468	 * The only method left to us is to check the VBT to see
2469	 * if the port is a dual mode capable DP port. But let's
2470	 * only do that when we sucesfully read the EDID, to avoid
2471	 * confusing log messages about DP dual mode adaptors when
2472	 * there's nothing connected to the port.
2473	 */
2474	if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2475		/* An overridden EDID imply that we want this port for testing.
2476		 * Make sure not to set limits for that port.
2477		 */
2478		if (has_edid && !connector->override_edid &&
2479		    intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2480			DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2481			type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2482		} else {
2483			type = DRM_DP_DUAL_MODE_NONE;
2484		}
2485	}
2486
2487	if (type == DRM_DP_DUAL_MODE_NONE)
2488		return;
2489
2490	hdmi->dp_dual_mode.type = type;
2491	hdmi->dp_dual_mode.max_tmds_clock =
2492		drm_dp_dual_mode_max_tmds_clock(type, adapter);
2493
2494	DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2495		      drm_dp_get_dual_mode_type_name(type),
2496		      hdmi->dp_dual_mode.max_tmds_clock);
2497}
2498
2499static bool
2500intel_hdmi_set_edid(struct drm_connector *connector)
2501{
2502	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2503	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2504	intel_wakeref_t wakeref;
2505	struct edid *edid;
2506	bool connected = false;
2507	struct i2c_adapter *i2c;
2508
2509	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2510
2511	i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2512
2513	edid = drm_get_edid(connector, i2c);
2514
2515	if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2516		DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2517		intel_gmbus_force_bit(i2c, true);
2518		edid = drm_get_edid(connector, i2c);
2519		intel_gmbus_force_bit(i2c, false);
2520	}
2521
2522	intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2523
2524	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2525
2526	to_intel_connector(connector)->detect_edid = edid;
2527	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2528		intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2529		intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2530
2531		connected = true;
2532	}
2533
2534	cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2535
2536	return connected;
2537}
2538
2539static enum drm_connector_status
2540intel_hdmi_detect(struct drm_connector *connector, bool force)
2541{
2542	enum drm_connector_status status = connector_status_disconnected;
2543	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2544	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2545	struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2546	intel_wakeref_t wakeref;
2547
2548	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2549		      connector->base.id, connector->name);
2550
2551	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2552
2553	if (INTEL_GEN(dev_priv) >= 11 &&
2554	    !intel_digital_port_connected(encoder))
2555		goto out;
2556
2557	intel_hdmi_unset_edid(connector);
2558
2559	if (intel_hdmi_set_edid(connector))
2560		status = connector_status_connected;
2561
2562out:
2563	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2564
2565	if (status != connector_status_connected)
2566		cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2567
2568	/*
2569	 * Make sure the refs for power wells enabled during detect are
2570	 * dropped to avoid a new detect cycle triggered by HPD polling.
2571	 */
2572	intel_display_power_flush_work(dev_priv);
2573
2574	return status;
2575}
2576
2577static void
2578intel_hdmi_force(struct drm_connector *connector)
2579{
2580	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2581		      connector->base.id, connector->name);
2582
2583	intel_hdmi_unset_edid(connector);
2584
2585	if (connector->status != connector_status_connected)
2586		return;
2587
2588	intel_hdmi_set_edid(connector);
2589}
2590
2591static int intel_hdmi_get_modes(struct drm_connector *connector)
2592{
2593	struct edid *edid;
2594
2595	edid = to_intel_connector(connector)->detect_edid;
2596	if (edid == NULL)
2597		return 0;
2598
2599	return intel_connector_update_modes(connector, edid);
2600}
2601
2602static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2603				  const struct intel_crtc_state *pipe_config,
2604				  const struct drm_connector_state *conn_state)
2605{
2606	struct intel_digital_port *intel_dig_port =
2607		enc_to_dig_port(&encoder->base);
2608
2609	intel_hdmi_prepare(encoder, pipe_config);
2610
2611	intel_dig_port->set_infoframes(encoder,
2612				       pipe_config->has_infoframe,
2613				       pipe_config, conn_state);
2614}
2615
2616static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2617				const struct intel_crtc_state *pipe_config,
2618				const struct drm_connector_state *conn_state)
2619{
2620	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2621	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2622
2623	vlv_phy_pre_encoder_enable(encoder, pipe_config);
2624
2625	/* HDMI 1.0V-2dB */
2626	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2627				 0x2b247878);
2628
2629	dport->set_infoframes(encoder,
2630			      pipe_config->has_infoframe,
2631			      pipe_config, conn_state);
2632
2633	g4x_enable_hdmi(encoder, pipe_config, conn_state);
2634
2635	vlv_wait_port_ready(dev_priv, dport, 0x0);
2636}
2637
2638static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2639				    const struct intel_crtc_state *pipe_config,
2640				    const struct drm_connector_state *conn_state)
2641{
2642	intel_hdmi_prepare(encoder, pipe_config);
2643
2644	vlv_phy_pre_pll_enable(encoder, pipe_config);
2645}
2646
2647static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2648				    const struct intel_crtc_state *pipe_config,
2649				    const struct drm_connector_state *conn_state)
2650{
2651	intel_hdmi_prepare(encoder, pipe_config);
2652
2653	chv_phy_pre_pll_enable(encoder, pipe_config);
2654}
2655
2656static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2657				      const struct intel_crtc_state *old_crtc_state,
2658				      const struct drm_connector_state *old_conn_state)
2659{
2660	chv_phy_post_pll_disable(encoder, old_crtc_state);
2661}
2662
2663static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2664				  const struct intel_crtc_state *old_crtc_state,
2665				  const struct drm_connector_state *old_conn_state)
2666{
2667	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
2668	vlv_phy_reset_lanes(encoder, old_crtc_state);
2669}
2670
2671static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2672				  const struct intel_crtc_state *old_crtc_state,
2673				  const struct drm_connector_state *old_conn_state)
2674{
2675	struct drm_device *dev = encoder->base.dev;
2676	struct drm_i915_private *dev_priv = to_i915(dev);
2677
2678	vlv_dpio_get(dev_priv);
2679
2680	/* Assert data lane reset */
2681	chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2682
2683	vlv_dpio_put(dev_priv);
2684}
2685
2686static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2687				const struct intel_crtc_state *pipe_config,
2688				const struct drm_connector_state *conn_state)
2689{
2690	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2691	struct drm_device *dev = encoder->base.dev;
2692	struct drm_i915_private *dev_priv = to_i915(dev);
2693
2694	chv_phy_pre_encoder_enable(encoder, pipe_config);
2695
2696	/* FIXME: Program the support xxx V-dB */
2697	/* Use 800mV-0dB */
2698	chv_set_phy_signal_level(encoder, 128, 102, false);
2699
2700	dport->set_infoframes(encoder,
2701			      pipe_config->has_infoframe,
2702			      pipe_config, conn_state);
2703
2704	g4x_enable_hdmi(encoder, pipe_config, conn_state);
2705
2706	vlv_wait_port_ready(dev_priv, dport, 0x0);
2707
2708	/* Second common lane will stay alive on its own now */
2709	chv_phy_release_cl2_override(encoder);
2710}
2711
2712static struct i2c_adapter *
2713intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2714{
2715	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2716	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2717
2718	return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2719}
2720
2721static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2722{
2723	struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2724	struct kobject *i2c_kobj = &adapter->dev.kobj;
2725	struct kobject *connector_kobj = &connector->kdev->kobj;
2726	int ret;
2727
2728	ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2729	if (ret)
2730		DRM_ERROR("Failed to create i2c symlink (%d)\n", ret);
2731}
2732
2733static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2734{
2735	struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2736	struct kobject *i2c_kobj = &adapter->dev.kobj;
2737	struct kobject *connector_kobj = &connector->kdev->kobj;
2738
2739	sysfs_remove_link(connector_kobj, i2c_kobj->name);
2740}
2741
2742static int
2743intel_hdmi_connector_register(struct drm_connector *connector)
2744{
2745	int ret;
2746
2747	ret = intel_connector_register(connector);
2748	if (ret)
2749		return ret;
2750
2751	i915_debugfs_connector_add(connector);
2752
2753	intel_hdmi_create_i2c_symlink(connector);
2754
2755	return ret;
2756}
2757
2758static void intel_hdmi_destroy(struct drm_connector *connector)
2759{
2760	if (intel_attached_hdmi(connector)->cec_notifier)
2761		cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2762
2763	intel_connector_destroy(connector);
2764}
2765
2766static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2767{
2768	intel_hdmi_remove_i2c_symlink(connector);
2769
2770	intel_connector_unregister(connector);
2771}
2772
2773static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2774	.detect = intel_hdmi_detect,
2775	.force = intel_hdmi_force,
2776	.fill_modes = drm_helper_probe_single_connector_modes,
2777	.atomic_get_property = intel_digital_connector_atomic_get_property,
2778	.atomic_set_property = intel_digital_connector_atomic_set_property,
2779	.late_register = intel_hdmi_connector_register,
2780	.early_unregister = intel_hdmi_connector_unregister,
2781	.destroy = intel_hdmi_destroy,
2782	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2783	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
2784};
2785
2786static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2787	.get_modes = intel_hdmi_get_modes,
2788	.mode_valid = intel_hdmi_mode_valid,
2789	.atomic_check = intel_digital_connector_atomic_check,
2790};
2791
2792static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2793	.destroy = intel_encoder_destroy,
2794};
2795
2796static void
2797intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2798{
2799	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2800	struct intel_digital_port *intel_dig_port =
2801				hdmi_to_dig_port(intel_hdmi);
2802
2803	intel_attach_force_audio_property(connector);
2804	intel_attach_broadcast_rgb_property(connector);
2805	intel_attach_aspect_ratio_property(connector);
2806
2807	/*
2808	 * Attach Colorspace property for Non LSPCON based device
2809	 * ToDo: This needs to be extended for LSPCON implementation
2810	 * as well. Will be implemented separately.
2811	 */
2812	if (!intel_dig_port->lspcon.active)
2813		intel_attach_colorspace_property(connector);
2814
2815	drm_connector_attach_content_type_property(connector);
2816	connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2817
2818	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2819		drm_object_attach_property(&connector->base,
2820			connector->dev->mode_config.hdr_output_metadata_property, 0);
2821
2822	if (!HAS_GMCH(dev_priv))
2823		drm_connector_attach_max_bpc_property(connector, 8, 12);
2824}
2825
2826/*
2827 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2828 * @encoder: intel_encoder
2829 * @connector: drm_connector
2830 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2831 *  or reset the high tmds clock ratio for scrambling
2832 * @scrambling: bool to Indicate if the function needs to set or reset
2833 *  sink scrambling
2834 *
2835 * This function handles scrambling on HDMI 2.0 capable sinks.
2836 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2837 * it enables scrambling. This should be called before enabling the HDMI
2838 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2839 * detect a scrambled clock within 100 ms.
2840 *
2841 * Returns:
2842 * True on success, false on failure.
2843 */
2844bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2845				       struct drm_connector *connector,
2846				       bool high_tmds_clock_ratio,
2847				       bool scrambling)
2848{
2849	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2850	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2851	struct drm_scrambling *sink_scrambling =
2852		&connector->display_info.hdmi.scdc.scrambling;
2853	struct i2c_adapter *adapter =
2854		intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2855
2856	if (!sink_scrambling->supported)
2857		return true;
2858
2859	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2860		      connector->base.id, connector->name,
2861		      yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2862
2863	/* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2864	return drm_scdc_set_high_tmds_clock_ratio(adapter,
2865						  high_tmds_clock_ratio) &&
2866		drm_scdc_set_scrambling(adapter, scrambling);
2867}
2868
2869static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2870{
2871	u8 ddc_pin;
2872
2873	switch (port) {
2874	case PORT_B:
2875		ddc_pin = GMBUS_PIN_DPB;
2876		break;
2877	case PORT_C:
2878		ddc_pin = GMBUS_PIN_DPC;
2879		break;
2880	case PORT_D:
2881		ddc_pin = GMBUS_PIN_DPD_CHV;
2882		break;
2883	default:
2884		MISSING_CASE(port);
2885		ddc_pin = GMBUS_PIN_DPB;
2886		break;
2887	}
2888	return ddc_pin;
2889}
2890
2891static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2892{
2893	u8 ddc_pin;
2894
2895	switch (port) {
2896	case PORT_B:
2897		ddc_pin = GMBUS_PIN_1_BXT;
2898		break;
2899	case PORT_C:
2900		ddc_pin = GMBUS_PIN_2_BXT;
2901		break;
2902	default:
2903		MISSING_CASE(port);
2904		ddc_pin = GMBUS_PIN_1_BXT;
2905		break;
2906	}
2907	return ddc_pin;
2908}
2909
2910static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2911			      enum port port)
2912{
2913	u8 ddc_pin;
2914
2915	switch (port) {
2916	case PORT_B:
2917		ddc_pin = GMBUS_PIN_1_BXT;
2918		break;
2919	case PORT_C:
2920		ddc_pin = GMBUS_PIN_2_BXT;
2921		break;
2922	case PORT_D:
2923		ddc_pin = GMBUS_PIN_4_CNP;
2924		break;
2925	case PORT_F:
2926		ddc_pin = GMBUS_PIN_3_BXT;
2927		break;
2928	default:
2929		MISSING_CASE(port);
2930		ddc_pin = GMBUS_PIN_1_BXT;
2931		break;
2932	}
2933	return ddc_pin;
2934}
2935
2936static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2937{
2938	enum phy phy = intel_port_to_phy(dev_priv, port);
2939
2940	if (intel_phy_is_combo(dev_priv, phy))
2941		return GMBUS_PIN_1_BXT + port;
2942	else if (intel_phy_is_tc(dev_priv, phy))
2943		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2944
2945	WARN(1, "Unknown port:%c\n", port_name(port));
2946	return GMBUS_PIN_2_BXT;
2947}
2948
2949static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2950{
2951	enum phy phy = intel_port_to_phy(dev_priv, port);
2952	u8 ddc_pin;
2953
2954	switch (phy) {
2955	case PHY_A:
2956		ddc_pin = GMBUS_PIN_1_BXT;
2957		break;
2958	case PHY_B:
2959		ddc_pin = GMBUS_PIN_2_BXT;
2960		break;
2961	case PHY_C:
2962		ddc_pin = GMBUS_PIN_9_TC1_ICP;
2963		break;
2964	default:
2965		MISSING_CASE(phy);
2966		ddc_pin = GMBUS_PIN_1_BXT;
2967		break;
2968	}
2969	return ddc_pin;
2970}
2971
2972static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2973			      enum port port)
2974{
2975	u8 ddc_pin;
2976
2977	switch (port) {
2978	case PORT_B:
2979		ddc_pin = GMBUS_PIN_DPB;
2980		break;
2981	case PORT_C:
2982		ddc_pin = GMBUS_PIN_DPC;
2983		break;
2984	case PORT_D:
2985		ddc_pin = GMBUS_PIN_DPD;
2986		break;
2987	default:
2988		MISSING_CASE(port);
2989		ddc_pin = GMBUS_PIN_DPB;
2990		break;
2991	}
2992	return ddc_pin;
2993}
2994
2995static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2996			     enum port port)
2997{
2998	const struct ddi_vbt_port_info *info =
2999		&dev_priv->vbt.ddi_port_info[port];
3000	u8 ddc_pin;
3001
3002	if (info->alternate_ddc_pin) {
3003		DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
3004			      info->alternate_ddc_pin, port_name(port));
3005		return info->alternate_ddc_pin;
3006	}
3007
3008	if (HAS_PCH_MCC(dev_priv))
3009		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3010	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv))
3011		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3012	else if (HAS_PCH_CNP(dev_priv))
3013		ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3014	else if (IS_GEN9_LP(dev_priv))
3015		ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3016	else if (IS_CHERRYVIEW(dev_priv))
3017		ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3018	else
3019		ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3020
3021	DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
3022		      ddc_pin, port_name(port));
3023
3024	return ddc_pin;
3025}
3026
3027void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
3028{
3029	struct drm_i915_private *dev_priv =
3030		to_i915(intel_dig_port->base.base.dev);
3031
3032	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3033		intel_dig_port->write_infoframe = vlv_write_infoframe;
3034		intel_dig_port->read_infoframe = vlv_read_infoframe;
3035		intel_dig_port->set_infoframes = vlv_set_infoframes;
3036		intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
3037	} else if (IS_G4X(dev_priv)) {
3038		intel_dig_port->write_infoframe = g4x_write_infoframe;
3039		intel_dig_port->read_infoframe = g4x_read_infoframe;
3040		intel_dig_port->set_infoframes = g4x_set_infoframes;
3041		intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
3042	} else if (HAS_DDI(dev_priv)) {
3043		if (intel_dig_port->lspcon.active) {
3044			intel_dig_port->write_infoframe = lspcon_write_infoframe;
3045			intel_dig_port->read_infoframe = lspcon_read_infoframe;
3046			intel_dig_port->set_infoframes = lspcon_set_infoframes;
3047			intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3048		} else {
3049			intel_dig_port->write_infoframe = hsw_write_infoframe;
3050			intel_dig_port->read_infoframe = hsw_read_infoframe;
3051			intel_dig_port->set_infoframes = hsw_set_infoframes;
3052			intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
3053		}
3054	} else if (HAS_PCH_IBX(dev_priv)) {
3055		intel_dig_port->write_infoframe = ibx_write_infoframe;
3056		intel_dig_port->read_infoframe = ibx_read_infoframe;
3057		intel_dig_port->set_infoframes = ibx_set_infoframes;
3058		intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
3059	} else {
3060		intel_dig_port->write_infoframe = cpt_write_infoframe;
3061		intel_dig_port->read_infoframe = cpt_read_infoframe;
3062		intel_dig_port->set_infoframes = cpt_set_infoframes;
3063		intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
3064	}
3065}
3066
3067void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
3068			       struct intel_connector *intel_connector)
3069{
3070	struct drm_connector *connector = &intel_connector->base;
3071	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3072	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3073	struct drm_device *dev = intel_encoder->base.dev;
3074	struct drm_i915_private *dev_priv = to_i915(dev);
3075	enum port port = intel_encoder->port;
3076
3077	DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
3078		      port_name(port));
3079
3080	if (WARN(intel_dig_port->max_lanes < 4,
3081		 "Not enough lanes (%d) for HDMI on port %c\n",
3082		 intel_dig_port->max_lanes, port_name(port)))
3083		return;
3084
3085	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
3086			   DRM_MODE_CONNECTOR_HDMIA);
3087	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3088
3089	connector->interlace_allowed = 1;
3090	connector->doublescan_allowed = 0;
3091	connector->stereo_allowed = 1;
3092
3093	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3094		connector->ycbcr_420_allowed = true;
3095
3096	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
3097
3098	if (WARN_ON(port == PORT_A))
3099		return;
3100	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3101
3102	if (HAS_DDI(dev_priv))
3103		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3104	else
3105		intel_connector->get_hw_state = intel_connector_get_hw_state;
3106
3107	intel_hdmi_add_properties(intel_hdmi, connector);
3108
3109	intel_connector_attach_encoder(intel_connector, intel_encoder);
3110	intel_hdmi->attached_connector = intel_connector;
3111
3112	if (is_hdcp_supported(dev_priv, port)) {
3113		int ret = intel_hdcp_init(intel_connector,
3114					  &intel_hdmi_hdcp_shim);
3115		if (ret)
3116			DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3117	}
3118
3119	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3120	 * 0xd.  Failure to do so will result in spurious interrupts being
3121	 * generated on the port when a cable is not attached.
3122	 */
3123	if (IS_G45(dev_priv)) {
3124		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3125		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3126	}
3127
3128	intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
3129							 port_identifier(port));
3130	if (!intel_hdmi->cec_notifier)
3131		DRM_DEBUG_KMS("CEC notifier get failed\n");
3132}
3133
3134static enum intel_hotplug_state
3135intel_hdmi_hotplug(struct intel_encoder *encoder,
3136		   struct intel_connector *connector, bool irq_received)
3137{
3138	enum intel_hotplug_state state;
3139
3140	state = intel_encoder_hotplug(encoder, connector, irq_received);
3141
3142	/*
3143	 * On many platforms the HDMI live state signal is known to be
3144	 * unreliable, so we can't use it to detect if a sink is connected or
3145	 * not. Instead we detect if it's connected based on whether we can
3146	 * read the EDID or not. That in turn has a problem during disconnect,
3147	 * since the HPD interrupt may be raised before the DDC lines get
3148	 * disconnected (due to how the required length of DDC vs. HPD
3149	 * connector pins are specified) and so we'll still be able to get a
3150	 * valid EDID. To solve this schedule another detection cycle if this
3151	 * time around we didn't detect any change in the sink's connection
3152	 * status.
3153	 */
3154	if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
3155		state = INTEL_HOTPLUG_RETRY;
3156
3157	return state;
3158}
3159
3160void intel_hdmi_init(struct drm_i915_private *dev_priv,
3161		     i915_reg_t hdmi_reg, enum port port)
3162{
3163	struct intel_digital_port *intel_dig_port;
3164	struct intel_encoder *intel_encoder;
3165	struct intel_connector *intel_connector;
3166
3167	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3168	if (!intel_dig_port)
3169		return;
3170
3171	intel_connector = intel_connector_alloc();
3172	if (!intel_connector) {
3173		kfree(intel_dig_port);
3174		return;
3175	}
3176
3177	intel_encoder = &intel_dig_port->base;
3178
3179	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3180			 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3181			 "HDMI %c", port_name(port));
3182
3183	intel_encoder->hotplug = intel_hdmi_hotplug;
3184	intel_encoder->compute_config = intel_hdmi_compute_config;
3185	if (HAS_PCH_SPLIT(dev_priv)) {
3186		intel_encoder->disable = pch_disable_hdmi;
3187		intel_encoder->post_disable = pch_post_disable_hdmi;
3188	} else {
3189		intel_encoder->disable = g4x_disable_hdmi;
3190	}
3191	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3192	intel_encoder->get_config = intel_hdmi_get_config;
3193	if (IS_CHERRYVIEW(dev_priv)) {
3194		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3195		intel_encoder->pre_enable = chv_hdmi_pre_enable;
3196		intel_encoder->enable = vlv_enable_hdmi;
3197		intel_encoder->post_disable = chv_hdmi_post_disable;
3198		intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3199	} else if (IS_VALLEYVIEW(dev_priv)) {
3200		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3201		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3202		intel_encoder->enable = vlv_enable_hdmi;
3203		intel_encoder->post_disable = vlv_hdmi_post_disable;
3204	} else {
3205		intel_encoder->pre_enable = intel_hdmi_pre_enable;
3206		if (HAS_PCH_CPT(dev_priv))
3207			intel_encoder->enable = cpt_enable_hdmi;
3208		else if (HAS_PCH_IBX(dev_priv))
3209			intel_encoder->enable = ibx_enable_hdmi;
3210		else
3211			intel_encoder->enable = g4x_enable_hdmi;
3212	}
3213
3214	intel_encoder->type = INTEL_OUTPUT_HDMI;
3215	intel_encoder->power_domain = intel_port_to_power_domain(port);
3216	intel_encoder->port = port;
3217	if (IS_CHERRYVIEW(dev_priv)) {
3218		if (port == PORT_D)
3219			intel_encoder->crtc_mask = 1 << 2;
3220		else
3221			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
3222	} else {
3223		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3224	}
3225	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3226	/*
3227	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3228	 * to work on real hardware. And since g4x can send infoframes to
3229	 * only one port anyway, nothing is lost by allowing it.
3230	 */
3231	if (IS_G4X(dev_priv))
3232		intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3233
3234	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3235	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3236	intel_dig_port->max_lanes = 4;
3237
3238	intel_infoframe_init(intel_dig_port);
3239
3240	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3241	intel_hdmi_init_connector(intel_dig_port, intel_connector);
3242}