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1/*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Madhav Chauhan <madhav.chauhan@intel.com>
25 * Jani Nikula <jani.nikula@intel.com>
26 */
27
28#include <drm/drm_atomic_helper.h>
29#include <drm/drm_mipi_dsi.h>
30
31#include "intel_atomic.h"
32#include "intel_combo_phy.h"
33#include "intel_connector.h"
34#include "intel_ddi.h"
35#include "intel_dsi.h"
36#include "intel_panel.h"
37
38static inline int header_credits_available(struct drm_i915_private *dev_priv,
39 enum transcoder dsi_trans)
40{
41 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
42 >> FREE_HEADER_CREDIT_SHIFT;
43}
44
45static inline int payload_credits_available(struct drm_i915_private *dev_priv,
46 enum transcoder dsi_trans)
47{
48 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
49 >> FREE_PLOAD_CREDIT_SHIFT;
50}
51
52static void wait_for_header_credits(struct drm_i915_private *dev_priv,
53 enum transcoder dsi_trans)
54{
55 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
56 MAX_HEADER_CREDIT, 100))
57 DRM_ERROR("DSI header credits not released\n");
58}
59
60static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
61 enum transcoder dsi_trans)
62{
63 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
64 MAX_PLOAD_CREDIT, 100))
65 DRM_ERROR("DSI payload credits not released\n");
66}
67
68static enum transcoder dsi_port_to_transcoder(enum port port)
69{
70 if (port == PORT_A)
71 return TRANSCODER_DSI_0;
72 else
73 return TRANSCODER_DSI_1;
74}
75
76static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
77{
78 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
79 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
80 struct mipi_dsi_device *dsi;
81 enum port port;
82 enum transcoder dsi_trans;
83 int ret;
84
85 /* wait for header/payload credits to be released */
86 for_each_dsi_port(port, intel_dsi->ports) {
87 dsi_trans = dsi_port_to_transcoder(port);
88 wait_for_header_credits(dev_priv, dsi_trans);
89 wait_for_payload_credits(dev_priv, dsi_trans);
90 }
91
92 /* send nop DCS command */
93 for_each_dsi_port(port, intel_dsi->ports) {
94 dsi = intel_dsi->dsi_hosts[port]->device;
95 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
96 dsi->channel = 0;
97 ret = mipi_dsi_dcs_nop(dsi);
98 if (ret < 0)
99 DRM_ERROR("error sending DCS NOP command\n");
100 }
101
102 /* wait for header credits to be released */
103 for_each_dsi_port(port, intel_dsi->ports) {
104 dsi_trans = dsi_port_to_transcoder(port);
105 wait_for_header_credits(dev_priv, dsi_trans);
106 }
107
108 /* wait for LP TX in progress bit to be cleared */
109 for_each_dsi_port(port, intel_dsi->ports) {
110 dsi_trans = dsi_port_to_transcoder(port);
111 if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
112 LPTX_IN_PROGRESS), 20))
113 DRM_ERROR("LPTX bit not cleared\n");
114 }
115}
116
117static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
118 u32 len)
119{
120 struct intel_dsi *intel_dsi = host->intel_dsi;
121 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
122 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
123 int free_credits;
124 int i, j;
125
126 for (i = 0; i < len; i += 4) {
127 u32 tmp = 0;
128
129 free_credits = payload_credits_available(dev_priv, dsi_trans);
130 if (free_credits < 1) {
131 DRM_ERROR("Payload credit not available\n");
132 return false;
133 }
134
135 for (j = 0; j < min_t(u32, len - i, 4); j++)
136 tmp |= *data++ << 8 * j;
137
138 I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
139 }
140
141 return true;
142}
143
144static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
145 struct mipi_dsi_packet pkt, bool enable_lpdt)
146{
147 struct intel_dsi *intel_dsi = host->intel_dsi;
148 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
149 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
150 u32 tmp;
151 int free_credits;
152
153 /* check if header credit available */
154 free_credits = header_credits_available(dev_priv, dsi_trans);
155 if (free_credits < 1) {
156 DRM_ERROR("send pkt header failed, not enough hdr credits\n");
157 return -1;
158 }
159
160 tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
161
162 if (pkt.payload)
163 tmp |= PAYLOAD_PRESENT;
164 else
165 tmp &= ~PAYLOAD_PRESENT;
166
167 tmp &= ~VBLANK_FENCE;
168
169 if (enable_lpdt)
170 tmp |= LP_DATA_TRANSFER;
171
172 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
173 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
174 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
175 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
176 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
177 I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
178
179 return 0;
180}
181
182static int dsi_send_pkt_payld(struct intel_dsi_host *host,
183 struct mipi_dsi_packet pkt)
184{
185 /* payload queue can accept *256 bytes*, check limit */
186 if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
187 DRM_ERROR("payload size exceeds max queue limit\n");
188 return -1;
189 }
190
191 /* load data into command payload queue */
192 if (!add_payld_to_queue(host, pkt.payload,
193 pkt.payload_length)) {
194 DRM_ERROR("adding payload to queue failed\n");
195 return -1;
196 }
197
198 return 0;
199}
200
201static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
202{
203 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
204 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
205 enum phy phy;
206 u32 tmp;
207 int lane;
208
209 for_each_dsi_phy(phy, intel_dsi->phys) {
210 /*
211 * Program voltage swing and pre-emphasis level values as per
212 * table in BSPEC under DDI buffer programing
213 */
214 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
215 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
216 tmp |= SCALING_MODE_SEL(0x2);
217 tmp |= TAP2_DISABLE | TAP3_DISABLE;
218 tmp |= RTERM_SELECT(0x6);
219 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
220
221 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
222 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
223 tmp |= SCALING_MODE_SEL(0x2);
224 tmp |= TAP2_DISABLE | TAP3_DISABLE;
225 tmp |= RTERM_SELECT(0x6);
226 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
227
228 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
229 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
230 RCOMP_SCALAR_MASK);
231 tmp |= SWING_SEL_UPPER(0x2);
232 tmp |= SWING_SEL_LOWER(0x2);
233 tmp |= RCOMP_SCALAR(0x98);
234 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
235
236 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
237 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
238 RCOMP_SCALAR_MASK);
239 tmp |= SWING_SEL_UPPER(0x2);
240 tmp |= SWING_SEL_LOWER(0x2);
241 tmp |= RCOMP_SCALAR(0x98);
242 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
243
244 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
245 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
246 CURSOR_COEFF_MASK);
247 tmp |= POST_CURSOR_1(0x0);
248 tmp |= POST_CURSOR_2(0x0);
249 tmp |= CURSOR_COEFF(0x3f);
250 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
251
252 for (lane = 0; lane <= 3; lane++) {
253 /* Bspec: must not use GRP register for write */
254 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
255 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
256 CURSOR_COEFF_MASK);
257 tmp |= POST_CURSOR_1(0x0);
258 tmp |= POST_CURSOR_2(0x0);
259 tmp |= CURSOR_COEFF(0x3f);
260 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
261 }
262 }
263}
264
265static void configure_dual_link_mode(struct intel_encoder *encoder,
266 const struct intel_crtc_state *pipe_config)
267{
268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
269 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
270 u32 dss_ctl1;
271
272 dss_ctl1 = I915_READ(DSS_CTL1);
273 dss_ctl1 |= SPLITTER_ENABLE;
274 dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
275 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
276
277 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
278 const struct drm_display_mode *adjusted_mode =
279 &pipe_config->base.adjusted_mode;
280 u32 dss_ctl2;
281 u16 hactive = adjusted_mode->crtc_hdisplay;
282 u16 dl_buffer_depth;
283
284 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
285 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
286
287 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
288 DRM_ERROR("DL buffer depth exceed max value\n");
289
290 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
291 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
292 dss_ctl2 = I915_READ(DSS_CTL2);
293 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
294 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
295 I915_WRITE(DSS_CTL2, dss_ctl2);
296 } else {
297 /* Interleave */
298 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
299 }
300
301 I915_WRITE(DSS_CTL1, dss_ctl1);
302}
303
304static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
305{
306 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
307 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
308 enum port port;
309 u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
310 u32 afe_clk_khz; /* 8X Clock */
311 u32 esc_clk_div_m;
312
313 afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
314 intel_dsi->lane_count);
315
316 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
317
318 for_each_dsi_port(port, intel_dsi->ports) {
319 I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
320 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
321 POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
322 }
323
324 for_each_dsi_port(port, intel_dsi->ports) {
325 I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
326 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
327 POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
328 }
329}
330
331static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
332 struct intel_dsi *intel_dsi)
333{
334 enum port port;
335
336 for_each_dsi_port(port, intel_dsi->ports) {
337 WARN_ON(intel_dsi->io_wakeref[port]);
338 intel_dsi->io_wakeref[port] =
339 intel_display_power_get(dev_priv,
340 port == PORT_A ?
341 POWER_DOMAIN_PORT_DDI_A_IO :
342 POWER_DOMAIN_PORT_DDI_B_IO);
343 }
344}
345
346static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
347{
348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
349 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
350 enum port port;
351 u32 tmp;
352
353 for_each_dsi_port(port, intel_dsi->ports) {
354 tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
355 tmp |= COMBO_PHY_MODE_DSI;
356 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
357 }
358
359 get_dsi_io_power_domains(dev_priv, intel_dsi);
360}
361
362static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
363{
364 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
365 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
366 enum phy phy;
367
368 for_each_dsi_phy(phy, intel_dsi->phys)
369 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
370 intel_dsi->lane_count, false);
371}
372
373static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
374{
375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
376 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
377 enum phy phy;
378 u32 tmp;
379 int lane;
380
381 /* Step 4b(i) set loadgen select for transmit and aux lanes */
382 for_each_dsi_phy(phy, intel_dsi->phys) {
383 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
384 tmp &= ~LOADGEN_SELECT;
385 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
386 for (lane = 0; lane <= 3; lane++) {
387 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
388 tmp &= ~LOADGEN_SELECT;
389 if (lane != 2)
390 tmp |= LOADGEN_SELECT;
391 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
392 }
393 }
394
395 /* Step 4b(ii) set latency optimization for transmit and aux lanes */
396 for_each_dsi_phy(phy, intel_dsi->phys) {
397 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
398 tmp &= ~FRC_LATENCY_OPTIM_MASK;
399 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
400 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
401 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
402 tmp &= ~FRC_LATENCY_OPTIM_MASK;
403 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
404 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
405
406 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
407 if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
408 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
409 tmp &= ~LATENCY_OPTIM_MASK;
410 tmp |= LATENCY_OPTIM_VAL(0);
411 I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
412
413 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
414 tmp &= ~LATENCY_OPTIM_MASK;
415 tmp |= LATENCY_OPTIM_VAL(0x1);
416 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
417 }
418 }
419
420}
421
422static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
423{
424 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
425 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
426 u32 tmp;
427 enum phy phy;
428
429 /* clear common keeper enable bit */
430 for_each_dsi_phy(phy, intel_dsi->phys) {
431 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
432 tmp &= ~COMMON_KEEPER_EN;
433 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
434 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
435 tmp &= ~COMMON_KEEPER_EN;
436 I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
437 }
438
439 /*
440 * Set SUS Clock Config bitfield to 11b
441 * Note: loadgen select program is done
442 * as part of lane phy sequence configuration
443 */
444 for_each_dsi_phy(phy, intel_dsi->phys) {
445 tmp = I915_READ(ICL_PORT_CL_DW5(phy));
446 tmp |= SUS_CLOCK_CONFIG;
447 I915_WRITE(ICL_PORT_CL_DW5(phy), tmp);
448 }
449
450 /* Clear training enable to change swing values */
451 for_each_dsi_phy(phy, intel_dsi->phys) {
452 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
453 tmp &= ~TX_TRAINING_EN;
454 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
455 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
456 tmp &= ~TX_TRAINING_EN;
457 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
458 }
459
460 /* Program swing and de-emphasis */
461 dsi_program_swing_and_deemphasis(encoder);
462
463 /* Set training enable to trigger update */
464 for_each_dsi_phy(phy, intel_dsi->phys) {
465 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
466 tmp |= TX_TRAINING_EN;
467 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
468 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
469 tmp |= TX_TRAINING_EN;
470 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
471 }
472}
473
474static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
475{
476 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
477 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
478 u32 tmp;
479 enum port port;
480
481 for_each_dsi_port(port, intel_dsi->ports) {
482 tmp = I915_READ(DDI_BUF_CTL(port));
483 tmp |= DDI_BUF_CTL_ENABLE;
484 I915_WRITE(DDI_BUF_CTL(port), tmp);
485
486 if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
487 DDI_BUF_IS_IDLE),
488 500))
489 DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
490 }
491}
492
493static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
494{
495 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
496 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
497 u32 tmp;
498 enum port port;
499 enum phy phy;
500
501 /* Program T-INIT master registers */
502 for_each_dsi_port(port, intel_dsi->ports) {
503 tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
504 tmp &= ~MASTER_INIT_TIMER_MASK;
505 tmp |= intel_dsi->init_count;
506 I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
507 }
508
509 /* Program DPHY clock lanes timings */
510 for_each_dsi_port(port, intel_dsi->ports) {
511 I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
512
513 /* shadow register inside display core */
514 I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
515 }
516
517 /* Program DPHY data lanes timings */
518 for_each_dsi_port(port, intel_dsi->ports) {
519 I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
520 intel_dsi->dphy_data_lane_reg);
521
522 /* shadow register inside display core */
523 I915_WRITE(DSI_DATA_TIMING_PARAM(port),
524 intel_dsi->dphy_data_lane_reg);
525 }
526
527 /*
528 * If DSI link operating at or below an 800 MHz,
529 * TA_SURE should be override and programmed to
530 * a value '0' inside TA_PARAM_REGISTERS otherwise
531 * leave all fields at HW default values.
532 */
533 if (IS_GEN(dev_priv, 11)) {
534 if (intel_dsi_bitrate(intel_dsi) <= 800000) {
535 for_each_dsi_port(port, intel_dsi->ports) {
536 tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
537 tmp &= ~TA_SURE_MASK;
538 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
539 I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
540
541 /* shadow register inside display core */
542 tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
543 tmp &= ~TA_SURE_MASK;
544 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
545 I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
546 }
547 }
548 }
549
550 if (IS_ELKHARTLAKE(dev_priv)) {
551 for_each_dsi_phy(phy, intel_dsi->phys) {
552 tmp = I915_READ(ICL_DPHY_CHKN(phy));
553 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
554 I915_WRITE(ICL_DPHY_CHKN(phy), tmp);
555 }
556 }
557}
558
559static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
560{
561 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
562 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
563 u32 tmp;
564 enum phy phy;
565
566 mutex_lock(&dev_priv->dpll_lock);
567 tmp = I915_READ(ICL_DPCLKA_CFGCR0);
568 for_each_dsi_phy(phy, intel_dsi->phys)
569 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
570
571 I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
572 mutex_unlock(&dev_priv->dpll_lock);
573}
574
575static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
576{
577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
578 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
579 u32 tmp;
580 enum phy phy;
581
582 mutex_lock(&dev_priv->dpll_lock);
583 tmp = I915_READ(ICL_DPCLKA_CFGCR0);
584 for_each_dsi_phy(phy, intel_dsi->phys)
585 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
586
587 I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
588 mutex_unlock(&dev_priv->dpll_lock);
589}
590
591static void gen11_dsi_map_pll(struct intel_encoder *encoder,
592 const struct intel_crtc_state *crtc_state)
593{
594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
595 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
596 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
597 enum phy phy;
598 u32 val;
599
600 mutex_lock(&dev_priv->dpll_lock);
601
602 val = I915_READ(ICL_DPCLKA_CFGCR0);
603 for_each_dsi_phy(phy, intel_dsi->phys) {
604 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
605 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
606 }
607 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
608
609 for_each_dsi_phy(phy, intel_dsi->phys) {
610 if (INTEL_GEN(dev_priv) >= 12)
611 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
612 else
613 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
614 }
615 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
616
617 POSTING_READ(ICL_DPCLKA_CFGCR0);
618
619 mutex_unlock(&dev_priv->dpll_lock);
620}
621
622static void
623gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
624 const struct intel_crtc_state *pipe_config)
625{
626 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
627 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
628 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
629 enum pipe pipe = intel_crtc->pipe;
630 u32 tmp;
631 enum port port;
632 enum transcoder dsi_trans;
633
634 for_each_dsi_port(port, intel_dsi->ports) {
635 dsi_trans = dsi_port_to_transcoder(port);
636 tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
637
638 if (intel_dsi->eotp_pkt)
639 tmp &= ~EOTP_DISABLED;
640 else
641 tmp |= EOTP_DISABLED;
642
643 /* enable link calibration if freq > 1.5Gbps */
644 if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
645 tmp &= ~LINK_CALIBRATION_MASK;
646 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
647 }
648
649 /* configure continuous clock */
650 tmp &= ~CONTINUOUS_CLK_MASK;
651 if (intel_dsi->clock_stop)
652 tmp |= CLK_ENTER_LP_AFTER_DATA;
653 else
654 tmp |= CLK_HS_CONTINUOUS;
655
656 /* configure buffer threshold limit to minimum */
657 tmp &= ~PIX_BUF_THRESHOLD_MASK;
658 tmp |= PIX_BUF_THRESHOLD_1_4;
659
660 /* set virtual channel to '0' */
661 tmp &= ~PIX_VIRT_CHAN_MASK;
662 tmp |= PIX_VIRT_CHAN(0);
663
664 /* program BGR transmission */
665 if (intel_dsi->bgr_enabled)
666 tmp |= BGR_TRANSMISSION;
667
668 /* select pixel format */
669 tmp &= ~PIX_FMT_MASK;
670 switch (intel_dsi->pixel_format) {
671 default:
672 MISSING_CASE(intel_dsi->pixel_format);
673 /* fallthrough */
674 case MIPI_DSI_FMT_RGB565:
675 tmp |= PIX_FMT_RGB565;
676 break;
677 case MIPI_DSI_FMT_RGB666_PACKED:
678 tmp |= PIX_FMT_RGB666_PACKED;
679 break;
680 case MIPI_DSI_FMT_RGB666:
681 tmp |= PIX_FMT_RGB666_LOOSE;
682 break;
683 case MIPI_DSI_FMT_RGB888:
684 tmp |= PIX_FMT_RGB888;
685 break;
686 }
687
688 if (INTEL_GEN(dev_priv) >= 12) {
689 if (is_vid_mode(intel_dsi))
690 tmp |= BLANKING_PACKET_ENABLE;
691 }
692
693 /* program DSI operation mode */
694 if (is_vid_mode(intel_dsi)) {
695 tmp &= ~OP_MODE_MASK;
696 switch (intel_dsi->video_mode_format) {
697 default:
698 MISSING_CASE(intel_dsi->video_mode_format);
699 /* fallthrough */
700 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
701 tmp |= VIDEO_MODE_SYNC_EVENT;
702 break;
703 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
704 tmp |= VIDEO_MODE_SYNC_PULSE;
705 break;
706 }
707 }
708
709 I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
710 }
711
712 /* enable port sync mode if dual link */
713 if (intel_dsi->dual_link) {
714 for_each_dsi_port(port, intel_dsi->ports) {
715 dsi_trans = dsi_port_to_transcoder(port);
716 tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
717 tmp |= PORT_SYNC_MODE_ENABLE;
718 I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
719 }
720
721 /* configure stream splitting */
722 configure_dual_link_mode(encoder, pipe_config);
723 }
724
725 for_each_dsi_port(port, intel_dsi->ports) {
726 dsi_trans = dsi_port_to_transcoder(port);
727
728 /* select data lane width */
729 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
730 tmp &= ~DDI_PORT_WIDTH_MASK;
731 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
732
733 /* select input pipe */
734 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
735 switch (pipe) {
736 default:
737 MISSING_CASE(pipe);
738 /* fallthrough */
739 case PIPE_A:
740 tmp |= TRANS_DDI_EDP_INPUT_A_ON;
741 break;
742 case PIPE_B:
743 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
744 break;
745 case PIPE_C:
746 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
747 break;
748 }
749
750 /* enable DDI buffer */
751 tmp |= TRANS_DDI_FUNC_ENABLE;
752 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
753 }
754
755 /* wait for link ready */
756 for_each_dsi_port(port, intel_dsi->ports) {
757 dsi_trans = dsi_port_to_transcoder(port);
758 if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
759 LINK_READY), 2500))
760 DRM_ERROR("DSI link not ready\n");
761 }
762}
763
764static void
765gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
766 const struct intel_crtc_state *pipe_config)
767{
768 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
769 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
770 const struct drm_display_mode *adjusted_mode =
771 &pipe_config->base.adjusted_mode;
772 enum port port;
773 enum transcoder dsi_trans;
774 /* horizontal timings */
775 u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
776 u16 hback_porch;
777 /* vertical timings */
778 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
779
780 hactive = adjusted_mode->crtc_hdisplay;
781 htotal = adjusted_mode->crtc_htotal;
782 hsync_start = adjusted_mode->crtc_hsync_start;
783 hsync_end = adjusted_mode->crtc_hsync_end;
784 hsync_size = hsync_end - hsync_start;
785 hback_porch = (adjusted_mode->crtc_htotal -
786 adjusted_mode->crtc_hsync_end);
787 vactive = adjusted_mode->crtc_vdisplay;
788 vtotal = adjusted_mode->crtc_vtotal;
789 vsync_start = adjusted_mode->crtc_vsync_start;
790 vsync_end = adjusted_mode->crtc_vsync_end;
791 vsync_shift = hsync_start - htotal / 2;
792
793 if (intel_dsi->dual_link) {
794 hactive /= 2;
795 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
796 hactive += intel_dsi->pixel_overlap;
797 htotal /= 2;
798 }
799
800 /* minimum hactive as per bspec: 256 pixels */
801 if (adjusted_mode->crtc_hdisplay < 256)
802 DRM_ERROR("hactive is less then 256 pixels\n");
803
804 /* if RGB666 format, then hactive must be multiple of 4 pixels */
805 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
806 DRM_ERROR("hactive pixels are not multiple of 4\n");
807
808 /* program TRANS_HTOTAL register */
809 for_each_dsi_port(port, intel_dsi->ports) {
810 dsi_trans = dsi_port_to_transcoder(port);
811 I915_WRITE(HTOTAL(dsi_trans),
812 (hactive - 1) | ((htotal - 1) << 16));
813 }
814
815 /* TRANS_HSYNC register to be programmed only for video mode */
816 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
817 if (intel_dsi->video_mode_format ==
818 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
819 /* BSPEC: hsync size should be atleast 16 pixels */
820 if (hsync_size < 16)
821 DRM_ERROR("hsync size < 16 pixels\n");
822 }
823
824 if (hback_porch < 16)
825 DRM_ERROR("hback porch < 16 pixels\n");
826
827 if (intel_dsi->dual_link) {
828 hsync_start /= 2;
829 hsync_end /= 2;
830 }
831
832 for_each_dsi_port(port, intel_dsi->ports) {
833 dsi_trans = dsi_port_to_transcoder(port);
834 I915_WRITE(HSYNC(dsi_trans),
835 (hsync_start - 1) | ((hsync_end - 1) << 16));
836 }
837 }
838
839 /* program TRANS_VTOTAL register */
840 for_each_dsi_port(port, intel_dsi->ports) {
841 dsi_trans = dsi_port_to_transcoder(port);
842 /*
843 * FIXME: Programing this by assuming progressive mode, since
844 * non-interlaced info from VBT is not saved inside
845 * struct drm_display_mode.
846 * For interlace mode: program required pixel minus 2
847 */
848 I915_WRITE(VTOTAL(dsi_trans),
849 (vactive - 1) | ((vtotal - 1) << 16));
850 }
851
852 if (vsync_end < vsync_start || vsync_end > vtotal)
853 DRM_ERROR("Invalid vsync_end value\n");
854
855 if (vsync_start < vactive)
856 DRM_ERROR("vsync_start less than vactive\n");
857
858 /* program TRANS_VSYNC register */
859 for_each_dsi_port(port, intel_dsi->ports) {
860 dsi_trans = dsi_port_to_transcoder(port);
861 I915_WRITE(VSYNC(dsi_trans),
862 (vsync_start - 1) | ((vsync_end - 1) << 16));
863 }
864
865 /*
866 * FIXME: It has to be programmed only for interlaced
867 * modes. Put the check condition here once interlaced
868 * info available as described above.
869 * program TRANS_VSYNCSHIFT register
870 */
871 for_each_dsi_port(port, intel_dsi->ports) {
872 dsi_trans = dsi_port_to_transcoder(port);
873 I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
874 }
875
876 /* program TRANS_VBLANK register, should be same as vtotal programmed */
877 if (INTEL_GEN(dev_priv) >= 12) {
878 for_each_dsi_port(port, intel_dsi->ports) {
879 dsi_trans = dsi_port_to_transcoder(port);
880 I915_WRITE(VBLANK(dsi_trans),
881 (vactive - 1) | ((vtotal - 1) << 16));
882 }
883 }
884}
885
886static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
887{
888 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
889 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
890 enum port port;
891 enum transcoder dsi_trans;
892 u32 tmp;
893
894 for_each_dsi_port(port, intel_dsi->ports) {
895 dsi_trans = dsi_port_to_transcoder(port);
896 tmp = I915_READ(PIPECONF(dsi_trans));
897 tmp |= PIPECONF_ENABLE;
898 I915_WRITE(PIPECONF(dsi_trans), tmp);
899
900 /* wait for transcoder to be enabled */
901 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
902 I965_PIPECONF_ACTIVE, 10))
903 DRM_ERROR("DSI transcoder not enabled\n");
904 }
905}
906
907static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
908{
909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
910 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
911 enum port port;
912 enum transcoder dsi_trans;
913 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
914
915 /*
916 * escape clock count calculation:
917 * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
918 * UI (nsec) = (10^6)/Bitrate
919 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
920 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
921 */
922 divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
923 mul = 8 * 1000000;
924 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
925 divisor);
926 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
927 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
928
929 for_each_dsi_port(port, intel_dsi->ports) {
930 dsi_trans = dsi_port_to_transcoder(port);
931
932 /* program hst_tx_timeout */
933 tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
934 tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
935 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
936 I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
937
938 /* FIXME: DSI_CALIB_TO */
939
940 /* program lp_rx_host timeout */
941 tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
942 tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
943 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
944 I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
945
946 /* FIXME: DSI_PWAIT_TO */
947
948 /* program turn around timeout */
949 tmp = I915_READ(DSI_TA_TO(dsi_trans));
950 tmp &= ~TA_TIMEOUT_VALUE_MASK;
951 tmp |= TA_TIMEOUT_VALUE(ta_timeout);
952 I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
953 }
954}
955
956static void
957gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
958 const struct intel_crtc_state *pipe_config)
959{
960 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
961
962 /* step 4a: power up all lanes of the DDI used by DSI */
963 gen11_dsi_power_up_lanes(encoder);
964
965 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
966 gen11_dsi_config_phy_lanes_sequence(encoder);
967
968 /* step 4c: configure voltage swing and skew */
969 gen11_dsi_voltage_swing_program_seq(encoder);
970
971 /* enable DDI buffer */
972 gen11_dsi_enable_ddi_buffer(encoder);
973
974 /* setup D-PHY timings */
975 gen11_dsi_setup_dphy_timings(encoder);
976
977 /* step 4h: setup DSI protocol timeouts */
978 gen11_dsi_setup_timeouts(encoder);
979
980 /* Step (4h, 4i, 4j, 4k): Configure transcoder */
981 gen11_dsi_configure_transcoder(encoder, pipe_config);
982
983 /* Step 4l: Gate DDI clocks */
984 if (IS_GEN(dev_priv, 11))
985 gen11_dsi_gate_clocks(encoder);
986}
987
988static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
989{
990 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
991 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
992 struct mipi_dsi_device *dsi;
993 enum port port;
994 enum transcoder dsi_trans;
995 u32 tmp;
996 int ret;
997
998 /* set maximum return packet size */
999 for_each_dsi_port(port, intel_dsi->ports) {
1000 dsi_trans = dsi_port_to_transcoder(port);
1001
1002 /*
1003 * FIXME: This uses the number of DW's currently in the payload
1004 * receive queue. This is probably not what we want here.
1005 */
1006 tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
1007 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1008 /* multiply "Number Rx Payload DW" by 4 to get max value */
1009 tmp = tmp * 4;
1010 dsi = intel_dsi->dsi_hosts[port]->device;
1011 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1012 if (ret < 0)
1013 DRM_ERROR("error setting max return pkt size%d\n", tmp);
1014 }
1015
1016 /* panel power on related mipi dsi vbt sequences */
1017 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1018 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
1019 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1020 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1021 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1022
1023 /* ensure all panel commands dispatched before enabling transcoder */
1024 wait_for_cmds_dispatched_to_panel(encoder);
1025}
1026
1027static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
1028 const struct intel_crtc_state *pipe_config,
1029 const struct drm_connector_state *conn_state)
1030{
1031 /* step2: enable IO power */
1032 gen11_dsi_enable_io_power(encoder);
1033
1034 /* step3: enable DSI PLL */
1035 gen11_dsi_program_esc_clk_div(encoder);
1036}
1037
1038static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
1039 const struct intel_crtc_state *pipe_config,
1040 const struct drm_connector_state *conn_state)
1041{
1042 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1043
1044 /* step3b */
1045 gen11_dsi_map_pll(encoder, pipe_config);
1046
1047 /* step4: enable DSI port and DPHY */
1048 gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1049
1050 /* step5: program and powerup panel */
1051 gen11_dsi_powerup_panel(encoder);
1052
1053 /* step6c: configure transcoder timings */
1054 gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1055
1056 /* step6d: enable dsi transcoder */
1057 gen11_dsi_enable_transcoder(encoder);
1058
1059 /* step7: enable backlight */
1060 intel_panel_enable_backlight(pipe_config, conn_state);
1061 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1062}
1063
1064static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1065{
1066 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1067 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1068 enum port port;
1069 enum transcoder dsi_trans;
1070 u32 tmp;
1071
1072 for_each_dsi_port(port, intel_dsi->ports) {
1073 dsi_trans = dsi_port_to_transcoder(port);
1074
1075 /* disable transcoder */
1076 tmp = I915_READ(PIPECONF(dsi_trans));
1077 tmp &= ~PIPECONF_ENABLE;
1078 I915_WRITE(PIPECONF(dsi_trans), tmp);
1079
1080 /* wait for transcoder to be disabled */
1081 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
1082 I965_PIPECONF_ACTIVE, 50))
1083 DRM_ERROR("DSI trancoder not disabled\n");
1084 }
1085}
1086
1087static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1088{
1089 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1090
1091 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1092 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1093 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1094
1095 /* ensure cmds dispatched to panel */
1096 wait_for_cmds_dispatched_to_panel(encoder);
1097}
1098
1099static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1100{
1101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1102 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1103 enum port port;
1104 enum transcoder dsi_trans;
1105 u32 tmp;
1106
1107 /* put dsi link in ULPS */
1108 for_each_dsi_port(port, intel_dsi->ports) {
1109 dsi_trans = dsi_port_to_transcoder(port);
1110 tmp = I915_READ(DSI_LP_MSG(dsi_trans));
1111 tmp |= LINK_ENTER_ULPS;
1112 tmp &= ~LINK_ULPS_TYPE_LP11;
1113 I915_WRITE(DSI_LP_MSG(dsi_trans), tmp);
1114
1115 if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) &
1116 LINK_IN_ULPS),
1117 10))
1118 DRM_ERROR("DSI link not in ULPS\n");
1119 }
1120
1121 /* disable ddi function */
1122 for_each_dsi_port(port, intel_dsi->ports) {
1123 dsi_trans = dsi_port_to_transcoder(port);
1124 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
1125 tmp &= ~TRANS_DDI_FUNC_ENABLE;
1126 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
1127 }
1128
1129 /* disable port sync mode if dual link */
1130 if (intel_dsi->dual_link) {
1131 for_each_dsi_port(port, intel_dsi->ports) {
1132 dsi_trans = dsi_port_to_transcoder(port);
1133 tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
1134 tmp &= ~PORT_SYNC_MODE_ENABLE;
1135 I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
1136 }
1137 }
1138}
1139
1140static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1141{
1142 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1143 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1144 u32 tmp;
1145 enum port port;
1146
1147 gen11_dsi_ungate_clocks(encoder);
1148 for_each_dsi_port(port, intel_dsi->ports) {
1149 tmp = I915_READ(DDI_BUF_CTL(port));
1150 tmp &= ~DDI_BUF_CTL_ENABLE;
1151 I915_WRITE(DDI_BUF_CTL(port), tmp);
1152
1153 if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) &
1154 DDI_BUF_IS_IDLE),
1155 8))
1156 DRM_ERROR("DDI port:%c buffer not idle\n",
1157 port_name(port));
1158 }
1159 gen11_dsi_gate_clocks(encoder);
1160}
1161
1162static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1163{
1164 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1165 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1166 enum port port;
1167 u32 tmp;
1168
1169 for_each_dsi_port(port, intel_dsi->ports) {
1170 intel_wakeref_t wakeref;
1171
1172 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1173 intel_display_power_put(dev_priv,
1174 port == PORT_A ?
1175 POWER_DOMAIN_PORT_DDI_A_IO :
1176 POWER_DOMAIN_PORT_DDI_B_IO,
1177 wakeref);
1178 }
1179
1180 /* set mode to DDI */
1181 for_each_dsi_port(port, intel_dsi->ports) {
1182 tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
1183 tmp &= ~COMBO_PHY_MODE_DSI;
1184 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
1185 }
1186}
1187
1188static void gen11_dsi_disable(struct intel_encoder *encoder,
1189 const struct intel_crtc_state *old_crtc_state,
1190 const struct drm_connector_state *old_conn_state)
1191{
1192 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1193
1194 /* step1: turn off backlight */
1195 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1196 intel_panel_disable_backlight(old_conn_state);
1197
1198 /* step2d,e: disable transcoder and wait */
1199 gen11_dsi_disable_transcoder(encoder);
1200
1201 /* step2f,g: powerdown panel */
1202 gen11_dsi_powerdown_panel(encoder);
1203
1204 /* step2h,i,j: deconfig trancoder */
1205 gen11_dsi_deconfigure_trancoder(encoder);
1206
1207 /* step3: disable port */
1208 gen11_dsi_disable_port(encoder);
1209
1210 /* step4: disable IO power */
1211 gen11_dsi_disable_io_power(encoder);
1212}
1213
1214static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1215 struct intel_crtc_state *pipe_config)
1216{
1217 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1218 struct drm_display_mode *adjusted_mode =
1219 &pipe_config->base.adjusted_mode;
1220
1221 if (intel_dsi->dual_link) {
1222 adjusted_mode->crtc_hdisplay *= 2;
1223 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1224 adjusted_mode->crtc_hdisplay -=
1225 intel_dsi->pixel_overlap;
1226 adjusted_mode->crtc_htotal *= 2;
1227 }
1228 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1229 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1230
1231 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1232 if (intel_dsi->dual_link) {
1233 adjusted_mode->crtc_hsync_start *= 2;
1234 adjusted_mode->crtc_hsync_end *= 2;
1235 }
1236 }
1237 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1238 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1239}
1240
1241static void gen11_dsi_get_config(struct intel_encoder *encoder,
1242 struct intel_crtc_state *pipe_config)
1243{
1244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1245 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1246 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1247
1248 /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
1249 pipe_config->port_clock =
1250 cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
1251
1252 pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
1253 if (intel_dsi->dual_link)
1254 pipe_config->base.adjusted_mode.crtc_clock *= 2;
1255
1256 gen11_dsi_get_timings(encoder, pipe_config);
1257 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1258 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1259}
1260
1261static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1262 struct intel_crtc_state *pipe_config,
1263 struct drm_connector_state *conn_state)
1264{
1265 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1266 base);
1267 struct intel_connector *intel_connector = intel_dsi->attached_connector;
1268 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1269 const struct drm_display_mode *fixed_mode =
1270 intel_connector->panel.fixed_mode;
1271 struct drm_display_mode *adjusted_mode =
1272 &pipe_config->base.adjusted_mode;
1273
1274 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1275 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
1276 intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
1277
1278 adjusted_mode->flags = 0;
1279
1280 /* Dual link goes to trancoder DSI'0' */
1281 if (intel_dsi->ports == BIT(PORT_B))
1282 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1283 else
1284 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1285
1286 pipe_config->clock_set = true;
1287 pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
1288
1289 return 0;
1290}
1291
1292static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1293 struct intel_crtc_state *crtc_state)
1294{
1295 get_dsi_io_power_domains(to_i915(encoder->base.dev),
1296 enc_to_intel_dsi(&encoder->base));
1297}
1298
1299static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1300 enum pipe *pipe)
1301{
1302 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1303 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1304 enum transcoder dsi_trans;
1305 intel_wakeref_t wakeref;
1306 enum port port;
1307 bool ret = false;
1308 u32 tmp;
1309
1310 wakeref = intel_display_power_get_if_enabled(dev_priv,
1311 encoder->power_domain);
1312 if (!wakeref)
1313 return false;
1314
1315 for_each_dsi_port(port, intel_dsi->ports) {
1316 dsi_trans = dsi_port_to_transcoder(port);
1317 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
1318 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1319 case TRANS_DDI_EDP_INPUT_A_ON:
1320 *pipe = PIPE_A;
1321 break;
1322 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1323 *pipe = PIPE_B;
1324 break;
1325 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1326 *pipe = PIPE_C;
1327 break;
1328 default:
1329 DRM_ERROR("Invalid PIPE input\n");
1330 goto out;
1331 }
1332
1333 tmp = I915_READ(PIPECONF(dsi_trans));
1334 ret = tmp & PIPECONF_ENABLE;
1335 }
1336out:
1337 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1338 return ret;
1339}
1340
1341static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1342{
1343 intel_encoder_destroy(encoder);
1344}
1345
1346static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1347 .destroy = gen11_dsi_encoder_destroy,
1348};
1349
1350static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1351 .late_register = intel_connector_register,
1352 .early_unregister = intel_connector_unregister,
1353 .destroy = intel_connector_destroy,
1354 .fill_modes = drm_helper_probe_single_connector_modes,
1355 .atomic_get_property = intel_digital_connector_atomic_get_property,
1356 .atomic_set_property = intel_digital_connector_atomic_set_property,
1357 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1358 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1359};
1360
1361static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1362 .get_modes = intel_dsi_get_modes,
1363 .mode_valid = intel_dsi_mode_valid,
1364 .atomic_check = intel_digital_connector_atomic_check,
1365};
1366
1367static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1368 struct mipi_dsi_device *dsi)
1369{
1370 return 0;
1371}
1372
1373static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1374 struct mipi_dsi_device *dsi)
1375{
1376 return 0;
1377}
1378
1379static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1380 const struct mipi_dsi_msg *msg)
1381{
1382 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1383 struct mipi_dsi_packet dsi_pkt;
1384 ssize_t ret;
1385 bool enable_lpdt = false;
1386
1387 ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1388 if (ret < 0)
1389 return ret;
1390
1391 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1392 enable_lpdt = true;
1393
1394 /* send packet header */
1395 ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
1396 if (ret < 0)
1397 return ret;
1398
1399 /* only long packet contains payload */
1400 if (mipi_dsi_packet_format_is_long(msg->type)) {
1401 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
1402 if (ret < 0)
1403 return ret;
1404 }
1405
1406 //TODO: add payload receive code if needed
1407
1408 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1409
1410 return ret;
1411}
1412
1413static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1414 .attach = gen11_dsi_host_attach,
1415 .detach = gen11_dsi_host_detach,
1416 .transfer = gen11_dsi_host_transfer,
1417};
1418
1419#define ICL_PREPARE_CNT_MAX 0x7
1420#define ICL_CLK_ZERO_CNT_MAX 0xf
1421#define ICL_TRAIL_CNT_MAX 0x7
1422#define ICL_TCLK_PRE_CNT_MAX 0x3
1423#define ICL_TCLK_POST_CNT_MAX 0x7
1424#define ICL_HS_ZERO_CNT_MAX 0xf
1425#define ICL_EXIT_ZERO_CNT_MAX 0x7
1426
1427static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1428{
1429 struct drm_device *dev = intel_dsi->base.base.dev;
1430 struct drm_i915_private *dev_priv = to_i915(dev);
1431 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1432 u32 tlpx_ns;
1433 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1434 u32 ths_prepare_ns, tclk_trail_ns;
1435 u32 hs_zero_cnt;
1436 u32 tclk_pre_cnt, tclk_post_cnt;
1437
1438 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1439
1440 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1441 ths_prepare_ns = max(mipi_config->ths_prepare,
1442 mipi_config->tclk_prepare);
1443
1444 /*
1445 * prepare cnt in escape clocks
1446 * this field represents a hexadecimal value with a precision
1447 * of 1.2 – i.e. the most significant bit is the integer
1448 * and the least significant 2 bits are fraction bits.
1449 * so, the field can represent a range of 0.25 to 1.75
1450 */
1451 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1452 if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1453 DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
1454 prepare_cnt = ICL_PREPARE_CNT_MAX;
1455 }
1456
1457 /* clk zero count in escape clocks */
1458 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1459 ths_prepare_ns, tlpx_ns);
1460 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1461 DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1462 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1463 }
1464
1465 /* trail cnt in escape clocks*/
1466 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1467 if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1468 DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
1469 trail_cnt = ICL_TRAIL_CNT_MAX;
1470 }
1471
1472 /* tclk pre count in escape clocks */
1473 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1474 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1475 DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1476 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1477 }
1478
1479 /* tclk post count in escape clocks */
1480 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1481 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1482 DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
1483 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1484 }
1485
1486 /* hs zero cnt in escape clocks */
1487 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1488 ths_prepare_ns, tlpx_ns);
1489 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1490 DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
1491 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1492 }
1493
1494 /* hs exit zero cnt in escape clocks */
1495 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1496 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1497 DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
1498 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1499 }
1500
1501 /* clock lane dphy timings */
1502 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1503 CLK_PREPARE(prepare_cnt) |
1504 CLK_ZERO_OVERRIDE |
1505 CLK_ZERO(clk_zero_cnt) |
1506 CLK_PRE_OVERRIDE |
1507 CLK_PRE(tclk_pre_cnt) |
1508 CLK_POST_OVERRIDE |
1509 CLK_POST(tclk_post_cnt) |
1510 CLK_TRAIL_OVERRIDE |
1511 CLK_TRAIL(trail_cnt));
1512
1513 /* data lanes dphy timings */
1514 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1515 HS_PREPARE(prepare_cnt) |
1516 HS_ZERO_OVERRIDE |
1517 HS_ZERO(hs_zero_cnt) |
1518 HS_TRAIL_OVERRIDE |
1519 HS_TRAIL(trail_cnt) |
1520 HS_EXIT_OVERRIDE |
1521 HS_EXIT(exit_zero_cnt));
1522
1523 intel_dsi_log_params(intel_dsi);
1524}
1525
1526static void icl_dsi_add_properties(struct intel_connector *connector)
1527{
1528 u32 allowed_scalers;
1529
1530 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
1531 BIT(DRM_MODE_SCALE_FULLSCREEN) |
1532 BIT(DRM_MODE_SCALE_CENTER);
1533
1534 drm_connector_attach_scaling_mode_property(&connector->base,
1535 allowed_scalers);
1536
1537 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1538
1539 connector->base.display_info.panel_orientation =
1540 intel_dsi_get_panel_orientation(connector);
1541 drm_connector_init_panel_orientation_property(&connector->base,
1542 connector->panel.fixed_mode->hdisplay,
1543 connector->panel.fixed_mode->vdisplay);
1544}
1545
1546void icl_dsi_init(struct drm_i915_private *dev_priv)
1547{
1548 struct drm_device *dev = &dev_priv->drm;
1549 struct intel_dsi *intel_dsi;
1550 struct intel_encoder *encoder;
1551 struct intel_connector *intel_connector;
1552 struct drm_connector *connector;
1553 struct drm_display_mode *fixed_mode;
1554 enum port port;
1555
1556 if (!intel_bios_is_dsi_present(dev_priv, &port))
1557 return;
1558
1559 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1560 if (!intel_dsi)
1561 return;
1562
1563 intel_connector = intel_connector_alloc();
1564 if (!intel_connector) {
1565 kfree(intel_dsi);
1566 return;
1567 }
1568
1569 encoder = &intel_dsi->base;
1570 intel_dsi->attached_connector = intel_connector;
1571 connector = &intel_connector->base;
1572
1573 /* register DSI encoder with DRM subsystem */
1574 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
1575 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1576
1577 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1578 encoder->pre_enable = gen11_dsi_pre_enable;
1579 encoder->disable = gen11_dsi_disable;
1580 encoder->port = port;
1581 encoder->get_config = gen11_dsi_get_config;
1582 encoder->update_pipe = intel_panel_update_backlight;
1583 encoder->compute_config = gen11_dsi_compute_config;
1584 encoder->get_hw_state = gen11_dsi_get_hw_state;
1585 encoder->type = INTEL_OUTPUT_DSI;
1586 encoder->cloneable = 0;
1587 encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1588 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1589 encoder->get_power_domains = gen11_dsi_get_power_domains;
1590
1591 /* register DSI connector with DRM subsystem */
1592 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
1593 DRM_MODE_CONNECTOR_DSI);
1594 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1595 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1596 connector->interlace_allowed = false;
1597 connector->doublescan_allowed = false;
1598 intel_connector->get_hw_state = intel_connector_get_hw_state;
1599
1600 /* attach connector to encoder */
1601 intel_connector_attach_encoder(intel_connector, encoder);
1602
1603 mutex_lock(&dev->mode_config.mutex);
1604 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1605 mutex_unlock(&dev->mode_config.mutex);
1606
1607 if (!fixed_mode) {
1608 DRM_ERROR("DSI fixed mode info missing\n");
1609 goto err;
1610 }
1611
1612 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1613 intel_panel_setup_backlight(connector, INVALID_PIPE);
1614
1615 if (dev_priv->vbt.dsi.config->dual_link)
1616 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1617 else
1618 intel_dsi->ports = BIT(port);
1619
1620 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1621 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1622
1623 for_each_dsi_port(port, intel_dsi->ports) {
1624 struct intel_dsi_host *host;
1625
1626 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
1627 if (!host)
1628 goto err;
1629
1630 intel_dsi->dsi_hosts[port] = host;
1631 }
1632
1633 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1634 DRM_DEBUG_KMS("no device found\n");
1635 goto err;
1636 }
1637
1638 icl_dphy_param_init(intel_dsi);
1639
1640 icl_dsi_add_properties(intel_connector);
1641 return;
1642
1643err:
1644 drm_encoder_cleanup(&encoder->base);
1645 kfree(intel_dsi);
1646 kfree(intel_connector);
1647}