Loading...
Note: File does not exist in v5.4.
1
2/*
3 * Copyright 2012 Red Hat
4 *
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
8 *
9 * Authors: Matthew Garrett
10 * Dave Airlie
11 *
12 * Portions of this code derived from cirrusfb.c:
13 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
14 *
15 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
16 */
17#include <drm/drmP.h>
18#include <drm/drm_crtc_helper.h>
19#include <drm/drm_plane_helper.h>
20
21#include <video/cirrus.h>
22
23#include "cirrus_drv.h"
24
25#define CIRRUS_LUT_SIZE 256
26
27#define PALETTE_INDEX 0x8
28#define PALETTE_DATA 0x9
29
30/*
31 * This file contains setup code for the CRTC.
32 */
33
34static void cirrus_crtc_load_lut(struct drm_crtc *crtc)
35{
36 struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
37 struct drm_device *dev = crtc->dev;
38 struct cirrus_device *cdev = dev->dev_private;
39 int i;
40
41 if (!crtc->enabled)
42 return;
43
44 for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
45 /* VGA registers */
46 WREG8(PALETTE_INDEX, i);
47 WREG8(PALETTE_DATA, cirrus_crtc->lut_r[i]);
48 WREG8(PALETTE_DATA, cirrus_crtc->lut_g[i]);
49 WREG8(PALETTE_DATA, cirrus_crtc->lut_b[i]);
50 }
51}
52
53/*
54 * The DRM core requires DPMS functions, but they make little sense in our
55 * case and so are just stubs
56 */
57
58static void cirrus_crtc_dpms(struct drm_crtc *crtc, int mode)
59{
60 struct drm_device *dev = crtc->dev;
61 struct cirrus_device *cdev = dev->dev_private;
62 u8 sr01, gr0e;
63
64 switch (mode) {
65 case DRM_MODE_DPMS_ON:
66 sr01 = 0x00;
67 gr0e = 0x00;
68 break;
69 case DRM_MODE_DPMS_STANDBY:
70 sr01 = 0x20;
71 gr0e = 0x02;
72 break;
73 case DRM_MODE_DPMS_SUSPEND:
74 sr01 = 0x20;
75 gr0e = 0x04;
76 break;
77 case DRM_MODE_DPMS_OFF:
78 sr01 = 0x20;
79 gr0e = 0x06;
80 break;
81 default:
82 return;
83 }
84
85 WREG8(SEQ_INDEX, 0x1);
86 sr01 |= RREG8(SEQ_DATA) & ~0x20;
87 WREG_SEQ(0x1, sr01);
88
89 WREG8(GFX_INDEX, 0xe);
90 gr0e |= RREG8(GFX_DATA) & ~0x06;
91 WREG_GFX(0xe, gr0e);
92}
93
94static void cirrus_set_start_address(struct drm_crtc *crtc, unsigned offset)
95{
96 struct cirrus_device *cdev = crtc->dev->dev_private;
97 u32 addr;
98 u8 tmp;
99
100 addr = offset >> 2;
101 WREG_CRT(0x0c, (u8)((addr >> 8) & 0xff));
102 WREG_CRT(0x0d, (u8)(addr & 0xff));
103
104 WREG8(CRT_INDEX, 0x1b);
105 tmp = RREG8(CRT_DATA);
106 tmp &= 0xf2;
107 tmp |= (addr >> 16) & 0x01;
108 tmp |= (addr >> 15) & 0x0c;
109 WREG_CRT(0x1b, tmp);
110 WREG8(CRT_INDEX, 0x1d);
111 tmp = RREG8(CRT_DATA);
112 tmp &= 0x7f;
113 tmp |= (addr >> 12) & 0x80;
114 WREG_CRT(0x1d, tmp);
115}
116
117/* cirrus is different - we will force move buffers out of VRAM */
118static int cirrus_crtc_do_set_base(struct drm_crtc *crtc,
119 struct drm_framebuffer *fb,
120 int x, int y, int atomic)
121{
122 struct cirrus_device *cdev = crtc->dev->dev_private;
123 struct drm_gem_object *obj;
124 struct cirrus_framebuffer *cirrus_fb;
125 struct cirrus_bo *bo;
126 int ret;
127 u64 gpu_addr;
128
129 /* push the previous fb to system ram */
130 if (!atomic && fb) {
131 cirrus_fb = to_cirrus_framebuffer(fb);
132 obj = cirrus_fb->obj;
133 bo = gem_to_cirrus_bo(obj);
134 ret = cirrus_bo_reserve(bo, false);
135 if (ret)
136 return ret;
137 cirrus_bo_push_sysram(bo);
138 cirrus_bo_unreserve(bo);
139 }
140
141 cirrus_fb = to_cirrus_framebuffer(crtc->primary->fb);
142 obj = cirrus_fb->obj;
143 bo = gem_to_cirrus_bo(obj);
144
145 ret = cirrus_bo_reserve(bo, false);
146 if (ret)
147 return ret;
148
149 ret = cirrus_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
150 if (ret) {
151 cirrus_bo_unreserve(bo);
152 return ret;
153 }
154
155 if (&cdev->mode_info.gfbdev->gfb == cirrus_fb) {
156 /* if pushing console in kmap it */
157 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
158 if (ret)
159 DRM_ERROR("failed to kmap fbcon\n");
160 }
161 cirrus_bo_unreserve(bo);
162
163 cirrus_set_start_address(crtc, (u32)gpu_addr);
164 return 0;
165}
166
167static int cirrus_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
168 struct drm_framebuffer *old_fb)
169{
170 return cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
171}
172
173/*
174 * The meat of this driver. The core passes us a mode and we have to program
175 * it. The modesetting here is the bare minimum required to satisfy the qemu
176 * emulation of this hardware, and running this against a real device is
177 * likely to result in an inadequately programmed mode. We've already had
178 * the opportunity to modify the mode, so whatever we receive here should
179 * be something that can be correctly programmed and displayed
180 */
181static int cirrus_crtc_mode_set(struct drm_crtc *crtc,
182 struct drm_display_mode *mode,
183 struct drm_display_mode *adjusted_mode,
184 int x, int y, struct drm_framebuffer *old_fb)
185{
186 struct drm_device *dev = crtc->dev;
187 struct cirrus_device *cdev = dev->dev_private;
188 int hsyncstart, hsyncend, htotal, hdispend;
189 int vtotal, vdispend;
190 int tmp;
191 int sr07 = 0, hdr = 0;
192
193 htotal = mode->htotal / 8;
194 hsyncend = mode->hsync_end / 8;
195 hsyncstart = mode->hsync_start / 8;
196 hdispend = mode->hdisplay / 8;
197
198 vtotal = mode->vtotal;
199 vdispend = mode->vdisplay;
200
201 vdispend -= 1;
202 vtotal -= 2;
203
204 htotal -= 5;
205 hdispend -= 1;
206 hsyncstart += 1;
207 hsyncend += 1;
208
209 WREG_CRT(VGA_CRTC_V_SYNC_END, 0x20);
210 WREG_CRT(VGA_CRTC_H_TOTAL, htotal);
211 WREG_CRT(VGA_CRTC_H_DISP, hdispend);
212 WREG_CRT(VGA_CRTC_H_SYNC_START, hsyncstart);
213 WREG_CRT(VGA_CRTC_H_SYNC_END, hsyncend);
214 WREG_CRT(VGA_CRTC_V_TOTAL, vtotal & 0xff);
215 WREG_CRT(VGA_CRTC_V_DISP_END, vdispend & 0xff);
216
217 tmp = 0x40;
218 if ((vdispend + 1) & 512)
219 tmp |= 0x20;
220 WREG_CRT(VGA_CRTC_MAX_SCAN, tmp);
221
222 /*
223 * Overflow bits for values that don't fit in the standard registers
224 */
225 tmp = 16;
226 if (vtotal & 256)
227 tmp |= 1;
228 if (vdispend & 256)
229 tmp |= 2;
230 if ((vdispend + 1) & 256)
231 tmp |= 8;
232 if (vtotal & 512)
233 tmp |= 32;
234 if (vdispend & 512)
235 tmp |= 64;
236 WREG_CRT(VGA_CRTC_OVERFLOW, tmp);
237
238 tmp = 0;
239
240 /* More overflow bits */
241
242 if ((htotal + 5) & 64)
243 tmp |= 16;
244 if ((htotal + 5) & 128)
245 tmp |= 32;
246 if (vtotal & 256)
247 tmp |= 64;
248 if (vtotal & 512)
249 tmp |= 128;
250
251 WREG_CRT(CL_CRT1A, tmp);
252
253 /* Disable Hercules/CGA compatibility */
254 WREG_CRT(VGA_CRTC_MODE, 0x03);
255
256 WREG8(SEQ_INDEX, 0x7);
257 sr07 = RREG8(SEQ_DATA);
258 sr07 &= 0xe0;
259 hdr = 0;
260 switch (crtc->primary->fb->bits_per_pixel) {
261 case 8:
262 sr07 |= 0x11;
263 break;
264 case 16:
265 sr07 |= 0x17;
266 hdr = 0xc1;
267 break;
268 case 24:
269 sr07 |= 0x15;
270 hdr = 0xc5;
271 break;
272 case 32:
273 sr07 |= 0x19;
274 hdr = 0xc5;
275 break;
276 default:
277 return -1;
278 }
279
280 WREG_SEQ(0x7, sr07);
281
282 /* Program the pitch */
283 tmp = crtc->primary->fb->pitches[0] / 8;
284 WREG_CRT(VGA_CRTC_OFFSET, tmp);
285
286 /* Enable extended blanking and pitch bits, and enable full memory */
287 tmp = 0x22;
288 tmp |= (crtc->primary->fb->pitches[0] >> 7) & 0x10;
289 tmp |= (crtc->primary->fb->pitches[0] >> 6) & 0x40;
290 WREG_CRT(0x1b, tmp);
291
292 /* Enable high-colour modes */
293 WREG_GFX(VGA_GFX_MODE, 0x40);
294
295 /* And set graphics mode */
296 WREG_GFX(VGA_GFX_MISC, 0x01);
297
298 WREG_HDR(hdr);
299 cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
300
301 /* Unblank (needed on S3 resume, vgabios doesn't do it then) */
302 outb(0x20, 0x3c0);
303 return 0;
304}
305
306/*
307 * This is called before a mode is programmed. A typical use might be to
308 * enable DPMS during the programming to avoid seeing intermediate stages,
309 * but that's not relevant to us
310 */
311static void cirrus_crtc_prepare(struct drm_crtc *crtc)
312{
313}
314
315/*
316 * This is called after a mode is programmed. It should reverse anything done
317 * by the prepare function
318 */
319static void cirrus_crtc_commit(struct drm_crtc *crtc)
320{
321}
322
323/*
324 * The core can pass us a set of gamma values to program. We actually only
325 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
326 * but it's a requirement that we provide the function
327 */
328static void cirrus_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
329 u16 *blue, uint32_t start, uint32_t size)
330{
331 struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
332 int i;
333
334 if (size != CIRRUS_LUT_SIZE)
335 return;
336
337 for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
338 cirrus_crtc->lut_r[i] = red[i];
339 cirrus_crtc->lut_g[i] = green[i];
340 cirrus_crtc->lut_b[i] = blue[i];
341 }
342 cirrus_crtc_load_lut(crtc);
343}
344
345/* Simple cleanup function */
346static void cirrus_crtc_destroy(struct drm_crtc *crtc)
347{
348 struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
349
350 drm_crtc_cleanup(crtc);
351 kfree(cirrus_crtc);
352}
353
354/* These provide the minimum set of functions required to handle a CRTC */
355static const struct drm_crtc_funcs cirrus_crtc_funcs = {
356 .gamma_set = cirrus_crtc_gamma_set,
357 .set_config = drm_crtc_helper_set_config,
358 .destroy = cirrus_crtc_destroy,
359};
360
361static const struct drm_crtc_helper_funcs cirrus_helper_funcs = {
362 .dpms = cirrus_crtc_dpms,
363 .mode_set = cirrus_crtc_mode_set,
364 .mode_set_base = cirrus_crtc_mode_set_base,
365 .prepare = cirrus_crtc_prepare,
366 .commit = cirrus_crtc_commit,
367 .load_lut = cirrus_crtc_load_lut,
368};
369
370/* CRTC setup */
371static void cirrus_crtc_init(struct drm_device *dev)
372{
373 struct cirrus_device *cdev = dev->dev_private;
374 struct cirrus_crtc *cirrus_crtc;
375 int i;
376
377 cirrus_crtc = kzalloc(sizeof(struct cirrus_crtc) +
378 (CIRRUSFB_CONN_LIMIT * sizeof(struct drm_connector *)),
379 GFP_KERNEL);
380
381 if (cirrus_crtc == NULL)
382 return;
383
384 drm_crtc_init(dev, &cirrus_crtc->base, &cirrus_crtc_funcs);
385
386 drm_mode_crtc_set_gamma_size(&cirrus_crtc->base, CIRRUS_LUT_SIZE);
387 cdev->mode_info.crtc = cirrus_crtc;
388
389 for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
390 cirrus_crtc->lut_r[i] = i;
391 cirrus_crtc->lut_g[i] = i;
392 cirrus_crtc->lut_b[i] = i;
393 }
394
395 drm_crtc_helper_add(&cirrus_crtc->base, &cirrus_helper_funcs);
396}
397
398/** Sets the color ramps on behalf of fbcon */
399void cirrus_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
400 u16 blue, int regno)
401{
402 struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
403
404 cirrus_crtc->lut_r[regno] = red;
405 cirrus_crtc->lut_g[regno] = green;
406 cirrus_crtc->lut_b[regno] = blue;
407}
408
409/** Gets the color ramps on behalf of fbcon */
410void cirrus_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
411 u16 *blue, int regno)
412{
413 struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
414
415 *red = cirrus_crtc->lut_r[regno];
416 *green = cirrus_crtc->lut_g[regno];
417 *blue = cirrus_crtc->lut_b[regno];
418}
419
420static void cirrus_encoder_mode_set(struct drm_encoder *encoder,
421 struct drm_display_mode *mode,
422 struct drm_display_mode *adjusted_mode)
423{
424}
425
426static void cirrus_encoder_dpms(struct drm_encoder *encoder, int state)
427{
428 return;
429}
430
431static void cirrus_encoder_prepare(struct drm_encoder *encoder)
432{
433}
434
435static void cirrus_encoder_commit(struct drm_encoder *encoder)
436{
437}
438
439static void cirrus_encoder_destroy(struct drm_encoder *encoder)
440{
441 struct cirrus_encoder *cirrus_encoder = to_cirrus_encoder(encoder);
442 drm_encoder_cleanup(encoder);
443 kfree(cirrus_encoder);
444}
445
446static const struct drm_encoder_helper_funcs cirrus_encoder_helper_funcs = {
447 .dpms = cirrus_encoder_dpms,
448 .mode_set = cirrus_encoder_mode_set,
449 .prepare = cirrus_encoder_prepare,
450 .commit = cirrus_encoder_commit,
451};
452
453static const struct drm_encoder_funcs cirrus_encoder_encoder_funcs = {
454 .destroy = cirrus_encoder_destroy,
455};
456
457static struct drm_encoder *cirrus_encoder_init(struct drm_device *dev)
458{
459 struct drm_encoder *encoder;
460 struct cirrus_encoder *cirrus_encoder;
461
462 cirrus_encoder = kzalloc(sizeof(struct cirrus_encoder), GFP_KERNEL);
463 if (!cirrus_encoder)
464 return NULL;
465
466 encoder = &cirrus_encoder->base;
467 encoder->possible_crtcs = 0x1;
468
469 drm_encoder_init(dev, encoder, &cirrus_encoder_encoder_funcs,
470 DRM_MODE_ENCODER_DAC, NULL);
471 drm_encoder_helper_add(encoder, &cirrus_encoder_helper_funcs);
472
473 return encoder;
474}
475
476
477static int cirrus_vga_get_modes(struct drm_connector *connector)
478{
479 int count;
480
481 /* Just add a static list of modes */
482 if (cirrus_bpp <= 24) {
483 count = drm_add_modes_noedid(connector, 1280, 1024);
484 drm_set_preferred_mode(connector, 1024, 768);
485 } else {
486 count = drm_add_modes_noedid(connector, 800, 600);
487 drm_set_preferred_mode(connector, 800, 600);
488 }
489 return count;
490}
491
492static struct drm_encoder *cirrus_connector_best_encoder(struct drm_connector
493 *connector)
494{
495 int enc_id = connector->encoder_ids[0];
496 /* pick the encoder ids */
497 if (enc_id)
498 return drm_encoder_find(connector->dev, enc_id);
499 return NULL;
500}
501
502static enum drm_connector_status cirrus_vga_detect(struct drm_connector
503 *connector, bool force)
504{
505 return connector_status_connected;
506}
507
508static void cirrus_connector_destroy(struct drm_connector *connector)
509{
510 drm_connector_cleanup(connector);
511 kfree(connector);
512}
513
514static const struct drm_connector_helper_funcs cirrus_vga_connector_helper_funcs = {
515 .get_modes = cirrus_vga_get_modes,
516 .best_encoder = cirrus_connector_best_encoder,
517};
518
519static const struct drm_connector_funcs cirrus_vga_connector_funcs = {
520 .dpms = drm_helper_connector_dpms,
521 .detect = cirrus_vga_detect,
522 .fill_modes = drm_helper_probe_single_connector_modes,
523 .destroy = cirrus_connector_destroy,
524};
525
526static struct drm_connector *cirrus_vga_init(struct drm_device *dev)
527{
528 struct drm_connector *connector;
529 struct cirrus_connector *cirrus_connector;
530
531 cirrus_connector = kzalloc(sizeof(struct cirrus_connector), GFP_KERNEL);
532 if (!cirrus_connector)
533 return NULL;
534
535 connector = &cirrus_connector->base;
536
537 drm_connector_init(dev, connector,
538 &cirrus_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
539
540 drm_connector_helper_add(connector, &cirrus_vga_connector_helper_funcs);
541
542 drm_connector_register(connector);
543 return connector;
544}
545
546
547int cirrus_modeset_init(struct cirrus_device *cdev)
548{
549 struct drm_encoder *encoder;
550 struct drm_connector *connector;
551 int ret;
552
553 drm_mode_config_init(cdev->dev);
554 cdev->mode_info.mode_config_initialized = true;
555
556 cdev->dev->mode_config.max_width = CIRRUS_MAX_FB_WIDTH;
557 cdev->dev->mode_config.max_height = CIRRUS_MAX_FB_HEIGHT;
558
559 cdev->dev->mode_config.fb_base = cdev->mc.vram_base;
560 cdev->dev->mode_config.preferred_depth = 24;
561 /* don't prefer a shadow on virt GPU */
562 cdev->dev->mode_config.prefer_shadow = 0;
563
564 cirrus_crtc_init(cdev->dev);
565
566 encoder = cirrus_encoder_init(cdev->dev);
567 if (!encoder) {
568 DRM_ERROR("cirrus_encoder_init failed\n");
569 return -1;
570 }
571
572 connector = cirrus_vga_init(cdev->dev);
573 if (!connector) {
574 DRM_ERROR("cirrus_vga_init failed\n");
575 return -1;
576 }
577
578 drm_mode_connector_attach_encoder(connector, encoder);
579
580 ret = cirrus_fbdev_init(cdev);
581 if (ret) {
582 DRM_ERROR("cirrus_fbdev_init failed\n");
583 return ret;
584 }
585
586 return 0;
587}
588
589void cirrus_modeset_fini(struct cirrus_device *cdev)
590{
591 cirrus_fbdev_fini(cdev);
592
593 if (cdev->mode_info.mode_config_initialized) {
594 drm_mode_config_cleanup(cdev->dev);
595 cdev->mode_info.mode_config_initialized = false;
596 }
597}