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1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
19#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
26#include <linux/scatterlist.h>
27#include <linux/of.h>
28#include <linux/of_dma.h>
29#include <linux/err.h>
30#include <linux/pm_runtime.h>
31
32#include "dmaengine.h"
33#define PL330_MAX_CHAN 8
34#define PL330_MAX_IRQS 32
35#define PL330_MAX_PERI 32
36#define PL330_MAX_BURST 16
37
38#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
39
40enum pl330_cachectrl {
41 CCTRL0, /* Noncacheable and nonbufferable */
42 CCTRL1, /* Bufferable only */
43 CCTRL2, /* Cacheable, but do not allocate */
44 CCTRL3, /* Cacheable and bufferable, but do not allocate */
45 INVALID1, /* AWCACHE = 0x1000 */
46 INVALID2,
47 CCTRL6, /* Cacheable write-through, allocate on writes only */
48 CCTRL7, /* Cacheable write-back, allocate on writes only */
49};
50
51enum pl330_byteswap {
52 SWAP_NO,
53 SWAP_2,
54 SWAP_4,
55 SWAP_8,
56 SWAP_16,
57};
58
59/* Register and Bit field Definitions */
60#define DS 0x0
61#define DS_ST_STOP 0x0
62#define DS_ST_EXEC 0x1
63#define DS_ST_CMISS 0x2
64#define DS_ST_UPDTPC 0x3
65#define DS_ST_WFE 0x4
66#define DS_ST_ATBRR 0x5
67#define DS_ST_QBUSY 0x6
68#define DS_ST_WFP 0x7
69#define DS_ST_KILL 0x8
70#define DS_ST_CMPLT 0x9
71#define DS_ST_FLTCMP 0xe
72#define DS_ST_FAULT 0xf
73
74#define DPC 0x4
75#define INTEN 0x20
76#define ES 0x24
77#define INTSTATUS 0x28
78#define INTCLR 0x2c
79#define FSM 0x30
80#define FSC 0x34
81#define FTM 0x38
82
83#define _FTC 0x40
84#define FTC(n) (_FTC + (n)*0x4)
85
86#define _CS 0x100
87#define CS(n) (_CS + (n)*0x8)
88#define CS_CNS (1 << 21)
89
90#define _CPC 0x104
91#define CPC(n) (_CPC + (n)*0x8)
92
93#define _SA 0x400
94#define SA(n) (_SA + (n)*0x20)
95
96#define _DA 0x404
97#define DA(n) (_DA + (n)*0x20)
98
99#define _CC 0x408
100#define CC(n) (_CC + (n)*0x20)
101
102#define CC_SRCINC (1 << 0)
103#define CC_DSTINC (1 << 14)
104#define CC_SRCPRI (1 << 8)
105#define CC_DSTPRI (1 << 22)
106#define CC_SRCNS (1 << 9)
107#define CC_DSTNS (1 << 23)
108#define CC_SRCIA (1 << 10)
109#define CC_DSTIA (1 << 24)
110#define CC_SRCBRSTLEN_SHFT 4
111#define CC_DSTBRSTLEN_SHFT 18
112#define CC_SRCBRSTSIZE_SHFT 1
113#define CC_DSTBRSTSIZE_SHFT 15
114#define CC_SRCCCTRL_SHFT 11
115#define CC_SRCCCTRL_MASK 0x7
116#define CC_DSTCCTRL_SHFT 25
117#define CC_DRCCCTRL_MASK 0x7
118#define CC_SWAP_SHFT 28
119
120#define _LC0 0x40c
121#define LC0(n) (_LC0 + (n)*0x20)
122
123#define _LC1 0x410
124#define LC1(n) (_LC1 + (n)*0x20)
125
126#define DBGSTATUS 0xd00
127#define DBG_BUSY (1 << 0)
128
129#define DBGCMD 0xd04
130#define DBGINST0 0xd08
131#define DBGINST1 0xd0c
132
133#define CR0 0xe00
134#define CR1 0xe04
135#define CR2 0xe08
136#define CR3 0xe0c
137#define CR4 0xe10
138#define CRD 0xe14
139
140#define PERIPH_ID 0xfe0
141#define PERIPH_REV_SHIFT 20
142#define PERIPH_REV_MASK 0xf
143#define PERIPH_REV_R0P0 0
144#define PERIPH_REV_R1P0 1
145#define PERIPH_REV_R1P1 2
146
147#define CR0_PERIPH_REQ_SET (1 << 0)
148#define CR0_BOOT_EN_SET (1 << 1)
149#define CR0_BOOT_MAN_NS (1 << 2)
150#define CR0_NUM_CHANS_SHIFT 4
151#define CR0_NUM_CHANS_MASK 0x7
152#define CR0_NUM_PERIPH_SHIFT 12
153#define CR0_NUM_PERIPH_MASK 0x1f
154#define CR0_NUM_EVENTS_SHIFT 17
155#define CR0_NUM_EVENTS_MASK 0x1f
156
157#define CR1_ICACHE_LEN_SHIFT 0
158#define CR1_ICACHE_LEN_MASK 0x7
159#define CR1_NUM_ICACHELINES_SHIFT 4
160#define CR1_NUM_ICACHELINES_MASK 0xf
161
162#define CRD_DATA_WIDTH_SHIFT 0
163#define CRD_DATA_WIDTH_MASK 0x7
164#define CRD_WR_CAP_SHIFT 4
165#define CRD_WR_CAP_MASK 0x7
166#define CRD_WR_Q_DEP_SHIFT 8
167#define CRD_WR_Q_DEP_MASK 0xf
168#define CRD_RD_CAP_SHIFT 12
169#define CRD_RD_CAP_MASK 0x7
170#define CRD_RD_Q_DEP_SHIFT 16
171#define CRD_RD_Q_DEP_MASK 0xf
172#define CRD_DATA_BUFF_SHIFT 20
173#define CRD_DATA_BUFF_MASK 0x3ff
174
175#define PART 0x330
176#define DESIGNER 0x41
177#define REVISION 0x0
178#define INTEG_CFG 0x0
179#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
180
181#define PL330_STATE_STOPPED (1 << 0)
182#define PL330_STATE_EXECUTING (1 << 1)
183#define PL330_STATE_WFE (1 << 2)
184#define PL330_STATE_FAULTING (1 << 3)
185#define PL330_STATE_COMPLETING (1 << 4)
186#define PL330_STATE_WFP (1 << 5)
187#define PL330_STATE_KILLING (1 << 6)
188#define PL330_STATE_FAULT_COMPLETING (1 << 7)
189#define PL330_STATE_CACHEMISS (1 << 8)
190#define PL330_STATE_UPDTPC (1 << 9)
191#define PL330_STATE_ATBARRIER (1 << 10)
192#define PL330_STATE_QUEUEBUSY (1 << 11)
193#define PL330_STATE_INVALID (1 << 15)
194
195#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
196 | PL330_STATE_WFE | PL330_STATE_FAULTING)
197
198#define CMD_DMAADDH 0x54
199#define CMD_DMAEND 0x00
200#define CMD_DMAFLUSHP 0x35
201#define CMD_DMAGO 0xa0
202#define CMD_DMALD 0x04
203#define CMD_DMALDP 0x25
204#define CMD_DMALP 0x20
205#define CMD_DMALPEND 0x28
206#define CMD_DMAKILL 0x01
207#define CMD_DMAMOV 0xbc
208#define CMD_DMANOP 0x18
209#define CMD_DMARMB 0x12
210#define CMD_DMASEV 0x34
211#define CMD_DMAST 0x08
212#define CMD_DMASTP 0x29
213#define CMD_DMASTZ 0x0c
214#define CMD_DMAWFE 0x36
215#define CMD_DMAWFP 0x30
216#define CMD_DMAWMB 0x13
217
218#define SZ_DMAADDH 3
219#define SZ_DMAEND 1
220#define SZ_DMAFLUSHP 2
221#define SZ_DMALD 1
222#define SZ_DMALDP 2
223#define SZ_DMALP 2
224#define SZ_DMALPEND 2
225#define SZ_DMAKILL 1
226#define SZ_DMAMOV 6
227#define SZ_DMANOP 1
228#define SZ_DMARMB 1
229#define SZ_DMASEV 2
230#define SZ_DMAST 1
231#define SZ_DMASTP 2
232#define SZ_DMASTZ 1
233#define SZ_DMAWFE 2
234#define SZ_DMAWFP 2
235#define SZ_DMAWMB 1
236#define SZ_DMAGO 6
237
238#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
239#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
240
241#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
242#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
243
244/*
245 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
246 * at 1byte/burst for P<->M and M<->M respectively.
247 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
248 * should be enough for P<->M and M<->M respectively.
249 */
250#define MCODE_BUFF_PER_REQ 256
251
252/* Use this _only_ to wait on transient states */
253#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254
255#ifdef PL330_DEBUG_MCGEN
256static unsigned cmd_line;
257#define PL330_DBGCMD_DUMP(off, x...) do { \
258 printk("%x:", cmd_line); \
259 printk(x); \
260 cmd_line += off; \
261 } while (0)
262#define PL330_DBGMC_START(addr) (cmd_line = addr)
263#else
264#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
265#define PL330_DBGMC_START(addr) do {} while (0)
266#endif
267
268/* The number of default descriptors */
269
270#define NR_DEFAULT_DESC 16
271
272/* Delay for runtime PM autosuspend, ms */
273#define PL330_AUTOSUSPEND_DELAY 20
274
275/* Populated by the PL330 core driver for DMA API driver's info */
276struct pl330_config {
277 u32 periph_id;
278#define DMAC_MODE_NS (1 << 0)
279 unsigned int mode;
280 unsigned int data_bus_width:10; /* In number of bits */
281 unsigned int data_buf_dep:11;
282 unsigned int num_chan:4;
283 unsigned int num_peri:6;
284 u32 peri_ns;
285 unsigned int num_events:6;
286 u32 irq_ns;
287};
288
289/**
290 * Request Configuration.
291 * The PL330 core does not modify this and uses the last
292 * working configuration if the request doesn't provide any.
293 *
294 * The Client may want to provide this info only for the
295 * first request and a request with new settings.
296 */
297struct pl330_reqcfg {
298 /* Address Incrementing */
299 unsigned dst_inc:1;
300 unsigned src_inc:1;
301
302 /*
303 * For now, the SRC & DST protection levels
304 * and burst size/length are assumed same.
305 */
306 bool nonsecure;
307 bool privileged;
308 bool insnaccess;
309 unsigned brst_len:5;
310 unsigned brst_size:3; /* in power of 2 */
311
312 enum pl330_cachectrl dcctl;
313 enum pl330_cachectrl scctl;
314 enum pl330_byteswap swap;
315 struct pl330_config *pcfg;
316};
317
318/*
319 * One cycle of DMAC operation.
320 * There may be more than one xfer in a request.
321 */
322struct pl330_xfer {
323 u32 src_addr;
324 u32 dst_addr;
325 /* Size to xfer */
326 u32 bytes;
327};
328
329/* The xfer callbacks are made with one of these arguments. */
330enum pl330_op_err {
331 /* The all xfers in the request were success. */
332 PL330_ERR_NONE,
333 /* If req aborted due to global error. */
334 PL330_ERR_ABORT,
335 /* If req failed due to problem with Channel. */
336 PL330_ERR_FAIL,
337};
338
339enum dmamov_dst {
340 SAR = 0,
341 CCR,
342 DAR,
343};
344
345enum pl330_dst {
346 SRC = 0,
347 DST,
348};
349
350enum pl330_cond {
351 SINGLE,
352 BURST,
353 ALWAYS,
354};
355
356struct dma_pl330_desc;
357
358struct _pl330_req {
359 u32 mc_bus;
360 void *mc_cpu;
361 struct dma_pl330_desc *desc;
362};
363
364/* ToBeDone for tasklet */
365struct _pl330_tbd {
366 bool reset_dmac;
367 bool reset_mngr;
368 u8 reset_chan;
369};
370
371/* A DMAC Thread */
372struct pl330_thread {
373 u8 id;
374 int ev;
375 /* If the channel is not yet acquired by any client */
376 bool free;
377 /* Parent DMAC */
378 struct pl330_dmac *dmac;
379 /* Only two at a time */
380 struct _pl330_req req[2];
381 /* Index of the last enqueued request */
382 unsigned lstenq;
383 /* Index of the last submitted request or -1 if the DMA is stopped */
384 int req_running;
385};
386
387enum pl330_dmac_state {
388 UNINIT,
389 INIT,
390 DYING,
391};
392
393enum desc_status {
394 /* In the DMAC pool */
395 FREE,
396 /*
397 * Allocated to some channel during prep_xxx
398 * Also may be sitting on the work_list.
399 */
400 PREP,
401 /*
402 * Sitting on the work_list and already submitted
403 * to the PL330 core. Not more than two descriptors
404 * of a channel can be BUSY at any time.
405 */
406 BUSY,
407 /*
408 * Sitting on the channel work_list but xfer done
409 * by PL330 core
410 */
411 DONE,
412};
413
414struct dma_pl330_chan {
415 /* Schedule desc completion */
416 struct tasklet_struct task;
417
418 /* DMA-Engine Channel */
419 struct dma_chan chan;
420
421 /* List of submitted descriptors */
422 struct list_head submitted_list;
423 /* List of issued descriptors */
424 struct list_head work_list;
425 /* List of completed descriptors */
426 struct list_head completed_list;
427
428 /* Pointer to the DMAC that manages this channel,
429 * NULL if the channel is available to be acquired.
430 * As the parent, this DMAC also provides descriptors
431 * to the channel.
432 */
433 struct pl330_dmac *dmac;
434
435 /* To protect channel manipulation */
436 spinlock_t lock;
437
438 /*
439 * Hardware channel thread of PL330 DMAC. NULL if the channel is
440 * available.
441 */
442 struct pl330_thread *thread;
443
444 /* For D-to-M and M-to-D channels */
445 int burst_sz; /* the peripheral fifo width */
446 int burst_len; /* the number of burst */
447 dma_addr_t fifo_addr;
448
449 /* for cyclic capability */
450 bool cyclic;
451};
452
453struct pl330_dmac {
454 /* DMA-Engine Device */
455 struct dma_device ddma;
456
457 /* Holds info about sg limitations */
458 struct device_dma_parameters dma_parms;
459
460 /* Pool of descriptors available for the DMAC's channels */
461 struct list_head desc_pool;
462 /* To protect desc_pool manipulation */
463 spinlock_t pool_lock;
464
465 /* Size of MicroCode buffers for each channel. */
466 unsigned mcbufsz;
467 /* ioremap'ed address of PL330 registers. */
468 void __iomem *base;
469 /* Populated by the PL330 core driver during pl330_add */
470 struct pl330_config pcfg;
471
472 spinlock_t lock;
473 /* Maximum possible events/irqs */
474 int events[32];
475 /* BUS address of MicroCode buffer */
476 dma_addr_t mcode_bus;
477 /* CPU address of MicroCode buffer */
478 void *mcode_cpu;
479 /* List of all Channel threads */
480 struct pl330_thread *channels;
481 /* Pointer to the MANAGER thread */
482 struct pl330_thread *manager;
483 /* To handle bad news in interrupt */
484 struct tasklet_struct tasks;
485 struct _pl330_tbd dmac_tbd;
486 /* State of DMAC operation */
487 enum pl330_dmac_state state;
488 /* Holds list of reqs with due callbacks */
489 struct list_head req_done;
490
491 /* Peripheral channels connected to this DMAC */
492 unsigned int num_peripherals;
493 struct dma_pl330_chan *peripherals; /* keep at end */
494 int quirks;
495};
496
497static struct pl330_of_quirks {
498 char *quirk;
499 int id;
500} of_quirks[] = {
501 {
502 .quirk = "arm,pl330-broken-no-flushp",
503 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
504 }
505};
506
507struct dma_pl330_desc {
508 /* To attach to a queue as child */
509 struct list_head node;
510
511 /* Descriptor for the DMA Engine API */
512 struct dma_async_tx_descriptor txd;
513
514 /* Xfer for PL330 core */
515 struct pl330_xfer px;
516
517 struct pl330_reqcfg rqcfg;
518
519 enum desc_status status;
520
521 int bytes_requested;
522 bool last;
523
524 /* The channel which currently holds this desc */
525 struct dma_pl330_chan *pchan;
526
527 enum dma_transfer_direction rqtype;
528 /* Index of peripheral for the xfer. */
529 unsigned peri:5;
530 /* Hook to attach to DMAC's list of reqs with due callback */
531 struct list_head rqd;
532};
533
534struct _xfer_spec {
535 u32 ccr;
536 struct dma_pl330_desc *desc;
537};
538
539static inline bool _queue_empty(struct pl330_thread *thrd)
540{
541 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
542}
543
544static inline bool _queue_full(struct pl330_thread *thrd)
545{
546 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
547}
548
549static inline bool is_manager(struct pl330_thread *thrd)
550{
551 return thrd->dmac->manager == thrd;
552}
553
554/* If manager of the thread is in Non-Secure mode */
555static inline bool _manager_ns(struct pl330_thread *thrd)
556{
557 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
558}
559
560static inline u32 get_revision(u32 periph_id)
561{
562 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
563}
564
565static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
566 enum pl330_dst da, u16 val)
567{
568 if (dry_run)
569 return SZ_DMAADDH;
570
571 buf[0] = CMD_DMAADDH;
572 buf[0] |= (da << 1);
573 *((__le16 *)&buf[1]) = cpu_to_le16(val);
574
575 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
576 da == 1 ? "DA" : "SA", val);
577
578 return SZ_DMAADDH;
579}
580
581static inline u32 _emit_END(unsigned dry_run, u8 buf[])
582{
583 if (dry_run)
584 return SZ_DMAEND;
585
586 buf[0] = CMD_DMAEND;
587
588 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
589
590 return SZ_DMAEND;
591}
592
593static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
594{
595 if (dry_run)
596 return SZ_DMAFLUSHP;
597
598 buf[0] = CMD_DMAFLUSHP;
599
600 peri &= 0x1f;
601 peri <<= 3;
602 buf[1] = peri;
603
604 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
605
606 return SZ_DMAFLUSHP;
607}
608
609static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
610{
611 if (dry_run)
612 return SZ_DMALD;
613
614 buf[0] = CMD_DMALD;
615
616 if (cond == SINGLE)
617 buf[0] |= (0 << 1) | (1 << 0);
618 else if (cond == BURST)
619 buf[0] |= (1 << 1) | (1 << 0);
620
621 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
622 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
623
624 return SZ_DMALD;
625}
626
627static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
628 enum pl330_cond cond, u8 peri)
629{
630 if (dry_run)
631 return SZ_DMALDP;
632
633 buf[0] = CMD_DMALDP;
634
635 if (cond == BURST)
636 buf[0] |= (1 << 1);
637
638 peri &= 0x1f;
639 peri <<= 3;
640 buf[1] = peri;
641
642 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
643 cond == SINGLE ? 'S' : 'B', peri >> 3);
644
645 return SZ_DMALDP;
646}
647
648static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
649 unsigned loop, u8 cnt)
650{
651 if (dry_run)
652 return SZ_DMALP;
653
654 buf[0] = CMD_DMALP;
655
656 if (loop)
657 buf[0] |= (1 << 1);
658
659 cnt--; /* DMAC increments by 1 internally */
660 buf[1] = cnt;
661
662 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
663
664 return SZ_DMALP;
665}
666
667struct _arg_LPEND {
668 enum pl330_cond cond;
669 bool forever;
670 unsigned loop;
671 u8 bjump;
672};
673
674static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
675 const struct _arg_LPEND *arg)
676{
677 enum pl330_cond cond = arg->cond;
678 bool forever = arg->forever;
679 unsigned loop = arg->loop;
680 u8 bjump = arg->bjump;
681
682 if (dry_run)
683 return SZ_DMALPEND;
684
685 buf[0] = CMD_DMALPEND;
686
687 if (loop)
688 buf[0] |= (1 << 2);
689
690 if (!forever)
691 buf[0] |= (1 << 4);
692
693 if (cond == SINGLE)
694 buf[0] |= (0 << 1) | (1 << 0);
695 else if (cond == BURST)
696 buf[0] |= (1 << 1) | (1 << 0);
697
698 buf[1] = bjump;
699
700 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
701 forever ? "FE" : "END",
702 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
703 loop ? '1' : '0',
704 bjump);
705
706 return SZ_DMALPEND;
707}
708
709static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
710{
711 if (dry_run)
712 return SZ_DMAKILL;
713
714 buf[0] = CMD_DMAKILL;
715
716 return SZ_DMAKILL;
717}
718
719static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
720 enum dmamov_dst dst, u32 val)
721{
722 if (dry_run)
723 return SZ_DMAMOV;
724
725 buf[0] = CMD_DMAMOV;
726 buf[1] = dst;
727 *((__le32 *)&buf[2]) = cpu_to_le32(val);
728
729 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
730 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
731
732 return SZ_DMAMOV;
733}
734
735static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
736{
737 if (dry_run)
738 return SZ_DMANOP;
739
740 buf[0] = CMD_DMANOP;
741
742 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
743
744 return SZ_DMANOP;
745}
746
747static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
748{
749 if (dry_run)
750 return SZ_DMARMB;
751
752 buf[0] = CMD_DMARMB;
753
754 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
755
756 return SZ_DMARMB;
757}
758
759static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
760{
761 if (dry_run)
762 return SZ_DMASEV;
763
764 buf[0] = CMD_DMASEV;
765
766 ev &= 0x1f;
767 ev <<= 3;
768 buf[1] = ev;
769
770 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
771
772 return SZ_DMASEV;
773}
774
775static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
776{
777 if (dry_run)
778 return SZ_DMAST;
779
780 buf[0] = CMD_DMAST;
781
782 if (cond == SINGLE)
783 buf[0] |= (0 << 1) | (1 << 0);
784 else if (cond == BURST)
785 buf[0] |= (1 << 1) | (1 << 0);
786
787 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
788 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
789
790 return SZ_DMAST;
791}
792
793static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
794 enum pl330_cond cond, u8 peri)
795{
796 if (dry_run)
797 return SZ_DMASTP;
798
799 buf[0] = CMD_DMASTP;
800
801 if (cond == BURST)
802 buf[0] |= (1 << 1);
803
804 peri &= 0x1f;
805 peri <<= 3;
806 buf[1] = peri;
807
808 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
809 cond == SINGLE ? 'S' : 'B', peri >> 3);
810
811 return SZ_DMASTP;
812}
813
814static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
815{
816 if (dry_run)
817 return SZ_DMASTZ;
818
819 buf[0] = CMD_DMASTZ;
820
821 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
822
823 return SZ_DMASTZ;
824}
825
826static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
827 unsigned invalidate)
828{
829 if (dry_run)
830 return SZ_DMAWFE;
831
832 buf[0] = CMD_DMAWFE;
833
834 ev &= 0x1f;
835 ev <<= 3;
836 buf[1] = ev;
837
838 if (invalidate)
839 buf[1] |= (1 << 1);
840
841 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
842 ev >> 3, invalidate ? ", I" : "");
843
844 return SZ_DMAWFE;
845}
846
847static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
848 enum pl330_cond cond, u8 peri)
849{
850 if (dry_run)
851 return SZ_DMAWFP;
852
853 buf[0] = CMD_DMAWFP;
854
855 if (cond == SINGLE)
856 buf[0] |= (0 << 1) | (0 << 0);
857 else if (cond == BURST)
858 buf[0] |= (1 << 1) | (0 << 0);
859 else
860 buf[0] |= (0 << 1) | (1 << 0);
861
862 peri &= 0x1f;
863 peri <<= 3;
864 buf[1] = peri;
865
866 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
867 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
868
869 return SZ_DMAWFP;
870}
871
872static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
873{
874 if (dry_run)
875 return SZ_DMAWMB;
876
877 buf[0] = CMD_DMAWMB;
878
879 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
880
881 return SZ_DMAWMB;
882}
883
884struct _arg_GO {
885 u8 chan;
886 u32 addr;
887 unsigned ns;
888};
889
890static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
891 const struct _arg_GO *arg)
892{
893 u8 chan = arg->chan;
894 u32 addr = arg->addr;
895 unsigned ns = arg->ns;
896
897 if (dry_run)
898 return SZ_DMAGO;
899
900 buf[0] = CMD_DMAGO;
901 buf[0] |= (ns << 1);
902
903 buf[1] = chan & 0x7;
904
905 *((__le32 *)&buf[2]) = cpu_to_le32(addr);
906
907 return SZ_DMAGO;
908}
909
910#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
911
912/* Returns Time-Out */
913static bool _until_dmac_idle(struct pl330_thread *thrd)
914{
915 void __iomem *regs = thrd->dmac->base;
916 unsigned long loops = msecs_to_loops(5);
917
918 do {
919 /* Until Manager is Idle */
920 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
921 break;
922
923 cpu_relax();
924 } while (--loops);
925
926 if (!loops)
927 return true;
928
929 return false;
930}
931
932static inline void _execute_DBGINSN(struct pl330_thread *thrd,
933 u8 insn[], bool as_manager)
934{
935 void __iomem *regs = thrd->dmac->base;
936 u32 val;
937
938 val = (insn[0] << 16) | (insn[1] << 24);
939 if (!as_manager) {
940 val |= (1 << 0);
941 val |= (thrd->id << 8); /* Channel Number */
942 }
943 writel(val, regs + DBGINST0);
944
945 val = le32_to_cpu(*((__le32 *)&insn[2]));
946 writel(val, regs + DBGINST1);
947
948 /* If timed out due to halted state-machine */
949 if (_until_dmac_idle(thrd)) {
950 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
951 return;
952 }
953
954 /* Get going */
955 writel(0, regs + DBGCMD);
956}
957
958static inline u32 _state(struct pl330_thread *thrd)
959{
960 void __iomem *regs = thrd->dmac->base;
961 u32 val;
962
963 if (is_manager(thrd))
964 val = readl(regs + DS) & 0xf;
965 else
966 val = readl(regs + CS(thrd->id)) & 0xf;
967
968 switch (val) {
969 case DS_ST_STOP:
970 return PL330_STATE_STOPPED;
971 case DS_ST_EXEC:
972 return PL330_STATE_EXECUTING;
973 case DS_ST_CMISS:
974 return PL330_STATE_CACHEMISS;
975 case DS_ST_UPDTPC:
976 return PL330_STATE_UPDTPC;
977 case DS_ST_WFE:
978 return PL330_STATE_WFE;
979 case DS_ST_FAULT:
980 return PL330_STATE_FAULTING;
981 case DS_ST_ATBRR:
982 if (is_manager(thrd))
983 return PL330_STATE_INVALID;
984 else
985 return PL330_STATE_ATBARRIER;
986 case DS_ST_QBUSY:
987 if (is_manager(thrd))
988 return PL330_STATE_INVALID;
989 else
990 return PL330_STATE_QUEUEBUSY;
991 case DS_ST_WFP:
992 if (is_manager(thrd))
993 return PL330_STATE_INVALID;
994 else
995 return PL330_STATE_WFP;
996 case DS_ST_KILL:
997 if (is_manager(thrd))
998 return PL330_STATE_INVALID;
999 else
1000 return PL330_STATE_KILLING;
1001 case DS_ST_CMPLT:
1002 if (is_manager(thrd))
1003 return PL330_STATE_INVALID;
1004 else
1005 return PL330_STATE_COMPLETING;
1006 case DS_ST_FLTCMP:
1007 if (is_manager(thrd))
1008 return PL330_STATE_INVALID;
1009 else
1010 return PL330_STATE_FAULT_COMPLETING;
1011 default:
1012 return PL330_STATE_INVALID;
1013 }
1014}
1015
1016static void _stop(struct pl330_thread *thrd)
1017{
1018 void __iomem *regs = thrd->dmac->base;
1019 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1020
1021 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1022 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1023
1024 /* Return if nothing needs to be done */
1025 if (_state(thrd) == PL330_STATE_COMPLETING
1026 || _state(thrd) == PL330_STATE_KILLING
1027 || _state(thrd) == PL330_STATE_STOPPED)
1028 return;
1029
1030 _emit_KILL(0, insn);
1031
1032 /* Stop generating interrupts for SEV */
1033 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1034
1035 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1036}
1037
1038/* Start doing req 'idx' of thread 'thrd' */
1039static bool _trigger(struct pl330_thread *thrd)
1040{
1041 void __iomem *regs = thrd->dmac->base;
1042 struct _pl330_req *req;
1043 struct dma_pl330_desc *desc;
1044 struct _arg_GO go;
1045 unsigned ns;
1046 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1047 int idx;
1048
1049 /* Return if already ACTIVE */
1050 if (_state(thrd) != PL330_STATE_STOPPED)
1051 return true;
1052
1053 idx = 1 - thrd->lstenq;
1054 if (thrd->req[idx].desc != NULL) {
1055 req = &thrd->req[idx];
1056 } else {
1057 idx = thrd->lstenq;
1058 if (thrd->req[idx].desc != NULL)
1059 req = &thrd->req[idx];
1060 else
1061 req = NULL;
1062 }
1063
1064 /* Return if no request */
1065 if (!req)
1066 return true;
1067
1068 /* Return if req is running */
1069 if (idx == thrd->req_running)
1070 return true;
1071
1072 desc = req->desc;
1073
1074 ns = desc->rqcfg.nonsecure ? 1 : 0;
1075
1076 /* See 'Abort Sources' point-4 at Page 2-25 */
1077 if (_manager_ns(thrd) && !ns)
1078 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1079 __func__, __LINE__);
1080
1081 go.chan = thrd->id;
1082 go.addr = req->mc_bus;
1083 go.ns = ns;
1084 _emit_GO(0, insn, &go);
1085
1086 /* Set to generate interrupts for SEV */
1087 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1088
1089 /* Only manager can execute GO */
1090 _execute_DBGINSN(thrd, insn, true);
1091
1092 thrd->req_running = idx;
1093
1094 return true;
1095}
1096
1097static bool _start(struct pl330_thread *thrd)
1098{
1099 switch (_state(thrd)) {
1100 case PL330_STATE_FAULT_COMPLETING:
1101 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1102
1103 if (_state(thrd) == PL330_STATE_KILLING)
1104 UNTIL(thrd, PL330_STATE_STOPPED)
1105
1106 case PL330_STATE_FAULTING:
1107 _stop(thrd);
1108
1109 case PL330_STATE_KILLING:
1110 case PL330_STATE_COMPLETING:
1111 UNTIL(thrd, PL330_STATE_STOPPED)
1112
1113 case PL330_STATE_STOPPED:
1114 return _trigger(thrd);
1115
1116 case PL330_STATE_WFP:
1117 case PL330_STATE_QUEUEBUSY:
1118 case PL330_STATE_ATBARRIER:
1119 case PL330_STATE_UPDTPC:
1120 case PL330_STATE_CACHEMISS:
1121 case PL330_STATE_EXECUTING:
1122 return true;
1123
1124 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1125 default:
1126 return false;
1127 }
1128}
1129
1130static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1131 const struct _xfer_spec *pxs, int cyc)
1132{
1133 int off = 0;
1134 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1135
1136 /* check lock-up free version */
1137 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1138 while (cyc--) {
1139 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1140 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1141 }
1142 } else {
1143 while (cyc--) {
1144 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1145 off += _emit_RMB(dry_run, &buf[off]);
1146 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1147 off += _emit_WMB(dry_run, &buf[off]);
1148 }
1149 }
1150
1151 return off;
1152}
1153
1154static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
1155 u8 buf[], const struct _xfer_spec *pxs,
1156 int cyc)
1157{
1158 int off = 0;
1159 enum pl330_cond cond;
1160
1161 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1162 cond = BURST;
1163 else
1164 cond = SINGLE;
1165
1166 while (cyc--) {
1167 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1168 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
1169 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1170
1171 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1172 off += _emit_FLUSHP(dry_run, &buf[off],
1173 pxs->desc->peri);
1174 }
1175
1176 return off;
1177}
1178
1179static inline int _ldst_memtodev(struct pl330_dmac *pl330,
1180 unsigned dry_run, u8 buf[],
1181 const struct _xfer_spec *pxs, int cyc)
1182{
1183 int off = 0;
1184 enum pl330_cond cond;
1185
1186 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1187 cond = BURST;
1188 else
1189 cond = SINGLE;
1190
1191 while (cyc--) {
1192 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1193 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1194 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
1195
1196 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1197 off += _emit_FLUSHP(dry_run, &buf[off],
1198 pxs->desc->peri);
1199 }
1200
1201 return off;
1202}
1203
1204static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1205 const struct _xfer_spec *pxs, int cyc)
1206{
1207 int off = 0;
1208
1209 switch (pxs->desc->rqtype) {
1210 case DMA_MEM_TO_DEV:
1211 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
1212 break;
1213 case DMA_DEV_TO_MEM:
1214 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
1215 break;
1216 case DMA_MEM_TO_MEM:
1217 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1218 break;
1219 default:
1220 off += 0x40000000; /* Scare off the Client */
1221 break;
1222 }
1223
1224 return off;
1225}
1226
1227/* Returns bytes consumed and updates bursts */
1228static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1229 unsigned long *bursts, const struct _xfer_spec *pxs)
1230{
1231 int cyc, cycmax, szlp, szlpend, szbrst, off;
1232 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1233 struct _arg_LPEND lpend;
1234
1235 if (*bursts == 1)
1236 return _bursts(pl330, dry_run, buf, pxs, 1);
1237
1238 /* Max iterations possible in DMALP is 256 */
1239 if (*bursts >= 256*256) {
1240 lcnt1 = 256;
1241 lcnt0 = 256;
1242 cyc = *bursts / lcnt1 / lcnt0;
1243 } else if (*bursts > 256) {
1244 lcnt1 = 256;
1245 lcnt0 = *bursts / lcnt1;
1246 cyc = 1;
1247 } else {
1248 lcnt1 = *bursts;
1249 lcnt0 = 0;
1250 cyc = 1;
1251 }
1252
1253 szlp = _emit_LP(1, buf, 0, 0);
1254 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1255
1256 lpend.cond = ALWAYS;
1257 lpend.forever = false;
1258 lpend.loop = 0;
1259 lpend.bjump = 0;
1260 szlpend = _emit_LPEND(1, buf, &lpend);
1261
1262 if (lcnt0) {
1263 szlp *= 2;
1264 szlpend *= 2;
1265 }
1266
1267 /*
1268 * Max bursts that we can unroll due to limit on the
1269 * size of backward jump that can be encoded in DMALPEND
1270 * which is 8-bits and hence 255
1271 */
1272 cycmax = (255 - (szlp + szlpend)) / szbrst;
1273
1274 cyc = (cycmax < cyc) ? cycmax : cyc;
1275
1276 off = 0;
1277
1278 if (lcnt0) {
1279 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1280 ljmp0 = off;
1281 }
1282
1283 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1284 ljmp1 = off;
1285
1286 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1287
1288 lpend.cond = ALWAYS;
1289 lpend.forever = false;
1290 lpend.loop = 1;
1291 lpend.bjump = off - ljmp1;
1292 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1293
1294 if (lcnt0) {
1295 lpend.cond = ALWAYS;
1296 lpend.forever = false;
1297 lpend.loop = 0;
1298 lpend.bjump = off - ljmp0;
1299 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1300 }
1301
1302 *bursts = lcnt1 * cyc;
1303 if (lcnt0)
1304 *bursts *= lcnt0;
1305
1306 return off;
1307}
1308
1309static inline int _setup_loops(struct pl330_dmac *pl330,
1310 unsigned dry_run, u8 buf[],
1311 const struct _xfer_spec *pxs)
1312{
1313 struct pl330_xfer *x = &pxs->desc->px;
1314 u32 ccr = pxs->ccr;
1315 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1316 int off = 0;
1317
1318 while (bursts) {
1319 c = bursts;
1320 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1321 bursts -= c;
1322 }
1323
1324 return off;
1325}
1326
1327static inline int _setup_xfer(struct pl330_dmac *pl330,
1328 unsigned dry_run, u8 buf[],
1329 const struct _xfer_spec *pxs)
1330{
1331 struct pl330_xfer *x = &pxs->desc->px;
1332 int off = 0;
1333
1334 /* DMAMOV SAR, x->src_addr */
1335 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1336 /* DMAMOV DAR, x->dst_addr */
1337 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1338
1339 /* Setup Loop(s) */
1340 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1341
1342 return off;
1343}
1344
1345/*
1346 * A req is a sequence of one or more xfer units.
1347 * Returns the number of bytes taken to setup the MC for the req.
1348 */
1349static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1350 struct pl330_thread *thrd, unsigned index,
1351 struct _xfer_spec *pxs)
1352{
1353 struct _pl330_req *req = &thrd->req[index];
1354 struct pl330_xfer *x;
1355 u8 *buf = req->mc_cpu;
1356 int off = 0;
1357
1358 PL330_DBGMC_START(req->mc_bus);
1359
1360 /* DMAMOV CCR, ccr */
1361 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1362
1363 x = &pxs->desc->px;
1364 /* Error if xfer length is not aligned at burst size */
1365 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1366 return -EINVAL;
1367
1368 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1369
1370 /* DMASEV peripheral/event */
1371 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1372 /* DMAEND */
1373 off += _emit_END(dry_run, &buf[off]);
1374
1375 return off;
1376}
1377
1378static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1379{
1380 u32 ccr = 0;
1381
1382 if (rqc->src_inc)
1383 ccr |= CC_SRCINC;
1384
1385 if (rqc->dst_inc)
1386 ccr |= CC_DSTINC;
1387
1388 /* We set same protection levels for Src and DST for now */
1389 if (rqc->privileged)
1390 ccr |= CC_SRCPRI | CC_DSTPRI;
1391 if (rqc->nonsecure)
1392 ccr |= CC_SRCNS | CC_DSTNS;
1393 if (rqc->insnaccess)
1394 ccr |= CC_SRCIA | CC_DSTIA;
1395
1396 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1397 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1398
1399 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1400 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1401
1402 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1403 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1404
1405 ccr |= (rqc->swap << CC_SWAP_SHFT);
1406
1407 return ccr;
1408}
1409
1410/*
1411 * Submit a list of xfers after which the client wants notification.
1412 * Client is not notified after each xfer unit, just once after all
1413 * xfer units are done or some error occurs.
1414 */
1415static int pl330_submit_req(struct pl330_thread *thrd,
1416 struct dma_pl330_desc *desc)
1417{
1418 struct pl330_dmac *pl330 = thrd->dmac;
1419 struct _xfer_spec xs;
1420 unsigned long flags;
1421 unsigned idx;
1422 u32 ccr;
1423 int ret = 0;
1424
1425 if (pl330->state == DYING
1426 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1427 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1428 __func__, __LINE__);
1429 return -EAGAIN;
1430 }
1431
1432 /* If request for non-existing peripheral */
1433 if (desc->rqtype != DMA_MEM_TO_MEM &&
1434 desc->peri >= pl330->pcfg.num_peri) {
1435 dev_info(thrd->dmac->ddma.dev,
1436 "%s:%d Invalid peripheral(%u)!\n",
1437 __func__, __LINE__, desc->peri);
1438 return -EINVAL;
1439 }
1440
1441 spin_lock_irqsave(&pl330->lock, flags);
1442
1443 if (_queue_full(thrd)) {
1444 ret = -EAGAIN;
1445 goto xfer_exit;
1446 }
1447
1448 /* Prefer Secure Channel */
1449 if (!_manager_ns(thrd))
1450 desc->rqcfg.nonsecure = 0;
1451 else
1452 desc->rqcfg.nonsecure = 1;
1453
1454 ccr = _prepare_ccr(&desc->rqcfg);
1455
1456 idx = thrd->req[0].desc == NULL ? 0 : 1;
1457
1458 xs.ccr = ccr;
1459 xs.desc = desc;
1460
1461 /* First dry run to check if req is acceptable */
1462 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1463 if (ret < 0)
1464 goto xfer_exit;
1465
1466 if (ret > pl330->mcbufsz / 2) {
1467 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1468 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1469 ret = -ENOMEM;
1470 goto xfer_exit;
1471 }
1472
1473 /* Hook the request */
1474 thrd->lstenq = idx;
1475 thrd->req[idx].desc = desc;
1476 _setup_req(pl330, 0, thrd, idx, &xs);
1477
1478 ret = 0;
1479
1480xfer_exit:
1481 spin_unlock_irqrestore(&pl330->lock, flags);
1482
1483 return ret;
1484}
1485
1486static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1487{
1488 struct dma_pl330_chan *pch;
1489 unsigned long flags;
1490
1491 if (!desc)
1492 return;
1493
1494 pch = desc->pchan;
1495
1496 /* If desc aborted */
1497 if (!pch)
1498 return;
1499
1500 spin_lock_irqsave(&pch->lock, flags);
1501
1502 desc->status = DONE;
1503
1504 spin_unlock_irqrestore(&pch->lock, flags);
1505
1506 tasklet_schedule(&pch->task);
1507}
1508
1509static void pl330_dotask(unsigned long data)
1510{
1511 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1512 unsigned long flags;
1513 int i;
1514
1515 spin_lock_irqsave(&pl330->lock, flags);
1516
1517 /* The DMAC itself gone nuts */
1518 if (pl330->dmac_tbd.reset_dmac) {
1519 pl330->state = DYING;
1520 /* Reset the manager too */
1521 pl330->dmac_tbd.reset_mngr = true;
1522 /* Clear the reset flag */
1523 pl330->dmac_tbd.reset_dmac = false;
1524 }
1525
1526 if (pl330->dmac_tbd.reset_mngr) {
1527 _stop(pl330->manager);
1528 /* Reset all channels */
1529 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1530 /* Clear the reset flag */
1531 pl330->dmac_tbd.reset_mngr = false;
1532 }
1533
1534 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1535
1536 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1537 struct pl330_thread *thrd = &pl330->channels[i];
1538 void __iomem *regs = pl330->base;
1539 enum pl330_op_err err;
1540
1541 _stop(thrd);
1542
1543 if (readl(regs + FSC) & (1 << thrd->id))
1544 err = PL330_ERR_FAIL;
1545 else
1546 err = PL330_ERR_ABORT;
1547
1548 spin_unlock_irqrestore(&pl330->lock, flags);
1549 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1550 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1551 spin_lock_irqsave(&pl330->lock, flags);
1552
1553 thrd->req[0].desc = NULL;
1554 thrd->req[1].desc = NULL;
1555 thrd->req_running = -1;
1556
1557 /* Clear the reset flag */
1558 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1559 }
1560 }
1561
1562 spin_unlock_irqrestore(&pl330->lock, flags);
1563
1564 return;
1565}
1566
1567/* Returns 1 if state was updated, 0 otherwise */
1568static int pl330_update(struct pl330_dmac *pl330)
1569{
1570 struct dma_pl330_desc *descdone, *tmp;
1571 unsigned long flags;
1572 void __iomem *regs;
1573 u32 val;
1574 int id, ev, ret = 0;
1575
1576 regs = pl330->base;
1577
1578 spin_lock_irqsave(&pl330->lock, flags);
1579
1580 val = readl(regs + FSM) & 0x1;
1581 if (val)
1582 pl330->dmac_tbd.reset_mngr = true;
1583 else
1584 pl330->dmac_tbd.reset_mngr = false;
1585
1586 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1587 pl330->dmac_tbd.reset_chan |= val;
1588 if (val) {
1589 int i = 0;
1590 while (i < pl330->pcfg.num_chan) {
1591 if (val & (1 << i)) {
1592 dev_info(pl330->ddma.dev,
1593 "Reset Channel-%d\t CS-%x FTC-%x\n",
1594 i, readl(regs + CS(i)),
1595 readl(regs + FTC(i)));
1596 _stop(&pl330->channels[i]);
1597 }
1598 i++;
1599 }
1600 }
1601
1602 /* Check which event happened i.e, thread notified */
1603 val = readl(regs + ES);
1604 if (pl330->pcfg.num_events < 32
1605 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1606 pl330->dmac_tbd.reset_dmac = true;
1607 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1608 __LINE__);
1609 ret = 1;
1610 goto updt_exit;
1611 }
1612
1613 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1614 if (val & (1 << ev)) { /* Event occurred */
1615 struct pl330_thread *thrd;
1616 u32 inten = readl(regs + INTEN);
1617 int active;
1618
1619 /* Clear the event */
1620 if (inten & (1 << ev))
1621 writel(1 << ev, regs + INTCLR);
1622
1623 ret = 1;
1624
1625 id = pl330->events[ev];
1626
1627 thrd = &pl330->channels[id];
1628
1629 active = thrd->req_running;
1630 if (active == -1) /* Aborted */
1631 continue;
1632
1633 /* Detach the req */
1634 descdone = thrd->req[active].desc;
1635 thrd->req[active].desc = NULL;
1636
1637 thrd->req_running = -1;
1638
1639 /* Get going again ASAP */
1640 _start(thrd);
1641
1642 /* For now, just make a list of callbacks to be done */
1643 list_add_tail(&descdone->rqd, &pl330->req_done);
1644 }
1645 }
1646
1647 /* Now that we are in no hurry, do the callbacks */
1648 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1649 list_del(&descdone->rqd);
1650 spin_unlock_irqrestore(&pl330->lock, flags);
1651 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1652 spin_lock_irqsave(&pl330->lock, flags);
1653 }
1654
1655updt_exit:
1656 spin_unlock_irqrestore(&pl330->lock, flags);
1657
1658 if (pl330->dmac_tbd.reset_dmac
1659 || pl330->dmac_tbd.reset_mngr
1660 || pl330->dmac_tbd.reset_chan) {
1661 ret = 1;
1662 tasklet_schedule(&pl330->tasks);
1663 }
1664
1665 return ret;
1666}
1667
1668/* Reserve an event */
1669static inline int _alloc_event(struct pl330_thread *thrd)
1670{
1671 struct pl330_dmac *pl330 = thrd->dmac;
1672 int ev;
1673
1674 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1675 if (pl330->events[ev] == -1) {
1676 pl330->events[ev] = thrd->id;
1677 return ev;
1678 }
1679
1680 return -1;
1681}
1682
1683static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1684{
1685 return pl330->pcfg.irq_ns & (1 << i);
1686}
1687
1688/* Upon success, returns IdentityToken for the
1689 * allocated channel, NULL otherwise.
1690 */
1691static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1692{
1693 struct pl330_thread *thrd = NULL;
1694 unsigned long flags;
1695 int chans, i;
1696
1697 if (pl330->state == DYING)
1698 return NULL;
1699
1700 chans = pl330->pcfg.num_chan;
1701
1702 spin_lock_irqsave(&pl330->lock, flags);
1703
1704 for (i = 0; i < chans; i++) {
1705 thrd = &pl330->channels[i];
1706 if ((thrd->free) && (!_manager_ns(thrd) ||
1707 _chan_ns(pl330, i))) {
1708 thrd->ev = _alloc_event(thrd);
1709 if (thrd->ev >= 0) {
1710 thrd->free = false;
1711 thrd->lstenq = 1;
1712 thrd->req[0].desc = NULL;
1713 thrd->req[1].desc = NULL;
1714 thrd->req_running = -1;
1715 break;
1716 }
1717 }
1718 thrd = NULL;
1719 }
1720
1721 spin_unlock_irqrestore(&pl330->lock, flags);
1722
1723 return thrd;
1724}
1725
1726/* Release an event */
1727static inline void _free_event(struct pl330_thread *thrd, int ev)
1728{
1729 struct pl330_dmac *pl330 = thrd->dmac;
1730
1731 /* If the event is valid and was held by the thread */
1732 if (ev >= 0 && ev < pl330->pcfg.num_events
1733 && pl330->events[ev] == thrd->id)
1734 pl330->events[ev] = -1;
1735}
1736
1737static void pl330_release_channel(struct pl330_thread *thrd)
1738{
1739 struct pl330_dmac *pl330;
1740 unsigned long flags;
1741
1742 if (!thrd || thrd->free)
1743 return;
1744
1745 _stop(thrd);
1746
1747 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1748 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1749
1750 pl330 = thrd->dmac;
1751
1752 spin_lock_irqsave(&pl330->lock, flags);
1753 _free_event(thrd, thrd->ev);
1754 thrd->free = true;
1755 spin_unlock_irqrestore(&pl330->lock, flags);
1756}
1757
1758/* Initialize the structure for PL330 configuration, that can be used
1759 * by the client driver the make best use of the DMAC
1760 */
1761static void read_dmac_config(struct pl330_dmac *pl330)
1762{
1763 void __iomem *regs = pl330->base;
1764 u32 val;
1765
1766 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1767 val &= CRD_DATA_WIDTH_MASK;
1768 pl330->pcfg.data_bus_width = 8 * (1 << val);
1769
1770 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1771 val &= CRD_DATA_BUFF_MASK;
1772 pl330->pcfg.data_buf_dep = val + 1;
1773
1774 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1775 val &= CR0_NUM_CHANS_MASK;
1776 val += 1;
1777 pl330->pcfg.num_chan = val;
1778
1779 val = readl(regs + CR0);
1780 if (val & CR0_PERIPH_REQ_SET) {
1781 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1782 val += 1;
1783 pl330->pcfg.num_peri = val;
1784 pl330->pcfg.peri_ns = readl(regs + CR4);
1785 } else {
1786 pl330->pcfg.num_peri = 0;
1787 }
1788
1789 val = readl(regs + CR0);
1790 if (val & CR0_BOOT_MAN_NS)
1791 pl330->pcfg.mode |= DMAC_MODE_NS;
1792 else
1793 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1794
1795 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1796 val &= CR0_NUM_EVENTS_MASK;
1797 val += 1;
1798 pl330->pcfg.num_events = val;
1799
1800 pl330->pcfg.irq_ns = readl(regs + CR3);
1801}
1802
1803static inline void _reset_thread(struct pl330_thread *thrd)
1804{
1805 struct pl330_dmac *pl330 = thrd->dmac;
1806
1807 thrd->req[0].mc_cpu = pl330->mcode_cpu
1808 + (thrd->id * pl330->mcbufsz);
1809 thrd->req[0].mc_bus = pl330->mcode_bus
1810 + (thrd->id * pl330->mcbufsz);
1811 thrd->req[0].desc = NULL;
1812
1813 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1814 + pl330->mcbufsz / 2;
1815 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1816 + pl330->mcbufsz / 2;
1817 thrd->req[1].desc = NULL;
1818
1819 thrd->req_running = -1;
1820}
1821
1822static int dmac_alloc_threads(struct pl330_dmac *pl330)
1823{
1824 int chans = pl330->pcfg.num_chan;
1825 struct pl330_thread *thrd;
1826 int i;
1827
1828 /* Allocate 1 Manager and 'chans' Channel threads */
1829 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1830 GFP_KERNEL);
1831 if (!pl330->channels)
1832 return -ENOMEM;
1833
1834 /* Init Channel threads */
1835 for (i = 0; i < chans; i++) {
1836 thrd = &pl330->channels[i];
1837 thrd->id = i;
1838 thrd->dmac = pl330;
1839 _reset_thread(thrd);
1840 thrd->free = true;
1841 }
1842
1843 /* MANAGER is indexed at the end */
1844 thrd = &pl330->channels[chans];
1845 thrd->id = chans;
1846 thrd->dmac = pl330;
1847 thrd->free = false;
1848 pl330->manager = thrd;
1849
1850 return 0;
1851}
1852
1853static int dmac_alloc_resources(struct pl330_dmac *pl330)
1854{
1855 int chans = pl330->pcfg.num_chan;
1856 int ret;
1857
1858 /*
1859 * Alloc MicroCode buffer for 'chans' Channel threads.
1860 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1861 */
1862 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1863 chans * pl330->mcbufsz,
1864 &pl330->mcode_bus, GFP_KERNEL);
1865 if (!pl330->mcode_cpu) {
1866 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1867 __func__, __LINE__);
1868 return -ENOMEM;
1869 }
1870
1871 ret = dmac_alloc_threads(pl330);
1872 if (ret) {
1873 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1874 __func__, __LINE__);
1875 dma_free_coherent(pl330->ddma.dev,
1876 chans * pl330->mcbufsz,
1877 pl330->mcode_cpu, pl330->mcode_bus);
1878 return ret;
1879 }
1880
1881 return 0;
1882}
1883
1884static int pl330_add(struct pl330_dmac *pl330)
1885{
1886 void __iomem *regs;
1887 int i, ret;
1888
1889 regs = pl330->base;
1890
1891 /* Check if we can handle this DMAC */
1892 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1893 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1894 pl330->pcfg.periph_id);
1895 return -EINVAL;
1896 }
1897
1898 /* Read the configuration of the DMAC */
1899 read_dmac_config(pl330);
1900
1901 if (pl330->pcfg.num_events == 0) {
1902 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1903 __func__, __LINE__);
1904 return -EINVAL;
1905 }
1906
1907 spin_lock_init(&pl330->lock);
1908
1909 INIT_LIST_HEAD(&pl330->req_done);
1910
1911 /* Use default MC buffer size if not provided */
1912 if (!pl330->mcbufsz)
1913 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1914
1915 /* Mark all events as free */
1916 for (i = 0; i < pl330->pcfg.num_events; i++)
1917 pl330->events[i] = -1;
1918
1919 /* Allocate resources needed by the DMAC */
1920 ret = dmac_alloc_resources(pl330);
1921 if (ret) {
1922 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1923 return ret;
1924 }
1925
1926 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1927
1928 pl330->state = INIT;
1929
1930 return 0;
1931}
1932
1933static int dmac_free_threads(struct pl330_dmac *pl330)
1934{
1935 struct pl330_thread *thrd;
1936 int i;
1937
1938 /* Release Channel threads */
1939 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1940 thrd = &pl330->channels[i];
1941 pl330_release_channel(thrd);
1942 }
1943
1944 /* Free memory */
1945 kfree(pl330->channels);
1946
1947 return 0;
1948}
1949
1950static void pl330_del(struct pl330_dmac *pl330)
1951{
1952 pl330->state = UNINIT;
1953
1954 tasklet_kill(&pl330->tasks);
1955
1956 /* Free DMAC resources */
1957 dmac_free_threads(pl330);
1958
1959 dma_free_coherent(pl330->ddma.dev,
1960 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1961 pl330->mcode_bus);
1962}
1963
1964/* forward declaration */
1965static struct amba_driver pl330_driver;
1966
1967static inline struct dma_pl330_chan *
1968to_pchan(struct dma_chan *ch)
1969{
1970 if (!ch)
1971 return NULL;
1972
1973 return container_of(ch, struct dma_pl330_chan, chan);
1974}
1975
1976static inline struct dma_pl330_desc *
1977to_desc(struct dma_async_tx_descriptor *tx)
1978{
1979 return container_of(tx, struct dma_pl330_desc, txd);
1980}
1981
1982static inline void fill_queue(struct dma_pl330_chan *pch)
1983{
1984 struct dma_pl330_desc *desc;
1985 int ret;
1986
1987 list_for_each_entry(desc, &pch->work_list, node) {
1988
1989 /* If already submitted */
1990 if (desc->status == BUSY)
1991 continue;
1992
1993 ret = pl330_submit_req(pch->thread, desc);
1994 if (!ret) {
1995 desc->status = BUSY;
1996 } else if (ret == -EAGAIN) {
1997 /* QFull or DMAC Dying */
1998 break;
1999 } else {
2000 /* Unacceptable request */
2001 desc->status = DONE;
2002 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2003 __func__, __LINE__, desc->txd.cookie);
2004 tasklet_schedule(&pch->task);
2005 }
2006 }
2007}
2008
2009static void pl330_tasklet(unsigned long data)
2010{
2011 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2012 struct dma_pl330_desc *desc, *_dt;
2013 unsigned long flags;
2014 bool power_down = false;
2015
2016 spin_lock_irqsave(&pch->lock, flags);
2017
2018 /* Pick up ripe tomatoes */
2019 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2020 if (desc->status == DONE) {
2021 if (!pch->cyclic)
2022 dma_cookie_complete(&desc->txd);
2023 list_move_tail(&desc->node, &pch->completed_list);
2024 }
2025
2026 /* Try to submit a req imm. next to the last completed cookie */
2027 fill_queue(pch);
2028
2029 if (list_empty(&pch->work_list)) {
2030 spin_lock(&pch->thread->dmac->lock);
2031 _stop(pch->thread);
2032 spin_unlock(&pch->thread->dmac->lock);
2033 power_down = true;
2034 } else {
2035 /* Make sure the PL330 Channel thread is active */
2036 spin_lock(&pch->thread->dmac->lock);
2037 _start(pch->thread);
2038 spin_unlock(&pch->thread->dmac->lock);
2039 }
2040
2041 while (!list_empty(&pch->completed_list)) {
2042 dma_async_tx_callback callback;
2043 void *callback_param;
2044
2045 desc = list_first_entry(&pch->completed_list,
2046 struct dma_pl330_desc, node);
2047
2048 callback = desc->txd.callback;
2049 callback_param = desc->txd.callback_param;
2050
2051 if (pch->cyclic) {
2052 desc->status = PREP;
2053 list_move_tail(&desc->node, &pch->work_list);
2054 if (power_down) {
2055 spin_lock(&pch->thread->dmac->lock);
2056 _start(pch->thread);
2057 spin_unlock(&pch->thread->dmac->lock);
2058 power_down = false;
2059 }
2060 } else {
2061 desc->status = FREE;
2062 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2063 }
2064
2065 dma_descriptor_unmap(&desc->txd);
2066
2067 if (callback) {
2068 spin_unlock_irqrestore(&pch->lock, flags);
2069 callback(callback_param);
2070 spin_lock_irqsave(&pch->lock, flags);
2071 }
2072 }
2073 spin_unlock_irqrestore(&pch->lock, flags);
2074
2075 /* If work list empty, power down */
2076 if (power_down) {
2077 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2078 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2079 }
2080}
2081
2082bool pl330_filter(struct dma_chan *chan, void *param)
2083{
2084 u8 *peri_id;
2085
2086 if (chan->device->dev->driver != &pl330_driver.drv)
2087 return false;
2088
2089 peri_id = chan->private;
2090 return *peri_id == (unsigned long)param;
2091}
2092EXPORT_SYMBOL(pl330_filter);
2093
2094static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2095 struct of_dma *ofdma)
2096{
2097 int count = dma_spec->args_count;
2098 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2099 unsigned int chan_id;
2100
2101 if (!pl330)
2102 return NULL;
2103
2104 if (count != 1)
2105 return NULL;
2106
2107 chan_id = dma_spec->args[0];
2108 if (chan_id >= pl330->num_peripherals)
2109 return NULL;
2110
2111 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2112}
2113
2114static int pl330_alloc_chan_resources(struct dma_chan *chan)
2115{
2116 struct dma_pl330_chan *pch = to_pchan(chan);
2117 struct pl330_dmac *pl330 = pch->dmac;
2118 unsigned long flags;
2119
2120 spin_lock_irqsave(&pch->lock, flags);
2121
2122 dma_cookie_init(chan);
2123 pch->cyclic = false;
2124
2125 pch->thread = pl330_request_channel(pl330);
2126 if (!pch->thread) {
2127 spin_unlock_irqrestore(&pch->lock, flags);
2128 return -ENOMEM;
2129 }
2130
2131 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2132
2133 spin_unlock_irqrestore(&pch->lock, flags);
2134
2135 return 1;
2136}
2137
2138static int pl330_config(struct dma_chan *chan,
2139 struct dma_slave_config *slave_config)
2140{
2141 struct dma_pl330_chan *pch = to_pchan(chan);
2142
2143 if (slave_config->direction == DMA_MEM_TO_DEV) {
2144 if (slave_config->dst_addr)
2145 pch->fifo_addr = slave_config->dst_addr;
2146 if (slave_config->dst_addr_width)
2147 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2148 if (slave_config->dst_maxburst)
2149 pch->burst_len = slave_config->dst_maxburst;
2150 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2151 if (slave_config->src_addr)
2152 pch->fifo_addr = slave_config->src_addr;
2153 if (slave_config->src_addr_width)
2154 pch->burst_sz = __ffs(slave_config->src_addr_width);
2155 if (slave_config->src_maxburst)
2156 pch->burst_len = slave_config->src_maxburst;
2157 }
2158
2159 return 0;
2160}
2161
2162static int pl330_terminate_all(struct dma_chan *chan)
2163{
2164 struct dma_pl330_chan *pch = to_pchan(chan);
2165 struct dma_pl330_desc *desc;
2166 unsigned long flags;
2167 struct pl330_dmac *pl330 = pch->dmac;
2168 LIST_HEAD(list);
2169
2170 pm_runtime_get_sync(pl330->ddma.dev);
2171 spin_lock_irqsave(&pch->lock, flags);
2172 spin_lock(&pl330->lock);
2173 _stop(pch->thread);
2174 spin_unlock(&pl330->lock);
2175
2176 pch->thread->req[0].desc = NULL;
2177 pch->thread->req[1].desc = NULL;
2178 pch->thread->req_running = -1;
2179
2180 /* Mark all desc done */
2181 list_for_each_entry(desc, &pch->submitted_list, node) {
2182 desc->status = FREE;
2183 dma_cookie_complete(&desc->txd);
2184 }
2185
2186 list_for_each_entry(desc, &pch->work_list , node) {
2187 desc->status = FREE;
2188 dma_cookie_complete(&desc->txd);
2189 }
2190
2191 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2192 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2193 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2194 spin_unlock_irqrestore(&pch->lock, flags);
2195 pm_runtime_mark_last_busy(pl330->ddma.dev);
2196 pm_runtime_put_autosuspend(pl330->ddma.dev);
2197
2198 return 0;
2199}
2200
2201/*
2202 * We don't support DMA_RESUME command because of hardware
2203 * limitations, so after pausing the channel we cannot restore
2204 * it to active state. We have to terminate channel and setup
2205 * DMA transfer again. This pause feature was implemented to
2206 * allow safely read residue before channel termination.
2207 */
2208static int pl330_pause(struct dma_chan *chan)
2209{
2210 struct dma_pl330_chan *pch = to_pchan(chan);
2211 struct pl330_dmac *pl330 = pch->dmac;
2212 unsigned long flags;
2213
2214 pm_runtime_get_sync(pl330->ddma.dev);
2215 spin_lock_irqsave(&pch->lock, flags);
2216
2217 spin_lock(&pl330->lock);
2218 _stop(pch->thread);
2219 spin_unlock(&pl330->lock);
2220
2221 spin_unlock_irqrestore(&pch->lock, flags);
2222 pm_runtime_mark_last_busy(pl330->ddma.dev);
2223 pm_runtime_put_autosuspend(pl330->ddma.dev);
2224
2225 return 0;
2226}
2227
2228static void pl330_free_chan_resources(struct dma_chan *chan)
2229{
2230 struct dma_pl330_chan *pch = to_pchan(chan);
2231 unsigned long flags;
2232
2233 tasklet_kill(&pch->task);
2234
2235 pm_runtime_get_sync(pch->dmac->ddma.dev);
2236 spin_lock_irqsave(&pch->lock, flags);
2237
2238 pl330_release_channel(pch->thread);
2239 pch->thread = NULL;
2240
2241 if (pch->cyclic)
2242 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2243
2244 spin_unlock_irqrestore(&pch->lock, flags);
2245 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2246 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2247}
2248
2249static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2250 struct dma_pl330_desc *desc)
2251{
2252 struct pl330_thread *thrd = pch->thread;
2253 struct pl330_dmac *pl330 = pch->dmac;
2254 void __iomem *regs = thrd->dmac->base;
2255 u32 val, addr;
2256
2257 pm_runtime_get_sync(pl330->ddma.dev);
2258 val = addr = 0;
2259 if (desc->rqcfg.src_inc) {
2260 val = readl(regs + SA(thrd->id));
2261 addr = desc->px.src_addr;
2262 } else {
2263 val = readl(regs + DA(thrd->id));
2264 addr = desc->px.dst_addr;
2265 }
2266 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2267 pm_runtime_put_autosuspend(pl330->ddma.dev);
2268 return val - addr;
2269}
2270
2271static enum dma_status
2272pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2273 struct dma_tx_state *txstate)
2274{
2275 enum dma_status ret;
2276 unsigned long flags;
2277 struct dma_pl330_desc *desc, *running = NULL;
2278 struct dma_pl330_chan *pch = to_pchan(chan);
2279 unsigned int transferred, residual = 0;
2280
2281 ret = dma_cookie_status(chan, cookie, txstate);
2282
2283 if (!txstate)
2284 return ret;
2285
2286 if (ret == DMA_COMPLETE)
2287 goto out;
2288
2289 spin_lock_irqsave(&pch->lock, flags);
2290
2291 if (pch->thread->req_running != -1)
2292 running = pch->thread->req[pch->thread->req_running].desc;
2293
2294 /* Check in pending list */
2295 list_for_each_entry(desc, &pch->work_list, node) {
2296 if (desc->status == DONE)
2297 transferred = desc->bytes_requested;
2298 else if (running && desc == running)
2299 transferred =
2300 pl330_get_current_xferred_count(pch, desc);
2301 else
2302 transferred = 0;
2303 residual += desc->bytes_requested - transferred;
2304 if (desc->txd.cookie == cookie) {
2305 switch (desc->status) {
2306 case DONE:
2307 ret = DMA_COMPLETE;
2308 break;
2309 case PREP:
2310 case BUSY:
2311 ret = DMA_IN_PROGRESS;
2312 break;
2313 default:
2314 WARN_ON(1);
2315 }
2316 break;
2317 }
2318 if (desc->last)
2319 residual = 0;
2320 }
2321 spin_unlock_irqrestore(&pch->lock, flags);
2322
2323out:
2324 dma_set_residue(txstate, residual);
2325
2326 return ret;
2327}
2328
2329static void pl330_issue_pending(struct dma_chan *chan)
2330{
2331 struct dma_pl330_chan *pch = to_pchan(chan);
2332 unsigned long flags;
2333
2334 spin_lock_irqsave(&pch->lock, flags);
2335 if (list_empty(&pch->work_list)) {
2336 /*
2337 * Warn on nothing pending. Empty submitted_list may
2338 * break our pm_runtime usage counter as it is
2339 * updated on work_list emptiness status.
2340 */
2341 WARN_ON(list_empty(&pch->submitted_list));
2342 pm_runtime_get_sync(pch->dmac->ddma.dev);
2343 }
2344 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2345 spin_unlock_irqrestore(&pch->lock, flags);
2346
2347 pl330_tasklet((unsigned long)pch);
2348}
2349
2350/*
2351 * We returned the last one of the circular list of descriptor(s)
2352 * from prep_xxx, so the argument to submit corresponds to the last
2353 * descriptor of the list.
2354 */
2355static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2356{
2357 struct dma_pl330_desc *desc, *last = to_desc(tx);
2358 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2359 dma_cookie_t cookie;
2360 unsigned long flags;
2361
2362 spin_lock_irqsave(&pch->lock, flags);
2363
2364 /* Assign cookies to all nodes */
2365 while (!list_empty(&last->node)) {
2366 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2367 if (pch->cyclic) {
2368 desc->txd.callback = last->txd.callback;
2369 desc->txd.callback_param = last->txd.callback_param;
2370 }
2371 desc->last = false;
2372
2373 dma_cookie_assign(&desc->txd);
2374
2375 list_move_tail(&desc->node, &pch->submitted_list);
2376 }
2377
2378 last->last = true;
2379 cookie = dma_cookie_assign(&last->txd);
2380 list_add_tail(&last->node, &pch->submitted_list);
2381 spin_unlock_irqrestore(&pch->lock, flags);
2382
2383 return cookie;
2384}
2385
2386static inline void _init_desc(struct dma_pl330_desc *desc)
2387{
2388 desc->rqcfg.swap = SWAP_NO;
2389 desc->rqcfg.scctl = CCTRL0;
2390 desc->rqcfg.dcctl = CCTRL0;
2391 desc->txd.tx_submit = pl330_tx_submit;
2392
2393 INIT_LIST_HEAD(&desc->node);
2394}
2395
2396/* Returns the number of descriptors added to the DMAC pool */
2397static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2398{
2399 struct dma_pl330_desc *desc;
2400 unsigned long flags;
2401 int i;
2402
2403 desc = kcalloc(count, sizeof(*desc), flg);
2404 if (!desc)
2405 return 0;
2406
2407 spin_lock_irqsave(&pl330->pool_lock, flags);
2408
2409 for (i = 0; i < count; i++) {
2410 _init_desc(&desc[i]);
2411 list_add_tail(&desc[i].node, &pl330->desc_pool);
2412 }
2413
2414 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2415
2416 return count;
2417}
2418
2419static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2420{
2421 struct dma_pl330_desc *desc = NULL;
2422 unsigned long flags;
2423
2424 spin_lock_irqsave(&pl330->pool_lock, flags);
2425
2426 if (!list_empty(&pl330->desc_pool)) {
2427 desc = list_entry(pl330->desc_pool.next,
2428 struct dma_pl330_desc, node);
2429
2430 list_del_init(&desc->node);
2431
2432 desc->status = PREP;
2433 desc->txd.callback = NULL;
2434 }
2435
2436 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2437
2438 return desc;
2439}
2440
2441static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2442{
2443 struct pl330_dmac *pl330 = pch->dmac;
2444 u8 *peri_id = pch->chan.private;
2445 struct dma_pl330_desc *desc;
2446
2447 /* Pluck one desc from the pool of DMAC */
2448 desc = pluck_desc(pl330);
2449
2450 /* If the DMAC pool is empty, alloc new */
2451 if (!desc) {
2452 if (!add_desc(pl330, GFP_ATOMIC, 1))
2453 return NULL;
2454
2455 /* Try again */
2456 desc = pluck_desc(pl330);
2457 if (!desc) {
2458 dev_err(pch->dmac->ddma.dev,
2459 "%s:%d ALERT!\n", __func__, __LINE__);
2460 return NULL;
2461 }
2462 }
2463
2464 /* Initialize the descriptor */
2465 desc->pchan = pch;
2466 desc->txd.cookie = 0;
2467 async_tx_ack(&desc->txd);
2468
2469 desc->peri = peri_id ? pch->chan.chan_id : 0;
2470 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2471
2472 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2473
2474 return desc;
2475}
2476
2477static inline void fill_px(struct pl330_xfer *px,
2478 dma_addr_t dst, dma_addr_t src, size_t len)
2479{
2480 px->bytes = len;
2481 px->dst_addr = dst;
2482 px->src_addr = src;
2483}
2484
2485static struct dma_pl330_desc *
2486__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2487 dma_addr_t src, size_t len)
2488{
2489 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2490
2491 if (!desc) {
2492 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2493 __func__, __LINE__);
2494 return NULL;
2495 }
2496
2497 /*
2498 * Ideally we should lookout for reqs bigger than
2499 * those that can be programmed with 256 bytes of
2500 * MC buffer, but considering a req size is seldom
2501 * going to be word-unaligned and more than 200MB,
2502 * we take it easy.
2503 * Also, should the limit is reached we'd rather
2504 * have the platform increase MC buffer size than
2505 * complicating this API driver.
2506 */
2507 fill_px(&desc->px, dst, src, len);
2508
2509 return desc;
2510}
2511
2512/* Call after fixing burst size */
2513static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2514{
2515 struct dma_pl330_chan *pch = desc->pchan;
2516 struct pl330_dmac *pl330 = pch->dmac;
2517 int burst_len;
2518
2519 burst_len = pl330->pcfg.data_bus_width / 8;
2520 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2521 burst_len >>= desc->rqcfg.brst_size;
2522
2523 /* src/dst_burst_len can't be more than 16 */
2524 if (burst_len > 16)
2525 burst_len = 16;
2526
2527 while (burst_len > 1) {
2528 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2529 break;
2530 burst_len--;
2531 }
2532
2533 return burst_len;
2534}
2535
2536static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2537 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2538 size_t period_len, enum dma_transfer_direction direction,
2539 unsigned long flags)
2540{
2541 struct dma_pl330_desc *desc = NULL, *first = NULL;
2542 struct dma_pl330_chan *pch = to_pchan(chan);
2543 struct pl330_dmac *pl330 = pch->dmac;
2544 unsigned int i;
2545 dma_addr_t dst;
2546 dma_addr_t src;
2547
2548 if (len % period_len != 0)
2549 return NULL;
2550
2551 if (!is_slave_direction(direction)) {
2552 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2553 __func__, __LINE__);
2554 return NULL;
2555 }
2556
2557 for (i = 0; i < len / period_len; i++) {
2558 desc = pl330_get_desc(pch);
2559 if (!desc) {
2560 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2561 __func__, __LINE__);
2562
2563 if (!first)
2564 return NULL;
2565
2566 spin_lock_irqsave(&pl330->pool_lock, flags);
2567
2568 while (!list_empty(&first->node)) {
2569 desc = list_entry(first->node.next,
2570 struct dma_pl330_desc, node);
2571 list_move_tail(&desc->node, &pl330->desc_pool);
2572 }
2573
2574 list_move_tail(&first->node, &pl330->desc_pool);
2575
2576 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2577
2578 return NULL;
2579 }
2580
2581 switch (direction) {
2582 case DMA_MEM_TO_DEV:
2583 desc->rqcfg.src_inc = 1;
2584 desc->rqcfg.dst_inc = 0;
2585 src = dma_addr;
2586 dst = pch->fifo_addr;
2587 break;
2588 case DMA_DEV_TO_MEM:
2589 desc->rqcfg.src_inc = 0;
2590 desc->rqcfg.dst_inc = 1;
2591 src = pch->fifo_addr;
2592 dst = dma_addr;
2593 break;
2594 default:
2595 break;
2596 }
2597
2598 desc->rqtype = direction;
2599 desc->rqcfg.brst_size = pch->burst_sz;
2600 desc->rqcfg.brst_len = 1;
2601 desc->bytes_requested = period_len;
2602 fill_px(&desc->px, dst, src, period_len);
2603
2604 if (!first)
2605 first = desc;
2606 else
2607 list_add_tail(&desc->node, &first->node);
2608
2609 dma_addr += period_len;
2610 }
2611
2612 if (!desc)
2613 return NULL;
2614
2615 pch->cyclic = true;
2616 desc->txd.flags = flags;
2617
2618 return &desc->txd;
2619}
2620
2621static struct dma_async_tx_descriptor *
2622pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2623 dma_addr_t src, size_t len, unsigned long flags)
2624{
2625 struct dma_pl330_desc *desc;
2626 struct dma_pl330_chan *pch = to_pchan(chan);
2627 struct pl330_dmac *pl330;
2628 int burst;
2629
2630 if (unlikely(!pch || !len))
2631 return NULL;
2632
2633 pl330 = pch->dmac;
2634
2635 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2636 if (!desc)
2637 return NULL;
2638
2639 desc->rqcfg.src_inc = 1;
2640 desc->rqcfg.dst_inc = 1;
2641 desc->rqtype = DMA_MEM_TO_MEM;
2642
2643 /* Select max possible burst size */
2644 burst = pl330->pcfg.data_bus_width / 8;
2645
2646 /*
2647 * Make sure we use a burst size that aligns with all the memcpy
2648 * parameters because our DMA programming algorithm doesn't cope with
2649 * transfers which straddle an entry in the DMA device's MFIFO.
2650 */
2651 while ((src | dst | len) & (burst - 1))
2652 burst /= 2;
2653
2654 desc->rqcfg.brst_size = 0;
2655 while (burst != (1 << desc->rqcfg.brst_size))
2656 desc->rqcfg.brst_size++;
2657
2658 /*
2659 * If burst size is smaller than bus width then make sure we only
2660 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2661 */
2662 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2663 desc->rqcfg.brst_len = 1;
2664
2665 desc->rqcfg.brst_len = get_burst_len(desc, len);
2666 desc->bytes_requested = len;
2667
2668 desc->txd.flags = flags;
2669
2670 return &desc->txd;
2671}
2672
2673static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2674 struct dma_pl330_desc *first)
2675{
2676 unsigned long flags;
2677 struct dma_pl330_desc *desc;
2678
2679 if (!first)
2680 return;
2681
2682 spin_lock_irqsave(&pl330->pool_lock, flags);
2683
2684 while (!list_empty(&first->node)) {
2685 desc = list_entry(first->node.next,
2686 struct dma_pl330_desc, node);
2687 list_move_tail(&desc->node, &pl330->desc_pool);
2688 }
2689
2690 list_move_tail(&first->node, &pl330->desc_pool);
2691
2692 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2693}
2694
2695static struct dma_async_tx_descriptor *
2696pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2697 unsigned int sg_len, enum dma_transfer_direction direction,
2698 unsigned long flg, void *context)
2699{
2700 struct dma_pl330_desc *first, *desc = NULL;
2701 struct dma_pl330_chan *pch = to_pchan(chan);
2702 struct scatterlist *sg;
2703 int i;
2704 dma_addr_t addr;
2705
2706 if (unlikely(!pch || !sgl || !sg_len))
2707 return NULL;
2708
2709 addr = pch->fifo_addr;
2710
2711 first = NULL;
2712
2713 for_each_sg(sgl, sg, sg_len, i) {
2714
2715 desc = pl330_get_desc(pch);
2716 if (!desc) {
2717 struct pl330_dmac *pl330 = pch->dmac;
2718
2719 dev_err(pch->dmac->ddma.dev,
2720 "%s:%d Unable to fetch desc\n",
2721 __func__, __LINE__);
2722 __pl330_giveback_desc(pl330, first);
2723
2724 return NULL;
2725 }
2726
2727 if (!first)
2728 first = desc;
2729 else
2730 list_add_tail(&desc->node, &first->node);
2731
2732 if (direction == DMA_MEM_TO_DEV) {
2733 desc->rqcfg.src_inc = 1;
2734 desc->rqcfg.dst_inc = 0;
2735 fill_px(&desc->px,
2736 addr, sg_dma_address(sg), sg_dma_len(sg));
2737 } else {
2738 desc->rqcfg.src_inc = 0;
2739 desc->rqcfg.dst_inc = 1;
2740 fill_px(&desc->px,
2741 sg_dma_address(sg), addr, sg_dma_len(sg));
2742 }
2743
2744 desc->rqcfg.brst_size = pch->burst_sz;
2745 desc->rqcfg.brst_len = 1;
2746 desc->rqtype = direction;
2747 desc->bytes_requested = sg_dma_len(sg);
2748 }
2749
2750 /* Return the last desc in the chain */
2751 desc->txd.flags = flg;
2752 return &desc->txd;
2753}
2754
2755static irqreturn_t pl330_irq_handler(int irq, void *data)
2756{
2757 if (pl330_update(data))
2758 return IRQ_HANDLED;
2759 else
2760 return IRQ_NONE;
2761}
2762
2763#define PL330_DMA_BUSWIDTHS \
2764 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2765 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2766 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2767 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2768 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2769
2770/*
2771 * Runtime PM callbacks are provided by amba/bus.c driver.
2772 *
2773 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2774 * bus driver will only disable/enable the clock in runtime PM callbacks.
2775 */
2776static int __maybe_unused pl330_suspend(struct device *dev)
2777{
2778 struct amba_device *pcdev = to_amba_device(dev);
2779
2780 pm_runtime_disable(dev);
2781
2782 if (!pm_runtime_status_suspended(dev)) {
2783 /* amba did not disable the clock */
2784 amba_pclk_disable(pcdev);
2785 }
2786 amba_pclk_unprepare(pcdev);
2787
2788 return 0;
2789}
2790
2791static int __maybe_unused pl330_resume(struct device *dev)
2792{
2793 struct amba_device *pcdev = to_amba_device(dev);
2794 int ret;
2795
2796 ret = amba_pclk_prepare(pcdev);
2797 if (ret)
2798 return ret;
2799
2800 if (!pm_runtime_status_suspended(dev))
2801 ret = amba_pclk_enable(pcdev);
2802
2803 pm_runtime_enable(dev);
2804
2805 return ret;
2806}
2807
2808static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2809
2810static int
2811pl330_probe(struct amba_device *adev, const struct amba_id *id)
2812{
2813 struct dma_pl330_platdata *pdat;
2814 struct pl330_config *pcfg;
2815 struct pl330_dmac *pl330;
2816 struct dma_pl330_chan *pch, *_p;
2817 struct dma_device *pd;
2818 struct resource *res;
2819 int i, ret, irq;
2820 int num_chan;
2821 struct device_node *np = adev->dev.of_node;
2822
2823 pdat = dev_get_platdata(&adev->dev);
2824
2825 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2826 if (ret)
2827 return ret;
2828
2829 /* Allocate a new DMAC and its Channels */
2830 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2831 if (!pl330) {
2832 dev_err(&adev->dev, "unable to allocate mem\n");
2833 return -ENOMEM;
2834 }
2835
2836 pd = &pl330->ddma;
2837 pd->dev = &adev->dev;
2838
2839 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2840
2841 /* get quirk */
2842 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2843 if (of_property_read_bool(np, of_quirks[i].quirk))
2844 pl330->quirks |= of_quirks[i].id;
2845
2846 res = &adev->res;
2847 pl330->base = devm_ioremap_resource(&adev->dev, res);
2848 if (IS_ERR(pl330->base))
2849 return PTR_ERR(pl330->base);
2850
2851 amba_set_drvdata(adev, pl330);
2852
2853 for (i = 0; i < AMBA_NR_IRQS; i++) {
2854 irq = adev->irq[i];
2855 if (irq) {
2856 ret = devm_request_irq(&adev->dev, irq,
2857 pl330_irq_handler, 0,
2858 dev_name(&adev->dev), pl330);
2859 if (ret)
2860 return ret;
2861 } else {
2862 break;
2863 }
2864 }
2865
2866 pcfg = &pl330->pcfg;
2867
2868 pcfg->periph_id = adev->periphid;
2869 ret = pl330_add(pl330);
2870 if (ret)
2871 return ret;
2872
2873 INIT_LIST_HEAD(&pl330->desc_pool);
2874 spin_lock_init(&pl330->pool_lock);
2875
2876 /* Create a descriptor pool of default size */
2877 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2878 dev_warn(&adev->dev, "unable to allocate desc\n");
2879
2880 INIT_LIST_HEAD(&pd->channels);
2881
2882 /* Initialize channel parameters */
2883 if (pdat)
2884 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2885 else
2886 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2887
2888 pl330->num_peripherals = num_chan;
2889
2890 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2891 if (!pl330->peripherals) {
2892 ret = -ENOMEM;
2893 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
2894 goto probe_err2;
2895 }
2896
2897 for (i = 0; i < num_chan; i++) {
2898 pch = &pl330->peripherals[i];
2899 if (!adev->dev.of_node)
2900 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2901 else
2902 pch->chan.private = adev->dev.of_node;
2903
2904 INIT_LIST_HEAD(&pch->submitted_list);
2905 INIT_LIST_HEAD(&pch->work_list);
2906 INIT_LIST_HEAD(&pch->completed_list);
2907 spin_lock_init(&pch->lock);
2908 pch->thread = NULL;
2909 pch->chan.device = pd;
2910 pch->dmac = pl330;
2911
2912 /* Add the channel to the DMAC list */
2913 list_add_tail(&pch->chan.device_node, &pd->channels);
2914 }
2915
2916 if (pdat) {
2917 pd->cap_mask = pdat->cap_mask;
2918 } else {
2919 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2920 if (pcfg->num_peri) {
2921 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2922 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2923 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2924 }
2925 }
2926
2927 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2928 pd->device_free_chan_resources = pl330_free_chan_resources;
2929 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2930 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2931 pd->device_tx_status = pl330_tx_status;
2932 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2933 pd->device_config = pl330_config;
2934 pd->device_pause = pl330_pause;
2935 pd->device_terminate_all = pl330_terminate_all;
2936 pd->device_issue_pending = pl330_issue_pending;
2937 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2938 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2939 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2940 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2941 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
2942 1 : PL330_MAX_BURST);
2943
2944 ret = dma_async_device_register(pd);
2945 if (ret) {
2946 dev_err(&adev->dev, "unable to register DMAC\n");
2947 goto probe_err3;
2948 }
2949
2950 if (adev->dev.of_node) {
2951 ret = of_dma_controller_register(adev->dev.of_node,
2952 of_dma_pl330_xlate, pl330);
2953 if (ret) {
2954 dev_err(&adev->dev,
2955 "unable to register DMA to the generic DT DMA helpers\n");
2956 }
2957 }
2958
2959 adev->dev.dma_parms = &pl330->dma_parms;
2960
2961 /*
2962 * This is the limit for transfers with a buswidth of 1, larger
2963 * buswidths will have larger limits.
2964 */
2965 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2966 if (ret)
2967 dev_err(&adev->dev, "unable to set the seg size\n");
2968
2969
2970 dev_info(&adev->dev,
2971 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
2972 dev_info(&adev->dev,
2973 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2974 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2975 pcfg->num_peri, pcfg->num_events);
2976
2977 pm_runtime_irq_safe(&adev->dev);
2978 pm_runtime_use_autosuspend(&adev->dev);
2979 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2980 pm_runtime_mark_last_busy(&adev->dev);
2981 pm_runtime_put_autosuspend(&adev->dev);
2982
2983 return 0;
2984probe_err3:
2985 /* Idle the DMAC */
2986 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2987 chan.device_node) {
2988
2989 /* Remove the channel */
2990 list_del(&pch->chan.device_node);
2991
2992 /* Flush the channel */
2993 if (pch->thread) {
2994 pl330_terminate_all(&pch->chan);
2995 pl330_free_chan_resources(&pch->chan);
2996 }
2997 }
2998probe_err2:
2999 pl330_del(pl330);
3000
3001 return ret;
3002}
3003
3004static int pl330_remove(struct amba_device *adev)
3005{
3006 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3007 struct dma_pl330_chan *pch, *_p;
3008
3009 pm_runtime_get_noresume(pl330->ddma.dev);
3010
3011 if (adev->dev.of_node)
3012 of_dma_controller_free(adev->dev.of_node);
3013
3014 dma_async_device_unregister(&pl330->ddma);
3015
3016 /* Idle the DMAC */
3017 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3018 chan.device_node) {
3019
3020 /* Remove the channel */
3021 list_del(&pch->chan.device_node);
3022
3023 /* Flush the channel */
3024 if (pch->thread) {
3025 pl330_terminate_all(&pch->chan);
3026 pl330_free_chan_resources(&pch->chan);
3027 }
3028 }
3029
3030 pl330_del(pl330);
3031
3032 return 0;
3033}
3034
3035static struct amba_id pl330_ids[] = {
3036 {
3037 .id = 0x00041330,
3038 .mask = 0x000fffff,
3039 },
3040 { 0, 0 },
3041};
3042
3043MODULE_DEVICE_TABLE(amba, pl330_ids);
3044
3045static struct amba_driver pl330_driver = {
3046 .drv = {
3047 .owner = THIS_MODULE,
3048 .name = "dma-pl330",
3049 .pm = &pl330_pm,
3050 },
3051 .id_table = pl330_ids,
3052 .probe = pl330_probe,
3053 .remove = pl330_remove,
3054};
3055
3056module_amba_driver(pl330_driver);
3057
3058MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3059MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3060MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 */
9
10#include <linux/debugfs.h>
11#include <linux/kernel.h>
12#include <linux/io.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/amba/bus.h>
22#include <linux/scatterlist.h>
23#include <linux/of.h>
24#include <linux/of_dma.h>
25#include <linux/err.h>
26#include <linux/pm_runtime.h>
27#include <linux/bug.h>
28#include <linux/reset.h>
29
30#include "dmaengine.h"
31#define PL330_MAX_CHAN 8
32#define PL330_MAX_IRQS 32
33#define PL330_MAX_PERI 32
34#define PL330_MAX_BURST 16
35
36#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
37
38enum pl330_cachectrl {
39 CCTRL0, /* Noncacheable and nonbufferable */
40 CCTRL1, /* Bufferable only */
41 CCTRL2, /* Cacheable, but do not allocate */
42 CCTRL3, /* Cacheable and bufferable, but do not allocate */
43 INVALID1, /* AWCACHE = 0x1000 */
44 INVALID2,
45 CCTRL6, /* Cacheable write-through, allocate on writes only */
46 CCTRL7, /* Cacheable write-back, allocate on writes only */
47};
48
49enum pl330_byteswap {
50 SWAP_NO,
51 SWAP_2,
52 SWAP_4,
53 SWAP_8,
54 SWAP_16,
55};
56
57/* Register and Bit field Definitions */
58#define DS 0x0
59#define DS_ST_STOP 0x0
60#define DS_ST_EXEC 0x1
61#define DS_ST_CMISS 0x2
62#define DS_ST_UPDTPC 0x3
63#define DS_ST_WFE 0x4
64#define DS_ST_ATBRR 0x5
65#define DS_ST_QBUSY 0x6
66#define DS_ST_WFP 0x7
67#define DS_ST_KILL 0x8
68#define DS_ST_CMPLT 0x9
69#define DS_ST_FLTCMP 0xe
70#define DS_ST_FAULT 0xf
71
72#define DPC 0x4
73#define INTEN 0x20
74#define ES 0x24
75#define INTSTATUS 0x28
76#define INTCLR 0x2c
77#define FSM 0x30
78#define FSC 0x34
79#define FTM 0x38
80
81#define _FTC 0x40
82#define FTC(n) (_FTC + (n)*0x4)
83
84#define _CS 0x100
85#define CS(n) (_CS + (n)*0x8)
86#define CS_CNS (1 << 21)
87
88#define _CPC 0x104
89#define CPC(n) (_CPC + (n)*0x8)
90
91#define _SA 0x400
92#define SA(n) (_SA + (n)*0x20)
93
94#define _DA 0x404
95#define DA(n) (_DA + (n)*0x20)
96
97#define _CC 0x408
98#define CC(n) (_CC + (n)*0x20)
99
100#define CC_SRCINC (1 << 0)
101#define CC_DSTINC (1 << 14)
102#define CC_SRCPRI (1 << 8)
103#define CC_DSTPRI (1 << 22)
104#define CC_SRCNS (1 << 9)
105#define CC_DSTNS (1 << 23)
106#define CC_SRCIA (1 << 10)
107#define CC_DSTIA (1 << 24)
108#define CC_SRCBRSTLEN_SHFT 4
109#define CC_DSTBRSTLEN_SHFT 18
110#define CC_SRCBRSTSIZE_SHFT 1
111#define CC_DSTBRSTSIZE_SHFT 15
112#define CC_SRCCCTRL_SHFT 11
113#define CC_SRCCCTRL_MASK 0x7
114#define CC_DSTCCTRL_SHFT 25
115#define CC_DRCCCTRL_MASK 0x7
116#define CC_SWAP_SHFT 28
117
118#define _LC0 0x40c
119#define LC0(n) (_LC0 + (n)*0x20)
120
121#define _LC1 0x410
122#define LC1(n) (_LC1 + (n)*0x20)
123
124#define DBGSTATUS 0xd00
125#define DBG_BUSY (1 << 0)
126
127#define DBGCMD 0xd04
128#define DBGINST0 0xd08
129#define DBGINST1 0xd0c
130
131#define CR0 0xe00
132#define CR1 0xe04
133#define CR2 0xe08
134#define CR3 0xe0c
135#define CR4 0xe10
136#define CRD 0xe14
137
138#define PERIPH_ID 0xfe0
139#define PERIPH_REV_SHIFT 20
140#define PERIPH_REV_MASK 0xf
141#define PERIPH_REV_R0P0 0
142#define PERIPH_REV_R1P0 1
143#define PERIPH_REV_R1P1 2
144
145#define CR0_PERIPH_REQ_SET (1 << 0)
146#define CR0_BOOT_EN_SET (1 << 1)
147#define CR0_BOOT_MAN_NS (1 << 2)
148#define CR0_NUM_CHANS_SHIFT 4
149#define CR0_NUM_CHANS_MASK 0x7
150#define CR0_NUM_PERIPH_SHIFT 12
151#define CR0_NUM_PERIPH_MASK 0x1f
152#define CR0_NUM_EVENTS_SHIFT 17
153#define CR0_NUM_EVENTS_MASK 0x1f
154
155#define CR1_ICACHE_LEN_SHIFT 0
156#define CR1_ICACHE_LEN_MASK 0x7
157#define CR1_NUM_ICACHELINES_SHIFT 4
158#define CR1_NUM_ICACHELINES_MASK 0xf
159
160#define CRD_DATA_WIDTH_SHIFT 0
161#define CRD_DATA_WIDTH_MASK 0x7
162#define CRD_WR_CAP_SHIFT 4
163#define CRD_WR_CAP_MASK 0x7
164#define CRD_WR_Q_DEP_SHIFT 8
165#define CRD_WR_Q_DEP_MASK 0xf
166#define CRD_RD_CAP_SHIFT 12
167#define CRD_RD_CAP_MASK 0x7
168#define CRD_RD_Q_DEP_SHIFT 16
169#define CRD_RD_Q_DEP_MASK 0xf
170#define CRD_DATA_BUFF_SHIFT 20
171#define CRD_DATA_BUFF_MASK 0x3ff
172
173#define PART 0x330
174#define DESIGNER 0x41
175#define REVISION 0x0
176#define INTEG_CFG 0x0
177#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
178
179#define PL330_STATE_STOPPED (1 << 0)
180#define PL330_STATE_EXECUTING (1 << 1)
181#define PL330_STATE_WFE (1 << 2)
182#define PL330_STATE_FAULTING (1 << 3)
183#define PL330_STATE_COMPLETING (1 << 4)
184#define PL330_STATE_WFP (1 << 5)
185#define PL330_STATE_KILLING (1 << 6)
186#define PL330_STATE_FAULT_COMPLETING (1 << 7)
187#define PL330_STATE_CACHEMISS (1 << 8)
188#define PL330_STATE_UPDTPC (1 << 9)
189#define PL330_STATE_ATBARRIER (1 << 10)
190#define PL330_STATE_QUEUEBUSY (1 << 11)
191#define PL330_STATE_INVALID (1 << 15)
192
193#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
194 | PL330_STATE_WFE | PL330_STATE_FAULTING)
195
196#define CMD_DMAADDH 0x54
197#define CMD_DMAEND 0x00
198#define CMD_DMAFLUSHP 0x35
199#define CMD_DMAGO 0xa0
200#define CMD_DMALD 0x04
201#define CMD_DMALDP 0x25
202#define CMD_DMALP 0x20
203#define CMD_DMALPEND 0x28
204#define CMD_DMAKILL 0x01
205#define CMD_DMAMOV 0xbc
206#define CMD_DMANOP 0x18
207#define CMD_DMARMB 0x12
208#define CMD_DMASEV 0x34
209#define CMD_DMAST 0x08
210#define CMD_DMASTP 0x29
211#define CMD_DMASTZ 0x0c
212#define CMD_DMAWFE 0x36
213#define CMD_DMAWFP 0x30
214#define CMD_DMAWMB 0x13
215
216#define SZ_DMAADDH 3
217#define SZ_DMAEND 1
218#define SZ_DMAFLUSHP 2
219#define SZ_DMALD 1
220#define SZ_DMALDP 2
221#define SZ_DMALP 2
222#define SZ_DMALPEND 2
223#define SZ_DMAKILL 1
224#define SZ_DMAMOV 6
225#define SZ_DMANOP 1
226#define SZ_DMARMB 1
227#define SZ_DMASEV 2
228#define SZ_DMAST 1
229#define SZ_DMASTP 2
230#define SZ_DMASTZ 1
231#define SZ_DMAWFE 2
232#define SZ_DMAWFP 2
233#define SZ_DMAWMB 1
234#define SZ_DMAGO 6
235
236#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
237#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
238
239#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
240#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
241
242/*
243 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
244 * at 1byte/burst for P<->M and M<->M respectively.
245 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
246 * should be enough for P<->M and M<->M respectively.
247 */
248#define MCODE_BUFF_PER_REQ 256
249
250/* Use this _only_ to wait on transient states */
251#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
252
253#ifdef PL330_DEBUG_MCGEN
254static unsigned cmd_line;
255#define PL330_DBGCMD_DUMP(off, x...) do { \
256 printk("%x:", cmd_line); \
257 printk(x); \
258 cmd_line += off; \
259 } while (0)
260#define PL330_DBGMC_START(addr) (cmd_line = addr)
261#else
262#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
263#define PL330_DBGMC_START(addr) do {} while (0)
264#endif
265
266/* The number of default descriptors */
267
268#define NR_DEFAULT_DESC 16
269
270/* Delay for runtime PM autosuspend, ms */
271#define PL330_AUTOSUSPEND_DELAY 20
272
273/* Populated by the PL330 core driver for DMA API driver's info */
274struct pl330_config {
275 u32 periph_id;
276#define DMAC_MODE_NS (1 << 0)
277 unsigned int mode;
278 unsigned int data_bus_width:10; /* In number of bits */
279 unsigned int data_buf_dep:11;
280 unsigned int num_chan:4;
281 unsigned int num_peri:6;
282 u32 peri_ns;
283 unsigned int num_events:6;
284 u32 irq_ns;
285};
286
287/**
288 * Request Configuration.
289 * The PL330 core does not modify this and uses the last
290 * working configuration if the request doesn't provide any.
291 *
292 * The Client may want to provide this info only for the
293 * first request and a request with new settings.
294 */
295struct pl330_reqcfg {
296 /* Address Incrementing */
297 unsigned dst_inc:1;
298 unsigned src_inc:1;
299
300 /*
301 * For now, the SRC & DST protection levels
302 * and burst size/length are assumed same.
303 */
304 bool nonsecure;
305 bool privileged;
306 bool insnaccess;
307 unsigned brst_len:5;
308 unsigned brst_size:3; /* in power of 2 */
309
310 enum pl330_cachectrl dcctl;
311 enum pl330_cachectrl scctl;
312 enum pl330_byteswap swap;
313 struct pl330_config *pcfg;
314};
315
316/*
317 * One cycle of DMAC operation.
318 * There may be more than one xfer in a request.
319 */
320struct pl330_xfer {
321 u32 src_addr;
322 u32 dst_addr;
323 /* Size to xfer */
324 u32 bytes;
325};
326
327/* The xfer callbacks are made with one of these arguments. */
328enum pl330_op_err {
329 /* The all xfers in the request were success. */
330 PL330_ERR_NONE,
331 /* If req aborted due to global error. */
332 PL330_ERR_ABORT,
333 /* If req failed due to problem with Channel. */
334 PL330_ERR_FAIL,
335};
336
337enum dmamov_dst {
338 SAR = 0,
339 CCR,
340 DAR,
341};
342
343enum pl330_dst {
344 SRC = 0,
345 DST,
346};
347
348enum pl330_cond {
349 SINGLE,
350 BURST,
351 ALWAYS,
352};
353
354struct dma_pl330_desc;
355
356struct _pl330_req {
357 u32 mc_bus;
358 void *mc_cpu;
359 struct dma_pl330_desc *desc;
360};
361
362/* ToBeDone for tasklet */
363struct _pl330_tbd {
364 bool reset_dmac;
365 bool reset_mngr;
366 u8 reset_chan;
367};
368
369/* A DMAC Thread */
370struct pl330_thread {
371 u8 id;
372 int ev;
373 /* If the channel is not yet acquired by any client */
374 bool free;
375 /* Parent DMAC */
376 struct pl330_dmac *dmac;
377 /* Only two at a time */
378 struct _pl330_req req[2];
379 /* Index of the last enqueued request */
380 unsigned lstenq;
381 /* Index of the last submitted request or -1 if the DMA is stopped */
382 int req_running;
383};
384
385enum pl330_dmac_state {
386 UNINIT,
387 INIT,
388 DYING,
389};
390
391enum desc_status {
392 /* In the DMAC pool */
393 FREE,
394 /*
395 * Allocated to some channel during prep_xxx
396 * Also may be sitting on the work_list.
397 */
398 PREP,
399 /*
400 * Sitting on the work_list and already submitted
401 * to the PL330 core. Not more than two descriptors
402 * of a channel can be BUSY at any time.
403 */
404 BUSY,
405 /*
406 * Sitting on the channel work_list but xfer done
407 * by PL330 core
408 */
409 DONE,
410};
411
412struct dma_pl330_chan {
413 /* Schedule desc completion */
414 struct tasklet_struct task;
415
416 /* DMA-Engine Channel */
417 struct dma_chan chan;
418
419 /* List of submitted descriptors */
420 struct list_head submitted_list;
421 /* List of issued descriptors */
422 struct list_head work_list;
423 /* List of completed descriptors */
424 struct list_head completed_list;
425
426 /* Pointer to the DMAC that manages this channel,
427 * NULL if the channel is available to be acquired.
428 * As the parent, this DMAC also provides descriptors
429 * to the channel.
430 */
431 struct pl330_dmac *dmac;
432
433 /* To protect channel manipulation */
434 spinlock_t lock;
435
436 /*
437 * Hardware channel thread of PL330 DMAC. NULL if the channel is
438 * available.
439 */
440 struct pl330_thread *thread;
441
442 /* For D-to-M and M-to-D channels */
443 int burst_sz; /* the peripheral fifo width */
444 int burst_len; /* the number of burst */
445 phys_addr_t fifo_addr;
446 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
447 dma_addr_t fifo_dma;
448 enum dma_data_direction dir;
449 struct dma_slave_config slave_config;
450
451 /* for cyclic capability */
452 bool cyclic;
453
454 /* for runtime pm tracking */
455 bool active;
456};
457
458struct pl330_dmac {
459 /* DMA-Engine Device */
460 struct dma_device ddma;
461
462 /* Holds info about sg limitations */
463 struct device_dma_parameters dma_parms;
464
465 /* Pool of descriptors available for the DMAC's channels */
466 struct list_head desc_pool;
467 /* To protect desc_pool manipulation */
468 spinlock_t pool_lock;
469
470 /* Size of MicroCode buffers for each channel. */
471 unsigned mcbufsz;
472 /* ioremap'ed address of PL330 registers. */
473 void __iomem *base;
474 /* Populated by the PL330 core driver during pl330_add */
475 struct pl330_config pcfg;
476
477 spinlock_t lock;
478 /* Maximum possible events/irqs */
479 int events[32];
480 /* BUS address of MicroCode buffer */
481 dma_addr_t mcode_bus;
482 /* CPU address of MicroCode buffer */
483 void *mcode_cpu;
484 /* List of all Channel threads */
485 struct pl330_thread *channels;
486 /* Pointer to the MANAGER thread */
487 struct pl330_thread *manager;
488 /* To handle bad news in interrupt */
489 struct tasklet_struct tasks;
490 struct _pl330_tbd dmac_tbd;
491 /* State of DMAC operation */
492 enum pl330_dmac_state state;
493 /* Holds list of reqs with due callbacks */
494 struct list_head req_done;
495
496 /* Peripheral channels connected to this DMAC */
497 unsigned int num_peripherals;
498 struct dma_pl330_chan *peripherals; /* keep at end */
499 int quirks;
500
501 struct reset_control *rstc;
502 struct reset_control *rstc_ocp;
503};
504
505static struct pl330_of_quirks {
506 char *quirk;
507 int id;
508} of_quirks[] = {
509 {
510 .quirk = "arm,pl330-broken-no-flushp",
511 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
512 }
513};
514
515struct dma_pl330_desc {
516 /* To attach to a queue as child */
517 struct list_head node;
518
519 /* Descriptor for the DMA Engine API */
520 struct dma_async_tx_descriptor txd;
521
522 /* Xfer for PL330 core */
523 struct pl330_xfer px;
524
525 struct pl330_reqcfg rqcfg;
526
527 enum desc_status status;
528
529 int bytes_requested;
530 bool last;
531
532 /* The channel which currently holds this desc */
533 struct dma_pl330_chan *pchan;
534
535 enum dma_transfer_direction rqtype;
536 /* Index of peripheral for the xfer. */
537 unsigned peri:5;
538 /* Hook to attach to DMAC's list of reqs with due callback */
539 struct list_head rqd;
540};
541
542struct _xfer_spec {
543 u32 ccr;
544 struct dma_pl330_desc *desc;
545};
546
547static int pl330_config_write(struct dma_chan *chan,
548 struct dma_slave_config *slave_config,
549 enum dma_transfer_direction direction);
550
551static inline bool _queue_full(struct pl330_thread *thrd)
552{
553 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
554}
555
556static inline bool is_manager(struct pl330_thread *thrd)
557{
558 return thrd->dmac->manager == thrd;
559}
560
561/* If manager of the thread is in Non-Secure mode */
562static inline bool _manager_ns(struct pl330_thread *thrd)
563{
564 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
565}
566
567static inline u32 get_revision(u32 periph_id)
568{
569 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
570}
571
572static inline u32 _emit_END(unsigned dry_run, u8 buf[])
573{
574 if (dry_run)
575 return SZ_DMAEND;
576
577 buf[0] = CMD_DMAEND;
578
579 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
580
581 return SZ_DMAEND;
582}
583
584static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
585{
586 if (dry_run)
587 return SZ_DMAFLUSHP;
588
589 buf[0] = CMD_DMAFLUSHP;
590
591 peri &= 0x1f;
592 peri <<= 3;
593 buf[1] = peri;
594
595 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
596
597 return SZ_DMAFLUSHP;
598}
599
600static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
601{
602 if (dry_run)
603 return SZ_DMALD;
604
605 buf[0] = CMD_DMALD;
606
607 if (cond == SINGLE)
608 buf[0] |= (0 << 1) | (1 << 0);
609 else if (cond == BURST)
610 buf[0] |= (1 << 1) | (1 << 0);
611
612 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
613 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
614
615 return SZ_DMALD;
616}
617
618static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
619 enum pl330_cond cond, u8 peri)
620{
621 if (dry_run)
622 return SZ_DMALDP;
623
624 buf[0] = CMD_DMALDP;
625
626 if (cond == BURST)
627 buf[0] |= (1 << 1);
628
629 peri &= 0x1f;
630 peri <<= 3;
631 buf[1] = peri;
632
633 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
634 cond == SINGLE ? 'S' : 'B', peri >> 3);
635
636 return SZ_DMALDP;
637}
638
639static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
640 unsigned loop, u8 cnt)
641{
642 if (dry_run)
643 return SZ_DMALP;
644
645 buf[0] = CMD_DMALP;
646
647 if (loop)
648 buf[0] |= (1 << 1);
649
650 cnt--; /* DMAC increments by 1 internally */
651 buf[1] = cnt;
652
653 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
654
655 return SZ_DMALP;
656}
657
658struct _arg_LPEND {
659 enum pl330_cond cond;
660 bool forever;
661 unsigned loop;
662 u8 bjump;
663};
664
665static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
666 const struct _arg_LPEND *arg)
667{
668 enum pl330_cond cond = arg->cond;
669 bool forever = arg->forever;
670 unsigned loop = arg->loop;
671 u8 bjump = arg->bjump;
672
673 if (dry_run)
674 return SZ_DMALPEND;
675
676 buf[0] = CMD_DMALPEND;
677
678 if (loop)
679 buf[0] |= (1 << 2);
680
681 if (!forever)
682 buf[0] |= (1 << 4);
683
684 if (cond == SINGLE)
685 buf[0] |= (0 << 1) | (1 << 0);
686 else if (cond == BURST)
687 buf[0] |= (1 << 1) | (1 << 0);
688
689 buf[1] = bjump;
690
691 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
692 forever ? "FE" : "END",
693 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
694 loop ? '1' : '0',
695 bjump);
696
697 return SZ_DMALPEND;
698}
699
700static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
701{
702 if (dry_run)
703 return SZ_DMAKILL;
704
705 buf[0] = CMD_DMAKILL;
706
707 return SZ_DMAKILL;
708}
709
710static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
711 enum dmamov_dst dst, u32 val)
712{
713 if (dry_run)
714 return SZ_DMAMOV;
715
716 buf[0] = CMD_DMAMOV;
717 buf[1] = dst;
718 buf[2] = val;
719 buf[3] = val >> 8;
720 buf[4] = val >> 16;
721 buf[5] = val >> 24;
722
723 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
724 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
725
726 return SZ_DMAMOV;
727}
728
729static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
730{
731 if (dry_run)
732 return SZ_DMARMB;
733
734 buf[0] = CMD_DMARMB;
735
736 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
737
738 return SZ_DMARMB;
739}
740
741static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
742{
743 if (dry_run)
744 return SZ_DMASEV;
745
746 buf[0] = CMD_DMASEV;
747
748 ev &= 0x1f;
749 ev <<= 3;
750 buf[1] = ev;
751
752 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
753
754 return SZ_DMASEV;
755}
756
757static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
758{
759 if (dry_run)
760 return SZ_DMAST;
761
762 buf[0] = CMD_DMAST;
763
764 if (cond == SINGLE)
765 buf[0] |= (0 << 1) | (1 << 0);
766 else if (cond == BURST)
767 buf[0] |= (1 << 1) | (1 << 0);
768
769 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
770 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
771
772 return SZ_DMAST;
773}
774
775static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
776 enum pl330_cond cond, u8 peri)
777{
778 if (dry_run)
779 return SZ_DMASTP;
780
781 buf[0] = CMD_DMASTP;
782
783 if (cond == BURST)
784 buf[0] |= (1 << 1);
785
786 peri &= 0x1f;
787 peri <<= 3;
788 buf[1] = peri;
789
790 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
791 cond == SINGLE ? 'S' : 'B', peri >> 3);
792
793 return SZ_DMASTP;
794}
795
796static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
797 enum pl330_cond cond, u8 peri)
798{
799 if (dry_run)
800 return SZ_DMAWFP;
801
802 buf[0] = CMD_DMAWFP;
803
804 if (cond == SINGLE)
805 buf[0] |= (0 << 1) | (0 << 0);
806 else if (cond == BURST)
807 buf[0] |= (1 << 1) | (0 << 0);
808 else
809 buf[0] |= (0 << 1) | (1 << 0);
810
811 peri &= 0x1f;
812 peri <<= 3;
813 buf[1] = peri;
814
815 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
816 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
817
818 return SZ_DMAWFP;
819}
820
821static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
822{
823 if (dry_run)
824 return SZ_DMAWMB;
825
826 buf[0] = CMD_DMAWMB;
827
828 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
829
830 return SZ_DMAWMB;
831}
832
833struct _arg_GO {
834 u8 chan;
835 u32 addr;
836 unsigned ns;
837};
838
839static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
840 const struct _arg_GO *arg)
841{
842 u8 chan = arg->chan;
843 u32 addr = arg->addr;
844 unsigned ns = arg->ns;
845
846 if (dry_run)
847 return SZ_DMAGO;
848
849 buf[0] = CMD_DMAGO;
850 buf[0] |= (ns << 1);
851 buf[1] = chan & 0x7;
852 buf[2] = addr;
853 buf[3] = addr >> 8;
854 buf[4] = addr >> 16;
855 buf[5] = addr >> 24;
856
857 return SZ_DMAGO;
858}
859
860#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
861
862/* Returns Time-Out */
863static bool _until_dmac_idle(struct pl330_thread *thrd)
864{
865 void __iomem *regs = thrd->dmac->base;
866 unsigned long loops = msecs_to_loops(5);
867
868 do {
869 /* Until Manager is Idle */
870 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
871 break;
872
873 cpu_relax();
874 } while (--loops);
875
876 if (!loops)
877 return true;
878
879 return false;
880}
881
882static inline void _execute_DBGINSN(struct pl330_thread *thrd,
883 u8 insn[], bool as_manager)
884{
885 void __iomem *regs = thrd->dmac->base;
886 u32 val;
887
888 val = (insn[0] << 16) | (insn[1] << 24);
889 if (!as_manager) {
890 val |= (1 << 0);
891 val |= (thrd->id << 8); /* Channel Number */
892 }
893 writel(val, regs + DBGINST0);
894
895 val = le32_to_cpu(*((__le32 *)&insn[2]));
896 writel(val, regs + DBGINST1);
897
898 /* If timed out due to halted state-machine */
899 if (_until_dmac_idle(thrd)) {
900 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
901 return;
902 }
903
904 /* Get going */
905 writel(0, regs + DBGCMD);
906}
907
908static inline u32 _state(struct pl330_thread *thrd)
909{
910 void __iomem *regs = thrd->dmac->base;
911 u32 val;
912
913 if (is_manager(thrd))
914 val = readl(regs + DS) & 0xf;
915 else
916 val = readl(regs + CS(thrd->id)) & 0xf;
917
918 switch (val) {
919 case DS_ST_STOP:
920 return PL330_STATE_STOPPED;
921 case DS_ST_EXEC:
922 return PL330_STATE_EXECUTING;
923 case DS_ST_CMISS:
924 return PL330_STATE_CACHEMISS;
925 case DS_ST_UPDTPC:
926 return PL330_STATE_UPDTPC;
927 case DS_ST_WFE:
928 return PL330_STATE_WFE;
929 case DS_ST_FAULT:
930 return PL330_STATE_FAULTING;
931 case DS_ST_ATBRR:
932 if (is_manager(thrd))
933 return PL330_STATE_INVALID;
934 else
935 return PL330_STATE_ATBARRIER;
936 case DS_ST_QBUSY:
937 if (is_manager(thrd))
938 return PL330_STATE_INVALID;
939 else
940 return PL330_STATE_QUEUEBUSY;
941 case DS_ST_WFP:
942 if (is_manager(thrd))
943 return PL330_STATE_INVALID;
944 else
945 return PL330_STATE_WFP;
946 case DS_ST_KILL:
947 if (is_manager(thrd))
948 return PL330_STATE_INVALID;
949 else
950 return PL330_STATE_KILLING;
951 case DS_ST_CMPLT:
952 if (is_manager(thrd))
953 return PL330_STATE_INVALID;
954 else
955 return PL330_STATE_COMPLETING;
956 case DS_ST_FLTCMP:
957 if (is_manager(thrd))
958 return PL330_STATE_INVALID;
959 else
960 return PL330_STATE_FAULT_COMPLETING;
961 default:
962 return PL330_STATE_INVALID;
963 }
964}
965
966static void _stop(struct pl330_thread *thrd)
967{
968 void __iomem *regs = thrd->dmac->base;
969 u8 insn[6] = {0, 0, 0, 0, 0, 0};
970 u32 inten = readl(regs + INTEN);
971
972 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
973 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
974
975 /* Return if nothing needs to be done */
976 if (_state(thrd) == PL330_STATE_COMPLETING
977 || _state(thrd) == PL330_STATE_KILLING
978 || _state(thrd) == PL330_STATE_STOPPED)
979 return;
980
981 _emit_KILL(0, insn);
982
983 _execute_DBGINSN(thrd, insn, is_manager(thrd));
984
985 /* clear the event */
986 if (inten & (1 << thrd->ev))
987 writel(1 << thrd->ev, regs + INTCLR);
988 /* Stop generating interrupts for SEV */
989 writel(inten & ~(1 << thrd->ev), regs + INTEN);
990}
991
992/* Start doing req 'idx' of thread 'thrd' */
993static bool _trigger(struct pl330_thread *thrd)
994{
995 void __iomem *regs = thrd->dmac->base;
996 struct _pl330_req *req;
997 struct dma_pl330_desc *desc;
998 struct _arg_GO go;
999 unsigned ns;
1000 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1001 int idx;
1002
1003 /* Return if already ACTIVE */
1004 if (_state(thrd) != PL330_STATE_STOPPED)
1005 return true;
1006
1007 idx = 1 - thrd->lstenq;
1008 if (thrd->req[idx].desc != NULL) {
1009 req = &thrd->req[idx];
1010 } else {
1011 idx = thrd->lstenq;
1012 if (thrd->req[idx].desc != NULL)
1013 req = &thrd->req[idx];
1014 else
1015 req = NULL;
1016 }
1017
1018 /* Return if no request */
1019 if (!req)
1020 return true;
1021
1022 /* Return if req is running */
1023 if (idx == thrd->req_running)
1024 return true;
1025
1026 desc = req->desc;
1027
1028 ns = desc->rqcfg.nonsecure ? 1 : 0;
1029
1030 /* See 'Abort Sources' point-4 at Page 2-25 */
1031 if (_manager_ns(thrd) && !ns)
1032 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1033 __func__, __LINE__);
1034
1035 go.chan = thrd->id;
1036 go.addr = req->mc_bus;
1037 go.ns = ns;
1038 _emit_GO(0, insn, &go);
1039
1040 /* Set to generate interrupts for SEV */
1041 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1042
1043 /* Only manager can execute GO */
1044 _execute_DBGINSN(thrd, insn, true);
1045
1046 thrd->req_running = idx;
1047
1048 return true;
1049}
1050
1051static bool _start(struct pl330_thread *thrd)
1052{
1053 switch (_state(thrd)) {
1054 case PL330_STATE_FAULT_COMPLETING:
1055 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1056
1057 if (_state(thrd) == PL330_STATE_KILLING)
1058 UNTIL(thrd, PL330_STATE_STOPPED)
1059 /* fall through */
1060
1061 case PL330_STATE_FAULTING:
1062 _stop(thrd);
1063 /* fall through */
1064
1065 case PL330_STATE_KILLING:
1066 case PL330_STATE_COMPLETING:
1067 UNTIL(thrd, PL330_STATE_STOPPED)
1068 /* fall through */
1069
1070 case PL330_STATE_STOPPED:
1071 return _trigger(thrd);
1072
1073 case PL330_STATE_WFP:
1074 case PL330_STATE_QUEUEBUSY:
1075 case PL330_STATE_ATBARRIER:
1076 case PL330_STATE_UPDTPC:
1077 case PL330_STATE_CACHEMISS:
1078 case PL330_STATE_EXECUTING:
1079 return true;
1080
1081 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1082 default:
1083 return false;
1084 }
1085}
1086
1087static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1088 const struct _xfer_spec *pxs, int cyc)
1089{
1090 int off = 0;
1091 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1092
1093 /* check lock-up free version */
1094 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1095 while (cyc--) {
1096 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1097 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1098 }
1099 } else {
1100 while (cyc--) {
1101 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1102 off += _emit_RMB(dry_run, &buf[off]);
1103 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1104 off += _emit_WMB(dry_run, &buf[off]);
1105 }
1106 }
1107
1108 return off;
1109}
1110
1111static u32 _emit_load(unsigned int dry_run, u8 buf[],
1112 enum pl330_cond cond, enum dma_transfer_direction direction,
1113 u8 peri)
1114{
1115 int off = 0;
1116
1117 switch (direction) {
1118 case DMA_MEM_TO_MEM:
1119 /* fall through */
1120 case DMA_MEM_TO_DEV:
1121 off += _emit_LD(dry_run, &buf[off], cond);
1122 break;
1123
1124 case DMA_DEV_TO_MEM:
1125 if (cond == ALWAYS) {
1126 off += _emit_LDP(dry_run, &buf[off], SINGLE,
1127 peri);
1128 off += _emit_LDP(dry_run, &buf[off], BURST,
1129 peri);
1130 } else {
1131 off += _emit_LDP(dry_run, &buf[off], cond,
1132 peri);
1133 }
1134 break;
1135
1136 default:
1137 /* this code should be unreachable */
1138 WARN_ON(1);
1139 break;
1140 }
1141
1142 return off;
1143}
1144
1145static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
1146 enum pl330_cond cond, enum dma_transfer_direction direction,
1147 u8 peri)
1148{
1149 int off = 0;
1150
1151 switch (direction) {
1152 case DMA_MEM_TO_MEM:
1153 /* fall through */
1154 case DMA_DEV_TO_MEM:
1155 off += _emit_ST(dry_run, &buf[off], cond);
1156 break;
1157
1158 case DMA_MEM_TO_DEV:
1159 if (cond == ALWAYS) {
1160 off += _emit_STP(dry_run, &buf[off], SINGLE,
1161 peri);
1162 off += _emit_STP(dry_run, &buf[off], BURST,
1163 peri);
1164 } else {
1165 off += _emit_STP(dry_run, &buf[off], cond,
1166 peri);
1167 }
1168 break;
1169
1170 default:
1171 /* this code should be unreachable */
1172 WARN_ON(1);
1173 break;
1174 }
1175
1176 return off;
1177}
1178
1179static inline int _ldst_peripheral(struct pl330_dmac *pl330,
1180 unsigned dry_run, u8 buf[],
1181 const struct _xfer_spec *pxs, int cyc,
1182 enum pl330_cond cond)
1183{
1184 int off = 0;
1185
1186 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1187 cond = BURST;
1188
1189 /*
1190 * do FLUSHP at beginning to clear any stale dma requests before the
1191 * first WFP.
1192 */
1193 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1194 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1195 while (cyc--) {
1196 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1197 off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1198 pxs->desc->peri);
1199 off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1200 pxs->desc->peri);
1201 }
1202
1203 return off;
1204}
1205
1206static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1207 const struct _xfer_spec *pxs, int cyc)
1208{
1209 int off = 0;
1210 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
1211
1212 switch (pxs->desc->rqtype) {
1213 case DMA_MEM_TO_DEV:
1214 /* fall through */
1215 case DMA_DEV_TO_MEM:
1216 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1217 cond);
1218 break;
1219
1220 case DMA_MEM_TO_MEM:
1221 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1222 break;
1223
1224 default:
1225 /* this code should be unreachable */
1226 WARN_ON(1);
1227 break;
1228 }
1229
1230 return off;
1231}
1232
1233/*
1234 * transfer dregs with single transfers to peripheral, or a reduced size burst
1235 * for mem-to-mem.
1236 */
1237static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
1238 const struct _xfer_spec *pxs, int transfer_length)
1239{
1240 int off = 0;
1241 int dregs_ccr;
1242
1243 if (transfer_length == 0)
1244 return off;
1245
1246 switch (pxs->desc->rqtype) {
1247 case DMA_MEM_TO_DEV:
1248 /* fall through */
1249 case DMA_DEV_TO_MEM:
1250 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs,
1251 transfer_length, SINGLE);
1252 break;
1253
1254 case DMA_MEM_TO_MEM:
1255 dregs_ccr = pxs->ccr;
1256 dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
1257 (0xf << CC_DSTBRSTLEN_SHFT));
1258 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1259 CC_SRCBRSTLEN_SHFT);
1260 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1261 CC_DSTBRSTLEN_SHFT);
1262 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1263 off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
1264 break;
1265
1266 default:
1267 /* this code should be unreachable */
1268 WARN_ON(1);
1269 break;
1270 }
1271
1272 return off;
1273}
1274
1275/* Returns bytes consumed and updates bursts */
1276static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1277 unsigned long *bursts, const struct _xfer_spec *pxs)
1278{
1279 int cyc, cycmax, szlp, szlpend, szbrst, off;
1280 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1281 struct _arg_LPEND lpend;
1282
1283 if (*bursts == 1)
1284 return _bursts(pl330, dry_run, buf, pxs, 1);
1285
1286 /* Max iterations possible in DMALP is 256 */
1287 if (*bursts >= 256*256) {
1288 lcnt1 = 256;
1289 lcnt0 = 256;
1290 cyc = *bursts / lcnt1 / lcnt0;
1291 } else if (*bursts > 256) {
1292 lcnt1 = 256;
1293 lcnt0 = *bursts / lcnt1;
1294 cyc = 1;
1295 } else {
1296 lcnt1 = *bursts;
1297 lcnt0 = 0;
1298 cyc = 1;
1299 }
1300
1301 szlp = _emit_LP(1, buf, 0, 0);
1302 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1303
1304 lpend.cond = ALWAYS;
1305 lpend.forever = false;
1306 lpend.loop = 0;
1307 lpend.bjump = 0;
1308 szlpend = _emit_LPEND(1, buf, &lpend);
1309
1310 if (lcnt0) {
1311 szlp *= 2;
1312 szlpend *= 2;
1313 }
1314
1315 /*
1316 * Max bursts that we can unroll due to limit on the
1317 * size of backward jump that can be encoded in DMALPEND
1318 * which is 8-bits and hence 255
1319 */
1320 cycmax = (255 - (szlp + szlpend)) / szbrst;
1321
1322 cyc = (cycmax < cyc) ? cycmax : cyc;
1323
1324 off = 0;
1325
1326 if (lcnt0) {
1327 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1328 ljmp0 = off;
1329 }
1330
1331 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1332 ljmp1 = off;
1333
1334 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1335
1336 lpend.cond = ALWAYS;
1337 lpend.forever = false;
1338 lpend.loop = 1;
1339 lpend.bjump = off - ljmp1;
1340 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1341
1342 if (lcnt0) {
1343 lpend.cond = ALWAYS;
1344 lpend.forever = false;
1345 lpend.loop = 0;
1346 lpend.bjump = off - ljmp0;
1347 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1348 }
1349
1350 *bursts = lcnt1 * cyc;
1351 if (lcnt0)
1352 *bursts *= lcnt0;
1353
1354 return off;
1355}
1356
1357static inline int _setup_loops(struct pl330_dmac *pl330,
1358 unsigned dry_run, u8 buf[],
1359 const struct _xfer_spec *pxs)
1360{
1361 struct pl330_xfer *x = &pxs->desc->px;
1362 u32 ccr = pxs->ccr;
1363 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1364 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
1365 BRST_SIZE(ccr);
1366 int off = 0;
1367
1368 while (bursts) {
1369 c = bursts;
1370 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1371 bursts -= c;
1372 }
1373 off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1374
1375 return off;
1376}
1377
1378static inline int _setup_xfer(struct pl330_dmac *pl330,
1379 unsigned dry_run, u8 buf[],
1380 const struct _xfer_spec *pxs)
1381{
1382 struct pl330_xfer *x = &pxs->desc->px;
1383 int off = 0;
1384
1385 /* DMAMOV SAR, x->src_addr */
1386 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1387 /* DMAMOV DAR, x->dst_addr */
1388 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1389
1390 /* Setup Loop(s) */
1391 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1392
1393 return off;
1394}
1395
1396/*
1397 * A req is a sequence of one or more xfer units.
1398 * Returns the number of bytes taken to setup the MC for the req.
1399 */
1400static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1401 struct pl330_thread *thrd, unsigned index,
1402 struct _xfer_spec *pxs)
1403{
1404 struct _pl330_req *req = &thrd->req[index];
1405 u8 *buf = req->mc_cpu;
1406 int off = 0;
1407
1408 PL330_DBGMC_START(req->mc_bus);
1409
1410 /* DMAMOV CCR, ccr */
1411 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1412
1413 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1414
1415 /* DMASEV peripheral/event */
1416 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1417 /* DMAEND */
1418 off += _emit_END(dry_run, &buf[off]);
1419
1420 return off;
1421}
1422
1423static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1424{
1425 u32 ccr = 0;
1426
1427 if (rqc->src_inc)
1428 ccr |= CC_SRCINC;
1429
1430 if (rqc->dst_inc)
1431 ccr |= CC_DSTINC;
1432
1433 /* We set same protection levels for Src and DST for now */
1434 if (rqc->privileged)
1435 ccr |= CC_SRCPRI | CC_DSTPRI;
1436 if (rqc->nonsecure)
1437 ccr |= CC_SRCNS | CC_DSTNS;
1438 if (rqc->insnaccess)
1439 ccr |= CC_SRCIA | CC_DSTIA;
1440
1441 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1442 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1443
1444 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1445 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1446
1447 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1448 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1449
1450 ccr |= (rqc->swap << CC_SWAP_SHFT);
1451
1452 return ccr;
1453}
1454
1455/*
1456 * Submit a list of xfers after which the client wants notification.
1457 * Client is not notified after each xfer unit, just once after all
1458 * xfer units are done or some error occurs.
1459 */
1460static int pl330_submit_req(struct pl330_thread *thrd,
1461 struct dma_pl330_desc *desc)
1462{
1463 struct pl330_dmac *pl330 = thrd->dmac;
1464 struct _xfer_spec xs;
1465 unsigned long flags;
1466 unsigned idx;
1467 u32 ccr;
1468 int ret = 0;
1469
1470 switch (desc->rqtype) {
1471 case DMA_MEM_TO_DEV:
1472 break;
1473
1474 case DMA_DEV_TO_MEM:
1475 break;
1476
1477 case DMA_MEM_TO_MEM:
1478 break;
1479
1480 default:
1481 return -ENOTSUPP;
1482 }
1483
1484 if (pl330->state == DYING
1485 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1486 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1487 __func__, __LINE__);
1488 return -EAGAIN;
1489 }
1490
1491 /* If request for non-existing peripheral */
1492 if (desc->rqtype != DMA_MEM_TO_MEM &&
1493 desc->peri >= pl330->pcfg.num_peri) {
1494 dev_info(thrd->dmac->ddma.dev,
1495 "%s:%d Invalid peripheral(%u)!\n",
1496 __func__, __LINE__, desc->peri);
1497 return -EINVAL;
1498 }
1499
1500 spin_lock_irqsave(&pl330->lock, flags);
1501
1502 if (_queue_full(thrd)) {
1503 ret = -EAGAIN;
1504 goto xfer_exit;
1505 }
1506
1507 /* Prefer Secure Channel */
1508 if (!_manager_ns(thrd))
1509 desc->rqcfg.nonsecure = 0;
1510 else
1511 desc->rqcfg.nonsecure = 1;
1512
1513 ccr = _prepare_ccr(&desc->rqcfg);
1514
1515 idx = thrd->req[0].desc == NULL ? 0 : 1;
1516
1517 xs.ccr = ccr;
1518 xs.desc = desc;
1519
1520 /* First dry run to check if req is acceptable */
1521 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1522 if (ret < 0)
1523 goto xfer_exit;
1524
1525 if (ret > pl330->mcbufsz / 2) {
1526 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1527 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1528 ret = -ENOMEM;
1529 goto xfer_exit;
1530 }
1531
1532 /* Hook the request */
1533 thrd->lstenq = idx;
1534 thrd->req[idx].desc = desc;
1535 _setup_req(pl330, 0, thrd, idx, &xs);
1536
1537 ret = 0;
1538
1539xfer_exit:
1540 spin_unlock_irqrestore(&pl330->lock, flags);
1541
1542 return ret;
1543}
1544
1545static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1546{
1547 struct dma_pl330_chan *pch;
1548 unsigned long flags;
1549
1550 if (!desc)
1551 return;
1552
1553 pch = desc->pchan;
1554
1555 /* If desc aborted */
1556 if (!pch)
1557 return;
1558
1559 spin_lock_irqsave(&pch->lock, flags);
1560
1561 desc->status = DONE;
1562
1563 spin_unlock_irqrestore(&pch->lock, flags);
1564
1565 tasklet_schedule(&pch->task);
1566}
1567
1568static void pl330_dotask(unsigned long data)
1569{
1570 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1571 unsigned long flags;
1572 int i;
1573
1574 spin_lock_irqsave(&pl330->lock, flags);
1575
1576 /* The DMAC itself gone nuts */
1577 if (pl330->dmac_tbd.reset_dmac) {
1578 pl330->state = DYING;
1579 /* Reset the manager too */
1580 pl330->dmac_tbd.reset_mngr = true;
1581 /* Clear the reset flag */
1582 pl330->dmac_tbd.reset_dmac = false;
1583 }
1584
1585 if (pl330->dmac_tbd.reset_mngr) {
1586 _stop(pl330->manager);
1587 /* Reset all channels */
1588 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1589 /* Clear the reset flag */
1590 pl330->dmac_tbd.reset_mngr = false;
1591 }
1592
1593 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1594
1595 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1596 struct pl330_thread *thrd = &pl330->channels[i];
1597 void __iomem *regs = pl330->base;
1598 enum pl330_op_err err;
1599
1600 _stop(thrd);
1601
1602 if (readl(regs + FSC) & (1 << thrd->id))
1603 err = PL330_ERR_FAIL;
1604 else
1605 err = PL330_ERR_ABORT;
1606
1607 spin_unlock_irqrestore(&pl330->lock, flags);
1608 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1609 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1610 spin_lock_irqsave(&pl330->lock, flags);
1611
1612 thrd->req[0].desc = NULL;
1613 thrd->req[1].desc = NULL;
1614 thrd->req_running = -1;
1615
1616 /* Clear the reset flag */
1617 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1618 }
1619 }
1620
1621 spin_unlock_irqrestore(&pl330->lock, flags);
1622
1623 return;
1624}
1625
1626/* Returns 1 if state was updated, 0 otherwise */
1627static int pl330_update(struct pl330_dmac *pl330)
1628{
1629 struct dma_pl330_desc *descdone;
1630 unsigned long flags;
1631 void __iomem *regs;
1632 u32 val;
1633 int id, ev, ret = 0;
1634
1635 regs = pl330->base;
1636
1637 spin_lock_irqsave(&pl330->lock, flags);
1638
1639 val = readl(regs + FSM) & 0x1;
1640 if (val)
1641 pl330->dmac_tbd.reset_mngr = true;
1642 else
1643 pl330->dmac_tbd.reset_mngr = false;
1644
1645 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1646 pl330->dmac_tbd.reset_chan |= val;
1647 if (val) {
1648 int i = 0;
1649 while (i < pl330->pcfg.num_chan) {
1650 if (val & (1 << i)) {
1651 dev_info(pl330->ddma.dev,
1652 "Reset Channel-%d\t CS-%x FTC-%x\n",
1653 i, readl(regs + CS(i)),
1654 readl(regs + FTC(i)));
1655 _stop(&pl330->channels[i]);
1656 }
1657 i++;
1658 }
1659 }
1660
1661 /* Check which event happened i.e, thread notified */
1662 val = readl(regs + ES);
1663 if (pl330->pcfg.num_events < 32
1664 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1665 pl330->dmac_tbd.reset_dmac = true;
1666 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1667 __LINE__);
1668 ret = 1;
1669 goto updt_exit;
1670 }
1671
1672 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1673 if (val & (1 << ev)) { /* Event occurred */
1674 struct pl330_thread *thrd;
1675 u32 inten = readl(regs + INTEN);
1676 int active;
1677
1678 /* Clear the event */
1679 if (inten & (1 << ev))
1680 writel(1 << ev, regs + INTCLR);
1681
1682 ret = 1;
1683
1684 id = pl330->events[ev];
1685
1686 thrd = &pl330->channels[id];
1687
1688 active = thrd->req_running;
1689 if (active == -1) /* Aborted */
1690 continue;
1691
1692 /* Detach the req */
1693 descdone = thrd->req[active].desc;
1694 thrd->req[active].desc = NULL;
1695
1696 thrd->req_running = -1;
1697
1698 /* Get going again ASAP */
1699 _start(thrd);
1700
1701 /* For now, just make a list of callbacks to be done */
1702 list_add_tail(&descdone->rqd, &pl330->req_done);
1703 }
1704 }
1705
1706 /* Now that we are in no hurry, do the callbacks */
1707 while (!list_empty(&pl330->req_done)) {
1708 descdone = list_first_entry(&pl330->req_done,
1709 struct dma_pl330_desc, rqd);
1710 list_del(&descdone->rqd);
1711 spin_unlock_irqrestore(&pl330->lock, flags);
1712 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1713 spin_lock_irqsave(&pl330->lock, flags);
1714 }
1715
1716updt_exit:
1717 spin_unlock_irqrestore(&pl330->lock, flags);
1718
1719 if (pl330->dmac_tbd.reset_dmac
1720 || pl330->dmac_tbd.reset_mngr
1721 || pl330->dmac_tbd.reset_chan) {
1722 ret = 1;
1723 tasklet_schedule(&pl330->tasks);
1724 }
1725
1726 return ret;
1727}
1728
1729/* Reserve an event */
1730static inline int _alloc_event(struct pl330_thread *thrd)
1731{
1732 struct pl330_dmac *pl330 = thrd->dmac;
1733 int ev;
1734
1735 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1736 if (pl330->events[ev] == -1) {
1737 pl330->events[ev] = thrd->id;
1738 return ev;
1739 }
1740
1741 return -1;
1742}
1743
1744static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1745{
1746 return pl330->pcfg.irq_ns & (1 << i);
1747}
1748
1749/* Upon success, returns IdentityToken for the
1750 * allocated channel, NULL otherwise.
1751 */
1752static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1753{
1754 struct pl330_thread *thrd = NULL;
1755 int chans, i;
1756
1757 if (pl330->state == DYING)
1758 return NULL;
1759
1760 chans = pl330->pcfg.num_chan;
1761
1762 for (i = 0; i < chans; i++) {
1763 thrd = &pl330->channels[i];
1764 if ((thrd->free) && (!_manager_ns(thrd) ||
1765 _chan_ns(pl330, i))) {
1766 thrd->ev = _alloc_event(thrd);
1767 if (thrd->ev >= 0) {
1768 thrd->free = false;
1769 thrd->lstenq = 1;
1770 thrd->req[0].desc = NULL;
1771 thrd->req[1].desc = NULL;
1772 thrd->req_running = -1;
1773 break;
1774 }
1775 }
1776 thrd = NULL;
1777 }
1778
1779 return thrd;
1780}
1781
1782/* Release an event */
1783static inline void _free_event(struct pl330_thread *thrd, int ev)
1784{
1785 struct pl330_dmac *pl330 = thrd->dmac;
1786
1787 /* If the event is valid and was held by the thread */
1788 if (ev >= 0 && ev < pl330->pcfg.num_events
1789 && pl330->events[ev] == thrd->id)
1790 pl330->events[ev] = -1;
1791}
1792
1793static void pl330_release_channel(struct pl330_thread *thrd)
1794{
1795 if (!thrd || thrd->free)
1796 return;
1797
1798 _stop(thrd);
1799
1800 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1801 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1802
1803 _free_event(thrd, thrd->ev);
1804 thrd->free = true;
1805}
1806
1807/* Initialize the structure for PL330 configuration, that can be used
1808 * by the client driver the make best use of the DMAC
1809 */
1810static void read_dmac_config(struct pl330_dmac *pl330)
1811{
1812 void __iomem *regs = pl330->base;
1813 u32 val;
1814
1815 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1816 val &= CRD_DATA_WIDTH_MASK;
1817 pl330->pcfg.data_bus_width = 8 * (1 << val);
1818
1819 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1820 val &= CRD_DATA_BUFF_MASK;
1821 pl330->pcfg.data_buf_dep = val + 1;
1822
1823 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1824 val &= CR0_NUM_CHANS_MASK;
1825 val += 1;
1826 pl330->pcfg.num_chan = val;
1827
1828 val = readl(regs + CR0);
1829 if (val & CR0_PERIPH_REQ_SET) {
1830 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1831 val += 1;
1832 pl330->pcfg.num_peri = val;
1833 pl330->pcfg.peri_ns = readl(regs + CR4);
1834 } else {
1835 pl330->pcfg.num_peri = 0;
1836 }
1837
1838 val = readl(regs + CR0);
1839 if (val & CR0_BOOT_MAN_NS)
1840 pl330->pcfg.mode |= DMAC_MODE_NS;
1841 else
1842 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1843
1844 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1845 val &= CR0_NUM_EVENTS_MASK;
1846 val += 1;
1847 pl330->pcfg.num_events = val;
1848
1849 pl330->pcfg.irq_ns = readl(regs + CR3);
1850}
1851
1852static inline void _reset_thread(struct pl330_thread *thrd)
1853{
1854 struct pl330_dmac *pl330 = thrd->dmac;
1855
1856 thrd->req[0].mc_cpu = pl330->mcode_cpu
1857 + (thrd->id * pl330->mcbufsz);
1858 thrd->req[0].mc_bus = pl330->mcode_bus
1859 + (thrd->id * pl330->mcbufsz);
1860 thrd->req[0].desc = NULL;
1861
1862 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1863 + pl330->mcbufsz / 2;
1864 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1865 + pl330->mcbufsz / 2;
1866 thrd->req[1].desc = NULL;
1867
1868 thrd->req_running = -1;
1869}
1870
1871static int dmac_alloc_threads(struct pl330_dmac *pl330)
1872{
1873 int chans = pl330->pcfg.num_chan;
1874 struct pl330_thread *thrd;
1875 int i;
1876
1877 /* Allocate 1 Manager and 'chans' Channel threads */
1878 pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
1879 GFP_KERNEL);
1880 if (!pl330->channels)
1881 return -ENOMEM;
1882
1883 /* Init Channel threads */
1884 for (i = 0; i < chans; i++) {
1885 thrd = &pl330->channels[i];
1886 thrd->id = i;
1887 thrd->dmac = pl330;
1888 _reset_thread(thrd);
1889 thrd->free = true;
1890 }
1891
1892 /* MANAGER is indexed at the end */
1893 thrd = &pl330->channels[chans];
1894 thrd->id = chans;
1895 thrd->dmac = pl330;
1896 thrd->free = false;
1897 pl330->manager = thrd;
1898
1899 return 0;
1900}
1901
1902static int dmac_alloc_resources(struct pl330_dmac *pl330)
1903{
1904 int chans = pl330->pcfg.num_chan;
1905 int ret;
1906
1907 /*
1908 * Alloc MicroCode buffer for 'chans' Channel threads.
1909 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1910 */
1911 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1912 chans * pl330->mcbufsz,
1913 &pl330->mcode_bus, GFP_KERNEL,
1914 DMA_ATTR_PRIVILEGED);
1915 if (!pl330->mcode_cpu) {
1916 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1917 __func__, __LINE__);
1918 return -ENOMEM;
1919 }
1920
1921 ret = dmac_alloc_threads(pl330);
1922 if (ret) {
1923 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1924 __func__, __LINE__);
1925 dma_free_attrs(pl330->ddma.dev,
1926 chans * pl330->mcbufsz,
1927 pl330->mcode_cpu, pl330->mcode_bus,
1928 DMA_ATTR_PRIVILEGED);
1929 return ret;
1930 }
1931
1932 return 0;
1933}
1934
1935static int pl330_add(struct pl330_dmac *pl330)
1936{
1937 int i, ret;
1938
1939 /* Check if we can handle this DMAC */
1940 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1941 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1942 pl330->pcfg.periph_id);
1943 return -EINVAL;
1944 }
1945
1946 /* Read the configuration of the DMAC */
1947 read_dmac_config(pl330);
1948
1949 if (pl330->pcfg.num_events == 0) {
1950 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1951 __func__, __LINE__);
1952 return -EINVAL;
1953 }
1954
1955 spin_lock_init(&pl330->lock);
1956
1957 INIT_LIST_HEAD(&pl330->req_done);
1958
1959 /* Use default MC buffer size if not provided */
1960 if (!pl330->mcbufsz)
1961 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1962
1963 /* Mark all events as free */
1964 for (i = 0; i < pl330->pcfg.num_events; i++)
1965 pl330->events[i] = -1;
1966
1967 /* Allocate resources needed by the DMAC */
1968 ret = dmac_alloc_resources(pl330);
1969 if (ret) {
1970 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1971 return ret;
1972 }
1973
1974 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1975
1976 pl330->state = INIT;
1977
1978 return 0;
1979}
1980
1981static int dmac_free_threads(struct pl330_dmac *pl330)
1982{
1983 struct pl330_thread *thrd;
1984 int i;
1985
1986 /* Release Channel threads */
1987 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1988 thrd = &pl330->channels[i];
1989 pl330_release_channel(thrd);
1990 }
1991
1992 /* Free memory */
1993 kfree(pl330->channels);
1994
1995 return 0;
1996}
1997
1998static void pl330_del(struct pl330_dmac *pl330)
1999{
2000 pl330->state = UNINIT;
2001
2002 tasklet_kill(&pl330->tasks);
2003
2004 /* Free DMAC resources */
2005 dmac_free_threads(pl330);
2006
2007 dma_free_attrs(pl330->ddma.dev,
2008 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2009 pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
2010}
2011
2012/* forward declaration */
2013static struct amba_driver pl330_driver;
2014
2015static inline struct dma_pl330_chan *
2016to_pchan(struct dma_chan *ch)
2017{
2018 if (!ch)
2019 return NULL;
2020
2021 return container_of(ch, struct dma_pl330_chan, chan);
2022}
2023
2024static inline struct dma_pl330_desc *
2025to_desc(struct dma_async_tx_descriptor *tx)
2026{
2027 return container_of(tx, struct dma_pl330_desc, txd);
2028}
2029
2030static inline void fill_queue(struct dma_pl330_chan *pch)
2031{
2032 struct dma_pl330_desc *desc;
2033 int ret;
2034
2035 list_for_each_entry(desc, &pch->work_list, node) {
2036
2037 /* If already submitted */
2038 if (desc->status == BUSY)
2039 continue;
2040
2041 ret = pl330_submit_req(pch->thread, desc);
2042 if (!ret) {
2043 desc->status = BUSY;
2044 } else if (ret == -EAGAIN) {
2045 /* QFull or DMAC Dying */
2046 break;
2047 } else {
2048 /* Unacceptable request */
2049 desc->status = DONE;
2050 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2051 __func__, __LINE__, desc->txd.cookie);
2052 tasklet_schedule(&pch->task);
2053 }
2054 }
2055}
2056
2057static void pl330_tasklet(unsigned long data)
2058{
2059 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2060 struct dma_pl330_desc *desc, *_dt;
2061 unsigned long flags;
2062 bool power_down = false;
2063
2064 spin_lock_irqsave(&pch->lock, flags);
2065
2066 /* Pick up ripe tomatoes */
2067 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2068 if (desc->status == DONE) {
2069 if (!pch->cyclic)
2070 dma_cookie_complete(&desc->txd);
2071 list_move_tail(&desc->node, &pch->completed_list);
2072 }
2073
2074 /* Try to submit a req imm. next to the last completed cookie */
2075 fill_queue(pch);
2076
2077 if (list_empty(&pch->work_list)) {
2078 spin_lock(&pch->thread->dmac->lock);
2079 _stop(pch->thread);
2080 spin_unlock(&pch->thread->dmac->lock);
2081 power_down = true;
2082 pch->active = false;
2083 } else {
2084 /* Make sure the PL330 Channel thread is active */
2085 spin_lock(&pch->thread->dmac->lock);
2086 _start(pch->thread);
2087 spin_unlock(&pch->thread->dmac->lock);
2088 }
2089
2090 while (!list_empty(&pch->completed_list)) {
2091 struct dmaengine_desc_callback cb;
2092
2093 desc = list_first_entry(&pch->completed_list,
2094 struct dma_pl330_desc, node);
2095
2096 dmaengine_desc_get_callback(&desc->txd, &cb);
2097
2098 if (pch->cyclic) {
2099 desc->status = PREP;
2100 list_move_tail(&desc->node, &pch->work_list);
2101 if (power_down) {
2102 pch->active = true;
2103 spin_lock(&pch->thread->dmac->lock);
2104 _start(pch->thread);
2105 spin_unlock(&pch->thread->dmac->lock);
2106 power_down = false;
2107 }
2108 } else {
2109 desc->status = FREE;
2110 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2111 }
2112
2113 dma_descriptor_unmap(&desc->txd);
2114
2115 if (dmaengine_desc_callback_valid(&cb)) {
2116 spin_unlock_irqrestore(&pch->lock, flags);
2117 dmaengine_desc_callback_invoke(&cb, NULL);
2118 spin_lock_irqsave(&pch->lock, flags);
2119 }
2120 }
2121 spin_unlock_irqrestore(&pch->lock, flags);
2122
2123 /* If work list empty, power down */
2124 if (power_down) {
2125 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2126 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2127 }
2128}
2129
2130static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2131 struct of_dma *ofdma)
2132{
2133 int count = dma_spec->args_count;
2134 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2135 unsigned int chan_id;
2136
2137 if (!pl330)
2138 return NULL;
2139
2140 if (count != 1)
2141 return NULL;
2142
2143 chan_id = dma_spec->args[0];
2144 if (chan_id >= pl330->num_peripherals)
2145 return NULL;
2146
2147 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2148}
2149
2150static int pl330_alloc_chan_resources(struct dma_chan *chan)
2151{
2152 struct dma_pl330_chan *pch = to_pchan(chan);
2153 struct pl330_dmac *pl330 = pch->dmac;
2154 unsigned long flags;
2155
2156 spin_lock_irqsave(&pl330->lock, flags);
2157
2158 dma_cookie_init(chan);
2159 pch->cyclic = false;
2160
2161 pch->thread = pl330_request_channel(pl330);
2162 if (!pch->thread) {
2163 spin_unlock_irqrestore(&pl330->lock, flags);
2164 return -ENOMEM;
2165 }
2166
2167 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2168
2169 spin_unlock_irqrestore(&pl330->lock, flags);
2170
2171 return 1;
2172}
2173
2174/*
2175 * We need the data direction between the DMAC (the dma-mapping "device") and
2176 * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
2177 */
2178static enum dma_data_direction
2179pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2180{
2181 switch (dir) {
2182 case DMA_MEM_TO_DEV:
2183 return DMA_FROM_DEVICE;
2184 case DMA_DEV_TO_MEM:
2185 return DMA_TO_DEVICE;
2186 case DMA_DEV_TO_DEV:
2187 return DMA_BIDIRECTIONAL;
2188 default:
2189 return DMA_NONE;
2190 }
2191}
2192
2193static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2194{
2195 if (pch->dir != DMA_NONE)
2196 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2197 1 << pch->burst_sz, pch->dir, 0);
2198 pch->dir = DMA_NONE;
2199}
2200
2201
2202static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2203 enum dma_transfer_direction dir)
2204{
2205 struct device *dev = pch->chan.device->dev;
2206 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2207
2208 /* Already mapped for this config? */
2209 if (pch->dir == dma_dir)
2210 return true;
2211
2212 pl330_unprep_slave_fifo(pch);
2213 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2214 1 << pch->burst_sz, dma_dir, 0);
2215 if (dma_mapping_error(dev, pch->fifo_dma))
2216 return false;
2217
2218 pch->dir = dma_dir;
2219 return true;
2220}
2221
2222static int fixup_burst_len(int max_burst_len, int quirks)
2223{
2224 if (quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
2225 return 1;
2226 else if (max_burst_len > PL330_MAX_BURST)
2227 return PL330_MAX_BURST;
2228 else if (max_burst_len < 1)
2229 return 1;
2230 else
2231 return max_burst_len;
2232}
2233
2234static int pl330_config_write(struct dma_chan *chan,
2235 struct dma_slave_config *slave_config,
2236 enum dma_transfer_direction direction)
2237{
2238 struct dma_pl330_chan *pch = to_pchan(chan);
2239
2240 pl330_unprep_slave_fifo(pch);
2241 if (direction == DMA_MEM_TO_DEV) {
2242 if (slave_config->dst_addr)
2243 pch->fifo_addr = slave_config->dst_addr;
2244 if (slave_config->dst_addr_width)
2245 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2246 pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
2247 pch->dmac->quirks);
2248 } else if (direction == DMA_DEV_TO_MEM) {
2249 if (slave_config->src_addr)
2250 pch->fifo_addr = slave_config->src_addr;
2251 if (slave_config->src_addr_width)
2252 pch->burst_sz = __ffs(slave_config->src_addr_width);
2253 pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
2254 pch->dmac->quirks);
2255 }
2256
2257 return 0;
2258}
2259
2260static int pl330_config(struct dma_chan *chan,
2261 struct dma_slave_config *slave_config)
2262{
2263 struct dma_pl330_chan *pch = to_pchan(chan);
2264
2265 memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
2266
2267 return 0;
2268}
2269
2270static int pl330_terminate_all(struct dma_chan *chan)
2271{
2272 struct dma_pl330_chan *pch = to_pchan(chan);
2273 struct dma_pl330_desc *desc;
2274 unsigned long flags;
2275 struct pl330_dmac *pl330 = pch->dmac;
2276 bool power_down = false;
2277
2278 pm_runtime_get_sync(pl330->ddma.dev);
2279 spin_lock_irqsave(&pch->lock, flags);
2280
2281 spin_lock(&pl330->lock);
2282 _stop(pch->thread);
2283 pch->thread->req[0].desc = NULL;
2284 pch->thread->req[1].desc = NULL;
2285 pch->thread->req_running = -1;
2286 spin_unlock(&pl330->lock);
2287
2288 power_down = pch->active;
2289 pch->active = false;
2290
2291 /* Mark all desc done */
2292 list_for_each_entry(desc, &pch->submitted_list, node) {
2293 desc->status = FREE;
2294 dma_cookie_complete(&desc->txd);
2295 }
2296
2297 list_for_each_entry(desc, &pch->work_list , node) {
2298 desc->status = FREE;
2299 dma_cookie_complete(&desc->txd);
2300 }
2301
2302 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2303 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2304 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2305 spin_unlock_irqrestore(&pch->lock, flags);
2306 pm_runtime_mark_last_busy(pl330->ddma.dev);
2307 if (power_down)
2308 pm_runtime_put_autosuspend(pl330->ddma.dev);
2309 pm_runtime_put_autosuspend(pl330->ddma.dev);
2310
2311 return 0;
2312}
2313
2314/*
2315 * We don't support DMA_RESUME command because of hardware
2316 * limitations, so after pausing the channel we cannot restore
2317 * it to active state. We have to terminate channel and setup
2318 * DMA transfer again. This pause feature was implemented to
2319 * allow safely read residue before channel termination.
2320 */
2321static int pl330_pause(struct dma_chan *chan)
2322{
2323 struct dma_pl330_chan *pch = to_pchan(chan);
2324 struct pl330_dmac *pl330 = pch->dmac;
2325 unsigned long flags;
2326
2327 pm_runtime_get_sync(pl330->ddma.dev);
2328 spin_lock_irqsave(&pch->lock, flags);
2329
2330 spin_lock(&pl330->lock);
2331 _stop(pch->thread);
2332 spin_unlock(&pl330->lock);
2333
2334 spin_unlock_irqrestore(&pch->lock, flags);
2335 pm_runtime_mark_last_busy(pl330->ddma.dev);
2336 pm_runtime_put_autosuspend(pl330->ddma.dev);
2337
2338 return 0;
2339}
2340
2341static void pl330_free_chan_resources(struct dma_chan *chan)
2342{
2343 struct dma_pl330_chan *pch = to_pchan(chan);
2344 struct pl330_dmac *pl330 = pch->dmac;
2345 unsigned long flags;
2346
2347 tasklet_kill(&pch->task);
2348
2349 pm_runtime_get_sync(pch->dmac->ddma.dev);
2350 spin_lock_irqsave(&pl330->lock, flags);
2351
2352 pl330_release_channel(pch->thread);
2353 pch->thread = NULL;
2354
2355 if (pch->cyclic)
2356 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2357
2358 spin_unlock_irqrestore(&pl330->lock, flags);
2359 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2360 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2361 pl330_unprep_slave_fifo(pch);
2362}
2363
2364static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2365 struct dma_pl330_desc *desc)
2366{
2367 struct pl330_thread *thrd = pch->thread;
2368 struct pl330_dmac *pl330 = pch->dmac;
2369 void __iomem *regs = thrd->dmac->base;
2370 u32 val, addr;
2371
2372 pm_runtime_get_sync(pl330->ddma.dev);
2373 val = addr = 0;
2374 if (desc->rqcfg.src_inc) {
2375 val = readl(regs + SA(thrd->id));
2376 addr = desc->px.src_addr;
2377 } else {
2378 val = readl(regs + DA(thrd->id));
2379 addr = desc->px.dst_addr;
2380 }
2381 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2382 pm_runtime_put_autosuspend(pl330->ddma.dev);
2383
2384 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2385 if (!val)
2386 return 0;
2387
2388 return val - addr;
2389}
2390
2391static enum dma_status
2392pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2393 struct dma_tx_state *txstate)
2394{
2395 enum dma_status ret;
2396 unsigned long flags;
2397 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2398 struct dma_pl330_chan *pch = to_pchan(chan);
2399 unsigned int transferred, residual = 0;
2400
2401 ret = dma_cookie_status(chan, cookie, txstate);
2402
2403 if (!txstate)
2404 return ret;
2405
2406 if (ret == DMA_COMPLETE)
2407 goto out;
2408
2409 spin_lock_irqsave(&pch->lock, flags);
2410 spin_lock(&pch->thread->dmac->lock);
2411
2412 if (pch->thread->req_running != -1)
2413 running = pch->thread->req[pch->thread->req_running].desc;
2414
2415 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2416
2417 /* Check in pending list */
2418 list_for_each_entry(desc, &pch->work_list, node) {
2419 if (desc->status == DONE)
2420 transferred = desc->bytes_requested;
2421 else if (running && desc == running)
2422 transferred =
2423 pl330_get_current_xferred_count(pch, desc);
2424 else if (desc->status == BUSY)
2425 /*
2426 * Busy but not running means either just enqueued,
2427 * or finished and not yet marked done
2428 */
2429 if (desc == last_enq)
2430 transferred = 0;
2431 else
2432 transferred = desc->bytes_requested;
2433 else
2434 transferred = 0;
2435 residual += desc->bytes_requested - transferred;
2436 if (desc->txd.cookie == cookie) {
2437 switch (desc->status) {
2438 case DONE:
2439 ret = DMA_COMPLETE;
2440 break;
2441 case PREP:
2442 case BUSY:
2443 ret = DMA_IN_PROGRESS;
2444 break;
2445 default:
2446 WARN_ON(1);
2447 }
2448 break;
2449 }
2450 if (desc->last)
2451 residual = 0;
2452 }
2453 spin_unlock(&pch->thread->dmac->lock);
2454 spin_unlock_irqrestore(&pch->lock, flags);
2455
2456out:
2457 dma_set_residue(txstate, residual);
2458
2459 return ret;
2460}
2461
2462static void pl330_issue_pending(struct dma_chan *chan)
2463{
2464 struct dma_pl330_chan *pch = to_pchan(chan);
2465 unsigned long flags;
2466
2467 spin_lock_irqsave(&pch->lock, flags);
2468 if (list_empty(&pch->work_list)) {
2469 /*
2470 * Warn on nothing pending. Empty submitted_list may
2471 * break our pm_runtime usage counter as it is
2472 * updated on work_list emptiness status.
2473 */
2474 WARN_ON(list_empty(&pch->submitted_list));
2475 pch->active = true;
2476 pm_runtime_get_sync(pch->dmac->ddma.dev);
2477 }
2478 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2479 spin_unlock_irqrestore(&pch->lock, flags);
2480
2481 pl330_tasklet((unsigned long)pch);
2482}
2483
2484/*
2485 * We returned the last one of the circular list of descriptor(s)
2486 * from prep_xxx, so the argument to submit corresponds to the last
2487 * descriptor of the list.
2488 */
2489static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2490{
2491 struct dma_pl330_desc *desc, *last = to_desc(tx);
2492 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2493 dma_cookie_t cookie;
2494 unsigned long flags;
2495
2496 spin_lock_irqsave(&pch->lock, flags);
2497
2498 /* Assign cookies to all nodes */
2499 while (!list_empty(&last->node)) {
2500 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2501 if (pch->cyclic) {
2502 desc->txd.callback = last->txd.callback;
2503 desc->txd.callback_param = last->txd.callback_param;
2504 }
2505 desc->last = false;
2506
2507 dma_cookie_assign(&desc->txd);
2508
2509 list_move_tail(&desc->node, &pch->submitted_list);
2510 }
2511
2512 last->last = true;
2513 cookie = dma_cookie_assign(&last->txd);
2514 list_add_tail(&last->node, &pch->submitted_list);
2515 spin_unlock_irqrestore(&pch->lock, flags);
2516
2517 return cookie;
2518}
2519
2520static inline void _init_desc(struct dma_pl330_desc *desc)
2521{
2522 desc->rqcfg.swap = SWAP_NO;
2523 desc->rqcfg.scctl = CCTRL0;
2524 desc->rqcfg.dcctl = CCTRL0;
2525 desc->txd.tx_submit = pl330_tx_submit;
2526
2527 INIT_LIST_HEAD(&desc->node);
2528}
2529
2530/* Returns the number of descriptors added to the DMAC pool */
2531static int add_desc(struct list_head *pool, spinlock_t *lock,
2532 gfp_t flg, int count)
2533{
2534 struct dma_pl330_desc *desc;
2535 unsigned long flags;
2536 int i;
2537
2538 desc = kcalloc(count, sizeof(*desc), flg);
2539 if (!desc)
2540 return 0;
2541
2542 spin_lock_irqsave(lock, flags);
2543
2544 for (i = 0; i < count; i++) {
2545 _init_desc(&desc[i]);
2546 list_add_tail(&desc[i].node, pool);
2547 }
2548
2549 spin_unlock_irqrestore(lock, flags);
2550
2551 return count;
2552}
2553
2554static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
2555 spinlock_t *lock)
2556{
2557 struct dma_pl330_desc *desc = NULL;
2558 unsigned long flags;
2559
2560 spin_lock_irqsave(lock, flags);
2561
2562 if (!list_empty(pool)) {
2563 desc = list_entry(pool->next,
2564 struct dma_pl330_desc, node);
2565
2566 list_del_init(&desc->node);
2567
2568 desc->status = PREP;
2569 desc->txd.callback = NULL;
2570 }
2571
2572 spin_unlock_irqrestore(lock, flags);
2573
2574 return desc;
2575}
2576
2577static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2578{
2579 struct pl330_dmac *pl330 = pch->dmac;
2580 u8 *peri_id = pch->chan.private;
2581 struct dma_pl330_desc *desc;
2582
2583 /* Pluck one desc from the pool of DMAC */
2584 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2585
2586 /* If the DMAC pool is empty, alloc new */
2587 if (!desc) {
2588 DEFINE_SPINLOCK(lock);
2589 LIST_HEAD(pool);
2590
2591 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2592 return NULL;
2593
2594 desc = pluck_desc(&pool, &lock);
2595 WARN_ON(!desc || !list_empty(&pool));
2596 }
2597
2598 /* Initialize the descriptor */
2599 desc->pchan = pch;
2600 desc->txd.cookie = 0;
2601 async_tx_ack(&desc->txd);
2602
2603 desc->peri = peri_id ? pch->chan.chan_id : 0;
2604 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2605
2606 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2607
2608 return desc;
2609}
2610
2611static inline void fill_px(struct pl330_xfer *px,
2612 dma_addr_t dst, dma_addr_t src, size_t len)
2613{
2614 px->bytes = len;
2615 px->dst_addr = dst;
2616 px->src_addr = src;
2617}
2618
2619static struct dma_pl330_desc *
2620__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2621 dma_addr_t src, size_t len)
2622{
2623 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2624
2625 if (!desc) {
2626 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2627 __func__, __LINE__);
2628 return NULL;
2629 }
2630
2631 /*
2632 * Ideally we should lookout for reqs bigger than
2633 * those that can be programmed with 256 bytes of
2634 * MC buffer, but considering a req size is seldom
2635 * going to be word-unaligned and more than 200MB,
2636 * we take it easy.
2637 * Also, should the limit is reached we'd rather
2638 * have the platform increase MC buffer size than
2639 * complicating this API driver.
2640 */
2641 fill_px(&desc->px, dst, src, len);
2642
2643 return desc;
2644}
2645
2646/* Call after fixing burst size */
2647static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2648{
2649 struct dma_pl330_chan *pch = desc->pchan;
2650 struct pl330_dmac *pl330 = pch->dmac;
2651 int burst_len;
2652
2653 burst_len = pl330->pcfg.data_bus_width / 8;
2654 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2655 burst_len >>= desc->rqcfg.brst_size;
2656
2657 /* src/dst_burst_len can't be more than 16 */
2658 if (burst_len > PL330_MAX_BURST)
2659 burst_len = PL330_MAX_BURST;
2660
2661 return burst_len;
2662}
2663
2664static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2665 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2666 size_t period_len, enum dma_transfer_direction direction,
2667 unsigned long flags)
2668{
2669 struct dma_pl330_desc *desc = NULL, *first = NULL;
2670 struct dma_pl330_chan *pch = to_pchan(chan);
2671 struct pl330_dmac *pl330 = pch->dmac;
2672 unsigned int i;
2673 dma_addr_t dst;
2674 dma_addr_t src;
2675
2676 if (len % period_len != 0)
2677 return NULL;
2678
2679 if (!is_slave_direction(direction)) {
2680 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2681 __func__, __LINE__);
2682 return NULL;
2683 }
2684
2685 pl330_config_write(chan, &pch->slave_config, direction);
2686
2687 if (!pl330_prep_slave_fifo(pch, direction))
2688 return NULL;
2689
2690 for (i = 0; i < len / period_len; i++) {
2691 desc = pl330_get_desc(pch);
2692 if (!desc) {
2693 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2694 __func__, __LINE__);
2695
2696 if (!first)
2697 return NULL;
2698
2699 spin_lock_irqsave(&pl330->pool_lock, flags);
2700
2701 while (!list_empty(&first->node)) {
2702 desc = list_entry(first->node.next,
2703 struct dma_pl330_desc, node);
2704 list_move_tail(&desc->node, &pl330->desc_pool);
2705 }
2706
2707 list_move_tail(&first->node, &pl330->desc_pool);
2708
2709 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2710
2711 return NULL;
2712 }
2713
2714 switch (direction) {
2715 case DMA_MEM_TO_DEV:
2716 desc->rqcfg.src_inc = 1;
2717 desc->rqcfg.dst_inc = 0;
2718 src = dma_addr;
2719 dst = pch->fifo_dma;
2720 break;
2721 case DMA_DEV_TO_MEM:
2722 desc->rqcfg.src_inc = 0;
2723 desc->rqcfg.dst_inc = 1;
2724 src = pch->fifo_dma;
2725 dst = dma_addr;
2726 break;
2727 default:
2728 break;
2729 }
2730
2731 desc->rqtype = direction;
2732 desc->rqcfg.brst_size = pch->burst_sz;
2733 desc->rqcfg.brst_len = pch->burst_len;
2734 desc->bytes_requested = period_len;
2735 fill_px(&desc->px, dst, src, period_len);
2736
2737 if (!first)
2738 first = desc;
2739 else
2740 list_add_tail(&desc->node, &first->node);
2741
2742 dma_addr += period_len;
2743 }
2744
2745 if (!desc)
2746 return NULL;
2747
2748 pch->cyclic = true;
2749 desc->txd.flags = flags;
2750
2751 return &desc->txd;
2752}
2753
2754static struct dma_async_tx_descriptor *
2755pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2756 dma_addr_t src, size_t len, unsigned long flags)
2757{
2758 struct dma_pl330_desc *desc;
2759 struct dma_pl330_chan *pch = to_pchan(chan);
2760 struct pl330_dmac *pl330;
2761 int burst;
2762
2763 if (unlikely(!pch || !len))
2764 return NULL;
2765
2766 pl330 = pch->dmac;
2767
2768 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2769 if (!desc)
2770 return NULL;
2771
2772 desc->rqcfg.src_inc = 1;
2773 desc->rqcfg.dst_inc = 1;
2774 desc->rqtype = DMA_MEM_TO_MEM;
2775
2776 /* Select max possible burst size */
2777 burst = pl330->pcfg.data_bus_width / 8;
2778
2779 /*
2780 * Make sure we use a burst size that aligns with all the memcpy
2781 * parameters because our DMA programming algorithm doesn't cope with
2782 * transfers which straddle an entry in the DMA device's MFIFO.
2783 */
2784 while ((src | dst | len) & (burst - 1))
2785 burst /= 2;
2786
2787 desc->rqcfg.brst_size = 0;
2788 while (burst != (1 << desc->rqcfg.brst_size))
2789 desc->rqcfg.brst_size++;
2790
2791 /*
2792 * If burst size is smaller than bus width then make sure we only
2793 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2794 */
2795 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2796 desc->rqcfg.brst_len = 1;
2797
2798 desc->rqcfg.brst_len = get_burst_len(desc, len);
2799 desc->bytes_requested = len;
2800
2801 desc->txd.flags = flags;
2802
2803 return &desc->txd;
2804}
2805
2806static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2807 struct dma_pl330_desc *first)
2808{
2809 unsigned long flags;
2810 struct dma_pl330_desc *desc;
2811
2812 if (!first)
2813 return;
2814
2815 spin_lock_irqsave(&pl330->pool_lock, flags);
2816
2817 while (!list_empty(&first->node)) {
2818 desc = list_entry(first->node.next,
2819 struct dma_pl330_desc, node);
2820 list_move_tail(&desc->node, &pl330->desc_pool);
2821 }
2822
2823 list_move_tail(&first->node, &pl330->desc_pool);
2824
2825 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2826}
2827
2828static struct dma_async_tx_descriptor *
2829pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2830 unsigned int sg_len, enum dma_transfer_direction direction,
2831 unsigned long flg, void *context)
2832{
2833 struct dma_pl330_desc *first, *desc = NULL;
2834 struct dma_pl330_chan *pch = to_pchan(chan);
2835 struct scatterlist *sg;
2836 int i;
2837
2838 if (unlikely(!pch || !sgl || !sg_len))
2839 return NULL;
2840
2841 pl330_config_write(chan, &pch->slave_config, direction);
2842
2843 if (!pl330_prep_slave_fifo(pch, direction))
2844 return NULL;
2845
2846 first = NULL;
2847
2848 for_each_sg(sgl, sg, sg_len, i) {
2849
2850 desc = pl330_get_desc(pch);
2851 if (!desc) {
2852 struct pl330_dmac *pl330 = pch->dmac;
2853
2854 dev_err(pch->dmac->ddma.dev,
2855 "%s:%d Unable to fetch desc\n",
2856 __func__, __LINE__);
2857 __pl330_giveback_desc(pl330, first);
2858
2859 return NULL;
2860 }
2861
2862 if (!first)
2863 first = desc;
2864 else
2865 list_add_tail(&desc->node, &first->node);
2866
2867 if (direction == DMA_MEM_TO_DEV) {
2868 desc->rqcfg.src_inc = 1;
2869 desc->rqcfg.dst_inc = 0;
2870 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2871 sg_dma_len(sg));
2872 } else {
2873 desc->rqcfg.src_inc = 0;
2874 desc->rqcfg.dst_inc = 1;
2875 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2876 sg_dma_len(sg));
2877 }
2878
2879 desc->rqcfg.brst_size = pch->burst_sz;
2880 desc->rqcfg.brst_len = pch->burst_len;
2881 desc->rqtype = direction;
2882 desc->bytes_requested = sg_dma_len(sg);
2883 }
2884
2885 /* Return the last desc in the chain */
2886 desc->txd.flags = flg;
2887 return &desc->txd;
2888}
2889
2890static irqreturn_t pl330_irq_handler(int irq, void *data)
2891{
2892 if (pl330_update(data))
2893 return IRQ_HANDLED;
2894 else
2895 return IRQ_NONE;
2896}
2897
2898#define PL330_DMA_BUSWIDTHS \
2899 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2900 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2901 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2902 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2903 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2904
2905#ifdef CONFIG_DEBUG_FS
2906static int pl330_debugfs_show(struct seq_file *s, void *data)
2907{
2908 struct pl330_dmac *pl330 = s->private;
2909 int chans, pchs, ch, pr;
2910
2911 chans = pl330->pcfg.num_chan;
2912 pchs = pl330->num_peripherals;
2913
2914 seq_puts(s, "PL330 physical channels:\n");
2915 seq_puts(s, "THREAD:\t\tCHANNEL:\n");
2916 seq_puts(s, "--------\t-----\n");
2917 for (ch = 0; ch < chans; ch++) {
2918 struct pl330_thread *thrd = &pl330->channels[ch];
2919 int found = -1;
2920
2921 for (pr = 0; pr < pchs; pr++) {
2922 struct dma_pl330_chan *pch = &pl330->peripherals[pr];
2923
2924 if (!pch->thread || thrd->id != pch->thread->id)
2925 continue;
2926
2927 found = pr;
2928 }
2929
2930 seq_printf(s, "%d\t\t", thrd->id);
2931 if (found == -1)
2932 seq_puts(s, "--\n");
2933 else
2934 seq_printf(s, "%d\n", found);
2935 }
2936
2937 return 0;
2938}
2939
2940DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
2941
2942static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2943{
2944 debugfs_create_file(dev_name(pl330->ddma.dev),
2945 S_IFREG | 0444, NULL, pl330,
2946 &pl330_debugfs_fops);
2947}
2948#else
2949static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2950{
2951}
2952#endif
2953
2954/*
2955 * Runtime PM callbacks are provided by amba/bus.c driver.
2956 *
2957 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2958 * bus driver will only disable/enable the clock in runtime PM callbacks.
2959 */
2960static int __maybe_unused pl330_suspend(struct device *dev)
2961{
2962 struct amba_device *pcdev = to_amba_device(dev);
2963
2964 pm_runtime_disable(dev);
2965
2966 if (!pm_runtime_status_suspended(dev)) {
2967 /* amba did not disable the clock */
2968 amba_pclk_disable(pcdev);
2969 }
2970 amba_pclk_unprepare(pcdev);
2971
2972 return 0;
2973}
2974
2975static int __maybe_unused pl330_resume(struct device *dev)
2976{
2977 struct amba_device *pcdev = to_amba_device(dev);
2978 int ret;
2979
2980 ret = amba_pclk_prepare(pcdev);
2981 if (ret)
2982 return ret;
2983
2984 if (!pm_runtime_status_suspended(dev))
2985 ret = amba_pclk_enable(pcdev);
2986
2987 pm_runtime_enable(dev);
2988
2989 return ret;
2990}
2991
2992static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2993
2994static int
2995pl330_probe(struct amba_device *adev, const struct amba_id *id)
2996{
2997 struct pl330_config *pcfg;
2998 struct pl330_dmac *pl330;
2999 struct dma_pl330_chan *pch, *_p;
3000 struct dma_device *pd;
3001 struct resource *res;
3002 int i, ret, irq;
3003 int num_chan;
3004 struct device_node *np = adev->dev.of_node;
3005
3006 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
3007 if (ret)
3008 return ret;
3009
3010 /* Allocate a new DMAC and its Channels */
3011 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
3012 if (!pl330)
3013 return -ENOMEM;
3014
3015 pd = &pl330->ddma;
3016 pd->dev = &adev->dev;
3017
3018 pl330->mcbufsz = 0;
3019
3020 /* get quirk */
3021 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
3022 if (of_property_read_bool(np, of_quirks[i].quirk))
3023 pl330->quirks |= of_quirks[i].id;
3024
3025 res = &adev->res;
3026 pl330->base = devm_ioremap_resource(&adev->dev, res);
3027 if (IS_ERR(pl330->base))
3028 return PTR_ERR(pl330->base);
3029
3030 amba_set_drvdata(adev, pl330);
3031
3032 pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
3033 if (IS_ERR(pl330->rstc)) {
3034 if (PTR_ERR(pl330->rstc) != -EPROBE_DEFER)
3035 dev_err(&adev->dev, "Failed to get reset!\n");
3036 return PTR_ERR(pl330->rstc);
3037 } else {
3038 ret = reset_control_deassert(pl330->rstc);
3039 if (ret) {
3040 dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
3041 return ret;
3042 }
3043 }
3044
3045 pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
3046 if (IS_ERR(pl330->rstc_ocp)) {
3047 if (PTR_ERR(pl330->rstc_ocp) != -EPROBE_DEFER)
3048 dev_err(&adev->dev, "Failed to get OCP reset!\n");
3049 return PTR_ERR(pl330->rstc_ocp);
3050 } else {
3051 ret = reset_control_deassert(pl330->rstc_ocp);
3052 if (ret) {
3053 dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
3054 return ret;
3055 }
3056 }
3057
3058 for (i = 0; i < AMBA_NR_IRQS; i++) {
3059 irq = adev->irq[i];
3060 if (irq) {
3061 ret = devm_request_irq(&adev->dev, irq,
3062 pl330_irq_handler, 0,
3063 dev_name(&adev->dev), pl330);
3064 if (ret)
3065 return ret;
3066 } else {
3067 break;
3068 }
3069 }
3070
3071 pcfg = &pl330->pcfg;
3072
3073 pcfg->periph_id = adev->periphid;
3074 ret = pl330_add(pl330);
3075 if (ret)
3076 return ret;
3077
3078 INIT_LIST_HEAD(&pl330->desc_pool);
3079 spin_lock_init(&pl330->pool_lock);
3080
3081 /* Create a descriptor pool of default size */
3082 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
3083 GFP_KERNEL, NR_DEFAULT_DESC))
3084 dev_warn(&adev->dev, "unable to allocate desc\n");
3085
3086 INIT_LIST_HEAD(&pd->channels);
3087
3088 /* Initialize channel parameters */
3089 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
3090
3091 pl330->num_peripherals = num_chan;
3092
3093 pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
3094 if (!pl330->peripherals) {
3095 ret = -ENOMEM;
3096 goto probe_err2;
3097 }
3098
3099 for (i = 0; i < num_chan; i++) {
3100 pch = &pl330->peripherals[i];
3101
3102 pch->chan.private = adev->dev.of_node;
3103 INIT_LIST_HEAD(&pch->submitted_list);
3104 INIT_LIST_HEAD(&pch->work_list);
3105 INIT_LIST_HEAD(&pch->completed_list);
3106 spin_lock_init(&pch->lock);
3107 pch->thread = NULL;
3108 pch->chan.device = pd;
3109 pch->dmac = pl330;
3110 pch->dir = DMA_NONE;
3111
3112 /* Add the channel to the DMAC list */
3113 list_add_tail(&pch->chan.device_node, &pd->channels);
3114 }
3115
3116 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3117 if (pcfg->num_peri) {
3118 dma_cap_set(DMA_SLAVE, pd->cap_mask);
3119 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3120 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3121 }
3122
3123 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3124 pd->device_free_chan_resources = pl330_free_chan_resources;
3125 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3126 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3127 pd->device_tx_status = pl330_tx_status;
3128 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3129 pd->device_config = pl330_config;
3130 pd->device_pause = pl330_pause;
3131 pd->device_terminate_all = pl330_terminate_all;
3132 pd->device_issue_pending = pl330_issue_pending;
3133 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
3134 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
3135 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
3136 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3137 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
3138 1 : PL330_MAX_BURST);
3139
3140 ret = dma_async_device_register(pd);
3141 if (ret) {
3142 dev_err(&adev->dev, "unable to register DMAC\n");
3143 goto probe_err3;
3144 }
3145
3146 if (adev->dev.of_node) {
3147 ret = of_dma_controller_register(adev->dev.of_node,
3148 of_dma_pl330_xlate, pl330);
3149 if (ret) {
3150 dev_err(&adev->dev,
3151 "unable to register DMA to the generic DT DMA helpers\n");
3152 }
3153 }
3154
3155 adev->dev.dma_parms = &pl330->dma_parms;
3156
3157 /*
3158 * This is the limit for transfers with a buswidth of 1, larger
3159 * buswidths will have larger limits.
3160 */
3161 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3162 if (ret)
3163 dev_err(&adev->dev, "unable to set the seg size\n");
3164
3165
3166 init_pl330_debugfs(pl330);
3167 dev_info(&adev->dev,
3168 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3169 dev_info(&adev->dev,
3170 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3171 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3172 pcfg->num_peri, pcfg->num_events);
3173
3174 pm_runtime_irq_safe(&adev->dev);
3175 pm_runtime_use_autosuspend(&adev->dev);
3176 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3177 pm_runtime_mark_last_busy(&adev->dev);
3178 pm_runtime_put_autosuspend(&adev->dev);
3179
3180 return 0;
3181probe_err3:
3182 /* Idle the DMAC */
3183 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3184 chan.device_node) {
3185
3186 /* Remove the channel */
3187 list_del(&pch->chan.device_node);
3188
3189 /* Flush the channel */
3190 if (pch->thread) {
3191 pl330_terminate_all(&pch->chan);
3192 pl330_free_chan_resources(&pch->chan);
3193 }
3194 }
3195probe_err2:
3196 pl330_del(pl330);
3197
3198 if (pl330->rstc_ocp)
3199 reset_control_assert(pl330->rstc_ocp);
3200
3201 if (pl330->rstc)
3202 reset_control_assert(pl330->rstc);
3203 return ret;
3204}
3205
3206static int pl330_remove(struct amba_device *adev)
3207{
3208 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3209 struct dma_pl330_chan *pch, *_p;
3210 int i, irq;
3211
3212 pm_runtime_get_noresume(pl330->ddma.dev);
3213
3214 if (adev->dev.of_node)
3215 of_dma_controller_free(adev->dev.of_node);
3216
3217 for (i = 0; i < AMBA_NR_IRQS; i++) {
3218 irq = adev->irq[i];
3219 if (irq)
3220 devm_free_irq(&adev->dev, irq, pl330);
3221 }
3222
3223 dma_async_device_unregister(&pl330->ddma);
3224
3225 /* Idle the DMAC */
3226 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3227 chan.device_node) {
3228
3229 /* Remove the channel */
3230 list_del(&pch->chan.device_node);
3231
3232 /* Flush the channel */
3233 if (pch->thread) {
3234 pl330_terminate_all(&pch->chan);
3235 pl330_free_chan_resources(&pch->chan);
3236 }
3237 }
3238
3239 pl330_del(pl330);
3240
3241 if (pl330->rstc_ocp)
3242 reset_control_assert(pl330->rstc_ocp);
3243
3244 if (pl330->rstc)
3245 reset_control_assert(pl330->rstc);
3246 return 0;
3247}
3248
3249static const struct amba_id pl330_ids[] = {
3250 {
3251 .id = 0x00041330,
3252 .mask = 0x000fffff,
3253 },
3254 { 0, 0 },
3255};
3256
3257MODULE_DEVICE_TABLE(amba, pl330_ids);
3258
3259static struct amba_driver pl330_driver = {
3260 .drv = {
3261 .owner = THIS_MODULE,
3262 .name = "dma-pl330",
3263 .pm = &pl330_pm,
3264 },
3265 .id_table = pl330_ids,
3266 .probe = pl330_probe,
3267 .remove = pl330_remove,
3268};
3269
3270module_amba_driver(pl330_driver);
3271
3272MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3273MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3274MODULE_LICENSE("GPL");