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1#include <linux/jump_label.h>
2
3/*
4
5 x86 function call convention, 64-bit:
6 -------------------------------------
7 arguments | callee-saved | extra caller-saved | return
8 [callee-clobbered] | | [callee-clobbered] |
9 ---------------------------------------------------------------------------
10 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
11
12 ( rsp is obviously invariant across normal function calls. (gcc can 'merge'
13 functions when it sees tail-call optimization possibilities) rflags is
14 clobbered. Leftover arguments are passed over the stack frame.)
15
16 [*] In the frame-pointers case rbp is fixed to the stack frame.
17
18 [**] for struct return values wider than 64 bits the return convention is a
19 bit more complex: up to 128 bits width we return small structures
20 straight in rax, rdx. For structures larger than that (3 words or
21 larger) the caller puts a pointer to an on-stack return struct
22 [allocated in the caller's stack frame] into the first argument - i.e.
23 into rdi. All other arguments shift up by one in this case.
24 Fortunately this case is rare in the kernel.
25
26For 32-bit we have the following conventions - kernel is built with
27-mregparm=3 and -freg-struct-return:
28
29 x86 function calling convention, 32-bit:
30 ----------------------------------------
31 arguments | callee-saved | extra caller-saved | return
32 [callee-clobbered] | | [callee-clobbered] |
33 -------------------------------------------------------------------------
34 eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
35
36 ( here too esp is obviously invariant across normal function calls. eflags
37 is clobbered. Leftover arguments are passed over the stack frame. )
38
39 [*] In the frame-pointers case ebp is fixed to the stack frame.
40
41 [**] We build with -freg-struct-return, which on 32-bit means similar
42 semantics as on 64-bit: edx can be used for a second return value
43 (i.e. covering integer and structure sizes up to 64 bits) - after that
44 it gets more complex and more expensive: 3-word or larger struct returns
45 get done in the caller's frame and the pointer to the return struct goes
46 into regparm0, i.e. eax - the other arguments shift up and the
47 function's register parameters degenerate to regparm=2 in essence.
48
49*/
50
51#ifdef CONFIG_X86_64
52
53/*
54 * 64-bit system call stack frame layout defines and helpers,
55 * for assembly code:
56 */
57
58/* The layout forms the "struct pt_regs" on the stack: */
59/*
60 * C ABI says these regs are callee-preserved. They aren't saved on kernel entry
61 * unless syscall needs a complete, fully filled "struct pt_regs".
62 */
63#define R15 0*8
64#define R14 1*8
65#define R13 2*8
66#define R12 3*8
67#define RBP 4*8
68#define RBX 5*8
69/* These regs are callee-clobbered. Always saved on kernel entry. */
70#define R11 6*8
71#define R10 7*8
72#define R9 8*8
73#define R8 9*8
74#define RAX 10*8
75#define RCX 11*8
76#define RDX 12*8
77#define RSI 13*8
78#define RDI 14*8
79/*
80 * On syscall entry, this is syscall#. On CPU exception, this is error code.
81 * On hw interrupt, it's IRQ number:
82 */
83#define ORIG_RAX 15*8
84/* Return frame for iretq */
85#define RIP 16*8
86#define CS 17*8
87#define EFLAGS 18*8
88#define RSP 19*8
89#define SS 20*8
90
91#define SIZEOF_PTREGS 21*8
92
93 .macro ALLOC_PT_GPREGS_ON_STACK addskip=0
94 addq $-(15*8+\addskip), %rsp
95 .endm
96
97 .macro SAVE_C_REGS_HELPER offset=0 rax=1 rcx=1 r8910=1 r11=1
98 .if \r11
99 movq %r11, 6*8+\offset(%rsp)
100 .endif
101 .if \r8910
102 movq %r10, 7*8+\offset(%rsp)
103 movq %r9, 8*8+\offset(%rsp)
104 movq %r8, 9*8+\offset(%rsp)
105 .endif
106 .if \rax
107 movq %rax, 10*8+\offset(%rsp)
108 .endif
109 .if \rcx
110 movq %rcx, 11*8+\offset(%rsp)
111 .endif
112 movq %rdx, 12*8+\offset(%rsp)
113 movq %rsi, 13*8+\offset(%rsp)
114 movq %rdi, 14*8+\offset(%rsp)
115 .endm
116 .macro SAVE_C_REGS offset=0
117 SAVE_C_REGS_HELPER \offset, 1, 1, 1, 1
118 .endm
119 .macro SAVE_C_REGS_EXCEPT_RAX_RCX offset=0
120 SAVE_C_REGS_HELPER \offset, 0, 0, 1, 1
121 .endm
122 .macro SAVE_C_REGS_EXCEPT_R891011
123 SAVE_C_REGS_HELPER 0, 1, 1, 0, 0
124 .endm
125 .macro SAVE_C_REGS_EXCEPT_RCX_R891011
126 SAVE_C_REGS_HELPER 0, 1, 0, 0, 0
127 .endm
128 .macro SAVE_C_REGS_EXCEPT_RAX_RCX_R11
129 SAVE_C_REGS_HELPER 0, 0, 0, 1, 0
130 .endm
131
132 .macro SAVE_EXTRA_REGS offset=0
133 movq %r15, 0*8+\offset(%rsp)
134 movq %r14, 1*8+\offset(%rsp)
135 movq %r13, 2*8+\offset(%rsp)
136 movq %r12, 3*8+\offset(%rsp)
137 movq %rbp, 4*8+\offset(%rsp)
138 movq %rbx, 5*8+\offset(%rsp)
139 .endm
140
141 .macro RESTORE_EXTRA_REGS offset=0
142 movq 0*8+\offset(%rsp), %r15
143 movq 1*8+\offset(%rsp), %r14
144 movq 2*8+\offset(%rsp), %r13
145 movq 3*8+\offset(%rsp), %r12
146 movq 4*8+\offset(%rsp), %rbp
147 movq 5*8+\offset(%rsp), %rbx
148 .endm
149
150 .macro ZERO_EXTRA_REGS
151 xorl %r15d, %r15d
152 xorl %r14d, %r14d
153 xorl %r13d, %r13d
154 xorl %r12d, %r12d
155 xorl %ebp, %ebp
156 xorl %ebx, %ebx
157 .endm
158
159 .macro RESTORE_C_REGS_HELPER rstor_rax=1, rstor_rcx=1, rstor_r11=1, rstor_r8910=1, rstor_rdx=1
160 .if \rstor_r11
161 movq 6*8(%rsp), %r11
162 .endif
163 .if \rstor_r8910
164 movq 7*8(%rsp), %r10
165 movq 8*8(%rsp), %r9
166 movq 9*8(%rsp), %r8
167 .endif
168 .if \rstor_rax
169 movq 10*8(%rsp), %rax
170 .endif
171 .if \rstor_rcx
172 movq 11*8(%rsp), %rcx
173 .endif
174 .if \rstor_rdx
175 movq 12*8(%rsp), %rdx
176 .endif
177 movq 13*8(%rsp), %rsi
178 movq 14*8(%rsp), %rdi
179 .endm
180 .macro RESTORE_C_REGS
181 RESTORE_C_REGS_HELPER 1,1,1,1,1
182 .endm
183 .macro RESTORE_C_REGS_EXCEPT_RAX
184 RESTORE_C_REGS_HELPER 0,1,1,1,1
185 .endm
186 .macro RESTORE_C_REGS_EXCEPT_RCX
187 RESTORE_C_REGS_HELPER 1,0,1,1,1
188 .endm
189 .macro RESTORE_C_REGS_EXCEPT_R11
190 RESTORE_C_REGS_HELPER 1,1,0,1,1
191 .endm
192 .macro RESTORE_C_REGS_EXCEPT_RCX_R11
193 RESTORE_C_REGS_HELPER 1,0,0,1,1
194 .endm
195
196 .macro REMOVE_PT_GPREGS_FROM_STACK addskip=0
197 subq $-(15*8+\addskip), %rsp
198 .endm
199
200 .macro icebp
201 .byte 0xf1
202 .endm
203
204#endif /* CONFIG_X86_64 */
205
206/*
207 * This does 'call enter_from_user_mode' unless we can avoid it based on
208 * kernel config or using the static jump infrastructure.
209 */
210.macro CALL_enter_from_user_mode
211#ifdef CONFIG_CONTEXT_TRACKING
212#ifdef HAVE_JUMP_LABEL
213 STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0
214#endif
215 call enter_from_user_mode
216.Lafter_call_\@:
217#endif
218.endm
1/* SPDX-License-Identifier: GPL-2.0 */
2#include <linux/jump_label.h>
3#include <asm/unwind_hints.h>
4#include <asm/cpufeatures.h>
5#include <asm/page_types.h>
6#include <asm/percpu.h>
7#include <asm/asm-offsets.h>
8#include <asm/processor-flags.h>
9
10/*
11
12 x86 function call convention, 64-bit:
13 -------------------------------------
14 arguments | callee-saved | extra caller-saved | return
15 [callee-clobbered] | | [callee-clobbered] |
16 ---------------------------------------------------------------------------
17 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
18
19 ( rsp is obviously invariant across normal function calls. (gcc can 'merge'
20 functions when it sees tail-call optimization possibilities) rflags is
21 clobbered. Leftover arguments are passed over the stack frame.)
22
23 [*] In the frame-pointers case rbp is fixed to the stack frame.
24
25 [**] for struct return values wider than 64 bits the return convention is a
26 bit more complex: up to 128 bits width we return small structures
27 straight in rax, rdx. For structures larger than that (3 words or
28 larger) the caller puts a pointer to an on-stack return struct
29 [allocated in the caller's stack frame] into the first argument - i.e.
30 into rdi. All other arguments shift up by one in this case.
31 Fortunately this case is rare in the kernel.
32
33For 32-bit we have the following conventions - kernel is built with
34-mregparm=3 and -freg-struct-return:
35
36 x86 function calling convention, 32-bit:
37 ----------------------------------------
38 arguments | callee-saved | extra caller-saved | return
39 [callee-clobbered] | | [callee-clobbered] |
40 -------------------------------------------------------------------------
41 eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
42
43 ( here too esp is obviously invariant across normal function calls. eflags
44 is clobbered. Leftover arguments are passed over the stack frame. )
45
46 [*] In the frame-pointers case ebp is fixed to the stack frame.
47
48 [**] We build with -freg-struct-return, which on 32-bit means similar
49 semantics as on 64-bit: edx can be used for a second return value
50 (i.e. covering integer and structure sizes up to 64 bits) - after that
51 it gets more complex and more expensive: 3-word or larger struct returns
52 get done in the caller's frame and the pointer to the return struct goes
53 into regparm0, i.e. eax - the other arguments shift up and the
54 function's register parameters degenerate to regparm=2 in essence.
55
56*/
57
58#ifdef CONFIG_X86_64
59
60/*
61 * 64-bit system call stack frame layout defines and helpers,
62 * for assembly code:
63 */
64
65/* The layout forms the "struct pt_regs" on the stack: */
66/*
67 * C ABI says these regs are callee-preserved. They aren't saved on kernel entry
68 * unless syscall needs a complete, fully filled "struct pt_regs".
69 */
70#define R15 0*8
71#define R14 1*8
72#define R13 2*8
73#define R12 3*8
74#define RBP 4*8
75#define RBX 5*8
76/* These regs are callee-clobbered. Always saved on kernel entry. */
77#define R11 6*8
78#define R10 7*8
79#define R9 8*8
80#define R8 9*8
81#define RAX 10*8
82#define RCX 11*8
83#define RDX 12*8
84#define RSI 13*8
85#define RDI 14*8
86/*
87 * On syscall entry, this is syscall#. On CPU exception, this is error code.
88 * On hw interrupt, it's IRQ number:
89 */
90#define ORIG_RAX 15*8
91/* Return frame for iretq */
92#define RIP 16*8
93#define CS 17*8
94#define EFLAGS 18*8
95#define RSP 19*8
96#define SS 20*8
97
98#define SIZEOF_PTREGS 21*8
99
100.macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
101 /*
102 * Push registers and sanitize registers of values that a
103 * speculation attack might otherwise want to exploit. The
104 * lower registers are likely clobbered well before they
105 * could be put to use in a speculative execution gadget.
106 * Interleave XOR with PUSH for better uop scheduling:
107 */
108 .if \save_ret
109 pushq %rsi /* pt_regs->si */
110 movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */
111 movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */
112 .else
113 pushq %rdi /* pt_regs->di */
114 pushq %rsi /* pt_regs->si */
115 .endif
116 pushq \rdx /* pt_regs->dx */
117 xorl %edx, %edx /* nospec dx */
118 pushq %rcx /* pt_regs->cx */
119 xorl %ecx, %ecx /* nospec cx */
120 pushq \rax /* pt_regs->ax */
121 pushq %r8 /* pt_regs->r8 */
122 xorl %r8d, %r8d /* nospec r8 */
123 pushq %r9 /* pt_regs->r9 */
124 xorl %r9d, %r9d /* nospec r9 */
125 pushq %r10 /* pt_regs->r10 */
126 xorl %r10d, %r10d /* nospec r10 */
127 pushq %r11 /* pt_regs->r11 */
128 xorl %r11d, %r11d /* nospec r11*/
129 pushq %rbx /* pt_regs->rbx */
130 xorl %ebx, %ebx /* nospec rbx*/
131 pushq %rbp /* pt_regs->rbp */
132 xorl %ebp, %ebp /* nospec rbp*/
133 pushq %r12 /* pt_regs->r12 */
134 xorl %r12d, %r12d /* nospec r12*/
135 pushq %r13 /* pt_regs->r13 */
136 xorl %r13d, %r13d /* nospec r13*/
137 pushq %r14 /* pt_regs->r14 */
138 xorl %r14d, %r14d /* nospec r14*/
139 pushq %r15 /* pt_regs->r15 */
140 xorl %r15d, %r15d /* nospec r15*/
141 UNWIND_HINT_REGS
142 .if \save_ret
143 pushq %rsi /* return address on top of stack */
144 .endif
145.endm
146
147.macro POP_REGS pop_rdi=1 skip_r11rcx=0
148 popq %r15
149 popq %r14
150 popq %r13
151 popq %r12
152 popq %rbp
153 popq %rbx
154 .if \skip_r11rcx
155 popq %rsi
156 .else
157 popq %r11
158 .endif
159 popq %r10
160 popq %r9
161 popq %r8
162 popq %rax
163 .if \skip_r11rcx
164 popq %rsi
165 .else
166 popq %rcx
167 .endif
168 popq %rdx
169 popq %rsi
170 .if \pop_rdi
171 popq %rdi
172 .endif
173.endm
174
175#ifdef CONFIG_PAGE_TABLE_ISOLATION
176
177/*
178 * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
179 * halves:
180 */
181#define PTI_USER_PGTABLE_BIT PAGE_SHIFT
182#define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
183#define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
184#define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
185#define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
186
187.macro SET_NOFLUSH_BIT reg:req
188 bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
189.endm
190
191.macro ADJUST_KERNEL_CR3 reg:req
192 ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
193 /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
194 andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
195.endm
196
197.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
198 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
199 mov %cr3, \scratch_reg
200 ADJUST_KERNEL_CR3 \scratch_reg
201 mov \scratch_reg, %cr3
202.Lend_\@:
203.endm
204
205#define THIS_CPU_user_pcid_flush_mask \
206 PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
207
208.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
209 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
210 mov %cr3, \scratch_reg
211
212 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
213
214 /*
215 * Test if the ASID needs a flush.
216 */
217 movq \scratch_reg, \scratch_reg2
218 andq $(0x7FF), \scratch_reg /* mask ASID */
219 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
220 jnc .Lnoflush_\@
221
222 /* Flush needed, clear the bit */
223 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
224 movq \scratch_reg2, \scratch_reg
225 jmp .Lwrcr3_pcid_\@
226
227.Lnoflush_\@:
228 movq \scratch_reg2, \scratch_reg
229 SET_NOFLUSH_BIT \scratch_reg
230
231.Lwrcr3_pcid_\@:
232 /* Flip the ASID to the user version */
233 orq $(PTI_USER_PCID_MASK), \scratch_reg
234
235.Lwrcr3_\@:
236 /* Flip the PGD to the user version */
237 orq $(PTI_USER_PGTABLE_MASK), \scratch_reg
238 mov \scratch_reg, %cr3
239.Lend_\@:
240.endm
241
242.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
243 pushq %rax
244 SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
245 popq %rax
246.endm
247
248.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
249 ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
250 movq %cr3, \scratch_reg
251 movq \scratch_reg, \save_reg
252 /*
253 * Test the user pagetable bit. If set, then the user page tables
254 * are active. If clear CR3 already has the kernel page table
255 * active.
256 */
257 bt $PTI_USER_PGTABLE_BIT, \scratch_reg
258 jnc .Ldone_\@
259
260 ADJUST_KERNEL_CR3 \scratch_reg
261 movq \scratch_reg, %cr3
262
263.Ldone_\@:
264.endm
265
266.macro RESTORE_CR3 scratch_reg:req save_reg:req
267 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
268
269 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
270
271 /*
272 * KERNEL pages can always resume with NOFLUSH as we do
273 * explicit flushes.
274 */
275 bt $PTI_USER_PGTABLE_BIT, \save_reg
276 jnc .Lnoflush_\@
277
278 /*
279 * Check if there's a pending flush for the user ASID we're
280 * about to set.
281 */
282 movq \save_reg, \scratch_reg
283 andq $(0x7FF), \scratch_reg
284 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
285 jnc .Lnoflush_\@
286
287 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
288 jmp .Lwrcr3_\@
289
290.Lnoflush_\@:
291 SET_NOFLUSH_BIT \save_reg
292
293.Lwrcr3_\@:
294 /*
295 * The CR3 write could be avoided when not changing its value,
296 * but would require a CR3 read *and* a scratch register.
297 */
298 movq \save_reg, %cr3
299.Lend_\@:
300.endm
301
302#else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
303
304.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
305.endm
306.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
307.endm
308.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
309.endm
310.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
311.endm
312.macro RESTORE_CR3 scratch_reg:req save_reg:req
313.endm
314
315#endif
316
317/*
318 * Mitigate Spectre v1 for conditional swapgs code paths.
319 *
320 * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
321 * prevent a speculative swapgs when coming from kernel space.
322 *
323 * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
324 * to prevent the swapgs from getting speculatively skipped when coming from
325 * user space.
326 */
327.macro FENCE_SWAPGS_USER_ENTRY
328 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
329.endm
330.macro FENCE_SWAPGS_KERNEL_ENTRY
331 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
332.endm
333
334.macro STACKLEAK_ERASE_NOCLOBBER
335#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
336 PUSH_AND_CLEAR_REGS
337 call stackleak_erase
338 POP_REGS
339#endif
340.endm
341
342#endif /* CONFIG_X86_64 */
343
344.macro STACKLEAK_ERASE
345#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
346 call stackleak_erase
347#endif
348.endm
349
350/*
351 * This does 'call enter_from_user_mode' unless we can avoid it based on
352 * kernel config or using the static jump infrastructure.
353 */
354.macro CALL_enter_from_user_mode
355#ifdef CONFIG_CONTEXT_TRACKING
356#ifdef CONFIG_JUMP_LABEL
357 STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0
358#endif
359 call enter_from_user_mode
360.Lafter_call_\@:
361#endif
362.endm
363
364#ifdef CONFIG_PARAVIRT_XXL
365#define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg
366#else
367#define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg
368#endif