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1/*
2 * SH7786 Setup
3 *
4 * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com>
7 *
8 * Based on SH7785 Setup
9 *
10 * Copyright (C) 2007 Paul Mundt
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/platform_device.h>
17#include <linux/init.h>
18#include <linux/serial.h>
19#include <linux/serial_sci.h>
20#include <linux/io.h>
21#include <linux/mm.h>
22#include <linux/dma-mapping.h>
23#include <linux/sh_timer.h>
24#include <linux/sh_dma.h>
25#include <linux/sh_intc.h>
26#include <linux/usb/ohci_pdriver.h>
27#include <cpu/dma-register.h>
28#include <asm/mmzone.h>
29
30static struct plat_sci_port scif0_platform_data = {
31 .flags = UPF_BOOT_AUTOCONF,
32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
33 .type = PORT_SCIF,
34 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
35};
36
37static struct resource scif0_resources[] = {
38 DEFINE_RES_MEM(0xffea0000, 0x100),
39 DEFINE_RES_IRQ(evt2irq(0x700)),
40 DEFINE_RES_IRQ(evt2irq(0x720)),
41 DEFINE_RES_IRQ(evt2irq(0x760)),
42 DEFINE_RES_IRQ(evt2irq(0x740)),
43};
44
45static struct platform_device scif0_device = {
46 .name = "sh-sci",
47 .id = 0,
48 .resource = scif0_resources,
49 .num_resources = ARRAY_SIZE(scif0_resources),
50 .dev = {
51 .platform_data = &scif0_platform_data,
52 },
53};
54
55/*
56 * The rest of these all have multiplexed IRQs
57 */
58static struct plat_sci_port scif1_platform_data = {
59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
61 .type = PORT_SCIF,
62 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
63};
64
65static struct resource scif1_resources[] = {
66 DEFINE_RES_MEM(0xffeb0000, 0x100),
67 DEFINE_RES_IRQ(evt2irq(0x780)),
68};
69
70static struct resource scif1_demux_resources[] = {
71 DEFINE_RES_MEM(0xffeb0000, 0x100),
72 /* Placeholders, see sh7786_devices_setup() */
73 DEFINE_RES_IRQ(0),
74 DEFINE_RES_IRQ(0),
75 DEFINE_RES_IRQ(0),
76 DEFINE_RES_IRQ(0),
77};
78
79static struct platform_device scif1_device = {
80 .name = "sh-sci",
81 .id = 1,
82 .resource = scif1_resources,
83 .num_resources = ARRAY_SIZE(scif1_resources),
84 .dev = {
85 .platform_data = &scif1_platform_data,
86 },
87};
88
89static struct plat_sci_port scif2_platform_data = {
90 .flags = UPF_BOOT_AUTOCONF,
91 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
92 .type = PORT_SCIF,
93 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
94};
95
96static struct resource scif2_resources[] = {
97 DEFINE_RES_MEM(0xffec0000, 0x100),
98 DEFINE_RES_IRQ(evt2irq(0x840)),
99};
100
101static struct platform_device scif2_device = {
102 .name = "sh-sci",
103 .id = 2,
104 .resource = scif2_resources,
105 .num_resources = ARRAY_SIZE(scif2_resources),
106 .dev = {
107 .platform_data = &scif2_platform_data,
108 },
109};
110
111static struct plat_sci_port scif3_platform_data = {
112 .flags = UPF_BOOT_AUTOCONF,
113 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
114 .type = PORT_SCIF,
115 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
116};
117
118static struct resource scif3_resources[] = {
119 DEFINE_RES_MEM(0xffed0000, 0x100),
120 DEFINE_RES_IRQ(evt2irq(0x860)),
121};
122
123static struct platform_device scif3_device = {
124 .name = "sh-sci",
125 .id = 3,
126 .resource = scif3_resources,
127 .num_resources = ARRAY_SIZE(scif3_resources),
128 .dev = {
129 .platform_data = &scif3_platform_data,
130 },
131};
132
133static struct plat_sci_port scif4_platform_data = {
134 .flags = UPF_BOOT_AUTOCONF,
135 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
136 .type = PORT_SCIF,
137 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
138};
139
140static struct resource scif4_resources[] = {
141 DEFINE_RES_MEM(0xffee0000, 0x100),
142 DEFINE_RES_IRQ(evt2irq(0x880)),
143};
144
145static struct platform_device scif4_device = {
146 .name = "sh-sci",
147 .id = 4,
148 .resource = scif4_resources,
149 .num_resources = ARRAY_SIZE(scif4_resources),
150 .dev = {
151 .platform_data = &scif4_platform_data,
152 },
153};
154
155static struct plat_sci_port scif5_platform_data = {
156 .flags = UPF_BOOT_AUTOCONF,
157 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
158 .type = PORT_SCIF,
159 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
160};
161
162static struct resource scif5_resources[] = {
163 DEFINE_RES_MEM(0xffef0000, 0x100),
164 DEFINE_RES_IRQ(evt2irq(0x8a0)),
165};
166
167static struct platform_device scif5_device = {
168 .name = "sh-sci",
169 .id = 5,
170 .resource = scif5_resources,
171 .num_resources = ARRAY_SIZE(scif5_resources),
172 .dev = {
173 .platform_data = &scif5_platform_data,
174 },
175};
176
177static struct sh_timer_config tmu0_platform_data = {
178 .channels_mask = 7,
179};
180
181static struct resource tmu0_resources[] = {
182 DEFINE_RES_MEM(0xffd80000, 0x30),
183 DEFINE_RES_IRQ(evt2irq(0x400)),
184 DEFINE_RES_IRQ(evt2irq(0x420)),
185 DEFINE_RES_IRQ(evt2irq(0x440)),
186};
187
188static struct platform_device tmu0_device = {
189 .name = "sh-tmu",
190 .id = 0,
191 .dev = {
192 .platform_data = &tmu0_platform_data,
193 },
194 .resource = tmu0_resources,
195 .num_resources = ARRAY_SIZE(tmu0_resources),
196};
197
198static struct sh_timer_config tmu1_platform_data = {
199 .channels_mask = 7,
200};
201
202static struct resource tmu1_resources[] = {
203 DEFINE_RES_MEM(0xffda0000, 0x2c),
204 DEFINE_RES_IRQ(evt2irq(0x480)),
205 DEFINE_RES_IRQ(evt2irq(0x4a0)),
206 DEFINE_RES_IRQ(evt2irq(0x4c0)),
207};
208
209static struct platform_device tmu1_device = {
210 .name = "sh-tmu",
211 .id = 1,
212 .dev = {
213 .platform_data = &tmu1_platform_data,
214 },
215 .resource = tmu1_resources,
216 .num_resources = ARRAY_SIZE(tmu1_resources),
217};
218
219static struct sh_timer_config tmu2_platform_data = {
220 .channels_mask = 7,
221};
222
223static struct resource tmu2_resources[] = {
224 DEFINE_RES_MEM(0xffdc0000, 0x2c),
225 DEFINE_RES_IRQ(evt2irq(0x7a0)),
226 DEFINE_RES_IRQ(evt2irq(0x7a0)),
227 DEFINE_RES_IRQ(evt2irq(0x7a0)),
228};
229
230static struct platform_device tmu2_device = {
231 .name = "sh-tmu",
232 .id = 2,
233 .dev = {
234 .platform_data = &tmu2_platform_data,
235 },
236 .resource = tmu2_resources,
237 .num_resources = ARRAY_SIZE(tmu2_resources),
238};
239
240static struct sh_timer_config tmu3_platform_data = {
241 .channels_mask = 7,
242};
243
244static struct resource tmu3_resources[] = {
245 DEFINE_RES_MEM(0xffde0000, 0x2c),
246 DEFINE_RES_IRQ(evt2irq(0x7c0)),
247 DEFINE_RES_IRQ(evt2irq(0x7c0)),
248 DEFINE_RES_IRQ(evt2irq(0x7c0)),
249};
250
251static struct platform_device tmu3_device = {
252 .name = "sh-tmu",
253 .id = 3,
254 .dev = {
255 .platform_data = &tmu3_platform_data,
256 },
257 .resource = tmu3_resources,
258 .num_resources = ARRAY_SIZE(tmu3_resources),
259};
260
261static const struct sh_dmae_channel dmac0_channels[] = {
262 {
263 .offset = 0,
264 .dmars = 0,
265 .dmars_bit = 0,
266 }, {
267 .offset = 0x10,
268 .dmars = 0,
269 .dmars_bit = 8,
270 }, {
271 .offset = 0x20,
272 .dmars = 4,
273 .dmars_bit = 0,
274 }, {
275 .offset = 0x30,
276 .dmars = 4,
277 .dmars_bit = 8,
278 }, {
279 .offset = 0x50,
280 .dmars = 8,
281 .dmars_bit = 0,
282 }, {
283 .offset = 0x60,
284 .dmars = 8,
285 .dmars_bit = 8,
286 }
287};
288
289static const unsigned int ts_shift[] = TS_SHIFT;
290
291static struct sh_dmae_pdata dma0_platform_data = {
292 .channel = dmac0_channels,
293 .channel_num = ARRAY_SIZE(dmac0_channels),
294 .ts_low_shift = CHCR_TS_LOW_SHIFT,
295 .ts_low_mask = CHCR_TS_LOW_MASK,
296 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
297 .ts_high_mask = CHCR_TS_HIGH_MASK,
298 .ts_shift = ts_shift,
299 .ts_shift_num = ARRAY_SIZE(ts_shift),
300 .dmaor_init = DMAOR_INIT,
301};
302
303/* Resource order important! */
304static struct resource dmac0_resources[] = {
305 {
306 /* Channel registers and DMAOR */
307 .start = 0xfe008020,
308 .end = 0xfe00808f,
309 .flags = IORESOURCE_MEM,
310 }, {
311 /* DMARSx */
312 .start = 0xfe009000,
313 .end = 0xfe00900b,
314 .flags = IORESOURCE_MEM,
315 }, {
316 .name = "error_irq",
317 .start = evt2irq(0x5c0),
318 .end = evt2irq(0x5c0),
319 .flags = IORESOURCE_IRQ,
320 }, {
321 /* IRQ for channels 0-5 */
322 .start = evt2irq(0x500),
323 .end = evt2irq(0x5a0),
324 .flags = IORESOURCE_IRQ,
325 },
326};
327
328static struct platform_device dma0_device = {
329 .name = "sh-dma-engine",
330 .id = 0,
331 .resource = dmac0_resources,
332 .num_resources = ARRAY_SIZE(dmac0_resources),
333 .dev = {
334 .platform_data = &dma0_platform_data,
335 },
336};
337
338#define USB_EHCI_START 0xffe70000
339#define USB_OHCI_START 0xffe70400
340
341static struct resource usb_ehci_resources[] = {
342 [0] = {
343 .start = USB_EHCI_START,
344 .end = USB_EHCI_START + 0x3ff,
345 .flags = IORESOURCE_MEM,
346 },
347 [1] = {
348 .start = evt2irq(0xba0),
349 .end = evt2irq(0xba0),
350 .flags = IORESOURCE_IRQ,
351 },
352};
353
354static struct platform_device usb_ehci_device = {
355 .name = "sh_ehci",
356 .id = -1,
357 .dev = {
358 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
359 .coherent_dma_mask = DMA_BIT_MASK(32),
360 },
361 .num_resources = ARRAY_SIZE(usb_ehci_resources),
362 .resource = usb_ehci_resources,
363};
364
365static struct resource usb_ohci_resources[] = {
366 [0] = {
367 .start = USB_OHCI_START,
368 .end = USB_OHCI_START + 0x3ff,
369 .flags = IORESOURCE_MEM,
370 },
371 [1] = {
372 .start = evt2irq(0xba0),
373 .end = evt2irq(0xba0),
374 .flags = IORESOURCE_IRQ,
375 },
376};
377
378static struct usb_ohci_pdata usb_ohci_pdata;
379
380static struct platform_device usb_ohci_device = {
381 .name = "ohci-platform",
382 .id = -1,
383 .dev = {
384 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
385 .coherent_dma_mask = DMA_BIT_MASK(32),
386 .platform_data = &usb_ohci_pdata,
387 },
388 .num_resources = ARRAY_SIZE(usb_ohci_resources),
389 .resource = usb_ohci_resources,
390};
391
392static struct platform_device *sh7786_early_devices[] __initdata = {
393 &scif0_device,
394 &scif1_device,
395 &scif2_device,
396 &scif3_device,
397 &scif4_device,
398 &scif5_device,
399 &tmu0_device,
400 &tmu1_device,
401 &tmu2_device,
402};
403
404static struct platform_device *sh7786_devices[] __initdata = {
405 &dma0_device,
406 &usb_ehci_device,
407 &usb_ohci_device,
408};
409
410/*
411 * Please call this function if your platform board
412 * use external clock for USB
413 * */
414#define USBCTL0 0xffe70858
415#define CLOCK_MODE_MASK 0xffffff7f
416#define EXT_CLOCK_MODE 0x00000080
417
418void __init sh7786_usb_use_exclock(void)
419{
420 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
421 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
422}
423
424#define USBINITREG1 0xffe70094
425#define USBINITREG2 0xffe7009c
426#define USBINITVAL1 0x00ff0040
427#define USBINITVAL2 0x00000001
428
429#define USBPCTL1 0xffe70804
430#define USBST 0xffe70808
431#define PHY_ENB 0x00000001
432#define PLL_ENB 0x00000002
433#define PHY_RST 0x00000004
434#define ACT_PLL_STATUS 0xc0000000
435
436static void __init sh7786_usb_setup(void)
437{
438 int i = 1000000;
439
440 /*
441 * USB initial settings
442 *
443 * The following settings are necessary
444 * for using the USB modules.
445 *
446 * see "USB Initial Settings" for detail
447 */
448 __raw_writel(USBINITVAL1, USBINITREG1);
449 __raw_writel(USBINITVAL2, USBINITREG2);
450
451 /*
452 * Set the PHY and PLL enable bit
453 */
454 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
455 while (i--) {
456 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
457 /* Set the PHY RST bit */
458 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
459 printk(KERN_INFO "sh7786 usb setup done\n");
460 break;
461 }
462 cpu_relax();
463 }
464}
465
466enum {
467 UNUSED = 0,
468
469 /* interrupt sources */
470 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
471 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
472 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
473 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
474
475 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
476 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
477 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
478 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
479
480 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
481 WDT,
482 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
483 TMU1_0, TMU1_1, TMU1_2,
484 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
485 HUDI1, HUDI0,
486 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
487 HPB_0, HPB_1, HPB_2,
488 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
489 SCIF1,
490 TMU2, TMU3,
491 SCIF2, SCIF3, SCIF4, SCIF5,
492 Eth_0, Eth_1,
493 PCIeC0_0, PCIeC0_1, PCIeC0_2,
494 PCIeC1_0, PCIeC1_1, PCIeC1_2,
495 USB,
496 I2C0, I2C1,
497 DU,
498 SSI0, SSI1, SSI2, SSI3,
499 PCIeC2_0, PCIeC2_1, PCIeC2_2,
500 HAC0, HAC1,
501 FLCTL,
502 HSPI,
503 GPIO0, GPIO1,
504 Thermal,
505 INTICI0, INTICI1, INTICI2, INTICI3,
506 INTICI4, INTICI5, INTICI6, INTICI7,
507
508 /* Muxed sub-events */
509 TXI1, BRI1, RXI1, ERI1,
510};
511
512static struct intc_vect sh7786_vectors[] __initdata = {
513 INTC_VECT(WDT, 0x3e0),
514 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
515 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
516 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
517 INTC_VECT(TMU1_2, 0x4c0),
518 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
519 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
520 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
521 INTC_VECT(DMAC0_6, 0x5c0),
522 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
523 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
524 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
525 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
526 INTC_VECT(HPB_2, 0x6e0),
527 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
528 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
529 INTC_VECT(SCIF1, 0x780),
530 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
531 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
532 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
533 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
534 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
535 INTC_VECT(PCIeC0_2, 0xb20),
536 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
537 INTC_VECT(PCIeC1_2, 0xb80),
538 INTC_VECT(USB, 0xba0),
539 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
540 INTC_VECT(DU, 0xd00),
541 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
542 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
543 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
544 INTC_VECT(PCIeC2_2, 0xde0),
545 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
546 INTC_VECT(FLCTL, 0xe40),
547 INTC_VECT(HSPI, 0xe80),
548 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
549 INTC_VECT(Thermal, 0xee0),
550 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
551 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
552 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
553 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
554};
555
556#define CnINTMSK0 0xfe410030
557#define CnINTMSK1 0xfe410040
558#define CnINTMSKCLR0 0xfe410050
559#define CnINTMSKCLR1 0xfe410060
560#define CnINT2MSKR0 0xfe410a20
561#define CnINT2MSKR1 0xfe410a24
562#define CnINT2MSKR2 0xfe410a28
563#define CnINT2MSKR3 0xfe410a2c
564#define CnINT2MSKCR0 0xfe410a30
565#define CnINT2MSKCR1 0xfe410a34
566#define CnINT2MSKCR2 0xfe410a38
567#define CnINT2MSKCR3 0xfe410a3c
568#define INTMSK2 0xfe410068
569#define INTMSKCLR2 0xfe41006c
570
571#define INTDISTCR0 0xfe4100b0
572#define INTDISTCR1 0xfe4100b4
573#define INT2DISTCR0 0xfe410900
574#define INT2DISTCR1 0xfe410904
575#define INT2DISTCR2 0xfe410908
576#define INT2DISTCR3 0xfe41090c
577
578static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
579 { CnINTMSK0, CnINTMSKCLR0, 32,
580 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
581 INTC_SMP_BALANCING(INTDISTCR0) },
582 { INTMSK2, INTMSKCLR2, 32,
583 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
584 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
585 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
586 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
587 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
588 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
589 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
590 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
591 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
592 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
594 INTC_SMP_BALANCING(INT2DISTCR0) },
595 { CnINT2MSKR1, CnINT2MSKCR1, 32,
596 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
597 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
598 HUDI1, HUDI0,
599 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
600 HPB_0, HPB_1, HPB_2,
601 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
602 SCIF1,
603 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
604 { CnINT2MSKR2, CnINT2MSKCR2, 32,
605 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
606 Eth_0, Eth_1,
607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
608 PCIeC0_0, PCIeC0_1, PCIeC0_2,
609 PCIeC1_0, PCIeC1_1, PCIeC1_2,
610 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
611 { CnINT2MSKR3, CnINT2MSKCR3, 32,
612 { 0, 0, 0, 0, 0, 0,
613 I2C0, I2C1,
614 DU, SSI0, SSI1, SSI2, SSI3,
615 PCIeC2_0, PCIeC2_1, PCIeC2_2,
616 HAC0, HAC1,
617 FLCTL, 0,
618 HSPI, GPIO0, GPIO1, Thermal,
619 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
620};
621
622static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
623 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
624 IRQ4, IRQ5, IRQ6, IRQ7 } },
625 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
626 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
627 TMU0_2, TMU0_3 } },
628 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
629 TMU1_2, 0 } },
630 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
631 DMAC0_2, DMAC0_3 } },
632 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
633 DMAC0_6, HUDI1 } },
634 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
635 DMAC1_1, DMAC1_2 } },
636 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
637 HPB_1, HPB_2 } },
638 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
639 SCIF0_2, SCIF0_3 } },
640 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
641 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
642 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
643 Eth_0, Eth_1 } },
644 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
645 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
646 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
647 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
648 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
649 PCIeC1_0, PCIeC1_1 } },
650 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
651 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
652 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
653 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
654 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
655 PCIeC2_1, PCIeC2_2 } },
656 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
657 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
658 GPIO1, Thermal } },
659 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
660 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
661 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
662 { INTICI7, INTICI6, INTICI5, INTICI4,
663 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
664};
665
666static struct intc_subgroup sh7786_subgroups[] __initdata = {
667 { 0xfe410c20, 32, SCIF1,
668 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
669 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
670};
671
672static struct intc_desc sh7786_intc_desc __initdata = {
673 .name = "sh7786",
674 .hw = {
675 .vectors = sh7786_vectors,
676 .nr_vectors = ARRAY_SIZE(sh7786_vectors),
677 .mask_regs = sh7786_mask_registers,
678 .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers),
679 .subgroups = sh7786_subgroups,
680 .nr_subgroups = ARRAY_SIZE(sh7786_subgroups),
681 .prio_regs = sh7786_prio_registers,
682 .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers),
683 },
684};
685
686/* Support for external interrupt pins in IRQ mode */
687static struct intc_vect vectors_irq0123[] __initdata = {
688 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
689 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
690};
691
692static struct intc_vect vectors_irq4567[] __initdata = {
693 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
694 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
695};
696
697static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
698 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
699 IRQ4, IRQ5, IRQ6, IRQ7 } },
700};
701
702static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
703 { 0xfe410024, 0, 32, /* INTREQ */
704 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
705};
706
707static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
708 vectors_irq0123, NULL, sh7786_mask_registers,
709 sh7786_prio_registers, sh7786_sense_registers,
710 sh7786_ack_registers);
711
712static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
713 vectors_irq4567, NULL, sh7786_mask_registers,
714 sh7786_prio_registers, sh7786_sense_registers,
715 sh7786_ack_registers);
716
717/* External interrupt pins in IRL mode */
718
719static struct intc_vect vectors_irl0123[] __initdata = {
720 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
721 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
722 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
723 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
724 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
725 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
726 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
727 INTC_VECT(IRL0_HHHL, 0x3c0),
728};
729
730static struct intc_vect vectors_irl4567[] __initdata = {
731 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
732 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
733 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
734 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
735 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
736 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
737 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
738 INTC_VECT(IRL4_HHHL, 0xac0),
739};
740
741static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
742 NULL, sh7786_mask_registers, NULL, NULL);
743
744static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
745 NULL, sh7786_mask_registers, NULL, NULL);
746
747#define INTC_ICR0 0xfe410000
748#define INTC_INTMSK0 CnINTMSK0
749#define INTC_INTMSK1 CnINTMSK1
750#define INTC_INTMSK2 INTMSK2
751#define INTC_INTMSKCLR1 CnINTMSKCLR1
752#define INTC_INTMSKCLR2 INTMSKCLR2
753
754void __init plat_irq_setup(void)
755{
756 /* disable IRQ3-0 + IRQ7-4 */
757 __raw_writel(0xff000000, INTC_INTMSK0);
758
759 /* disable IRL3-0 + IRL7-4 */
760 __raw_writel(0xc0000000, INTC_INTMSK1);
761 __raw_writel(0xfffefffe, INTC_INTMSK2);
762
763 /* select IRL mode for IRL3-0 + IRL7-4 */
764 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
765
766 register_intc_controller(&sh7786_intc_desc);
767}
768
769void __init plat_irq_setup_pins(int mode)
770{
771 switch (mode) {
772 case IRQ_MODE_IRQ7654:
773 /* select IRQ mode for IRL7-4 */
774 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
775 register_intc_controller(&intc_desc_irq4567);
776 break;
777 case IRQ_MODE_IRQ3210:
778 /* select IRQ mode for IRL3-0 */
779 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
780 register_intc_controller(&intc_desc_irq0123);
781 break;
782 case IRQ_MODE_IRL7654:
783 /* enable IRL7-4 but don't provide any masking */
784 __raw_writel(0x40000000, INTC_INTMSKCLR1);
785 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
786 break;
787 case IRQ_MODE_IRL3210:
788 /* enable IRL0-3 but don't provide any masking */
789 __raw_writel(0x80000000, INTC_INTMSKCLR1);
790 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
791 break;
792 case IRQ_MODE_IRL7654_MASK:
793 /* enable IRL7-4 and mask using cpu intc controller */
794 __raw_writel(0x40000000, INTC_INTMSKCLR1);
795 register_intc_controller(&intc_desc_irl4567);
796 break;
797 case IRQ_MODE_IRL3210_MASK:
798 /* enable IRL0-3 and mask using cpu intc controller */
799 __raw_writel(0x80000000, INTC_INTMSKCLR1);
800 register_intc_controller(&intc_desc_irl0123);
801 break;
802 default:
803 BUG();
804 }
805}
806
807void __init plat_mem_setup(void)
808{
809}
810
811static int __init sh7786_devices_setup(void)
812{
813 int ret, irq;
814
815 sh7786_usb_setup();
816
817 /*
818 * De-mux SCIF1 IRQs if possible
819 */
820 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
821 if (irq > 0) {
822 scif1_demux_resources[1].start =
823 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
824 scif1_demux_resources[2].start =
825 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
826 scif1_demux_resources[3].start = irq;
827 scif1_demux_resources[4].start =
828 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
829
830 scif1_device.resource = scif1_demux_resources;
831 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
832 }
833
834 ret = platform_add_devices(sh7786_early_devices,
835 ARRAY_SIZE(sh7786_early_devices));
836 if (unlikely(ret != 0))
837 return ret;
838
839 return platform_add_devices(sh7786_devices,
840 ARRAY_SIZE(sh7786_devices));
841}
842arch_initcall(sh7786_devices_setup);
843
844void __init plat_early_device_setup(void)
845{
846 early_platform_add_devices(sh7786_early_devices,
847 ARRAY_SIZE(sh7786_early_devices));
848}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SH7786 Setup
4 *
5 * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 * Paul Mundt <paul.mundt@renesas.com>
8 *
9 * Based on SH7785 Setup
10 *
11 * Copyright (C) 2007 Paul Mundt
12 */
13#include <linux/platform_device.h>
14#include <linux/init.h>
15#include <linux/serial.h>
16#include <linux/serial_sci.h>
17#include <linux/io.h>
18#include <linux/mm.h>
19#include <linux/dma-mapping.h>
20#include <linux/sh_timer.h>
21#include <linux/sh_dma.h>
22#include <linux/sh_intc.h>
23#include <linux/usb/ohci_pdriver.h>
24#include <cpu/dma-register.h>
25#include <asm/mmzone.h>
26
27static struct plat_sci_port scif0_platform_data = {
28 .scscr = SCSCR_REIE | SCSCR_CKE1,
29 .type = PORT_SCIF,
30 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
31};
32
33static struct resource scif0_resources[] = {
34 DEFINE_RES_MEM(0xffea0000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
39};
40
41static struct platform_device scif0_device = {
42 .name = "sh-sci",
43 .id = 0,
44 .resource = scif0_resources,
45 .num_resources = ARRAY_SIZE(scif0_resources),
46 .dev = {
47 .platform_data = &scif0_platform_data,
48 },
49};
50
51/*
52 * The rest of these all have multiplexed IRQs
53 */
54static struct plat_sci_port scif1_platform_data = {
55 .scscr = SCSCR_REIE | SCSCR_CKE1,
56 .type = PORT_SCIF,
57 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
58};
59
60static struct resource scif1_resources[] = {
61 DEFINE_RES_MEM(0xffeb0000, 0x100),
62 DEFINE_RES_IRQ(evt2irq(0x780)),
63};
64
65static struct resource scif1_demux_resources[] = {
66 DEFINE_RES_MEM(0xffeb0000, 0x100),
67 /* Placeholders, see sh7786_devices_setup() */
68 DEFINE_RES_IRQ(0),
69 DEFINE_RES_IRQ(0),
70 DEFINE_RES_IRQ(0),
71 DEFINE_RES_IRQ(0),
72};
73
74static struct platform_device scif1_device = {
75 .name = "sh-sci",
76 .id = 1,
77 .resource = scif1_resources,
78 .num_resources = ARRAY_SIZE(scif1_resources),
79 .dev = {
80 .platform_data = &scif1_platform_data,
81 },
82};
83
84static struct plat_sci_port scif2_platform_data = {
85 .scscr = SCSCR_REIE | SCSCR_CKE1,
86 .type = PORT_SCIF,
87 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
88};
89
90static struct resource scif2_resources[] = {
91 DEFINE_RES_MEM(0xffec0000, 0x100),
92 DEFINE_RES_IRQ(evt2irq(0x840)),
93};
94
95static struct platform_device scif2_device = {
96 .name = "sh-sci",
97 .id = 2,
98 .resource = scif2_resources,
99 .num_resources = ARRAY_SIZE(scif2_resources),
100 .dev = {
101 .platform_data = &scif2_platform_data,
102 },
103};
104
105static struct plat_sci_port scif3_platform_data = {
106 .scscr = SCSCR_REIE | SCSCR_CKE1,
107 .type = PORT_SCIF,
108 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
109};
110
111static struct resource scif3_resources[] = {
112 DEFINE_RES_MEM(0xffed0000, 0x100),
113 DEFINE_RES_IRQ(evt2irq(0x860)),
114};
115
116static struct platform_device scif3_device = {
117 .name = "sh-sci",
118 .id = 3,
119 .resource = scif3_resources,
120 .num_resources = ARRAY_SIZE(scif3_resources),
121 .dev = {
122 .platform_data = &scif3_platform_data,
123 },
124};
125
126static struct plat_sci_port scif4_platform_data = {
127 .scscr = SCSCR_REIE | SCSCR_CKE1,
128 .type = PORT_SCIF,
129 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
130};
131
132static struct resource scif4_resources[] = {
133 DEFINE_RES_MEM(0xffee0000, 0x100),
134 DEFINE_RES_IRQ(evt2irq(0x880)),
135};
136
137static struct platform_device scif4_device = {
138 .name = "sh-sci",
139 .id = 4,
140 .resource = scif4_resources,
141 .num_resources = ARRAY_SIZE(scif4_resources),
142 .dev = {
143 .platform_data = &scif4_platform_data,
144 },
145};
146
147static struct plat_sci_port scif5_platform_data = {
148 .scscr = SCSCR_REIE | SCSCR_CKE1,
149 .type = PORT_SCIF,
150 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
151};
152
153static struct resource scif5_resources[] = {
154 DEFINE_RES_MEM(0xffef0000, 0x100),
155 DEFINE_RES_IRQ(evt2irq(0x8a0)),
156};
157
158static struct platform_device scif5_device = {
159 .name = "sh-sci",
160 .id = 5,
161 .resource = scif5_resources,
162 .num_resources = ARRAY_SIZE(scif5_resources),
163 .dev = {
164 .platform_data = &scif5_platform_data,
165 },
166};
167
168static struct sh_timer_config tmu0_platform_data = {
169 .channels_mask = 7,
170};
171
172static struct resource tmu0_resources[] = {
173 DEFINE_RES_MEM(0xffd80000, 0x30),
174 DEFINE_RES_IRQ(evt2irq(0x400)),
175 DEFINE_RES_IRQ(evt2irq(0x420)),
176 DEFINE_RES_IRQ(evt2irq(0x440)),
177};
178
179static struct platform_device tmu0_device = {
180 .name = "sh-tmu",
181 .id = 0,
182 .dev = {
183 .platform_data = &tmu0_platform_data,
184 },
185 .resource = tmu0_resources,
186 .num_resources = ARRAY_SIZE(tmu0_resources),
187};
188
189static struct sh_timer_config tmu1_platform_data = {
190 .channels_mask = 7,
191};
192
193static struct resource tmu1_resources[] = {
194 DEFINE_RES_MEM(0xffda0000, 0x2c),
195 DEFINE_RES_IRQ(evt2irq(0x480)),
196 DEFINE_RES_IRQ(evt2irq(0x4a0)),
197 DEFINE_RES_IRQ(evt2irq(0x4c0)),
198};
199
200static struct platform_device tmu1_device = {
201 .name = "sh-tmu",
202 .id = 1,
203 .dev = {
204 .platform_data = &tmu1_platform_data,
205 },
206 .resource = tmu1_resources,
207 .num_resources = ARRAY_SIZE(tmu1_resources),
208};
209
210static struct sh_timer_config tmu2_platform_data = {
211 .channels_mask = 7,
212};
213
214static struct resource tmu2_resources[] = {
215 DEFINE_RES_MEM(0xffdc0000, 0x2c),
216 DEFINE_RES_IRQ(evt2irq(0x7a0)),
217 DEFINE_RES_IRQ(evt2irq(0x7a0)),
218 DEFINE_RES_IRQ(evt2irq(0x7a0)),
219};
220
221static struct platform_device tmu2_device = {
222 .name = "sh-tmu",
223 .id = 2,
224 .dev = {
225 .platform_data = &tmu2_platform_data,
226 },
227 .resource = tmu2_resources,
228 .num_resources = ARRAY_SIZE(tmu2_resources),
229};
230
231static struct sh_timer_config tmu3_platform_data = {
232 .channels_mask = 7,
233};
234
235static struct resource tmu3_resources[] = {
236 DEFINE_RES_MEM(0xffde0000, 0x2c),
237 DEFINE_RES_IRQ(evt2irq(0x7c0)),
238 DEFINE_RES_IRQ(evt2irq(0x7c0)),
239 DEFINE_RES_IRQ(evt2irq(0x7c0)),
240};
241
242static struct platform_device tmu3_device = {
243 .name = "sh-tmu",
244 .id = 3,
245 .dev = {
246 .platform_data = &tmu3_platform_data,
247 },
248 .resource = tmu3_resources,
249 .num_resources = ARRAY_SIZE(tmu3_resources),
250};
251
252static const struct sh_dmae_channel dmac0_channels[] = {
253 {
254 .offset = 0,
255 .dmars = 0,
256 .dmars_bit = 0,
257 }, {
258 .offset = 0x10,
259 .dmars = 0,
260 .dmars_bit = 8,
261 }, {
262 .offset = 0x20,
263 .dmars = 4,
264 .dmars_bit = 0,
265 }, {
266 .offset = 0x30,
267 .dmars = 4,
268 .dmars_bit = 8,
269 }, {
270 .offset = 0x50,
271 .dmars = 8,
272 .dmars_bit = 0,
273 }, {
274 .offset = 0x60,
275 .dmars = 8,
276 .dmars_bit = 8,
277 }
278};
279
280static const unsigned int ts_shift[] = TS_SHIFT;
281
282static struct sh_dmae_pdata dma0_platform_data = {
283 .channel = dmac0_channels,
284 .channel_num = ARRAY_SIZE(dmac0_channels),
285 .ts_low_shift = CHCR_TS_LOW_SHIFT,
286 .ts_low_mask = CHCR_TS_LOW_MASK,
287 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
288 .ts_high_mask = CHCR_TS_HIGH_MASK,
289 .ts_shift = ts_shift,
290 .ts_shift_num = ARRAY_SIZE(ts_shift),
291 .dmaor_init = DMAOR_INIT,
292};
293
294/* Resource order important! */
295static struct resource dmac0_resources[] = {
296 {
297 /* Channel registers and DMAOR */
298 .start = 0xfe008020,
299 .end = 0xfe00808f,
300 .flags = IORESOURCE_MEM,
301 }, {
302 /* DMARSx */
303 .start = 0xfe009000,
304 .end = 0xfe00900b,
305 .flags = IORESOURCE_MEM,
306 }, {
307 .name = "error_irq",
308 .start = evt2irq(0x5c0),
309 .end = evt2irq(0x5c0),
310 .flags = IORESOURCE_IRQ,
311 }, {
312 /* IRQ for channels 0-5 */
313 .start = evt2irq(0x500),
314 .end = evt2irq(0x5a0),
315 .flags = IORESOURCE_IRQ,
316 },
317};
318
319static struct platform_device dma0_device = {
320 .name = "sh-dma-engine",
321 .id = 0,
322 .resource = dmac0_resources,
323 .num_resources = ARRAY_SIZE(dmac0_resources),
324 .dev = {
325 .platform_data = &dma0_platform_data,
326 },
327};
328
329#define USB_EHCI_START 0xffe70000
330#define USB_OHCI_START 0xffe70400
331
332static struct resource usb_ehci_resources[] = {
333 [0] = {
334 .start = USB_EHCI_START,
335 .end = USB_EHCI_START + 0x3ff,
336 .flags = IORESOURCE_MEM,
337 },
338 [1] = {
339 .start = evt2irq(0xba0),
340 .end = evt2irq(0xba0),
341 .flags = IORESOURCE_IRQ,
342 },
343};
344
345static struct platform_device usb_ehci_device = {
346 .name = "sh_ehci",
347 .id = -1,
348 .dev = {
349 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
351 },
352 .num_resources = ARRAY_SIZE(usb_ehci_resources),
353 .resource = usb_ehci_resources,
354};
355
356static struct resource usb_ohci_resources[] = {
357 [0] = {
358 .start = USB_OHCI_START,
359 .end = USB_OHCI_START + 0x3ff,
360 .flags = IORESOURCE_MEM,
361 },
362 [1] = {
363 .start = evt2irq(0xba0),
364 .end = evt2irq(0xba0),
365 .flags = IORESOURCE_IRQ,
366 },
367};
368
369static struct usb_ohci_pdata usb_ohci_pdata;
370
371static struct platform_device usb_ohci_device = {
372 .name = "ohci-platform",
373 .id = -1,
374 .dev = {
375 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
376 .coherent_dma_mask = DMA_BIT_MASK(32),
377 .platform_data = &usb_ohci_pdata,
378 },
379 .num_resources = ARRAY_SIZE(usb_ohci_resources),
380 .resource = usb_ohci_resources,
381};
382
383static struct platform_device *sh7786_early_devices[] __initdata = {
384 &scif0_device,
385 &scif1_device,
386 &scif2_device,
387 &scif3_device,
388 &scif4_device,
389 &scif5_device,
390 &tmu0_device,
391 &tmu1_device,
392 &tmu2_device,
393};
394
395static struct platform_device *sh7786_devices[] __initdata = {
396 &dma0_device,
397 &usb_ehci_device,
398 &usb_ohci_device,
399};
400
401/*
402 * Please call this function if your platform board
403 * use external clock for USB
404 * */
405#define USBCTL0 0xffe70858
406#define CLOCK_MODE_MASK 0xffffff7f
407#define EXT_CLOCK_MODE 0x00000080
408
409void __init sh7786_usb_use_exclock(void)
410{
411 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
412 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
413}
414
415#define USBINITREG1 0xffe70094
416#define USBINITREG2 0xffe7009c
417#define USBINITVAL1 0x00ff0040
418#define USBINITVAL2 0x00000001
419
420#define USBPCTL1 0xffe70804
421#define USBST 0xffe70808
422#define PHY_ENB 0x00000001
423#define PLL_ENB 0x00000002
424#define PHY_RST 0x00000004
425#define ACT_PLL_STATUS 0xc0000000
426
427static void __init sh7786_usb_setup(void)
428{
429 int i = 1000000;
430
431 /*
432 * USB initial settings
433 *
434 * The following settings are necessary
435 * for using the USB modules.
436 *
437 * see "USB Initial Settings" for detail
438 */
439 __raw_writel(USBINITVAL1, USBINITREG1);
440 __raw_writel(USBINITVAL2, USBINITREG2);
441
442 /*
443 * Set the PHY and PLL enable bit
444 */
445 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
446 while (i--) {
447 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
448 /* Set the PHY RST bit */
449 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
450 printk(KERN_INFO "sh7786 usb setup done\n");
451 break;
452 }
453 cpu_relax();
454 }
455}
456
457enum {
458 UNUSED = 0,
459
460 /* interrupt sources */
461 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
462 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
463 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
464 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
465
466 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
467 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
468 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
469 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
470
471 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
472 WDT,
473 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
474 TMU1_0, TMU1_1, TMU1_2,
475 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
476 HUDI1, HUDI0,
477 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
478 HPB_0, HPB_1, HPB_2,
479 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
480 SCIF1,
481 TMU2, TMU3,
482 SCIF2, SCIF3, SCIF4, SCIF5,
483 Eth_0, Eth_1,
484 PCIeC0_0, PCIeC0_1, PCIeC0_2,
485 PCIeC1_0, PCIeC1_1, PCIeC1_2,
486 USB,
487 I2C0, I2C1,
488 DU,
489 SSI0, SSI1, SSI2, SSI3,
490 PCIeC2_0, PCIeC2_1, PCIeC2_2,
491 HAC0, HAC1,
492 FLCTL,
493 HSPI,
494 GPIO0, GPIO1,
495 Thermal,
496 INTICI0, INTICI1, INTICI2, INTICI3,
497 INTICI4, INTICI5, INTICI6, INTICI7,
498
499 /* Muxed sub-events */
500 TXI1, BRI1, RXI1, ERI1,
501};
502
503static struct intc_vect sh7786_vectors[] __initdata = {
504 INTC_VECT(WDT, 0x3e0),
505 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
506 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
507 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
508 INTC_VECT(TMU1_2, 0x4c0),
509 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
510 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
511 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
512 INTC_VECT(DMAC0_6, 0x5c0),
513 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
514 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
515 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
516 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
517 INTC_VECT(HPB_2, 0x6e0),
518 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
519 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
520 INTC_VECT(SCIF1, 0x780),
521 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
522 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
523 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
524 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
525 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
526 INTC_VECT(PCIeC0_2, 0xb20),
527 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
528 INTC_VECT(PCIeC1_2, 0xb80),
529 INTC_VECT(USB, 0xba0),
530 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
531 INTC_VECT(DU, 0xd00),
532 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
533 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
534 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
535 INTC_VECT(PCIeC2_2, 0xde0),
536 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
537 INTC_VECT(FLCTL, 0xe40),
538 INTC_VECT(HSPI, 0xe80),
539 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
540 INTC_VECT(Thermal, 0xee0),
541 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
542 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
543 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
544 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
545};
546
547#define CnINTMSK0 0xfe410030
548#define CnINTMSK1 0xfe410040
549#define CnINTMSKCLR0 0xfe410050
550#define CnINTMSKCLR1 0xfe410060
551#define CnINT2MSKR0 0xfe410a20
552#define CnINT2MSKR1 0xfe410a24
553#define CnINT2MSKR2 0xfe410a28
554#define CnINT2MSKR3 0xfe410a2c
555#define CnINT2MSKCR0 0xfe410a30
556#define CnINT2MSKCR1 0xfe410a34
557#define CnINT2MSKCR2 0xfe410a38
558#define CnINT2MSKCR3 0xfe410a3c
559#define INTMSK2 0xfe410068
560#define INTMSKCLR2 0xfe41006c
561
562#define INTDISTCR0 0xfe4100b0
563#define INTDISTCR1 0xfe4100b4
564#define INT2DISTCR0 0xfe410900
565#define INT2DISTCR1 0xfe410904
566#define INT2DISTCR2 0xfe410908
567#define INT2DISTCR3 0xfe41090c
568
569static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
570 { CnINTMSK0, CnINTMSKCLR0, 32,
571 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
572 INTC_SMP_BALANCING(INTDISTCR0) },
573 { INTMSK2, INTMSKCLR2, 32,
574 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
575 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
576 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
577 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
578 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
579 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
580 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
581 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
582 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
583 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
585 INTC_SMP_BALANCING(INT2DISTCR0) },
586 { CnINT2MSKR1, CnINT2MSKCR1, 32,
587 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
588 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
589 HUDI1, HUDI0,
590 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
591 HPB_0, HPB_1, HPB_2,
592 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
593 SCIF1,
594 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
595 { CnINT2MSKR2, CnINT2MSKCR2, 32,
596 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
597 Eth_0, Eth_1,
598 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
599 PCIeC0_0, PCIeC0_1, PCIeC0_2,
600 PCIeC1_0, PCIeC1_1, PCIeC1_2,
601 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
602 { CnINT2MSKR3, CnINT2MSKCR3, 32,
603 { 0, 0, 0, 0, 0, 0,
604 I2C0, I2C1,
605 DU, SSI0, SSI1, SSI2, SSI3,
606 PCIeC2_0, PCIeC2_1, PCIeC2_2,
607 HAC0, HAC1,
608 FLCTL, 0,
609 HSPI, GPIO0, GPIO1, Thermal,
610 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
611};
612
613static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
614 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
615 IRQ4, IRQ5, IRQ6, IRQ7 } },
616 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
617 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
618 TMU0_2, TMU0_3 } },
619 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
620 TMU1_2, 0 } },
621 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
622 DMAC0_2, DMAC0_3 } },
623 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
624 DMAC0_6, HUDI1 } },
625 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
626 DMAC1_1, DMAC1_2 } },
627 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
628 HPB_1, HPB_2 } },
629 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
630 SCIF0_2, SCIF0_3 } },
631 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
632 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
633 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
634 Eth_0, Eth_1 } },
635 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
636 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
637 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
638 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
639 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
640 PCIeC1_0, PCIeC1_1 } },
641 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
642 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
643 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
644 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
645 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
646 PCIeC2_1, PCIeC2_2 } },
647 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
648 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
649 GPIO1, Thermal } },
650 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
651 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
652 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
653 { INTICI7, INTICI6, INTICI5, INTICI4,
654 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
655};
656
657static struct intc_subgroup sh7786_subgroups[] __initdata = {
658 { 0xfe410c20, 32, SCIF1,
659 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
660 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
661};
662
663static struct intc_desc sh7786_intc_desc __initdata = {
664 .name = "sh7786",
665 .hw = {
666 .vectors = sh7786_vectors,
667 .nr_vectors = ARRAY_SIZE(sh7786_vectors),
668 .mask_regs = sh7786_mask_registers,
669 .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers),
670 .subgroups = sh7786_subgroups,
671 .nr_subgroups = ARRAY_SIZE(sh7786_subgroups),
672 .prio_regs = sh7786_prio_registers,
673 .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers),
674 },
675};
676
677/* Support for external interrupt pins in IRQ mode */
678static struct intc_vect vectors_irq0123[] __initdata = {
679 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
680 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
681};
682
683static struct intc_vect vectors_irq4567[] __initdata = {
684 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
685 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
686};
687
688static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
689 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
690 IRQ4, IRQ5, IRQ6, IRQ7 } },
691};
692
693static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
694 { 0xfe410024, 0, 32, /* INTREQ */
695 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
696};
697
698static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
699 vectors_irq0123, NULL, sh7786_mask_registers,
700 sh7786_prio_registers, sh7786_sense_registers,
701 sh7786_ack_registers);
702
703static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
704 vectors_irq4567, NULL, sh7786_mask_registers,
705 sh7786_prio_registers, sh7786_sense_registers,
706 sh7786_ack_registers);
707
708/* External interrupt pins in IRL mode */
709
710static struct intc_vect vectors_irl0123[] __initdata = {
711 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
712 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
713 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
714 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
715 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
716 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
717 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
718 INTC_VECT(IRL0_HHHL, 0x3c0),
719};
720
721static struct intc_vect vectors_irl4567[] __initdata = {
722 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
723 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
724 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
725 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
726 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
727 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
728 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
729 INTC_VECT(IRL4_HHHL, 0xac0),
730};
731
732static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
733 NULL, sh7786_mask_registers, NULL, NULL);
734
735static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
736 NULL, sh7786_mask_registers, NULL, NULL);
737
738#define INTC_ICR0 0xfe410000
739#define INTC_INTMSK0 CnINTMSK0
740#define INTC_INTMSK1 CnINTMSK1
741#define INTC_INTMSK2 INTMSK2
742#define INTC_INTMSKCLR1 CnINTMSKCLR1
743#define INTC_INTMSKCLR2 INTMSKCLR2
744
745void __init plat_irq_setup(void)
746{
747 /* disable IRQ3-0 + IRQ7-4 */
748 __raw_writel(0xff000000, INTC_INTMSK0);
749
750 /* disable IRL3-0 + IRL7-4 */
751 __raw_writel(0xc0000000, INTC_INTMSK1);
752 __raw_writel(0xfffefffe, INTC_INTMSK2);
753
754 /* select IRL mode for IRL3-0 + IRL7-4 */
755 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
756
757 register_intc_controller(&sh7786_intc_desc);
758}
759
760void __init plat_irq_setup_pins(int mode)
761{
762 switch (mode) {
763 case IRQ_MODE_IRQ7654:
764 /* select IRQ mode for IRL7-4 */
765 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
766 register_intc_controller(&intc_desc_irq4567);
767 break;
768 case IRQ_MODE_IRQ3210:
769 /* select IRQ mode for IRL3-0 */
770 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
771 register_intc_controller(&intc_desc_irq0123);
772 break;
773 case IRQ_MODE_IRL7654:
774 /* enable IRL7-4 but don't provide any masking */
775 __raw_writel(0x40000000, INTC_INTMSKCLR1);
776 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
777 break;
778 case IRQ_MODE_IRL3210:
779 /* enable IRL0-3 but don't provide any masking */
780 __raw_writel(0x80000000, INTC_INTMSKCLR1);
781 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
782 break;
783 case IRQ_MODE_IRL7654_MASK:
784 /* enable IRL7-4 and mask using cpu intc controller */
785 __raw_writel(0x40000000, INTC_INTMSKCLR1);
786 register_intc_controller(&intc_desc_irl4567);
787 break;
788 case IRQ_MODE_IRL3210_MASK:
789 /* enable IRL0-3 and mask using cpu intc controller */
790 __raw_writel(0x80000000, INTC_INTMSKCLR1);
791 register_intc_controller(&intc_desc_irl0123);
792 break;
793 default:
794 BUG();
795 }
796}
797
798void __init plat_mem_setup(void)
799{
800}
801
802static int __init sh7786_devices_setup(void)
803{
804 int ret, irq;
805
806 sh7786_usb_setup();
807
808 /*
809 * De-mux SCIF1 IRQs if possible
810 */
811 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
812 if (irq > 0) {
813 scif1_demux_resources[1].start =
814 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
815 scif1_demux_resources[2].start =
816 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
817 scif1_demux_resources[3].start = irq;
818 scif1_demux_resources[4].start =
819 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
820
821 scif1_device.resource = scif1_demux_resources;
822 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
823 }
824
825 ret = platform_add_devices(sh7786_early_devices,
826 ARRAY_SIZE(sh7786_early_devices));
827 if (unlikely(ret != 0))
828 return ret;
829
830 return platform_add_devices(sh7786_devices,
831 ARRAY_SIZE(sh7786_devices));
832}
833arch_initcall(sh7786_devices_setup);
834
835void __init plat_early_device_setup(void)
836{
837 early_platform_add_devices(sh7786_early_devices,
838 ARRAY_SIZE(sh7786_early_devices));
839}