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1/*
2 * SH7785 Setup
3 *
4 * Copyright (C) 2007 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/serial_sci.h>
14#include <linux/io.h>
15#include <linux/mm.h>
16#include <linux/sh_dma.h>
17#include <linux/sh_timer.h>
18#include <linux/sh_intc.h>
19#include <asm/mmzone.h>
20#include <cpu/dma-register.h>
21
22static struct plat_sci_port scif0_platform_data = {
23 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
25 .type = PORT_SCIF,
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
27};
28
29static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffea0000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0x700)),
32};
33
34static struct platform_device scif0_device = {
35 .name = "sh-sci",
36 .id = 0,
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
39 .dev = {
40 .platform_data = &scif0_platform_data,
41 },
42};
43
44static struct plat_sci_port scif1_platform_data = {
45 .flags = UPF_BOOT_AUTOCONF,
46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
47 .type = PORT_SCIF,
48 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
49};
50
51static struct resource scif1_resources[] = {
52 DEFINE_RES_MEM(0xffeb0000, 0x100),
53 DEFINE_RES_IRQ(evt2irq(0x780)),
54};
55
56static struct platform_device scif1_device = {
57 .name = "sh-sci",
58 .id = 1,
59 .resource = scif1_resources,
60 .num_resources = ARRAY_SIZE(scif1_resources),
61 .dev = {
62 .platform_data = &scif1_platform_data,
63 },
64};
65
66static struct plat_sci_port scif2_platform_data = {
67 .flags = UPF_BOOT_AUTOCONF,
68 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
69 .type = PORT_SCIF,
70 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
71};
72
73static struct resource scif2_resources[] = {
74 DEFINE_RES_MEM(0xffec0000, 0x100),
75 DEFINE_RES_IRQ(evt2irq(0x980)),
76};
77
78static struct platform_device scif2_device = {
79 .name = "sh-sci",
80 .id = 2,
81 .resource = scif2_resources,
82 .num_resources = ARRAY_SIZE(scif2_resources),
83 .dev = {
84 .platform_data = &scif2_platform_data,
85 },
86};
87
88static struct plat_sci_port scif3_platform_data = {
89 .flags = UPF_BOOT_AUTOCONF,
90 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
91 .type = PORT_SCIF,
92 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
93};
94
95static struct resource scif3_resources[] = {
96 DEFINE_RES_MEM(0xffed0000, 0x100),
97 DEFINE_RES_IRQ(evt2irq(0x9a0)),
98};
99
100static struct platform_device scif3_device = {
101 .name = "sh-sci",
102 .id = 3,
103 .resource = scif3_resources,
104 .num_resources = ARRAY_SIZE(scif3_resources),
105 .dev = {
106 .platform_data = &scif3_platform_data,
107 },
108};
109
110static struct plat_sci_port scif4_platform_data = {
111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
113 .type = PORT_SCIF,
114 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
115};
116
117static struct resource scif4_resources[] = {
118 DEFINE_RES_MEM(0xffee0000, 0x100),
119 DEFINE_RES_IRQ(evt2irq(0x9c0)),
120};
121
122static struct platform_device scif4_device = {
123 .name = "sh-sci",
124 .id = 4,
125 .resource = scif4_resources,
126 .num_resources = ARRAY_SIZE(scif4_resources),
127 .dev = {
128 .platform_data = &scif4_platform_data,
129 },
130};
131
132static struct plat_sci_port scif5_platform_data = {
133 .flags = UPF_BOOT_AUTOCONF,
134 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
135 .type = PORT_SCIF,
136 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
137};
138
139static struct resource scif5_resources[] = {
140 DEFINE_RES_MEM(0xffef0000, 0x100),
141 DEFINE_RES_IRQ(evt2irq(0x9e0)),
142};
143
144static struct platform_device scif5_device = {
145 .name = "sh-sci",
146 .id = 5,
147 .resource = scif5_resources,
148 .num_resources = ARRAY_SIZE(scif5_resources),
149 .dev = {
150 .platform_data = &scif5_platform_data,
151 },
152};
153
154static struct sh_timer_config tmu0_platform_data = {
155 .channels_mask = 7,
156};
157
158static struct resource tmu0_resources[] = {
159 DEFINE_RES_MEM(0xffd80000, 0x30),
160 DEFINE_RES_IRQ(evt2irq(0x580)),
161 DEFINE_RES_IRQ(evt2irq(0x5a0)),
162 DEFINE_RES_IRQ(evt2irq(0x5c0)),
163};
164
165static struct platform_device tmu0_device = {
166 .name = "sh-tmu",
167 .id = 0,
168 .dev = {
169 .platform_data = &tmu0_platform_data,
170 },
171 .resource = tmu0_resources,
172 .num_resources = ARRAY_SIZE(tmu0_resources),
173};
174
175static struct sh_timer_config tmu1_platform_data = {
176 .channels_mask = 7,
177};
178
179static struct resource tmu1_resources[] = {
180 DEFINE_RES_MEM(0xffdc0000, 0x2c),
181 DEFINE_RES_IRQ(evt2irq(0xe00)),
182 DEFINE_RES_IRQ(evt2irq(0xe20)),
183 DEFINE_RES_IRQ(evt2irq(0xe40)),
184};
185
186static struct platform_device tmu1_device = {
187 .name = "sh-tmu",
188 .id = 1,
189 .dev = {
190 .platform_data = &tmu1_platform_data,
191 },
192 .resource = tmu1_resources,
193 .num_resources = ARRAY_SIZE(tmu1_resources),
194};
195
196/* DMA */
197static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
198 {
199 .offset = 0,
200 .dmars = 0,
201 .dmars_bit = 0,
202 }, {
203 .offset = 0x10,
204 .dmars = 0,
205 .dmars_bit = 8,
206 }, {
207 .offset = 0x20,
208 .dmars = 4,
209 .dmars_bit = 0,
210 }, {
211 .offset = 0x30,
212 .dmars = 4,
213 .dmars_bit = 8,
214 }, {
215 .offset = 0x50,
216 .dmars = 8,
217 .dmars_bit = 0,
218 }, {
219 .offset = 0x60,
220 .dmars = 8,
221 .dmars_bit = 8,
222 }
223};
224
225static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
226 {
227 .offset = 0,
228 }, {
229 .offset = 0x10,
230 }, {
231 .offset = 0x20,
232 }, {
233 .offset = 0x30,
234 }, {
235 .offset = 0x50,
236 }, {
237 .offset = 0x60,
238 }
239};
240
241static const unsigned int ts_shift[] = TS_SHIFT;
242
243static struct sh_dmae_pdata dma0_platform_data = {
244 .channel = sh7785_dmae0_channels,
245 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
246 .ts_low_shift = CHCR_TS_LOW_SHIFT,
247 .ts_low_mask = CHCR_TS_LOW_MASK,
248 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
249 .ts_high_mask = CHCR_TS_HIGH_MASK,
250 .ts_shift = ts_shift,
251 .ts_shift_num = ARRAY_SIZE(ts_shift),
252 .dmaor_init = DMAOR_INIT,
253};
254
255static struct sh_dmae_pdata dma1_platform_data = {
256 .channel = sh7785_dmae1_channels,
257 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
258 .ts_low_shift = CHCR_TS_LOW_SHIFT,
259 .ts_low_mask = CHCR_TS_LOW_MASK,
260 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
261 .ts_high_mask = CHCR_TS_HIGH_MASK,
262 .ts_shift = ts_shift,
263 .ts_shift_num = ARRAY_SIZE(ts_shift),
264 .dmaor_init = DMAOR_INIT,
265};
266
267static struct resource sh7785_dmae0_resources[] = {
268 [0] = {
269 /* Channel registers and DMAOR */
270 .start = 0xfc808020,
271 .end = 0xfc80808f,
272 .flags = IORESOURCE_MEM,
273 },
274 [1] = {
275 /* DMARSx */
276 .start = 0xfc809000,
277 .end = 0xfc80900b,
278 .flags = IORESOURCE_MEM,
279 },
280 {
281 /*
282 * Real DMA error vector is 0x6e0, and channel
283 * vectors are 0x620-0x6c0
284 */
285 .name = "error_irq",
286 .start = evt2irq(0x620),
287 .end = evt2irq(0x620),
288 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
289 },
290};
291
292static struct resource sh7785_dmae1_resources[] = {
293 [0] = {
294 /* Channel registers and DMAOR */
295 .start = 0xfcc08020,
296 .end = 0xfcc0808f,
297 .flags = IORESOURCE_MEM,
298 },
299 /* DMAC1 has no DMARS */
300 {
301 /*
302 * Real DMA error vector is 0x940, and channel
303 * vectors are 0x880-0x920
304 */
305 .name = "error_irq",
306 .start = evt2irq(0x880),
307 .end = evt2irq(0x880),
308 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
309 },
310};
311
312static struct platform_device dma0_device = {
313 .name = "sh-dma-engine",
314 .id = 0,
315 .resource = sh7785_dmae0_resources,
316 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
317 .dev = {
318 .platform_data = &dma0_platform_data,
319 },
320};
321
322static struct platform_device dma1_device = {
323 .name = "sh-dma-engine",
324 .id = 1,
325 .resource = sh7785_dmae1_resources,
326 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
327 .dev = {
328 .platform_data = &dma1_platform_data,
329 },
330};
331
332static struct platform_device *sh7785_devices[] __initdata = {
333 &scif0_device,
334 &scif1_device,
335 &scif2_device,
336 &scif3_device,
337 &scif4_device,
338 &scif5_device,
339 &tmu0_device,
340 &tmu1_device,
341 &dma0_device,
342 &dma1_device,
343};
344
345static int __init sh7785_devices_setup(void)
346{
347 return platform_add_devices(sh7785_devices,
348 ARRAY_SIZE(sh7785_devices));
349}
350arch_initcall(sh7785_devices_setup);
351
352static struct platform_device *sh7785_early_devices[] __initdata = {
353 &scif0_device,
354 &scif1_device,
355 &scif2_device,
356 &scif3_device,
357 &scif4_device,
358 &scif5_device,
359 &tmu0_device,
360 &tmu1_device,
361};
362
363void __init plat_early_device_setup(void)
364{
365 early_platform_add_devices(sh7785_early_devices,
366 ARRAY_SIZE(sh7785_early_devices));
367}
368
369enum {
370 UNUSED = 0,
371
372 /* interrupt sources */
373
374 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
375 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
376 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
377 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
378
379 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
380 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
381 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
382 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
383
384 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
385 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
386 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
387 SCIF2, SCIF3, SCIF4, SCIF5,
388 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
389 SIOF, MMCIF, DU, GDTA,
390 TMU3, TMU4, TMU5,
391 SSI0, SSI1,
392 HAC0, HAC1,
393 FLCTL, GPIO,
394
395 /* interrupt groups */
396
397 TMU012, TMU345
398};
399
400static struct intc_vect vectors[] __initdata = {
401 INTC_VECT(WDT, 0x560),
402 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
403 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
404 INTC_VECT(HUDI, 0x600),
405 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
406 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
407 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
408 INTC_VECT(DMAC0, 0x6e0),
409 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
410 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
411 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
412 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
413 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
414 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
415 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
416 INTC_VECT(DMAC1, 0x940),
417 INTC_VECT(HSPI, 0x960),
418 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
419 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
420 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
421 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
422 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
423 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
424 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
425 INTC_VECT(SIOF, 0xc00),
426 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
427 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
428 INTC_VECT(DU, 0xd80),
429 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
430 INTC_VECT(GDTA, 0xde0),
431 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
432 INTC_VECT(TMU5, 0xe40),
433 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
434 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
435 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
436 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
437 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
438 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
439};
440
441static struct intc_group groups[] __initdata = {
442 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
443 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
444};
445
446static struct intc_mask_reg mask_registers[] __initdata = {
447 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
448 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
449
450 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
451 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
452 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
453 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
454 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
455 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
456 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
457 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
458 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
459
460 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
461 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
462 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
463 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
464 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
465};
466
467static struct intc_prio_reg prio_registers[] __initdata = {
468 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
469 IRQ4, IRQ5, IRQ6, IRQ7 } },
470 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
471 TMU2, TMU2_TICPI } },
472 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
473 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
474 SCIF2, SCIF3 } },
475 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
476 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
477 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
478 PCISERR, PCIINTA } },
479 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
480 PCIINTD, PCIC5 } },
481 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
482 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
483 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
484};
485
486static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
487 mask_registers, prio_registers, NULL);
488
489/* Support for external interrupt pins in IRQ mode */
490
491static struct intc_vect vectors_irq0123[] __initdata = {
492 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
493 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
494};
495
496static struct intc_vect vectors_irq4567[] __initdata = {
497 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
498 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
499};
500
501static struct intc_sense_reg sense_registers[] __initdata = {
502 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
503 IRQ4, IRQ5, IRQ6, IRQ7 } },
504};
505
506static struct intc_mask_reg ack_registers[] __initdata = {
507 { 0xffd00024, 0, 32, /* INTREQ */
508 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
509};
510
511static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
512 vectors_irq0123, NULL, mask_registers,
513 prio_registers, sense_registers, ack_registers);
514
515static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
516 vectors_irq4567, NULL, mask_registers,
517 prio_registers, sense_registers, ack_registers);
518
519/* External interrupt pins in IRL mode */
520
521static struct intc_vect vectors_irl0123[] __initdata = {
522 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
523 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
524 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
525 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
526 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
527 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
528 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
529 INTC_VECT(IRL0_HHHL, 0x3c0),
530};
531
532static struct intc_vect vectors_irl4567[] __initdata = {
533 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
534 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
535 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
536 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
537 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
538 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
539 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
540 INTC_VECT(IRL4_HHHL, 0xcc0),
541};
542
543static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
544 NULL, mask_registers, NULL, NULL);
545
546static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
547 NULL, mask_registers, NULL, NULL);
548
549#define INTC_ICR0 0xffd00000
550#define INTC_INTMSK0 0xffd00044
551#define INTC_INTMSK1 0xffd00048
552#define INTC_INTMSK2 0xffd40080
553#define INTC_INTMSKCLR1 0xffd00068
554#define INTC_INTMSKCLR2 0xffd40084
555
556void __init plat_irq_setup(void)
557{
558 /* disable IRQ3-0 + IRQ7-4 */
559 __raw_writel(0xff000000, INTC_INTMSK0);
560
561 /* disable IRL3-0 + IRL7-4 */
562 __raw_writel(0xc0000000, INTC_INTMSK1);
563 __raw_writel(0xfffefffe, INTC_INTMSK2);
564
565 /* select IRL mode for IRL3-0 + IRL7-4 */
566 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
567
568 /* disable holding function, ie enable "SH-4 Mode" */
569 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
570
571 register_intc_controller(&intc_desc);
572}
573
574void __init plat_irq_setup_pins(int mode)
575{
576 switch (mode) {
577 case IRQ_MODE_IRQ7654:
578 /* select IRQ mode for IRL7-4 */
579 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
580 register_intc_controller(&intc_desc_irq4567);
581 break;
582 case IRQ_MODE_IRQ3210:
583 /* select IRQ mode for IRL3-0 */
584 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
585 register_intc_controller(&intc_desc_irq0123);
586 break;
587 case IRQ_MODE_IRL7654:
588 /* enable IRL7-4 but don't provide any masking */
589 __raw_writel(0x40000000, INTC_INTMSKCLR1);
590 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
591 break;
592 case IRQ_MODE_IRL3210:
593 /* enable IRL0-3 but don't provide any masking */
594 __raw_writel(0x80000000, INTC_INTMSKCLR1);
595 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
596 break;
597 case IRQ_MODE_IRL7654_MASK:
598 /* enable IRL7-4 and mask using cpu intc controller */
599 __raw_writel(0x40000000, INTC_INTMSKCLR1);
600 register_intc_controller(&intc_desc_irl4567);
601 break;
602 case IRQ_MODE_IRL3210_MASK:
603 /* enable IRL0-3 and mask using cpu intc controller */
604 __raw_writel(0x80000000, INTC_INTMSKCLR1);
605 register_intc_controller(&intc_desc_irl0123);
606 break;
607 default:
608 BUG();
609 }
610}
611
612void __init plat_mem_setup(void)
613{
614 /* Register the URAM space as Node 1 */
615 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
616}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SH7785 Setup
4 *
5 * Copyright (C) 2007 Paul Mundt
6 */
7#include <linux/platform_device.h>
8#include <linux/init.h>
9#include <linux/serial.h>
10#include <linux/serial_sci.h>
11#include <linux/io.h>
12#include <linux/mm.h>
13#include <linux/sh_dma.h>
14#include <linux/sh_timer.h>
15#include <linux/sh_intc.h>
16#include <asm/mmzone.h>
17#include <cpu/dma-register.h>
18
19static struct plat_sci_port scif0_platform_data = {
20 .scscr = SCSCR_REIE | SCSCR_CKE1,
21 .type = PORT_SCIF,
22 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
23};
24
25static struct resource scif0_resources[] = {
26 DEFINE_RES_MEM(0xffea0000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
28};
29
30static struct platform_device scif0_device = {
31 .name = "sh-sci",
32 .id = 0,
33 .resource = scif0_resources,
34 .num_resources = ARRAY_SIZE(scif0_resources),
35 .dev = {
36 .platform_data = &scif0_platform_data,
37 },
38};
39
40static struct plat_sci_port scif1_platform_data = {
41 .scscr = SCSCR_REIE | SCSCR_CKE1,
42 .type = PORT_SCIF,
43 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
44};
45
46static struct resource scif1_resources[] = {
47 DEFINE_RES_MEM(0xffeb0000, 0x100),
48 DEFINE_RES_IRQ(evt2irq(0x780)),
49};
50
51static struct platform_device scif1_device = {
52 .name = "sh-sci",
53 .id = 1,
54 .resource = scif1_resources,
55 .num_resources = ARRAY_SIZE(scif1_resources),
56 .dev = {
57 .platform_data = &scif1_platform_data,
58 },
59};
60
61static struct plat_sci_port scif2_platform_data = {
62 .scscr = SCSCR_REIE | SCSCR_CKE1,
63 .type = PORT_SCIF,
64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
65};
66
67static struct resource scif2_resources[] = {
68 DEFINE_RES_MEM(0xffec0000, 0x100),
69 DEFINE_RES_IRQ(evt2irq(0x980)),
70};
71
72static struct platform_device scif2_device = {
73 .name = "sh-sci",
74 .id = 2,
75 .resource = scif2_resources,
76 .num_resources = ARRAY_SIZE(scif2_resources),
77 .dev = {
78 .platform_data = &scif2_platform_data,
79 },
80};
81
82static struct plat_sci_port scif3_platform_data = {
83 .scscr = SCSCR_REIE | SCSCR_CKE1,
84 .type = PORT_SCIF,
85 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
86};
87
88static struct resource scif3_resources[] = {
89 DEFINE_RES_MEM(0xffed0000, 0x100),
90 DEFINE_RES_IRQ(evt2irq(0x9a0)),
91};
92
93static struct platform_device scif3_device = {
94 .name = "sh-sci",
95 .id = 3,
96 .resource = scif3_resources,
97 .num_resources = ARRAY_SIZE(scif3_resources),
98 .dev = {
99 .platform_data = &scif3_platform_data,
100 },
101};
102
103static struct plat_sci_port scif4_platform_data = {
104 .scscr = SCSCR_REIE | SCSCR_CKE1,
105 .type = PORT_SCIF,
106 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
107};
108
109static struct resource scif4_resources[] = {
110 DEFINE_RES_MEM(0xffee0000, 0x100),
111 DEFINE_RES_IRQ(evt2irq(0x9c0)),
112};
113
114static struct platform_device scif4_device = {
115 .name = "sh-sci",
116 .id = 4,
117 .resource = scif4_resources,
118 .num_resources = ARRAY_SIZE(scif4_resources),
119 .dev = {
120 .platform_data = &scif4_platform_data,
121 },
122};
123
124static struct plat_sci_port scif5_platform_data = {
125 .scscr = SCSCR_REIE | SCSCR_CKE1,
126 .type = PORT_SCIF,
127 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
128};
129
130static struct resource scif5_resources[] = {
131 DEFINE_RES_MEM(0xffef0000, 0x100),
132 DEFINE_RES_IRQ(evt2irq(0x9e0)),
133};
134
135static struct platform_device scif5_device = {
136 .name = "sh-sci",
137 .id = 5,
138 .resource = scif5_resources,
139 .num_resources = ARRAY_SIZE(scif5_resources),
140 .dev = {
141 .platform_data = &scif5_platform_data,
142 },
143};
144
145static struct sh_timer_config tmu0_platform_data = {
146 .channels_mask = 7,
147};
148
149static struct resource tmu0_resources[] = {
150 DEFINE_RES_MEM(0xffd80000, 0x30),
151 DEFINE_RES_IRQ(evt2irq(0x580)),
152 DEFINE_RES_IRQ(evt2irq(0x5a0)),
153 DEFINE_RES_IRQ(evt2irq(0x5c0)),
154};
155
156static struct platform_device tmu0_device = {
157 .name = "sh-tmu",
158 .id = 0,
159 .dev = {
160 .platform_data = &tmu0_platform_data,
161 },
162 .resource = tmu0_resources,
163 .num_resources = ARRAY_SIZE(tmu0_resources),
164};
165
166static struct sh_timer_config tmu1_platform_data = {
167 .channels_mask = 7,
168};
169
170static struct resource tmu1_resources[] = {
171 DEFINE_RES_MEM(0xffdc0000, 0x2c),
172 DEFINE_RES_IRQ(evt2irq(0xe00)),
173 DEFINE_RES_IRQ(evt2irq(0xe20)),
174 DEFINE_RES_IRQ(evt2irq(0xe40)),
175};
176
177static struct platform_device tmu1_device = {
178 .name = "sh-tmu",
179 .id = 1,
180 .dev = {
181 .platform_data = &tmu1_platform_data,
182 },
183 .resource = tmu1_resources,
184 .num_resources = ARRAY_SIZE(tmu1_resources),
185};
186
187/* DMA */
188static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
189 {
190 .offset = 0,
191 .dmars = 0,
192 .dmars_bit = 0,
193 }, {
194 .offset = 0x10,
195 .dmars = 0,
196 .dmars_bit = 8,
197 }, {
198 .offset = 0x20,
199 .dmars = 4,
200 .dmars_bit = 0,
201 }, {
202 .offset = 0x30,
203 .dmars = 4,
204 .dmars_bit = 8,
205 }, {
206 .offset = 0x50,
207 .dmars = 8,
208 .dmars_bit = 0,
209 }, {
210 .offset = 0x60,
211 .dmars = 8,
212 .dmars_bit = 8,
213 }
214};
215
216static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
217 {
218 .offset = 0,
219 }, {
220 .offset = 0x10,
221 }, {
222 .offset = 0x20,
223 }, {
224 .offset = 0x30,
225 }, {
226 .offset = 0x50,
227 }, {
228 .offset = 0x60,
229 }
230};
231
232static const unsigned int ts_shift[] = TS_SHIFT;
233
234static struct sh_dmae_pdata dma0_platform_data = {
235 .channel = sh7785_dmae0_channels,
236 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
237 .ts_low_shift = CHCR_TS_LOW_SHIFT,
238 .ts_low_mask = CHCR_TS_LOW_MASK,
239 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
240 .ts_high_mask = CHCR_TS_HIGH_MASK,
241 .ts_shift = ts_shift,
242 .ts_shift_num = ARRAY_SIZE(ts_shift),
243 .dmaor_init = DMAOR_INIT,
244};
245
246static struct sh_dmae_pdata dma1_platform_data = {
247 .channel = sh7785_dmae1_channels,
248 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
249 .ts_low_shift = CHCR_TS_LOW_SHIFT,
250 .ts_low_mask = CHCR_TS_LOW_MASK,
251 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
252 .ts_high_mask = CHCR_TS_HIGH_MASK,
253 .ts_shift = ts_shift,
254 .ts_shift_num = ARRAY_SIZE(ts_shift),
255 .dmaor_init = DMAOR_INIT,
256};
257
258static struct resource sh7785_dmae0_resources[] = {
259 [0] = {
260 /* Channel registers and DMAOR */
261 .start = 0xfc808020,
262 .end = 0xfc80808f,
263 .flags = IORESOURCE_MEM,
264 },
265 [1] = {
266 /* DMARSx */
267 .start = 0xfc809000,
268 .end = 0xfc80900b,
269 .flags = IORESOURCE_MEM,
270 },
271 {
272 /*
273 * Real DMA error vector is 0x6e0, and channel
274 * vectors are 0x620-0x6c0
275 */
276 .name = "error_irq",
277 .start = evt2irq(0x620),
278 .end = evt2irq(0x620),
279 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
280 },
281};
282
283static struct resource sh7785_dmae1_resources[] = {
284 [0] = {
285 /* Channel registers and DMAOR */
286 .start = 0xfcc08020,
287 .end = 0xfcc0808f,
288 .flags = IORESOURCE_MEM,
289 },
290 /* DMAC1 has no DMARS */
291 {
292 /*
293 * Real DMA error vector is 0x940, and channel
294 * vectors are 0x880-0x920
295 */
296 .name = "error_irq",
297 .start = evt2irq(0x880),
298 .end = evt2irq(0x880),
299 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
300 },
301};
302
303static struct platform_device dma0_device = {
304 .name = "sh-dma-engine",
305 .id = 0,
306 .resource = sh7785_dmae0_resources,
307 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
308 .dev = {
309 .platform_data = &dma0_platform_data,
310 },
311};
312
313static struct platform_device dma1_device = {
314 .name = "sh-dma-engine",
315 .id = 1,
316 .resource = sh7785_dmae1_resources,
317 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
318 .dev = {
319 .platform_data = &dma1_platform_data,
320 },
321};
322
323static struct platform_device *sh7785_devices[] __initdata = {
324 &scif0_device,
325 &scif1_device,
326 &scif2_device,
327 &scif3_device,
328 &scif4_device,
329 &scif5_device,
330 &tmu0_device,
331 &tmu1_device,
332 &dma0_device,
333 &dma1_device,
334};
335
336static int __init sh7785_devices_setup(void)
337{
338 return platform_add_devices(sh7785_devices,
339 ARRAY_SIZE(sh7785_devices));
340}
341arch_initcall(sh7785_devices_setup);
342
343static struct platform_device *sh7785_early_devices[] __initdata = {
344 &scif0_device,
345 &scif1_device,
346 &scif2_device,
347 &scif3_device,
348 &scif4_device,
349 &scif5_device,
350 &tmu0_device,
351 &tmu1_device,
352};
353
354void __init plat_early_device_setup(void)
355{
356 early_platform_add_devices(sh7785_early_devices,
357 ARRAY_SIZE(sh7785_early_devices));
358}
359
360enum {
361 UNUSED = 0,
362
363 /* interrupt sources */
364
365 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
366 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
367 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
368 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
369
370 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
371 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
372 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
373 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
374
375 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
376 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
377 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
378 SCIF2, SCIF3, SCIF4, SCIF5,
379 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
380 SIOF, MMCIF, DU, GDTA,
381 TMU3, TMU4, TMU5,
382 SSI0, SSI1,
383 HAC0, HAC1,
384 FLCTL, GPIO,
385
386 /* interrupt groups */
387
388 TMU012, TMU345
389};
390
391static struct intc_vect vectors[] __initdata = {
392 INTC_VECT(WDT, 0x560),
393 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
394 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
395 INTC_VECT(HUDI, 0x600),
396 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
397 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
398 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
399 INTC_VECT(DMAC0, 0x6e0),
400 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
401 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
402 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
403 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
404 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
405 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
406 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
407 INTC_VECT(DMAC1, 0x940),
408 INTC_VECT(HSPI, 0x960),
409 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
410 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
411 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
412 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
413 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
414 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
415 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
416 INTC_VECT(SIOF, 0xc00),
417 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
418 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
419 INTC_VECT(DU, 0xd80),
420 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
421 INTC_VECT(GDTA, 0xde0),
422 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
423 INTC_VECT(TMU5, 0xe40),
424 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
425 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
426 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
427 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
428 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
429 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
430};
431
432static struct intc_group groups[] __initdata = {
433 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
434 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
435};
436
437static struct intc_mask_reg mask_registers[] __initdata = {
438 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
439 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
440
441 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
442 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
443 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
444 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
445 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
446 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
447 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
448 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
449 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
450
451 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
452 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
453 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
454 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
455 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
456};
457
458static struct intc_prio_reg prio_registers[] __initdata = {
459 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
460 IRQ4, IRQ5, IRQ6, IRQ7 } },
461 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
462 TMU2, TMU2_TICPI } },
463 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
464 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
465 SCIF2, SCIF3 } },
466 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
467 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
468 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
469 PCISERR, PCIINTA } },
470 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
471 PCIINTD, PCIC5 } },
472 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
473 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
474 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
475};
476
477static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
478 mask_registers, prio_registers, NULL);
479
480/* Support for external interrupt pins in IRQ mode */
481
482static struct intc_vect vectors_irq0123[] __initdata = {
483 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
484 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
485};
486
487static struct intc_vect vectors_irq4567[] __initdata = {
488 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
489 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
490};
491
492static struct intc_sense_reg sense_registers[] __initdata = {
493 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
494 IRQ4, IRQ5, IRQ6, IRQ7 } },
495};
496
497static struct intc_mask_reg ack_registers[] __initdata = {
498 { 0xffd00024, 0, 32, /* INTREQ */
499 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
500};
501
502static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
503 vectors_irq0123, NULL, mask_registers,
504 prio_registers, sense_registers, ack_registers);
505
506static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
507 vectors_irq4567, NULL, mask_registers,
508 prio_registers, sense_registers, ack_registers);
509
510/* External interrupt pins in IRL mode */
511
512static struct intc_vect vectors_irl0123[] __initdata = {
513 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
514 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
515 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
516 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
517 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
518 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
519 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
520 INTC_VECT(IRL0_HHHL, 0x3c0),
521};
522
523static struct intc_vect vectors_irl4567[] __initdata = {
524 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
525 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
526 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
527 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
528 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
529 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
530 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
531 INTC_VECT(IRL4_HHHL, 0xcc0),
532};
533
534static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
535 NULL, mask_registers, NULL, NULL);
536
537static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
538 NULL, mask_registers, NULL, NULL);
539
540#define INTC_ICR0 0xffd00000
541#define INTC_INTMSK0 0xffd00044
542#define INTC_INTMSK1 0xffd00048
543#define INTC_INTMSK2 0xffd40080
544#define INTC_INTMSKCLR1 0xffd00068
545#define INTC_INTMSKCLR2 0xffd40084
546
547void __init plat_irq_setup(void)
548{
549 /* disable IRQ3-0 + IRQ7-4 */
550 __raw_writel(0xff000000, INTC_INTMSK0);
551
552 /* disable IRL3-0 + IRL7-4 */
553 __raw_writel(0xc0000000, INTC_INTMSK1);
554 __raw_writel(0xfffefffe, INTC_INTMSK2);
555
556 /* select IRL mode for IRL3-0 + IRL7-4 */
557 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
558
559 /* disable holding function, ie enable "SH-4 Mode" */
560 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
561
562 register_intc_controller(&intc_desc);
563}
564
565void __init plat_irq_setup_pins(int mode)
566{
567 switch (mode) {
568 case IRQ_MODE_IRQ7654:
569 /* select IRQ mode for IRL7-4 */
570 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
571 register_intc_controller(&intc_desc_irq4567);
572 break;
573 case IRQ_MODE_IRQ3210:
574 /* select IRQ mode for IRL3-0 */
575 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
576 register_intc_controller(&intc_desc_irq0123);
577 break;
578 case IRQ_MODE_IRL7654:
579 /* enable IRL7-4 but don't provide any masking */
580 __raw_writel(0x40000000, INTC_INTMSKCLR1);
581 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
582 break;
583 case IRQ_MODE_IRL3210:
584 /* enable IRL0-3 but don't provide any masking */
585 __raw_writel(0x80000000, INTC_INTMSKCLR1);
586 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
587 break;
588 case IRQ_MODE_IRL7654_MASK:
589 /* enable IRL7-4 and mask using cpu intc controller */
590 __raw_writel(0x40000000, INTC_INTMSKCLR1);
591 register_intc_controller(&intc_desc_irl4567);
592 break;
593 case IRQ_MODE_IRL3210_MASK:
594 /* enable IRL0-3 and mask using cpu intc controller */
595 __raw_writel(0x80000000, INTC_INTMSKCLR1);
596 register_intc_controller(&intc_desc_irl0123);
597 break;
598 default:
599 BUG();
600 }
601}
602
603void __init plat_mem_setup(void)
604{
605 /* Register the URAM space as Node 1 */
606 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
607}