1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * arch-independent dma-mapping routines
  4 *
  5 * Copyright (c) 2006  SUSE Linux Products GmbH
  6 * Copyright (c) 2006  Tejun Heo <teheo@suse.de>
  7 */
  8#include <linux/memblock.h> /* for max_pfn */
  9#include <linux/acpi.h>
 10#include <linux/dma-direct.h>
 11#include <linux/dma-noncoherent.h>
 12#include <linux/export.h>
 13#include <linux/gfp.h>
 14#include <linux/of_device.h>
 15#include <linux/slab.h>
 16#include <linux/vmalloc.h>
 17
 18/*
 19 * Managed DMA API
 20 */
 21struct dma_devres {
 22	size_t		size;
 23	void		*vaddr;
 24	dma_addr_t	dma_handle;
 25	unsigned long	attrs;
 26};
 27
 28static void dmam_release(struct device *dev, void *res)
 29{
 30	struct dma_devres *this = res;
 31
 32	dma_free_attrs(dev, this->size, this->vaddr, this->dma_handle,
 33			this->attrs);
 34}
 35
 36static int dmam_match(struct device *dev, void *res, void *match_data)
 37{
 38	struct dma_devres *this = res, *match = match_data;
 39
 40	if (this->vaddr == match->vaddr) {
 41		WARN_ON(this->size != match->size ||
 42			this->dma_handle != match->dma_handle);
 43		return 1;
 44	}
 45	return 0;
 46}
 47
 48/**
 49 * dmam_free_coherent - Managed dma_free_coherent()
 50 * @dev: Device to free coherent memory for
 51 * @size: Size of allocation
 52 * @vaddr: Virtual address of the memory to free
 53 * @dma_handle: DMA handle of the memory to free
 54 *
 55 * Managed dma_free_coherent().
 56 */
 57void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
 58			dma_addr_t dma_handle)
 59{
 60	struct dma_devres match_data = { size, vaddr, dma_handle };
 61
 62	dma_free_coherent(dev, size, vaddr, dma_handle);
 63	WARN_ON(devres_destroy(dev, dmam_release, dmam_match, &match_data));
 64}
 65EXPORT_SYMBOL(dmam_free_coherent);
 66
 67/**
 68 * dmam_alloc_attrs - Managed dma_alloc_attrs()
 69 * @dev: Device to allocate non_coherent memory for
 70 * @size: Size of allocation
 71 * @dma_handle: Out argument for allocated DMA handle
 72 * @gfp: Allocation flags
 73 * @attrs: Flags in the DMA_ATTR_* namespace.
 74 *
 75 * Managed dma_alloc_attrs().  Memory allocated using this function will be
 76 * automatically released on driver detach.
 77 *
 78 * RETURNS:
 79 * Pointer to allocated memory on success, NULL on failure.
 80 */
 81void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
 82		gfp_t gfp, unsigned long attrs)
 83{
 84	struct dma_devres *dr;
 85	void *vaddr;
 86
 87	dr = devres_alloc(dmam_release, sizeof(*dr), gfp);
 88	if (!dr)
 89		return NULL;
 90
 91	vaddr = dma_alloc_attrs(dev, size, dma_handle, gfp, attrs);
 92	if (!vaddr) {
 93		devres_free(dr);
 94		return NULL;
 95	}
 96
 97	dr->vaddr = vaddr;
 98	dr->dma_handle = *dma_handle;
 99	dr->size = size;
100	dr->attrs = attrs;
101
102	devres_add(dev, dr);
103
104	return vaddr;
105}
106EXPORT_SYMBOL(dmam_alloc_attrs);
107
108/*
109 * Create scatter-list for the already allocated DMA buffer.
110 */
111int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
112		 void *cpu_addr, dma_addr_t dma_addr, size_t size,
113		 unsigned long attrs)
114{
115	struct page *page;
116	int ret;
117
118	if (!dev_is_dma_coherent(dev)) {
119		unsigned long pfn;
120
121		if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN))
122			return -ENXIO;
123
124		/* If the PFN is not valid, we do not have a struct page */
125		pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr);
126		if (!pfn_valid(pfn))
127			return -ENXIO;
128		page = pfn_to_page(pfn);
129	} else {
130		page = virt_to_page(cpu_addr);
131	}
132
133	ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
134	if (!ret)
135		sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
136	return ret;
137}
138
139/*
140 * The whole dma_get_sgtable() idea is fundamentally unsafe - it seems
141 * that the intention is to allow exporting memory allocated via the
142 * coherent DMA APIs through the dma_buf API, which only accepts a
143 * scattertable.  This presents a couple of problems:
144 * 1. Not all memory allocated via the coherent DMA APIs is backed by
145 *    a struct page
146 * 2. Passing coherent DMA memory into the streaming APIs is not allowed
147 *    as we will try to flush the memory through a different alias to that
148 *    actually being used (and the flushes are redundant.)
149 */
150int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt,
151		void *cpu_addr, dma_addr_t dma_addr, size_t size,
152		unsigned long attrs)
153{
154	const struct dma_map_ops *ops = get_dma_ops(dev);
155
156	if (dma_is_direct(ops))
157		return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr,
158				size, attrs);
159	if (!ops->get_sgtable)
160		return -ENXIO;
161	return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, attrs);
162}
163EXPORT_SYMBOL(dma_get_sgtable_attrs);
164
165#ifdef CONFIG_MMU
166/*
167 * Return the page attributes used for mapping dma_alloc_* memory, either in
168 * kernel space if remapping is needed, or to userspace through dma_mmap_*.
169 */
170pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs)
171{
172	if (dev_is_dma_coherent(dev) ||
173	    (IS_ENABLED(CONFIG_DMA_NONCOHERENT_CACHE_SYNC) &&
174             (attrs & DMA_ATTR_NON_CONSISTENT)))
175		return prot;
176#ifdef CONFIG_ARCH_HAS_DMA_WRITE_COMBINE
177	if (attrs & DMA_ATTR_WRITE_COMBINE)
178		return pgprot_writecombine(prot);
179#endif
180	return pgprot_dmacoherent(prot);
181}
182#endif /* CONFIG_MMU */
183
184/*
185 * Create userspace mapping for the DMA-coherent memory.
186 */
187int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
188		void *cpu_addr, dma_addr_t dma_addr, size_t size,
189		unsigned long attrs)
190{
191#ifdef CONFIG_MMU
192	unsigned long user_count = vma_pages(vma);
193	unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
194	unsigned long off = vma->vm_pgoff;
195	unsigned long pfn;
196	int ret = -ENXIO;
197
198	vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
199
200	if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
201		return ret;
202
203	if (off >= count || user_count > count - off)
204		return -ENXIO;
205
206	if (!dev_is_dma_coherent(dev)) {
207		if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN))
208			return -ENXIO;
209
210		/* If the PFN is not valid, we do not have a struct page */
211		pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr);
212		if (!pfn_valid(pfn))
213			return -ENXIO;
214	} else {
215		pfn = page_to_pfn(virt_to_page(cpu_addr));
216	}
217
218	return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
219			user_count << PAGE_SHIFT, vma->vm_page_prot);
220#else
221	return -ENXIO;
222#endif /* CONFIG_MMU */
223}
224
225/**
226 * dma_can_mmap - check if a given device supports dma_mmap_*
227 * @dev: device to check
228 *
229 * Returns %true if @dev supports dma_mmap_coherent() and dma_mmap_attrs() to
230 * map DMA allocations to userspace.
231 */
232bool dma_can_mmap(struct device *dev)
233{
234	const struct dma_map_ops *ops = get_dma_ops(dev);
235
236	if (dma_is_direct(ops)) {
237		return IS_ENABLED(CONFIG_MMU) &&
238		       (dev_is_dma_coherent(dev) ||
239			IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN));
240	}
241
242	return ops->mmap != NULL;
243}
244EXPORT_SYMBOL_GPL(dma_can_mmap);
245
246/**
247 * dma_mmap_attrs - map a coherent DMA allocation into user space
248 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
249 * @vma: vm_area_struct describing requested user mapping
250 * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs
251 * @dma_addr: device-view address returned from dma_alloc_attrs
252 * @size: size of memory originally requested in dma_alloc_attrs
253 * @attrs: attributes of mapping properties requested in dma_alloc_attrs
254 *
255 * Map a coherent DMA buffer previously allocated by dma_alloc_attrs into user
256 * space.  The coherent DMA buffer must not be freed by the driver until the
257 * user space mapping has been released.
258 */
259int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
260		void *cpu_addr, dma_addr_t dma_addr, size_t size,
261		unsigned long attrs)
262{
263	const struct dma_map_ops *ops = get_dma_ops(dev);
264
265	if (dma_is_direct(ops))
266		return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size,
267				attrs);
268	if (!ops->mmap)
269		return -ENXIO;
270	return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
271}
272EXPORT_SYMBOL(dma_mmap_attrs);
273
274u64 dma_get_required_mask(struct device *dev)
275{
276	const struct dma_map_ops *ops = get_dma_ops(dev);
277
278	if (dma_is_direct(ops))
279		return dma_direct_get_required_mask(dev);
280	if (ops->get_required_mask)
281		return ops->get_required_mask(dev);
282
283	/*
284	 * We require every DMA ops implementation to at least support a 32-bit
285	 * DMA mask (and use bounce buffering if that isn't supported in
286	 * hardware).  As the direct mapping code has its own routine to
287	 * actually report an optimal mask we default to 32-bit here as that
288	 * is the right thing for most IOMMUs, and at least not actively
289	 * harmful in general.
290	 */
291	return DMA_BIT_MASK(32);
292}
293EXPORT_SYMBOL_GPL(dma_get_required_mask);
294
295void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
296		gfp_t flag, unsigned long attrs)
297{
298	const struct dma_map_ops *ops = get_dma_ops(dev);
299	void *cpu_addr;
300
301	WARN_ON_ONCE(!dev->coherent_dma_mask);
302
303	if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr))
304		return cpu_addr;
305
306	/* let the implementation decide on the zone to allocate from: */
307	flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
308
309	if (dma_is_direct(ops))
310		cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs);
311	else if (ops->alloc)
312		cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
313	else
314		return NULL;
315
316	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
317	return cpu_addr;
318}
319EXPORT_SYMBOL(dma_alloc_attrs);
320
321void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
322		dma_addr_t dma_handle, unsigned long attrs)
323{
324	const struct dma_map_ops *ops = get_dma_ops(dev);
325
326	if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr))
327		return;
328	/*
329	 * On non-coherent platforms which implement DMA-coherent buffers via
330	 * non-cacheable remaps, ops->free() may call vunmap(). Thus getting
331	 * this far in IRQ context is a) at risk of a BUG_ON() or trying to
332	 * sleep on some machines, and b) an indication that the driver is
333	 * probably misusing the coherent API anyway.
334	 */
335	WARN_ON(irqs_disabled());
336
337	if (!cpu_addr)
338		return;
339
340	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
341	if (dma_is_direct(ops))
342		dma_direct_free(dev, size, cpu_addr, dma_handle, attrs);
343	else if (ops->free)
344		ops->free(dev, size, cpu_addr, dma_handle, attrs);
345}
346EXPORT_SYMBOL(dma_free_attrs);
347
348int dma_supported(struct device *dev, u64 mask)
349{
350	const struct dma_map_ops *ops = get_dma_ops(dev);
351
352	if (dma_is_direct(ops))
353		return dma_direct_supported(dev, mask);
354	if (!ops->dma_supported)
355		return 1;
356	return ops->dma_supported(dev, mask);
357}
358EXPORT_SYMBOL(dma_supported);
359
360#ifdef CONFIG_ARCH_HAS_DMA_SET_MASK
361void arch_dma_set_mask(struct device *dev, u64 mask);
362#else
363#define arch_dma_set_mask(dev, mask)	do { } while (0)
364#endif
365
366int dma_set_mask(struct device *dev, u64 mask)
367{
368	/*
369	 * Truncate the mask to the actually supported dma_addr_t width to
370	 * avoid generating unsupportable addresses.
371	 */
372	mask = (dma_addr_t)mask;
373
374	if (!dev->dma_mask || !dma_supported(dev, mask))
375		return -EIO;
376
377	arch_dma_set_mask(dev, mask);
378	*dev->dma_mask = mask;
379	return 0;
380}
381EXPORT_SYMBOL(dma_set_mask);
382
383#ifndef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
384int dma_set_coherent_mask(struct device *dev, u64 mask)
385{
386	/*
387	 * Truncate the mask to the actually supported dma_addr_t width to
388	 * avoid generating unsupportable addresses.
389	 */
390	mask = (dma_addr_t)mask;
391
392	if (!dma_supported(dev, mask))
393		return -EIO;
394
395	dev->coherent_dma_mask = mask;
396	return 0;
397}
398EXPORT_SYMBOL(dma_set_coherent_mask);
399#endif
400
401void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
402		enum dma_data_direction dir)
403{
404	const struct dma_map_ops *ops = get_dma_ops(dev);
405
406	BUG_ON(!valid_dma_direction(dir));
407
408	if (dma_is_direct(ops))
409		arch_dma_cache_sync(dev, vaddr, size, dir);
410	else if (ops->cache_sync)
411		ops->cache_sync(dev, vaddr, size, dir);
412}
413EXPORT_SYMBOL(dma_cache_sync);
414
415size_t dma_max_mapping_size(struct device *dev)
416{
417	const struct dma_map_ops *ops = get_dma_ops(dev);
418	size_t size = SIZE_MAX;
419
420	if (dma_is_direct(ops))
421		size = dma_direct_max_mapping_size(dev);
422	else if (ops && ops->max_mapping_size)
423		size = ops->max_mapping_size(dev);
424
425	return size;
426}
427EXPORT_SYMBOL_GPL(dma_max_mapping_size);
428
429unsigned long dma_get_merge_boundary(struct device *dev)
430{
431	const struct dma_map_ops *ops = get_dma_ops(dev);
432
433	if (!ops || !ops->get_merge_boundary)
434		return 0;	/* can't merge */
435
436	return ops->get_merge_boundary(dev);
437}
438EXPORT_SYMBOL_GPL(dma_get_merge_boundary);