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1#undef DEBUG
2
3/*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
8 *
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code.
11 */
12#define pr_fmt(fmt) "hw perfevents: " fmt
13
14#include <linux/bitmap.h>
15#include <linux/cpumask.h>
16#include <linux/cpu_pm.h>
17#include <linux/export.h>
18#include <linux/kernel.h>
19#include <linux/of_device.h>
20#include <linux/perf/arm_pmu.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/irq.h>
25#include <linux/irqdesc.h>
26
27#include <asm/cputype.h>
28#include <asm/irq_regs.h>
29
30static int
31armpmu_map_cache_event(const unsigned (*cache_map)
32 [PERF_COUNT_HW_CACHE_MAX]
33 [PERF_COUNT_HW_CACHE_OP_MAX]
34 [PERF_COUNT_HW_CACHE_RESULT_MAX],
35 u64 config)
36{
37 unsigned int cache_type, cache_op, cache_result, ret;
38
39 cache_type = (config >> 0) & 0xff;
40 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
41 return -EINVAL;
42
43 cache_op = (config >> 8) & 0xff;
44 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
45 return -EINVAL;
46
47 cache_result = (config >> 16) & 0xff;
48 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
49 return -EINVAL;
50
51 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
52
53 if (ret == CACHE_OP_UNSUPPORTED)
54 return -ENOENT;
55
56 return ret;
57}
58
59static int
60armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
61{
62 int mapping;
63
64 if (config >= PERF_COUNT_HW_MAX)
65 return -EINVAL;
66
67 mapping = (*event_map)[config];
68 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
69}
70
71static int
72armpmu_map_raw_event(u32 raw_event_mask, u64 config)
73{
74 return (int)(config & raw_event_mask);
75}
76
77int
78armpmu_map_event(struct perf_event *event,
79 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
80 const unsigned (*cache_map)
81 [PERF_COUNT_HW_CACHE_MAX]
82 [PERF_COUNT_HW_CACHE_OP_MAX]
83 [PERF_COUNT_HW_CACHE_RESULT_MAX],
84 u32 raw_event_mask)
85{
86 u64 config = event->attr.config;
87 int type = event->attr.type;
88
89 if (type == event->pmu->type)
90 return armpmu_map_raw_event(raw_event_mask, config);
91
92 switch (type) {
93 case PERF_TYPE_HARDWARE:
94 return armpmu_map_hw_event(event_map, config);
95 case PERF_TYPE_HW_CACHE:
96 return armpmu_map_cache_event(cache_map, config);
97 case PERF_TYPE_RAW:
98 return armpmu_map_raw_event(raw_event_mask, config);
99 }
100
101 return -ENOENT;
102}
103
104int armpmu_event_set_period(struct perf_event *event)
105{
106 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
107 struct hw_perf_event *hwc = &event->hw;
108 s64 left = local64_read(&hwc->period_left);
109 s64 period = hwc->sample_period;
110 int ret = 0;
111
112 if (unlikely(left <= -period)) {
113 left = period;
114 local64_set(&hwc->period_left, left);
115 hwc->last_period = period;
116 ret = 1;
117 }
118
119 if (unlikely(left <= 0)) {
120 left += period;
121 local64_set(&hwc->period_left, left);
122 hwc->last_period = period;
123 ret = 1;
124 }
125
126 /*
127 * Limit the maximum period to prevent the counter value
128 * from overtaking the one we are about to program. In
129 * effect we are reducing max_period to account for
130 * interrupt latency (and we are being very conservative).
131 */
132 if (left > (armpmu->max_period >> 1))
133 left = armpmu->max_period >> 1;
134
135 local64_set(&hwc->prev_count, (u64)-left);
136
137 armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
138
139 perf_event_update_userpage(event);
140
141 return ret;
142}
143
144u64 armpmu_event_update(struct perf_event *event)
145{
146 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
147 struct hw_perf_event *hwc = &event->hw;
148 u64 delta, prev_raw_count, new_raw_count;
149
150again:
151 prev_raw_count = local64_read(&hwc->prev_count);
152 new_raw_count = armpmu->read_counter(event);
153
154 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
155 new_raw_count) != prev_raw_count)
156 goto again;
157
158 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
159
160 local64_add(delta, &event->count);
161 local64_sub(delta, &hwc->period_left);
162
163 return new_raw_count;
164}
165
166static void
167armpmu_read(struct perf_event *event)
168{
169 armpmu_event_update(event);
170}
171
172static void
173armpmu_stop(struct perf_event *event, int flags)
174{
175 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
176 struct hw_perf_event *hwc = &event->hw;
177
178 /*
179 * ARM pmu always has to update the counter, so ignore
180 * PERF_EF_UPDATE, see comments in armpmu_start().
181 */
182 if (!(hwc->state & PERF_HES_STOPPED)) {
183 armpmu->disable(event);
184 armpmu_event_update(event);
185 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
186 }
187}
188
189static void armpmu_start(struct perf_event *event, int flags)
190{
191 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
192 struct hw_perf_event *hwc = &event->hw;
193
194 /*
195 * ARM pmu always has to reprogram the period, so ignore
196 * PERF_EF_RELOAD, see the comment below.
197 */
198 if (flags & PERF_EF_RELOAD)
199 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
200
201 hwc->state = 0;
202 /*
203 * Set the period again. Some counters can't be stopped, so when we
204 * were stopped we simply disabled the IRQ source and the counter
205 * may have been left counting. If we don't do this step then we may
206 * get an interrupt too soon or *way* too late if the overflow has
207 * happened since disabling.
208 */
209 armpmu_event_set_period(event);
210 armpmu->enable(event);
211}
212
213static void
214armpmu_del(struct perf_event *event, int flags)
215{
216 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
217 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
218 struct hw_perf_event *hwc = &event->hw;
219 int idx = hwc->idx;
220
221 armpmu_stop(event, PERF_EF_UPDATE);
222 hw_events->events[idx] = NULL;
223 clear_bit(idx, hw_events->used_mask);
224 if (armpmu->clear_event_idx)
225 armpmu->clear_event_idx(hw_events, event);
226
227 perf_event_update_userpage(event);
228}
229
230static int
231armpmu_add(struct perf_event *event, int flags)
232{
233 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
234 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
235 struct hw_perf_event *hwc = &event->hw;
236 int idx;
237 int err = 0;
238
239 /* An event following a process won't be stopped earlier */
240 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
241 return -ENOENT;
242
243 perf_pmu_disable(event->pmu);
244
245 /* If we don't have a space for the counter then finish early. */
246 idx = armpmu->get_event_idx(hw_events, event);
247 if (idx < 0) {
248 err = idx;
249 goto out;
250 }
251
252 /*
253 * If there is an event in the counter we are going to use then make
254 * sure it is disabled.
255 */
256 event->hw.idx = idx;
257 armpmu->disable(event);
258 hw_events->events[idx] = event;
259
260 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
261 if (flags & PERF_EF_START)
262 armpmu_start(event, PERF_EF_RELOAD);
263
264 /* Propagate our changes to the userspace mapping. */
265 perf_event_update_userpage(event);
266
267out:
268 perf_pmu_enable(event->pmu);
269 return err;
270}
271
272static int
273validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
274 struct perf_event *event)
275{
276 struct arm_pmu *armpmu;
277
278 if (is_software_event(event))
279 return 1;
280
281 /*
282 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
283 * core perf code won't check that the pmu->ctx == leader->ctx
284 * until after pmu->event_init(event).
285 */
286 if (event->pmu != pmu)
287 return 0;
288
289 if (event->state < PERF_EVENT_STATE_OFF)
290 return 1;
291
292 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
293 return 1;
294
295 armpmu = to_arm_pmu(event->pmu);
296 return armpmu->get_event_idx(hw_events, event) >= 0;
297}
298
299static int
300validate_group(struct perf_event *event)
301{
302 struct perf_event *sibling, *leader = event->group_leader;
303 struct pmu_hw_events fake_pmu;
304
305 /*
306 * Initialise the fake PMU. We only need to populate the
307 * used_mask for the purposes of validation.
308 */
309 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
310
311 if (!validate_event(event->pmu, &fake_pmu, leader))
312 return -EINVAL;
313
314 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
315 if (!validate_event(event->pmu, &fake_pmu, sibling))
316 return -EINVAL;
317 }
318
319 if (!validate_event(event->pmu, &fake_pmu, event))
320 return -EINVAL;
321
322 return 0;
323}
324
325static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
326{
327 struct arm_pmu *armpmu;
328 struct platform_device *plat_device;
329 struct arm_pmu_platdata *plat;
330 int ret;
331 u64 start_clock, finish_clock;
332
333 /*
334 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
335 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
336 * do any necessary shifting, we just need to perform the first
337 * dereference.
338 */
339 armpmu = *(void **)dev;
340 plat_device = armpmu->plat_device;
341 plat = dev_get_platdata(&plat_device->dev);
342
343 start_clock = sched_clock();
344 if (plat && plat->handle_irq)
345 ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
346 else
347 ret = armpmu->handle_irq(irq, armpmu);
348 finish_clock = sched_clock();
349
350 perf_sample_event_took(finish_clock - start_clock);
351 return ret;
352}
353
354static void
355armpmu_release_hardware(struct arm_pmu *armpmu)
356{
357 armpmu->free_irq(armpmu);
358}
359
360static int
361armpmu_reserve_hardware(struct arm_pmu *armpmu)
362{
363 int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
364 if (err) {
365 armpmu_release_hardware(armpmu);
366 return err;
367 }
368
369 return 0;
370}
371
372static void
373hw_perf_event_destroy(struct perf_event *event)
374{
375 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
376 atomic_t *active_events = &armpmu->active_events;
377 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
378
379 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
380 armpmu_release_hardware(armpmu);
381 mutex_unlock(pmu_reserve_mutex);
382 }
383}
384
385static int
386event_requires_mode_exclusion(struct perf_event_attr *attr)
387{
388 return attr->exclude_idle || attr->exclude_user ||
389 attr->exclude_kernel || attr->exclude_hv;
390}
391
392static int
393__hw_perf_event_init(struct perf_event *event)
394{
395 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
396 struct hw_perf_event *hwc = &event->hw;
397 int mapping;
398
399 mapping = armpmu->map_event(event);
400
401 if (mapping < 0) {
402 pr_debug("event %x:%llx not supported\n", event->attr.type,
403 event->attr.config);
404 return mapping;
405 }
406
407 /*
408 * We don't assign an index until we actually place the event onto
409 * hardware. Use -1 to signify that we haven't decided where to put it
410 * yet. For SMP systems, each core has it's own PMU so we can't do any
411 * clever allocation or constraints checking at this point.
412 */
413 hwc->idx = -1;
414 hwc->config_base = 0;
415 hwc->config = 0;
416 hwc->event_base = 0;
417
418 /*
419 * Check whether we need to exclude the counter from certain modes.
420 */
421 if ((!armpmu->set_event_filter ||
422 armpmu->set_event_filter(hwc, &event->attr)) &&
423 event_requires_mode_exclusion(&event->attr)) {
424 pr_debug("ARM performance counters do not support "
425 "mode exclusion\n");
426 return -EOPNOTSUPP;
427 }
428
429 /*
430 * Store the event encoding into the config_base field.
431 */
432 hwc->config_base |= (unsigned long)mapping;
433
434 if (!is_sampling_event(event)) {
435 /*
436 * For non-sampling runs, limit the sample_period to half
437 * of the counter width. That way, the new counter value
438 * is far less likely to overtake the previous one unless
439 * you have some serious IRQ latency issues.
440 */
441 hwc->sample_period = armpmu->max_period >> 1;
442 hwc->last_period = hwc->sample_period;
443 local64_set(&hwc->period_left, hwc->sample_period);
444 }
445
446 if (event->group_leader != event) {
447 if (validate_group(event) != 0)
448 return -EINVAL;
449 }
450
451 return 0;
452}
453
454static int armpmu_event_init(struct perf_event *event)
455{
456 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
457 int err = 0;
458 atomic_t *active_events = &armpmu->active_events;
459
460 /*
461 * Reject CPU-affine events for CPUs that are of a different class to
462 * that which this PMU handles. Process-following events (where
463 * event->cpu == -1) can be migrated between CPUs, and thus we have to
464 * reject them later (in armpmu_add) if they're scheduled on a
465 * different class of CPU.
466 */
467 if (event->cpu != -1 &&
468 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
469 return -ENOENT;
470
471 /* does not support taken branch sampling */
472 if (has_branch_stack(event))
473 return -EOPNOTSUPP;
474
475 if (armpmu->map_event(event) == -ENOENT)
476 return -ENOENT;
477
478 event->destroy = hw_perf_event_destroy;
479
480 if (!atomic_inc_not_zero(active_events)) {
481 mutex_lock(&armpmu->reserve_mutex);
482 if (atomic_read(active_events) == 0)
483 err = armpmu_reserve_hardware(armpmu);
484
485 if (!err)
486 atomic_inc(active_events);
487 mutex_unlock(&armpmu->reserve_mutex);
488 }
489
490 if (err)
491 return err;
492
493 err = __hw_perf_event_init(event);
494 if (err)
495 hw_perf_event_destroy(event);
496
497 return err;
498}
499
500static void armpmu_enable(struct pmu *pmu)
501{
502 struct arm_pmu *armpmu = to_arm_pmu(pmu);
503 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
504 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
505
506 /* For task-bound events we may be called on other CPUs */
507 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
508 return;
509
510 if (enabled)
511 armpmu->start(armpmu);
512}
513
514static void armpmu_disable(struct pmu *pmu)
515{
516 struct arm_pmu *armpmu = to_arm_pmu(pmu);
517
518 /* For task-bound events we may be called on other CPUs */
519 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
520 return;
521
522 armpmu->stop(armpmu);
523}
524
525/*
526 * In heterogeneous systems, events are specific to a particular
527 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
528 * the same microarchitecture.
529 */
530static int armpmu_filter_match(struct perf_event *event)
531{
532 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
533 unsigned int cpu = smp_processor_id();
534 return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
535}
536
537static void armpmu_init(struct arm_pmu *armpmu)
538{
539 atomic_set(&armpmu->active_events, 0);
540 mutex_init(&armpmu->reserve_mutex);
541
542 armpmu->pmu = (struct pmu) {
543 .pmu_enable = armpmu_enable,
544 .pmu_disable = armpmu_disable,
545 .event_init = armpmu_event_init,
546 .add = armpmu_add,
547 .del = armpmu_del,
548 .start = armpmu_start,
549 .stop = armpmu_stop,
550 .read = armpmu_read,
551 .filter_match = armpmu_filter_match,
552 };
553}
554
555/* Set at runtime when we know what CPU type we are. */
556static struct arm_pmu *__oprofile_cpu_pmu;
557
558/*
559 * Despite the names, these two functions are CPU-specific and are used
560 * by the OProfile/perf code.
561 */
562const char *perf_pmu_name(void)
563{
564 if (!__oprofile_cpu_pmu)
565 return NULL;
566
567 return __oprofile_cpu_pmu->name;
568}
569EXPORT_SYMBOL_GPL(perf_pmu_name);
570
571int perf_num_counters(void)
572{
573 int max_events = 0;
574
575 if (__oprofile_cpu_pmu != NULL)
576 max_events = __oprofile_cpu_pmu->num_events;
577
578 return max_events;
579}
580EXPORT_SYMBOL_GPL(perf_num_counters);
581
582static void cpu_pmu_enable_percpu_irq(void *data)
583{
584 int irq = *(int *)data;
585
586 enable_percpu_irq(irq, IRQ_TYPE_NONE);
587}
588
589static void cpu_pmu_disable_percpu_irq(void *data)
590{
591 int irq = *(int *)data;
592
593 disable_percpu_irq(irq);
594}
595
596static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
597{
598 int i, irq, irqs;
599 struct platform_device *pmu_device = cpu_pmu->plat_device;
600 struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
601
602 irqs = min(pmu_device->num_resources, num_possible_cpus());
603
604 irq = platform_get_irq(pmu_device, 0);
605 if (irq >= 0 && irq_is_percpu(irq)) {
606 on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1);
607 free_percpu_irq(irq, &hw_events->percpu_pmu);
608 } else {
609 for (i = 0; i < irqs; ++i) {
610 int cpu = i;
611
612 if (cpu_pmu->irq_affinity)
613 cpu = cpu_pmu->irq_affinity[i];
614
615 if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
616 continue;
617 irq = platform_get_irq(pmu_device, i);
618 if (irq >= 0)
619 free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
620 }
621 }
622}
623
624static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
625{
626 int i, err, irq, irqs;
627 struct platform_device *pmu_device = cpu_pmu->plat_device;
628 struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
629
630 if (!pmu_device)
631 return -ENODEV;
632
633 irqs = min(pmu_device->num_resources, num_possible_cpus());
634 if (irqs < 1) {
635 pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
636 return 0;
637 }
638
639 irq = platform_get_irq(pmu_device, 0);
640 if (irq >= 0 && irq_is_percpu(irq)) {
641 err = request_percpu_irq(irq, handler, "arm-pmu",
642 &hw_events->percpu_pmu);
643 if (err) {
644 pr_err("unable to request IRQ%d for ARM PMU counters\n",
645 irq);
646 return err;
647 }
648 on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1);
649 } else {
650 for (i = 0; i < irqs; ++i) {
651 int cpu = i;
652
653 err = 0;
654 irq = platform_get_irq(pmu_device, i);
655 if (irq < 0)
656 continue;
657
658 if (cpu_pmu->irq_affinity)
659 cpu = cpu_pmu->irq_affinity[i];
660
661 /*
662 * If we have a single PMU interrupt that we can't shift,
663 * assume that we're running on a uniprocessor machine and
664 * continue. Otherwise, continue without this interrupt.
665 */
666 if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
667 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
668 irq, cpu);
669 continue;
670 }
671
672 err = request_irq(irq, handler,
673 IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
674 per_cpu_ptr(&hw_events->percpu_pmu, cpu));
675 if (err) {
676 pr_err("unable to request IRQ%d for ARM PMU counters\n",
677 irq);
678 return err;
679 }
680
681 cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
682 }
683 }
684
685 return 0;
686}
687
688/*
689 * PMU hardware loses all context when a CPU goes offline.
690 * When a CPU is hotplugged back in, since some hardware registers are
691 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
692 * junk values out of them.
693 */
694static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
695 void *hcpu)
696{
697 int cpu = (unsigned long)hcpu;
698 struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb);
699
700 if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
701 return NOTIFY_DONE;
702
703 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
704 return NOTIFY_DONE;
705
706 if (pmu->reset)
707 pmu->reset(pmu);
708 else
709 return NOTIFY_DONE;
710
711 return NOTIFY_OK;
712}
713
714#ifdef CONFIG_CPU_PM
715static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
716{
717 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
718 struct perf_event *event;
719 int idx;
720
721 for (idx = 0; idx < armpmu->num_events; idx++) {
722 /*
723 * If the counter is not used skip it, there is no
724 * need of stopping/restarting it.
725 */
726 if (!test_bit(idx, hw_events->used_mask))
727 continue;
728
729 event = hw_events->events[idx];
730
731 switch (cmd) {
732 case CPU_PM_ENTER:
733 /*
734 * Stop and update the counter
735 */
736 armpmu_stop(event, PERF_EF_UPDATE);
737 break;
738 case CPU_PM_EXIT:
739 case CPU_PM_ENTER_FAILED:
740 /*
741 * Restore and enable the counter.
742 * armpmu_start() indirectly calls
743 *
744 * perf_event_update_userpage()
745 *
746 * that requires RCU read locking to be functional,
747 * wrap the call within RCU_NONIDLE to make the
748 * RCU subsystem aware this cpu is not idle from
749 * an RCU perspective for the armpmu_start() call
750 * duration.
751 */
752 RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
753 break;
754 default:
755 break;
756 }
757 }
758}
759
760static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
761 void *v)
762{
763 struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
764 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
765 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
766
767 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
768 return NOTIFY_DONE;
769
770 /*
771 * Always reset the PMU registers on power-up even if
772 * there are no events running.
773 */
774 if (cmd == CPU_PM_EXIT && armpmu->reset)
775 armpmu->reset(armpmu);
776
777 if (!enabled)
778 return NOTIFY_OK;
779
780 switch (cmd) {
781 case CPU_PM_ENTER:
782 armpmu->stop(armpmu);
783 cpu_pm_pmu_setup(armpmu, cmd);
784 break;
785 case CPU_PM_EXIT:
786 cpu_pm_pmu_setup(armpmu, cmd);
787 case CPU_PM_ENTER_FAILED:
788 armpmu->start(armpmu);
789 break;
790 default:
791 return NOTIFY_DONE;
792 }
793
794 return NOTIFY_OK;
795}
796
797static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
798{
799 cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
800 return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
801}
802
803static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
804{
805 cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
806}
807#else
808static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
809static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
810#endif
811
812static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
813{
814 int err;
815 int cpu;
816 struct pmu_hw_events __percpu *cpu_hw_events;
817
818 cpu_hw_events = alloc_percpu(struct pmu_hw_events);
819 if (!cpu_hw_events)
820 return -ENOMEM;
821
822 cpu_pmu->hotplug_nb.notifier_call = cpu_pmu_notify;
823 err = register_cpu_notifier(&cpu_pmu->hotplug_nb);
824 if (err)
825 goto out_hw_events;
826
827 err = cpu_pm_pmu_register(cpu_pmu);
828 if (err)
829 goto out_unregister;
830
831 for_each_possible_cpu(cpu) {
832 struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu);
833 raw_spin_lock_init(&events->pmu_lock);
834 events->percpu_pmu = cpu_pmu;
835 }
836
837 cpu_pmu->hw_events = cpu_hw_events;
838 cpu_pmu->request_irq = cpu_pmu_request_irq;
839 cpu_pmu->free_irq = cpu_pmu_free_irq;
840
841 /* Ensure the PMU has sane values out of reset. */
842 if (cpu_pmu->reset)
843 on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset,
844 cpu_pmu, 1);
845
846 /* If no interrupts available, set the corresponding capability flag */
847 if (!platform_get_irq(cpu_pmu->plat_device, 0))
848 cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
849
850 return 0;
851
852out_unregister:
853 unregister_cpu_notifier(&cpu_pmu->hotplug_nb);
854out_hw_events:
855 free_percpu(cpu_hw_events);
856 return err;
857}
858
859static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
860{
861 cpu_pm_pmu_unregister(cpu_pmu);
862 unregister_cpu_notifier(&cpu_pmu->hotplug_nb);
863 free_percpu(cpu_pmu->hw_events);
864}
865
866/*
867 * CPU PMU identification and probing.
868 */
869static int probe_current_pmu(struct arm_pmu *pmu,
870 const struct pmu_probe_info *info)
871{
872 int cpu = get_cpu();
873 unsigned int cpuid = read_cpuid_id();
874 int ret = -ENODEV;
875
876 pr_info("probing PMU on CPU %d\n", cpu);
877
878 for (; info->init != NULL; info++) {
879 if ((cpuid & info->mask) != info->cpuid)
880 continue;
881 ret = info->init(pmu);
882 break;
883 }
884
885 put_cpu();
886 return ret;
887}
888
889static int of_pmu_irq_cfg(struct arm_pmu *pmu)
890{
891 int *irqs, i = 0;
892 bool using_spi = false;
893 struct platform_device *pdev = pmu->plat_device;
894
895 irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
896 if (!irqs)
897 return -ENOMEM;
898
899 do {
900 struct device_node *dn;
901 int cpu, irq;
902
903 /* See if we have an affinity entry */
904 dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", i);
905 if (!dn)
906 break;
907
908 /* Check the IRQ type and prohibit a mix of PPIs and SPIs */
909 irq = platform_get_irq(pdev, i);
910 if (irq >= 0) {
911 bool spi = !irq_is_percpu(irq);
912
913 if (i > 0 && spi != using_spi) {
914 pr_err("PPI/SPI IRQ type mismatch for %s!\n",
915 dn->name);
916 kfree(irqs);
917 return -EINVAL;
918 }
919
920 using_spi = spi;
921 }
922
923 /* Now look up the logical CPU number */
924 for_each_possible_cpu(cpu) {
925 struct device_node *cpu_dn;
926
927 cpu_dn = of_cpu_device_node_get(cpu);
928 of_node_put(cpu_dn);
929
930 if (dn == cpu_dn)
931 break;
932 }
933
934 if (cpu >= nr_cpu_ids) {
935 pr_warn("Failed to find logical CPU for %s\n",
936 dn->name);
937 of_node_put(dn);
938 cpumask_setall(&pmu->supported_cpus);
939 break;
940 }
941 of_node_put(dn);
942
943 /* For SPIs, we need to track the affinity per IRQ */
944 if (using_spi) {
945 if (i >= pdev->num_resources) {
946 of_node_put(dn);
947 break;
948 }
949
950 irqs[i] = cpu;
951 }
952
953 /* Keep track of the CPUs containing this PMU type */
954 cpumask_set_cpu(cpu, &pmu->supported_cpus);
955 of_node_put(dn);
956 i++;
957 } while (1);
958
959 /* If we didn't manage to parse anything, claim to support all CPUs */
960 if (cpumask_weight(&pmu->supported_cpus) == 0)
961 cpumask_setall(&pmu->supported_cpus);
962
963 /* If we matched up the IRQ affinities, use them to route the SPIs */
964 if (using_spi && i == pdev->num_resources)
965 pmu->irq_affinity = irqs;
966 else
967 kfree(irqs);
968
969 return 0;
970}
971
972int arm_pmu_device_probe(struct platform_device *pdev,
973 const struct of_device_id *of_table,
974 const struct pmu_probe_info *probe_table)
975{
976 const struct of_device_id *of_id;
977 const int (*init_fn)(struct arm_pmu *);
978 struct device_node *node = pdev->dev.of_node;
979 struct arm_pmu *pmu;
980 int ret = -ENODEV;
981
982 pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
983 if (!pmu) {
984 pr_info("failed to allocate PMU device!\n");
985 return -ENOMEM;
986 }
987
988 armpmu_init(pmu);
989
990 if (!__oprofile_cpu_pmu)
991 __oprofile_cpu_pmu = pmu;
992
993 pmu->plat_device = pdev;
994
995 if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
996 init_fn = of_id->data;
997
998 pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
999 "secure-reg-access");
1000
1001 /* arm64 systems boot only as non-secure */
1002 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
1003 pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
1004 pmu->secure_access = false;
1005 }
1006
1007 ret = of_pmu_irq_cfg(pmu);
1008 if (!ret)
1009 ret = init_fn(pmu);
1010 } else {
1011 ret = probe_current_pmu(pmu, probe_table);
1012 cpumask_setall(&pmu->supported_cpus);
1013 }
1014
1015 if (ret) {
1016 pr_info("%s: failed to probe PMU!\n", of_node_full_name(node));
1017 goto out_free;
1018 }
1019
1020 ret = cpu_pmu_init(pmu);
1021 if (ret)
1022 goto out_free;
1023
1024 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
1025 if (ret)
1026 goto out_destroy;
1027
1028 pr_info("enabled with %s PMU driver, %d counters available\n",
1029 pmu->name, pmu->num_events);
1030
1031 return 0;
1032
1033out_destroy:
1034 cpu_pmu_destroy(pmu);
1035out_free:
1036 pr_info("%s: failed to register PMU devices!\n",
1037 of_node_full_name(node));
1038 kfree(pmu);
1039 return ret;
1040}
1// SPDX-License-Identifier: GPL-2.0-only
2#undef DEBUG
3
4/*
5 * ARM performance counter support.
6 *
7 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
8 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 *
10 * This code is based on the sparc64 perf event code, which is in turn based
11 * on the x86 code.
12 */
13#define pr_fmt(fmt) "hw perfevents: " fmt
14
15#include <linux/bitmap.h>
16#include <linux/cpumask.h>
17#include <linux/cpu_pm.h>
18#include <linux/export.h>
19#include <linux/kernel.h>
20#include <linux/perf/arm_pmu.h>
21#include <linux/slab.h>
22#include <linux/sched/clock.h>
23#include <linux/spinlock.h>
24#include <linux/irq.h>
25#include <linux/irqdesc.h>
26
27#include <asm/irq_regs.h>
28
29static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
30static DEFINE_PER_CPU(int, cpu_irq);
31
32static inline u64 arm_pmu_event_max_period(struct perf_event *event)
33{
34 if (event->hw.flags & ARMPMU_EVT_64BIT)
35 return GENMASK_ULL(63, 0);
36 else
37 return GENMASK_ULL(31, 0);
38}
39
40static int
41armpmu_map_cache_event(const unsigned (*cache_map)
42 [PERF_COUNT_HW_CACHE_MAX]
43 [PERF_COUNT_HW_CACHE_OP_MAX]
44 [PERF_COUNT_HW_CACHE_RESULT_MAX],
45 u64 config)
46{
47 unsigned int cache_type, cache_op, cache_result, ret;
48
49 cache_type = (config >> 0) & 0xff;
50 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
51 return -EINVAL;
52
53 cache_op = (config >> 8) & 0xff;
54 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
55 return -EINVAL;
56
57 cache_result = (config >> 16) & 0xff;
58 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
59 return -EINVAL;
60
61 if (!cache_map)
62 return -ENOENT;
63
64 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
65
66 if (ret == CACHE_OP_UNSUPPORTED)
67 return -ENOENT;
68
69 return ret;
70}
71
72static int
73armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
74{
75 int mapping;
76
77 if (config >= PERF_COUNT_HW_MAX)
78 return -EINVAL;
79
80 if (!event_map)
81 return -ENOENT;
82
83 mapping = (*event_map)[config];
84 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
85}
86
87static int
88armpmu_map_raw_event(u32 raw_event_mask, u64 config)
89{
90 return (int)(config & raw_event_mask);
91}
92
93int
94armpmu_map_event(struct perf_event *event,
95 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
96 const unsigned (*cache_map)
97 [PERF_COUNT_HW_CACHE_MAX]
98 [PERF_COUNT_HW_CACHE_OP_MAX]
99 [PERF_COUNT_HW_CACHE_RESULT_MAX],
100 u32 raw_event_mask)
101{
102 u64 config = event->attr.config;
103 int type = event->attr.type;
104
105 if (type == event->pmu->type)
106 return armpmu_map_raw_event(raw_event_mask, config);
107
108 switch (type) {
109 case PERF_TYPE_HARDWARE:
110 return armpmu_map_hw_event(event_map, config);
111 case PERF_TYPE_HW_CACHE:
112 return armpmu_map_cache_event(cache_map, config);
113 case PERF_TYPE_RAW:
114 return armpmu_map_raw_event(raw_event_mask, config);
115 }
116
117 return -ENOENT;
118}
119
120int armpmu_event_set_period(struct perf_event *event)
121{
122 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
123 struct hw_perf_event *hwc = &event->hw;
124 s64 left = local64_read(&hwc->period_left);
125 s64 period = hwc->sample_period;
126 u64 max_period;
127 int ret = 0;
128
129 max_period = arm_pmu_event_max_period(event);
130 if (unlikely(left <= -period)) {
131 left = period;
132 local64_set(&hwc->period_left, left);
133 hwc->last_period = period;
134 ret = 1;
135 }
136
137 if (unlikely(left <= 0)) {
138 left += period;
139 local64_set(&hwc->period_left, left);
140 hwc->last_period = period;
141 ret = 1;
142 }
143
144 /*
145 * Limit the maximum period to prevent the counter value
146 * from overtaking the one we are about to program. In
147 * effect we are reducing max_period to account for
148 * interrupt latency (and we are being very conservative).
149 */
150 if (left > (max_period >> 1))
151 left = (max_period >> 1);
152
153 local64_set(&hwc->prev_count, (u64)-left);
154
155 armpmu->write_counter(event, (u64)(-left) & max_period);
156
157 perf_event_update_userpage(event);
158
159 return ret;
160}
161
162u64 armpmu_event_update(struct perf_event *event)
163{
164 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
165 struct hw_perf_event *hwc = &event->hw;
166 u64 delta, prev_raw_count, new_raw_count;
167 u64 max_period = arm_pmu_event_max_period(event);
168
169again:
170 prev_raw_count = local64_read(&hwc->prev_count);
171 new_raw_count = armpmu->read_counter(event);
172
173 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
174 new_raw_count) != prev_raw_count)
175 goto again;
176
177 delta = (new_raw_count - prev_raw_count) & max_period;
178
179 local64_add(delta, &event->count);
180 local64_sub(delta, &hwc->period_left);
181
182 return new_raw_count;
183}
184
185static void
186armpmu_read(struct perf_event *event)
187{
188 armpmu_event_update(event);
189}
190
191static void
192armpmu_stop(struct perf_event *event, int flags)
193{
194 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
195 struct hw_perf_event *hwc = &event->hw;
196
197 /*
198 * ARM pmu always has to update the counter, so ignore
199 * PERF_EF_UPDATE, see comments in armpmu_start().
200 */
201 if (!(hwc->state & PERF_HES_STOPPED)) {
202 armpmu->disable(event);
203 armpmu_event_update(event);
204 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
205 }
206}
207
208static void armpmu_start(struct perf_event *event, int flags)
209{
210 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
211 struct hw_perf_event *hwc = &event->hw;
212
213 /*
214 * ARM pmu always has to reprogram the period, so ignore
215 * PERF_EF_RELOAD, see the comment below.
216 */
217 if (flags & PERF_EF_RELOAD)
218 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
219
220 hwc->state = 0;
221 /*
222 * Set the period again. Some counters can't be stopped, so when we
223 * were stopped we simply disabled the IRQ source and the counter
224 * may have been left counting. If we don't do this step then we may
225 * get an interrupt too soon or *way* too late if the overflow has
226 * happened since disabling.
227 */
228 armpmu_event_set_period(event);
229 armpmu->enable(event);
230}
231
232static void
233armpmu_del(struct perf_event *event, int flags)
234{
235 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
236 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
237 struct hw_perf_event *hwc = &event->hw;
238 int idx = hwc->idx;
239
240 armpmu_stop(event, PERF_EF_UPDATE);
241 hw_events->events[idx] = NULL;
242 armpmu->clear_event_idx(hw_events, event);
243 perf_event_update_userpage(event);
244 /* Clear the allocated counter */
245 hwc->idx = -1;
246}
247
248static int
249armpmu_add(struct perf_event *event, int flags)
250{
251 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
252 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
253 struct hw_perf_event *hwc = &event->hw;
254 int idx;
255
256 /* An event following a process won't be stopped earlier */
257 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
258 return -ENOENT;
259
260 /* If we don't have a space for the counter then finish early. */
261 idx = armpmu->get_event_idx(hw_events, event);
262 if (idx < 0)
263 return idx;
264
265 /*
266 * If there is an event in the counter we are going to use then make
267 * sure it is disabled.
268 */
269 event->hw.idx = idx;
270 armpmu->disable(event);
271 hw_events->events[idx] = event;
272
273 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
274 if (flags & PERF_EF_START)
275 armpmu_start(event, PERF_EF_RELOAD);
276
277 /* Propagate our changes to the userspace mapping. */
278 perf_event_update_userpage(event);
279
280 return 0;
281}
282
283static int
284validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
285 struct perf_event *event)
286{
287 struct arm_pmu *armpmu;
288
289 if (is_software_event(event))
290 return 1;
291
292 /*
293 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
294 * core perf code won't check that the pmu->ctx == leader->ctx
295 * until after pmu->event_init(event).
296 */
297 if (event->pmu != pmu)
298 return 0;
299
300 if (event->state < PERF_EVENT_STATE_OFF)
301 return 1;
302
303 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
304 return 1;
305
306 armpmu = to_arm_pmu(event->pmu);
307 return armpmu->get_event_idx(hw_events, event) >= 0;
308}
309
310static int
311validate_group(struct perf_event *event)
312{
313 struct perf_event *sibling, *leader = event->group_leader;
314 struct pmu_hw_events fake_pmu;
315
316 /*
317 * Initialise the fake PMU. We only need to populate the
318 * used_mask for the purposes of validation.
319 */
320 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
321
322 if (!validate_event(event->pmu, &fake_pmu, leader))
323 return -EINVAL;
324
325 for_each_sibling_event(sibling, leader) {
326 if (!validate_event(event->pmu, &fake_pmu, sibling))
327 return -EINVAL;
328 }
329
330 if (!validate_event(event->pmu, &fake_pmu, event))
331 return -EINVAL;
332
333 return 0;
334}
335
336static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
337{
338 struct arm_pmu *armpmu;
339 int ret;
340 u64 start_clock, finish_clock;
341
342 /*
343 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
344 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
345 * do any necessary shifting, we just need to perform the first
346 * dereference.
347 */
348 armpmu = *(void **)dev;
349 if (WARN_ON_ONCE(!armpmu))
350 return IRQ_NONE;
351
352 start_clock = sched_clock();
353 ret = armpmu->handle_irq(armpmu);
354 finish_clock = sched_clock();
355
356 perf_sample_event_took(finish_clock - start_clock);
357 return ret;
358}
359
360static int
361__hw_perf_event_init(struct perf_event *event)
362{
363 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
364 struct hw_perf_event *hwc = &event->hw;
365 int mapping;
366
367 hwc->flags = 0;
368 mapping = armpmu->map_event(event);
369
370 if (mapping < 0) {
371 pr_debug("event %x:%llx not supported\n", event->attr.type,
372 event->attr.config);
373 return mapping;
374 }
375
376 /*
377 * We don't assign an index until we actually place the event onto
378 * hardware. Use -1 to signify that we haven't decided where to put it
379 * yet. For SMP systems, each core has it's own PMU so we can't do any
380 * clever allocation or constraints checking at this point.
381 */
382 hwc->idx = -1;
383 hwc->config_base = 0;
384 hwc->config = 0;
385 hwc->event_base = 0;
386
387 /*
388 * Check whether we need to exclude the counter from certain modes.
389 */
390 if (armpmu->set_event_filter &&
391 armpmu->set_event_filter(hwc, &event->attr)) {
392 pr_debug("ARM performance counters do not support "
393 "mode exclusion\n");
394 return -EOPNOTSUPP;
395 }
396
397 /*
398 * Store the event encoding into the config_base field.
399 */
400 hwc->config_base |= (unsigned long)mapping;
401
402 if (!is_sampling_event(event)) {
403 /*
404 * For non-sampling runs, limit the sample_period to half
405 * of the counter width. That way, the new counter value
406 * is far less likely to overtake the previous one unless
407 * you have some serious IRQ latency issues.
408 */
409 hwc->sample_period = arm_pmu_event_max_period(event) >> 1;
410 hwc->last_period = hwc->sample_period;
411 local64_set(&hwc->period_left, hwc->sample_period);
412 }
413
414 if (event->group_leader != event) {
415 if (validate_group(event) != 0)
416 return -EINVAL;
417 }
418
419 return 0;
420}
421
422static int armpmu_event_init(struct perf_event *event)
423{
424 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
425
426 /*
427 * Reject CPU-affine events for CPUs that are of a different class to
428 * that which this PMU handles. Process-following events (where
429 * event->cpu == -1) can be migrated between CPUs, and thus we have to
430 * reject them later (in armpmu_add) if they're scheduled on a
431 * different class of CPU.
432 */
433 if (event->cpu != -1 &&
434 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
435 return -ENOENT;
436
437 /* does not support taken branch sampling */
438 if (has_branch_stack(event))
439 return -EOPNOTSUPP;
440
441 if (armpmu->map_event(event) == -ENOENT)
442 return -ENOENT;
443
444 return __hw_perf_event_init(event);
445}
446
447static void armpmu_enable(struct pmu *pmu)
448{
449 struct arm_pmu *armpmu = to_arm_pmu(pmu);
450 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
451 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
452
453 /* For task-bound events we may be called on other CPUs */
454 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
455 return;
456
457 if (enabled)
458 armpmu->start(armpmu);
459}
460
461static void armpmu_disable(struct pmu *pmu)
462{
463 struct arm_pmu *armpmu = to_arm_pmu(pmu);
464
465 /* For task-bound events we may be called on other CPUs */
466 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
467 return;
468
469 armpmu->stop(armpmu);
470}
471
472/*
473 * In heterogeneous systems, events are specific to a particular
474 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
475 * the same microarchitecture.
476 */
477static int armpmu_filter_match(struct perf_event *event)
478{
479 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
480 unsigned int cpu = smp_processor_id();
481 int ret;
482
483 ret = cpumask_test_cpu(cpu, &armpmu->supported_cpus);
484 if (ret && armpmu->filter_match)
485 return armpmu->filter_match(event);
486
487 return ret;
488}
489
490static ssize_t armpmu_cpumask_show(struct device *dev,
491 struct device_attribute *attr, char *buf)
492{
493 struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
494 return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
495}
496
497static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
498
499static struct attribute *armpmu_common_attrs[] = {
500 &dev_attr_cpus.attr,
501 NULL,
502};
503
504static struct attribute_group armpmu_common_attr_group = {
505 .attrs = armpmu_common_attrs,
506};
507
508/* Set at runtime when we know what CPU type we are. */
509static struct arm_pmu *__oprofile_cpu_pmu;
510
511/*
512 * Despite the names, these two functions are CPU-specific and are used
513 * by the OProfile/perf code.
514 */
515const char *perf_pmu_name(void)
516{
517 if (!__oprofile_cpu_pmu)
518 return NULL;
519
520 return __oprofile_cpu_pmu->name;
521}
522EXPORT_SYMBOL_GPL(perf_pmu_name);
523
524int perf_num_counters(void)
525{
526 int max_events = 0;
527
528 if (__oprofile_cpu_pmu != NULL)
529 max_events = __oprofile_cpu_pmu->num_events;
530
531 return max_events;
532}
533EXPORT_SYMBOL_GPL(perf_num_counters);
534
535static int armpmu_count_irq_users(const int irq)
536{
537 int cpu, count = 0;
538
539 for_each_possible_cpu(cpu) {
540 if (per_cpu(cpu_irq, cpu) == irq)
541 count++;
542 }
543
544 return count;
545}
546
547void armpmu_free_irq(int irq, int cpu)
548{
549 if (per_cpu(cpu_irq, cpu) == 0)
550 return;
551 if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
552 return;
553
554 if (!irq_is_percpu_devid(irq))
555 free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu));
556 else if (armpmu_count_irq_users(irq) == 1)
557 free_percpu_irq(irq, &cpu_armpmu);
558
559 per_cpu(cpu_irq, cpu) = 0;
560}
561
562int armpmu_request_irq(int irq, int cpu)
563{
564 int err = 0;
565 const irq_handler_t handler = armpmu_dispatch_irq;
566 if (!irq)
567 return 0;
568
569 if (!irq_is_percpu_devid(irq)) {
570 unsigned long irq_flags;
571
572 err = irq_force_affinity(irq, cpumask_of(cpu));
573
574 if (err && num_possible_cpus() > 1) {
575 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
576 irq, cpu);
577 goto err_out;
578 }
579
580 irq_flags = IRQF_PERCPU |
581 IRQF_NOBALANCING |
582 IRQF_NO_THREAD;
583
584 irq_set_status_flags(irq, IRQ_NOAUTOEN);
585 err = request_irq(irq, handler, irq_flags, "arm-pmu",
586 per_cpu_ptr(&cpu_armpmu, cpu));
587 } else if (armpmu_count_irq_users(irq) == 0) {
588 err = request_percpu_irq(irq, handler, "arm-pmu",
589 &cpu_armpmu);
590 }
591
592 if (err)
593 goto err_out;
594
595 per_cpu(cpu_irq, cpu) = irq;
596 return 0;
597
598err_out:
599 pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
600 return err;
601}
602
603static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
604{
605 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
606 return per_cpu(hw_events->irq, cpu);
607}
608
609/*
610 * PMU hardware loses all context when a CPU goes offline.
611 * When a CPU is hotplugged back in, since some hardware registers are
612 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
613 * junk values out of them.
614 */
615static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
616{
617 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
618 int irq;
619
620 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
621 return 0;
622 if (pmu->reset)
623 pmu->reset(pmu);
624
625 per_cpu(cpu_armpmu, cpu) = pmu;
626
627 irq = armpmu_get_cpu_irq(pmu, cpu);
628 if (irq) {
629 if (irq_is_percpu_devid(irq))
630 enable_percpu_irq(irq, IRQ_TYPE_NONE);
631 else
632 enable_irq(irq);
633 }
634
635 return 0;
636}
637
638static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
639{
640 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
641 int irq;
642
643 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
644 return 0;
645
646 irq = armpmu_get_cpu_irq(pmu, cpu);
647 if (irq) {
648 if (irq_is_percpu_devid(irq))
649 disable_percpu_irq(irq);
650 else
651 disable_irq_nosync(irq);
652 }
653
654 per_cpu(cpu_armpmu, cpu) = NULL;
655
656 return 0;
657}
658
659#ifdef CONFIG_CPU_PM
660static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
661{
662 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
663 struct perf_event *event;
664 int idx;
665
666 for (idx = 0; idx < armpmu->num_events; idx++) {
667 event = hw_events->events[idx];
668 if (!event)
669 continue;
670
671 switch (cmd) {
672 case CPU_PM_ENTER:
673 /*
674 * Stop and update the counter
675 */
676 armpmu_stop(event, PERF_EF_UPDATE);
677 break;
678 case CPU_PM_EXIT:
679 case CPU_PM_ENTER_FAILED:
680 /*
681 * Restore and enable the counter.
682 * armpmu_start() indirectly calls
683 *
684 * perf_event_update_userpage()
685 *
686 * that requires RCU read locking to be functional,
687 * wrap the call within RCU_NONIDLE to make the
688 * RCU subsystem aware this cpu is not idle from
689 * an RCU perspective for the armpmu_start() call
690 * duration.
691 */
692 RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
693 break;
694 default:
695 break;
696 }
697 }
698}
699
700static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
701 void *v)
702{
703 struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
704 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
705 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
706
707 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
708 return NOTIFY_DONE;
709
710 /*
711 * Always reset the PMU registers on power-up even if
712 * there are no events running.
713 */
714 if (cmd == CPU_PM_EXIT && armpmu->reset)
715 armpmu->reset(armpmu);
716
717 if (!enabled)
718 return NOTIFY_OK;
719
720 switch (cmd) {
721 case CPU_PM_ENTER:
722 armpmu->stop(armpmu);
723 cpu_pm_pmu_setup(armpmu, cmd);
724 break;
725 case CPU_PM_EXIT:
726 case CPU_PM_ENTER_FAILED:
727 cpu_pm_pmu_setup(armpmu, cmd);
728 armpmu->start(armpmu);
729 break;
730 default:
731 return NOTIFY_DONE;
732 }
733
734 return NOTIFY_OK;
735}
736
737static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
738{
739 cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
740 return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
741}
742
743static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
744{
745 cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
746}
747#else
748static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
749static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
750#endif
751
752static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
753{
754 int err;
755
756 err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
757 &cpu_pmu->node);
758 if (err)
759 goto out;
760
761 err = cpu_pm_pmu_register(cpu_pmu);
762 if (err)
763 goto out_unregister;
764
765 return 0;
766
767out_unregister:
768 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
769 &cpu_pmu->node);
770out:
771 return err;
772}
773
774static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
775{
776 cpu_pm_pmu_unregister(cpu_pmu);
777 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
778 &cpu_pmu->node);
779}
780
781static struct arm_pmu *__armpmu_alloc(gfp_t flags)
782{
783 struct arm_pmu *pmu;
784 int cpu;
785
786 pmu = kzalloc(sizeof(*pmu), flags);
787 if (!pmu) {
788 pr_info("failed to allocate PMU device!\n");
789 goto out;
790 }
791
792 pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
793 if (!pmu->hw_events) {
794 pr_info("failed to allocate per-cpu PMU data.\n");
795 goto out_free_pmu;
796 }
797
798 pmu->pmu = (struct pmu) {
799 .pmu_enable = armpmu_enable,
800 .pmu_disable = armpmu_disable,
801 .event_init = armpmu_event_init,
802 .add = armpmu_add,
803 .del = armpmu_del,
804 .start = armpmu_start,
805 .stop = armpmu_stop,
806 .read = armpmu_read,
807 .filter_match = armpmu_filter_match,
808 .attr_groups = pmu->attr_groups,
809 /*
810 * This is a CPU PMU potentially in a heterogeneous
811 * configuration (e.g. big.LITTLE). This is not an uncore PMU,
812 * and we have taken ctx sharing into account (e.g. with our
813 * pmu::filter_match callback and pmu::event_init group
814 * validation).
815 */
816 .capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
817 };
818
819 pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
820 &armpmu_common_attr_group;
821
822 for_each_possible_cpu(cpu) {
823 struct pmu_hw_events *events;
824
825 events = per_cpu_ptr(pmu->hw_events, cpu);
826 raw_spin_lock_init(&events->pmu_lock);
827 events->percpu_pmu = pmu;
828 }
829
830 return pmu;
831
832out_free_pmu:
833 kfree(pmu);
834out:
835 return NULL;
836}
837
838struct arm_pmu *armpmu_alloc(void)
839{
840 return __armpmu_alloc(GFP_KERNEL);
841}
842
843struct arm_pmu *armpmu_alloc_atomic(void)
844{
845 return __armpmu_alloc(GFP_ATOMIC);
846}
847
848
849void armpmu_free(struct arm_pmu *pmu)
850{
851 free_percpu(pmu->hw_events);
852 kfree(pmu);
853}
854
855int armpmu_register(struct arm_pmu *pmu)
856{
857 int ret;
858
859 ret = cpu_pmu_init(pmu);
860 if (ret)
861 return ret;
862
863 if (!pmu->set_event_filter)
864 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
865
866 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
867 if (ret)
868 goto out_destroy;
869
870 if (!__oprofile_cpu_pmu)
871 __oprofile_cpu_pmu = pmu;
872
873 pr_info("enabled with %s PMU driver, %d counters available\n",
874 pmu->name, pmu->num_events);
875
876 return 0;
877
878out_destroy:
879 cpu_pmu_destroy(pmu);
880 return ret;
881}
882
883static int arm_pmu_hp_init(void)
884{
885 int ret;
886
887 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
888 "perf/arm/pmu:starting",
889 arm_perf_starting_cpu,
890 arm_perf_teardown_cpu);
891 if (ret)
892 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
893 ret);
894 return ret;
895}
896subsys_initcall(arm_pmu_hp_init);