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1/*
2 * Freescale eSDHC i.MX controller driver for the platform bus.
3 *
4 * derived from the OF-version.
5 *
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <kernel@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/gpio.h>
19#include <linux/module.h>
20#include <linux/slab.h>
21#include <linux/mmc/host.h>
22#include <linux/mmc/mmc.h>
23#include <linux/mmc/sdio.h>
24#include <linux/mmc/slot-gpio.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/of_gpio.h>
28#include <linux/pinctrl/consumer.h>
29#include <linux/platform_data/mmc-esdhc-imx.h>
30#include <linux/pm_runtime.h>
31#include "sdhci-pltfm.h"
32#include "sdhci-esdhc.h"
33
34#define ESDHC_CTRL_D3CD 0x08
35#define ESDHC_BURST_LEN_EN_INCR (1 << 27)
36/* VENDOR SPEC register */
37#define ESDHC_VENDOR_SPEC 0xc0
38#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
39#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
40#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
41#define ESDHC_WTMK_LVL 0x44
42#define ESDHC_MIX_CTRL 0x48
43#define ESDHC_MIX_CTRL_DDREN (1 << 3)
44#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
45#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
46#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
47#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
48#define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
49/* Bits 3 and 6 are not SDHCI standard definitions */
50#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
51/* Tuning bits */
52#define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
53
54/* dll control register */
55#define ESDHC_DLL_CTRL 0x60
56#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
57#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
58
59/* tune control register */
60#define ESDHC_TUNE_CTRL_STATUS 0x68
61#define ESDHC_TUNE_CTRL_STEP 1
62#define ESDHC_TUNE_CTRL_MIN 0
63#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
64
65/* strobe dll register */
66#define ESDHC_STROBE_DLL_CTRL 0x70
67#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
68#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
69#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
70
71#define ESDHC_STROBE_DLL_STATUS 0x74
72#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
73#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
74
75#define ESDHC_TUNING_CTRL 0xcc
76#define ESDHC_STD_TUNING_EN (1 << 24)
77/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
78#define ESDHC_TUNING_START_TAP 0x1
79#define ESDHC_TUNING_STEP_MASK 0x00070000
80#define ESDHC_TUNING_STEP_SHIFT 16
81
82/* pinctrl state */
83#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
84#define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
85
86/*
87 * Our interpretation of the SDHCI_HOST_CONTROL register
88 */
89#define ESDHC_CTRL_4BITBUS (0x1 << 1)
90#define ESDHC_CTRL_8BITBUS (0x2 << 1)
91#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
92
93/*
94 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
95 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
96 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
97 * Define this macro DMA error INT for fsl eSDHC
98 */
99#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
100
101/*
102 * The CMDTYPE of the CMD register (offset 0xE) should be set to
103 * "11" when the STOP CMD12 is issued on imx53 to abort one
104 * open ended multi-blk IO. Otherwise the TC INT wouldn't
105 * be generated.
106 * In exact block transfer, the controller doesn't complete the
107 * operations automatically as required at the end of the
108 * transfer and remains on hold if the abort command is not sent.
109 * As a result, the TC flag is not asserted and SW received timeout
110 * exeception. Bit1 of Vendor Spec registor is used to fix it.
111 */
112#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
113/*
114 * The flag enables the workaround for ESDHC errata ENGcm07207 which
115 * affects i.MX25 and i.MX35.
116 */
117#define ESDHC_FLAG_ENGCM07207 BIT(2)
118/*
119 * The flag tells that the ESDHC controller is an USDHC block that is
120 * integrated on the i.MX6 series.
121 */
122#define ESDHC_FLAG_USDHC BIT(3)
123/* The IP supports manual tuning process */
124#define ESDHC_FLAG_MAN_TUNING BIT(4)
125/* The IP supports standard tuning process */
126#define ESDHC_FLAG_STD_TUNING BIT(5)
127/* The IP has SDHCI_CAPABILITIES_1 register */
128#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
129/*
130 * The IP has errata ERR004536
131 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
132 * when reading data from the card
133 */
134#define ESDHC_FLAG_ERR004536 BIT(7)
135/* The IP supports HS200 mode */
136#define ESDHC_FLAG_HS200 BIT(8)
137/* The IP supports HS400 mode */
138#define ESDHC_FLAG_HS400 BIT(9)
139
140/* A higher clock ferquency than this rate requires strobell dll control */
141#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
142
143struct esdhc_soc_data {
144 u32 flags;
145};
146
147static struct esdhc_soc_data esdhc_imx25_data = {
148 .flags = ESDHC_FLAG_ENGCM07207,
149};
150
151static struct esdhc_soc_data esdhc_imx35_data = {
152 .flags = ESDHC_FLAG_ENGCM07207,
153};
154
155static struct esdhc_soc_data esdhc_imx51_data = {
156 .flags = 0,
157};
158
159static struct esdhc_soc_data esdhc_imx53_data = {
160 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
161};
162
163static struct esdhc_soc_data usdhc_imx6q_data = {
164 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
165};
166
167static struct esdhc_soc_data usdhc_imx6sl_data = {
168 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
169 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
170 | ESDHC_FLAG_HS200,
171};
172
173static struct esdhc_soc_data usdhc_imx6sx_data = {
174 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
175 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
176};
177
178static struct esdhc_soc_data usdhc_imx7d_data = {
179 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
180 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
181 | ESDHC_FLAG_HS400,
182};
183
184struct pltfm_imx_data {
185 u32 scratchpad;
186 struct pinctrl *pinctrl;
187 struct pinctrl_state *pins_default;
188 struct pinctrl_state *pins_100mhz;
189 struct pinctrl_state *pins_200mhz;
190 const struct esdhc_soc_data *socdata;
191 struct esdhc_platform_data boarddata;
192 struct clk *clk_ipg;
193 struct clk *clk_ahb;
194 struct clk *clk_per;
195 enum {
196 NO_CMD_PENDING, /* no multiblock command pending*/
197 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
198 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
199 } multiblock_status;
200 u32 is_ddr;
201};
202
203static const struct platform_device_id imx_esdhc_devtype[] = {
204 {
205 .name = "sdhci-esdhc-imx25",
206 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
207 }, {
208 .name = "sdhci-esdhc-imx35",
209 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
210 }, {
211 .name = "sdhci-esdhc-imx51",
212 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
213 }, {
214 /* sentinel */
215 }
216};
217MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
218
219static const struct of_device_id imx_esdhc_dt_ids[] = {
220 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
221 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
222 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
223 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
224 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
225 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
226 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
227 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
228 { /* sentinel */ }
229};
230MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
231
232static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
233{
234 return data->socdata == &esdhc_imx25_data;
235}
236
237static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
238{
239 return data->socdata == &esdhc_imx53_data;
240}
241
242static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
243{
244 return data->socdata == &usdhc_imx6q_data;
245}
246
247static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
248{
249 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
250}
251
252static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
253{
254 void __iomem *base = host->ioaddr + (reg & ~0x3);
255 u32 shift = (reg & 0x3) * 8;
256
257 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
258}
259
260static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
261{
262 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
263 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
264 u32 val = readl(host->ioaddr + reg);
265
266 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
267 u32 fsl_prss = val;
268 /* save the least 20 bits */
269 val = fsl_prss & 0x000FFFFF;
270 /* move dat[0-3] bits */
271 val |= (fsl_prss & 0x0F000000) >> 4;
272 /* move cmd line bit */
273 val |= (fsl_prss & 0x00800000) << 1;
274 }
275
276 if (unlikely(reg == SDHCI_CAPABILITIES)) {
277 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
278 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
279 val &= 0xffff0000;
280
281 /* In FSL esdhc IC module, only bit20 is used to indicate the
282 * ADMA2 capability of esdhc, but this bit is messed up on
283 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
284 * don't actually support ADMA2). So set the BROKEN_ADMA
285 * uirk on MX25/35 platforms.
286 */
287
288 if (val & SDHCI_CAN_DO_ADMA1) {
289 val &= ~SDHCI_CAN_DO_ADMA1;
290 val |= SDHCI_CAN_DO_ADMA2;
291 }
292 }
293
294 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
295 if (esdhc_is_usdhc(imx_data)) {
296 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
297 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
298 else
299 /* imx6q/dl does not have cap_1 register, fake one */
300 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
301 | SDHCI_SUPPORT_SDR50
302 | SDHCI_USE_SDR50_TUNING;
303
304 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
305 val |= SDHCI_SUPPORT_HS400;
306 }
307 }
308
309 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
310 val = 0;
311 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
312 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
313 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
314 }
315
316 if (unlikely(reg == SDHCI_INT_STATUS)) {
317 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
318 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
319 val |= SDHCI_INT_ADMA_ERROR;
320 }
321
322 /*
323 * mask off the interrupt we get in response to the manually
324 * sent CMD12
325 */
326 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
327 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
328 val &= ~SDHCI_INT_RESPONSE;
329 writel(SDHCI_INT_RESPONSE, host->ioaddr +
330 SDHCI_INT_STATUS);
331 imx_data->multiblock_status = NO_CMD_PENDING;
332 }
333 }
334
335 return val;
336}
337
338static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
339{
340 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
341 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
342 u32 data;
343
344 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
345 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
346 /*
347 * Clear and then set D3CD bit to avoid missing the
348 * card interrupt. This is a eSDHC controller problem
349 * so we need to apply the following workaround: clear
350 * and set D3CD bit will make eSDHC re-sample the card
351 * interrupt. In case a card interrupt was lost,
352 * re-sample it by the following steps.
353 */
354 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
355 data &= ~ESDHC_CTRL_D3CD;
356 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
357 data |= ESDHC_CTRL_D3CD;
358 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
359 }
360
361 if (val & SDHCI_INT_ADMA_ERROR) {
362 val &= ~SDHCI_INT_ADMA_ERROR;
363 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
364 }
365 }
366
367 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
368 && (reg == SDHCI_INT_STATUS)
369 && (val & SDHCI_INT_DATA_END))) {
370 u32 v;
371 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
372 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
373 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
374
375 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
376 {
377 /* send a manual CMD12 with RESPTYP=none */
378 data = MMC_STOP_TRANSMISSION << 24 |
379 SDHCI_CMD_ABORTCMD << 16;
380 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
381 imx_data->multiblock_status = WAIT_FOR_INT;
382 }
383 }
384
385 writel(val, host->ioaddr + reg);
386}
387
388static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
389{
390 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
391 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
392 u16 ret = 0;
393 u32 val;
394
395 if (unlikely(reg == SDHCI_HOST_VERSION)) {
396 reg ^= 2;
397 if (esdhc_is_usdhc(imx_data)) {
398 /*
399 * The usdhc register returns a wrong host version.
400 * Correct it here.
401 */
402 return SDHCI_SPEC_300;
403 }
404 }
405
406 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
407 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
408 if (val & ESDHC_VENDOR_SPEC_VSELECT)
409 ret |= SDHCI_CTRL_VDD_180;
410
411 if (esdhc_is_usdhc(imx_data)) {
412 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
413 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
414 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
415 /* the std tuning bits is in ACMD12_ERR for imx6sl */
416 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
417 }
418
419 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
420 ret |= SDHCI_CTRL_EXEC_TUNING;
421 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
422 ret |= SDHCI_CTRL_TUNED_CLK;
423
424 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
425
426 return ret;
427 }
428
429 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
430 if (esdhc_is_usdhc(imx_data)) {
431 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
432 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
433 /* Swap AC23 bit */
434 if (m & ESDHC_MIX_CTRL_AC23EN) {
435 ret &= ~ESDHC_MIX_CTRL_AC23EN;
436 ret |= SDHCI_TRNS_AUTO_CMD23;
437 }
438 } else {
439 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
440 }
441
442 return ret;
443 }
444
445 return readw(host->ioaddr + reg);
446}
447
448static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
449{
450 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
451 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
452 u32 new_val = 0;
453
454 switch (reg) {
455 case SDHCI_CLOCK_CONTROL:
456 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
457 if (val & SDHCI_CLOCK_CARD_EN)
458 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
459 else
460 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
461 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
462 return;
463 case SDHCI_HOST_CONTROL2:
464 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
465 if (val & SDHCI_CTRL_VDD_180)
466 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
467 else
468 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
469 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
470 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
471 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
472 if (val & SDHCI_CTRL_TUNED_CLK)
473 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
474 else
475 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
476 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
477 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
478 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
479 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
480 u32 tuning_ctrl;
481 if (val & SDHCI_CTRL_TUNED_CLK) {
482 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
483 } else {
484 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
485 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
486 }
487
488 if (val & SDHCI_CTRL_EXEC_TUNING) {
489 v |= ESDHC_MIX_CTRL_EXE_TUNE;
490 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
491 tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL);
492 tuning_ctrl |= ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP;
493 if (imx_data->boarddata.tuning_step) {
494 tuning_ctrl &= ~ESDHC_TUNING_STEP_MASK;
495 tuning_ctrl |= imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT;
496 }
497 writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL);
498 } else {
499 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
500 }
501
502 writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
503 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
504 }
505 return;
506 case SDHCI_TRANSFER_MODE:
507 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
508 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
509 && (host->cmd->data->blocks > 1)
510 && (host->cmd->data->flags & MMC_DATA_READ)) {
511 u32 v;
512 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
513 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
514 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
515 }
516
517 if (esdhc_is_usdhc(imx_data)) {
518 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
519 /* Swap AC23 bit */
520 if (val & SDHCI_TRNS_AUTO_CMD23) {
521 val &= ~SDHCI_TRNS_AUTO_CMD23;
522 val |= ESDHC_MIX_CTRL_AC23EN;
523 }
524 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
525 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
526 } else {
527 /*
528 * Postpone this write, we must do it together with a
529 * command write that is down below.
530 */
531 imx_data->scratchpad = val;
532 }
533 return;
534 case SDHCI_COMMAND:
535 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
536 val |= SDHCI_CMD_ABORTCMD;
537
538 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
539 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
540 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
541
542 if (esdhc_is_usdhc(imx_data))
543 writel(val << 16,
544 host->ioaddr + SDHCI_TRANSFER_MODE);
545 else
546 writel(val << 16 | imx_data->scratchpad,
547 host->ioaddr + SDHCI_TRANSFER_MODE);
548 return;
549 case SDHCI_BLOCK_SIZE:
550 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
551 break;
552 }
553 esdhc_clrset_le(host, 0xffff, val, reg);
554}
555
556static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
557{
558 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
559 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
560 u32 new_val;
561 u32 mask;
562
563 switch (reg) {
564 case SDHCI_POWER_CONTROL:
565 /*
566 * FSL put some DMA bits here
567 * If your board has a regulator, code should be here
568 */
569 return;
570 case SDHCI_HOST_CONTROL:
571 /* FSL messed up here, so we need to manually compose it. */
572 new_val = val & SDHCI_CTRL_LED;
573 /* ensure the endianness */
574 new_val |= ESDHC_HOST_CONTROL_LE;
575 /* bits 8&9 are reserved on mx25 */
576 if (!is_imx25_esdhc(imx_data)) {
577 /* DMA mode bits are shifted */
578 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
579 }
580
581 /*
582 * Do not touch buswidth bits here. This is done in
583 * esdhc_pltfm_bus_width.
584 * Do not touch the D3CD bit either which is used for the
585 * SDIO interrupt errata workaround.
586 */
587 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
588
589 esdhc_clrset_le(host, mask, new_val, reg);
590 return;
591 }
592 esdhc_clrset_le(host, 0xff, val, reg);
593
594 /*
595 * The esdhc has a design violation to SDHC spec which tells
596 * that software reset should not affect card detection circuit.
597 * But esdhc clears its SYSCTL register bits [0..2] during the
598 * software reset. This will stop those clocks that card detection
599 * circuit relies on. To work around it, we turn the clocks on back
600 * to keep card detection circuit functional.
601 */
602 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
603 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
604 /*
605 * The reset on usdhc fails to clear MIX_CTRL register.
606 * Do it manually here.
607 */
608 if (esdhc_is_usdhc(imx_data)) {
609 /* the tuning bits should be kept during reset */
610 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
611 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
612 host->ioaddr + ESDHC_MIX_CTRL);
613 imx_data->is_ddr = 0;
614 }
615 }
616}
617
618static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
619{
620 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
621
622 return pltfm_host->clock;
623}
624
625static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
626{
627 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
628
629 return pltfm_host->clock / 256 / 16;
630}
631
632static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
633 unsigned int clock)
634{
635 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
636 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
637 unsigned int host_clock = pltfm_host->clock;
638 int pre_div = 2;
639 int div = 1;
640 u32 temp, val;
641
642 if (clock == 0) {
643 host->mmc->actual_clock = 0;
644
645 if (esdhc_is_usdhc(imx_data)) {
646 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
647 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
648 host->ioaddr + ESDHC_VENDOR_SPEC);
649 }
650 return;
651 }
652
653 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
654 pre_div = 1;
655
656 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
657 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
658 | ESDHC_CLOCK_MASK);
659 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
660
661 while (host_clock / pre_div / 16 > clock && pre_div < 256)
662 pre_div *= 2;
663
664 while (host_clock / pre_div / div > clock && div < 16)
665 div++;
666
667 host->mmc->actual_clock = host_clock / pre_div / div;
668 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
669 clock, host->mmc->actual_clock);
670
671 if (imx_data->is_ddr)
672 pre_div >>= 2;
673 else
674 pre_div >>= 1;
675 div--;
676
677 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
678 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
679 | (div << ESDHC_DIVIDER_SHIFT)
680 | (pre_div << ESDHC_PREDIV_SHIFT));
681 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
682
683 if (esdhc_is_usdhc(imx_data)) {
684 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
685 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
686 host->ioaddr + ESDHC_VENDOR_SPEC);
687 }
688
689 mdelay(1);
690}
691
692static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
693{
694 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
695 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
696 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
697
698 switch (boarddata->wp_type) {
699 case ESDHC_WP_GPIO:
700 return mmc_gpio_get_ro(host->mmc);
701 case ESDHC_WP_CONTROLLER:
702 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
703 SDHCI_WRITE_PROTECT);
704 case ESDHC_WP_NONE:
705 break;
706 }
707
708 return -ENOSYS;
709}
710
711static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
712{
713 u32 ctrl;
714
715 switch (width) {
716 case MMC_BUS_WIDTH_8:
717 ctrl = ESDHC_CTRL_8BITBUS;
718 break;
719 case MMC_BUS_WIDTH_4:
720 ctrl = ESDHC_CTRL_4BITBUS;
721 break;
722 default:
723 ctrl = 0;
724 break;
725 }
726
727 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
728 SDHCI_HOST_CONTROL);
729}
730
731static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
732{
733 u32 reg;
734
735 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
736 mdelay(1);
737
738 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
739 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
740 ESDHC_MIX_CTRL_FBCLK_SEL;
741 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
742 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
743 dev_dbg(mmc_dev(host->mmc),
744 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
745 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
746}
747
748static void esdhc_post_tuning(struct sdhci_host *host)
749{
750 u32 reg;
751
752 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
753 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
754 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
755}
756
757static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
758{
759 int min, max, avg, ret;
760
761 /* find the mininum delay first which can pass tuning */
762 min = ESDHC_TUNE_CTRL_MIN;
763 while (min < ESDHC_TUNE_CTRL_MAX) {
764 esdhc_prepare_tuning(host, min);
765 if (!mmc_send_tuning(host->mmc, opcode, NULL))
766 break;
767 min += ESDHC_TUNE_CTRL_STEP;
768 }
769
770 /* find the maxinum delay which can not pass tuning */
771 max = min + ESDHC_TUNE_CTRL_STEP;
772 while (max < ESDHC_TUNE_CTRL_MAX) {
773 esdhc_prepare_tuning(host, max);
774 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
775 max -= ESDHC_TUNE_CTRL_STEP;
776 break;
777 }
778 max += ESDHC_TUNE_CTRL_STEP;
779 }
780
781 /* use average delay to get the best timing */
782 avg = (min + max) / 2;
783 esdhc_prepare_tuning(host, avg);
784 ret = mmc_send_tuning(host->mmc, opcode, NULL);
785 esdhc_post_tuning(host);
786
787 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
788 ret ? "failed" : "passed", avg, ret);
789
790 return ret;
791}
792
793static int esdhc_change_pinstate(struct sdhci_host *host,
794 unsigned int uhs)
795{
796 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
797 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
798 struct pinctrl_state *pinctrl;
799
800 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
801
802 if (IS_ERR(imx_data->pinctrl) ||
803 IS_ERR(imx_data->pins_default) ||
804 IS_ERR(imx_data->pins_100mhz) ||
805 IS_ERR(imx_data->pins_200mhz))
806 return -EINVAL;
807
808 switch (uhs) {
809 case MMC_TIMING_UHS_SDR50:
810 pinctrl = imx_data->pins_100mhz;
811 break;
812 case MMC_TIMING_UHS_SDR104:
813 case MMC_TIMING_MMC_HS200:
814 case MMC_TIMING_MMC_HS400:
815 pinctrl = imx_data->pins_200mhz;
816 break;
817 default:
818 /* back to default state for other legacy timing */
819 pinctrl = imx_data->pins_default;
820 }
821
822 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
823}
824
825/*
826 * For HS400 eMMC, there is a data_strobe line, this signal is generated
827 * by the device and used for data output and CRC status response output
828 * in HS400 mode. The frequency of this signal follows the frequency of
829 * CLK generated by host. Host receive the data which is aligned to the
830 * edge of data_strobe line. Due to the time delay between CLK line and
831 * data_strobe line, if the delay time is larger than one clock cycle,
832 * then CLK and data_strobe line will misaligned, read error shows up.
833 * So when the CLK is higher than 100MHz, each clock cycle is short enough,
834 * host should config the delay target.
835 */
836static void esdhc_set_strobe_dll(struct sdhci_host *host)
837{
838 u32 v;
839
840 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
841 /* force a reset on strobe dll */
842 writel(ESDHC_STROBE_DLL_CTRL_RESET,
843 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
844 /*
845 * enable strobe dll ctrl and adjust the delay target
846 * for the uSDHC loopback read clock
847 */
848 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
849 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
850 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
851 /* wait 1us to make sure strobe dll status register stable */
852 udelay(1);
853 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
854 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
855 dev_warn(mmc_dev(host->mmc),
856 "warning! HS400 strobe DLL status REF not lock!\n");
857 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
858 dev_warn(mmc_dev(host->mmc),
859 "warning! HS400 strobe DLL status SLV not lock!\n");
860 }
861}
862
863static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
864{
865 u32 m;
866 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
867 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
868 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
869
870 /* disable ddr mode and disable HS400 mode */
871 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
872 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
873 imx_data->is_ddr = 0;
874
875 switch (timing) {
876 case MMC_TIMING_UHS_SDR12:
877 case MMC_TIMING_UHS_SDR25:
878 case MMC_TIMING_UHS_SDR50:
879 case MMC_TIMING_UHS_SDR104:
880 case MMC_TIMING_MMC_HS200:
881 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
882 break;
883 case MMC_TIMING_UHS_DDR50:
884 case MMC_TIMING_MMC_DDR52:
885 m |= ESDHC_MIX_CTRL_DDREN;
886 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
887 imx_data->is_ddr = 1;
888 if (boarddata->delay_line) {
889 u32 v;
890 v = boarddata->delay_line <<
891 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
892 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
893 if (is_imx53_esdhc(imx_data))
894 v <<= 1;
895 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
896 }
897 break;
898 case MMC_TIMING_MMC_HS400:
899 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
900 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
901 imx_data->is_ddr = 1;
902 esdhc_set_strobe_dll(host);
903 break;
904 }
905
906 esdhc_change_pinstate(host, timing);
907}
908
909static void esdhc_reset(struct sdhci_host *host, u8 mask)
910{
911 sdhci_reset(host, mask);
912
913 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
914 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
915}
916
917static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
918{
919 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
920 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
921
922 return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27;
923}
924
925static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
926{
927 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
928 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
929
930 /* use maximum timeout counter */
931 sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
932 SDHCI_TIMEOUT_CONTROL);
933}
934
935static struct sdhci_ops sdhci_esdhc_ops = {
936 .read_l = esdhc_readl_le,
937 .read_w = esdhc_readw_le,
938 .write_l = esdhc_writel_le,
939 .write_w = esdhc_writew_le,
940 .write_b = esdhc_writeb_le,
941 .set_clock = esdhc_pltfm_set_clock,
942 .get_max_clock = esdhc_pltfm_get_max_clock,
943 .get_min_clock = esdhc_pltfm_get_min_clock,
944 .get_max_timeout_count = esdhc_get_max_timeout_count,
945 .get_ro = esdhc_pltfm_get_ro,
946 .set_timeout = esdhc_set_timeout,
947 .set_bus_width = esdhc_pltfm_set_bus_width,
948 .set_uhs_signaling = esdhc_set_uhs_signaling,
949 .reset = esdhc_reset,
950};
951
952static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
953 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
954 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
955 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
956 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
957 .ops = &sdhci_esdhc_ops,
958};
959
960#ifdef CONFIG_OF
961static int
962sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
963 struct sdhci_host *host,
964 struct pltfm_imx_data *imx_data)
965{
966 struct device_node *np = pdev->dev.of_node;
967 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
968 int ret;
969
970 if (of_get_property(np, "fsl,wp-controller", NULL))
971 boarddata->wp_type = ESDHC_WP_CONTROLLER;
972
973 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
974 if (gpio_is_valid(boarddata->wp_gpio))
975 boarddata->wp_type = ESDHC_WP_GPIO;
976
977 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
978
979 if (of_find_property(np, "no-1-8-v", NULL))
980 boarddata->support_vsel = false;
981 else
982 boarddata->support_vsel = true;
983
984 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
985 boarddata->delay_line = 0;
986
987 mmc_of_parse_voltage(np, &host->ocr_mask);
988
989 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
990 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
991 !IS_ERR(imx_data->pins_default)) {
992 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
993 ESDHC_PINCTRL_STATE_100MHZ);
994 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
995 ESDHC_PINCTRL_STATE_200MHZ);
996 if (IS_ERR(imx_data->pins_100mhz) ||
997 IS_ERR(imx_data->pins_200mhz)) {
998 dev_warn(mmc_dev(host->mmc),
999 "could not get ultra high speed state, work on normal mode\n");
1000 /*
1001 * fall back to not support uhs by specify no 1.8v quirk
1002 */
1003 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1004 }
1005 } else {
1006 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1007 }
1008
1009 /* call to generic mmc_of_parse to support additional capabilities */
1010 ret = mmc_of_parse(host->mmc);
1011 if (ret)
1012 return ret;
1013
1014 if (!IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
1015 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1016
1017 return 0;
1018}
1019#else
1020static inline int
1021sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1022 struct sdhci_host *host,
1023 struct pltfm_imx_data *imx_data)
1024{
1025 return -ENODEV;
1026}
1027#endif
1028
1029static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1030 struct sdhci_host *host,
1031 struct pltfm_imx_data *imx_data)
1032{
1033 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1034 int err;
1035
1036 if (!host->mmc->parent->platform_data) {
1037 dev_err(mmc_dev(host->mmc), "no board data!\n");
1038 return -EINVAL;
1039 }
1040
1041 imx_data->boarddata = *((struct esdhc_platform_data *)
1042 host->mmc->parent->platform_data);
1043 /* write_protect */
1044 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1045 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1046 if (err) {
1047 dev_err(mmc_dev(host->mmc),
1048 "failed to request write-protect gpio!\n");
1049 return err;
1050 }
1051 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1052 }
1053
1054 /* card_detect */
1055 switch (boarddata->cd_type) {
1056 case ESDHC_CD_GPIO:
1057 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1058 if (err) {
1059 dev_err(mmc_dev(host->mmc),
1060 "failed to request card-detect gpio!\n");
1061 return err;
1062 }
1063 /* fall through */
1064
1065 case ESDHC_CD_CONTROLLER:
1066 /* we have a working card_detect back */
1067 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1068 break;
1069
1070 case ESDHC_CD_PERMANENT:
1071 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1072 break;
1073
1074 case ESDHC_CD_NONE:
1075 break;
1076 }
1077
1078 switch (boarddata->max_bus_width) {
1079 case 8:
1080 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1081 break;
1082 case 4:
1083 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1084 break;
1085 case 1:
1086 default:
1087 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1088 break;
1089 }
1090
1091 return 0;
1092}
1093
1094static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1095{
1096 const struct of_device_id *of_id =
1097 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1098 struct sdhci_pltfm_host *pltfm_host;
1099 struct sdhci_host *host;
1100 int err;
1101 struct pltfm_imx_data *imx_data;
1102
1103 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1104 sizeof(*imx_data));
1105 if (IS_ERR(host))
1106 return PTR_ERR(host);
1107
1108 pltfm_host = sdhci_priv(host);
1109
1110 imx_data = sdhci_pltfm_priv(pltfm_host);
1111
1112 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1113 pdev->id_entry->driver_data;
1114
1115 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1116 if (IS_ERR(imx_data->clk_ipg)) {
1117 err = PTR_ERR(imx_data->clk_ipg);
1118 goto free_sdhci;
1119 }
1120
1121 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1122 if (IS_ERR(imx_data->clk_ahb)) {
1123 err = PTR_ERR(imx_data->clk_ahb);
1124 goto free_sdhci;
1125 }
1126
1127 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1128 if (IS_ERR(imx_data->clk_per)) {
1129 err = PTR_ERR(imx_data->clk_per);
1130 goto free_sdhci;
1131 }
1132
1133 pltfm_host->clk = imx_data->clk_per;
1134 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1135 clk_prepare_enable(imx_data->clk_per);
1136 clk_prepare_enable(imx_data->clk_ipg);
1137 clk_prepare_enable(imx_data->clk_ahb);
1138
1139 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1140 if (IS_ERR(imx_data->pinctrl)) {
1141 err = PTR_ERR(imx_data->pinctrl);
1142 goto disable_clk;
1143 }
1144
1145 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1146 PINCTRL_STATE_DEFAULT);
1147 if (IS_ERR(imx_data->pins_default))
1148 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1149
1150 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1151
1152 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1153 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1154 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1155 | SDHCI_QUIRK_BROKEN_ADMA;
1156
1157 /*
1158 * The imx6q ROM code will change the default watermark level setting
1159 * to something insane. Change it back here.
1160 */
1161 if (esdhc_is_usdhc(imx_data)) {
1162 writel(0x10401040, host->ioaddr + ESDHC_WTMK_LVL);
1163
1164 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1165 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1166
1167 /*
1168 * ROM code will change the bit burst_length_enable setting
1169 * to zero if this usdhc is choosed to boot system. Change
1170 * it back here, otherwise it will impact the performance a
1171 * lot. This bit is used to enable/disable the burst length
1172 * for the external AHB2AXI bridge, it's usefully especially
1173 * for INCR transfer because without burst length indicator,
1174 * the AHB2AXI bridge does not know the burst length in
1175 * advance. And without burst length indicator, AHB INCR
1176 * transfer can only be converted to singles on the AXI side.
1177 */
1178 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1179 | ESDHC_BURST_LEN_EN_INCR,
1180 host->ioaddr + SDHCI_HOST_CONTROL);
1181
1182 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1183 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1184
1185 /*
1186 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1187 * TO1.1, it's harmless for MX6SL
1188 */
1189 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1190 host->ioaddr + 0x6c);
1191 }
1192
1193 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1194 sdhci_esdhc_ops.platform_execute_tuning =
1195 esdhc_executing_tuning;
1196
1197 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1198 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1199 ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1200 host->ioaddr + ESDHC_TUNING_CTRL);
1201
1202 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1203 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1204
1205 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1206 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1207
1208 if (of_id)
1209 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1210 else
1211 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1212 if (err)
1213 goto disable_clk;
1214
1215 err = sdhci_add_host(host);
1216 if (err)
1217 goto disable_clk;
1218
1219 pm_runtime_set_active(&pdev->dev);
1220 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1221 pm_runtime_use_autosuspend(&pdev->dev);
1222 pm_suspend_ignore_children(&pdev->dev, 1);
1223 pm_runtime_enable(&pdev->dev);
1224
1225 return 0;
1226
1227disable_clk:
1228 clk_disable_unprepare(imx_data->clk_per);
1229 clk_disable_unprepare(imx_data->clk_ipg);
1230 clk_disable_unprepare(imx_data->clk_ahb);
1231free_sdhci:
1232 sdhci_pltfm_free(pdev);
1233 return err;
1234}
1235
1236static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1237{
1238 struct sdhci_host *host = platform_get_drvdata(pdev);
1239 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1240 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1241 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1242
1243 pm_runtime_get_sync(&pdev->dev);
1244 pm_runtime_disable(&pdev->dev);
1245 pm_runtime_put_noidle(&pdev->dev);
1246
1247 sdhci_remove_host(host, dead);
1248
1249 clk_disable_unprepare(imx_data->clk_per);
1250 clk_disable_unprepare(imx_data->clk_ipg);
1251 clk_disable_unprepare(imx_data->clk_ahb);
1252
1253 sdhci_pltfm_free(pdev);
1254
1255 return 0;
1256}
1257
1258#ifdef CONFIG_PM
1259static int sdhci_esdhc_runtime_suspend(struct device *dev)
1260{
1261 struct sdhci_host *host = dev_get_drvdata(dev);
1262 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1263 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1264 int ret;
1265
1266 ret = sdhci_runtime_suspend_host(host);
1267
1268 if (!sdhci_sdio_irq_enabled(host)) {
1269 clk_disable_unprepare(imx_data->clk_per);
1270 clk_disable_unprepare(imx_data->clk_ipg);
1271 }
1272 clk_disable_unprepare(imx_data->clk_ahb);
1273
1274 return ret;
1275}
1276
1277static int sdhci_esdhc_runtime_resume(struct device *dev)
1278{
1279 struct sdhci_host *host = dev_get_drvdata(dev);
1280 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1281 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1282
1283 if (!sdhci_sdio_irq_enabled(host)) {
1284 clk_prepare_enable(imx_data->clk_per);
1285 clk_prepare_enable(imx_data->clk_ipg);
1286 }
1287 clk_prepare_enable(imx_data->clk_ahb);
1288
1289 return sdhci_runtime_resume_host(host);
1290}
1291#endif
1292
1293static const struct dev_pm_ops sdhci_esdhc_pmops = {
1294 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1295 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1296 sdhci_esdhc_runtime_resume, NULL)
1297};
1298
1299static struct platform_driver sdhci_esdhc_imx_driver = {
1300 .driver = {
1301 .name = "sdhci-esdhc-imx",
1302 .of_match_table = imx_esdhc_dt_ids,
1303 .pm = &sdhci_esdhc_pmops,
1304 },
1305 .id_table = imx_esdhc_devtype,
1306 .probe = sdhci_esdhc_imx_probe,
1307 .remove = sdhci_esdhc_imx_remove,
1308};
1309
1310module_platform_driver(sdhci_esdhc_imx_driver);
1311
1312MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1313MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1314MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Freescale eSDHC i.MX controller driver for the platform bus.
4 *
5 * derived from the OF-version.
6 *
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <kernel@pengutronix.de>
9 */
10
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/module.h>
16#include <linux/slab.h>
17#include <linux/pm_qos.h>
18#include <linux/mmc/host.h>
19#include <linux/mmc/mmc.h>
20#include <linux/mmc/sdio.h>
21#include <linux/mmc/slot-gpio.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/platform_data/mmc-esdhc-imx.h>
26#include <linux/pm_runtime.h>
27#include "sdhci-pltfm.h"
28#include "sdhci-esdhc.h"
29#include "cqhci.h"
30
31#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
32#define ESDHC_CTRL_D3CD 0x08
33#define ESDHC_BURST_LEN_EN_INCR (1 << 27)
34/* VENDOR SPEC register */
35#define ESDHC_VENDOR_SPEC 0xc0
36#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
37#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
38#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
39#define ESDHC_WTMK_LVL 0x44
40#define ESDHC_WTMK_DEFAULT_VAL 0x10401040
41#define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
42#define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
43#define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
44#define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
45#define ESDHC_WTMK_LVL_WML_VAL_DEF 64
46#define ESDHC_WTMK_LVL_WML_VAL_MAX 128
47#define ESDHC_MIX_CTRL 0x48
48#define ESDHC_MIX_CTRL_DDREN (1 << 3)
49#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
50#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
51#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
52#define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
53#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
54#define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
55#define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
56/* Bits 3 and 6 are not SDHCI standard definitions */
57#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
58/* Tuning bits */
59#define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
60
61/* dll control register */
62#define ESDHC_DLL_CTRL 0x60
63#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
64#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
65
66/* tune control register */
67#define ESDHC_TUNE_CTRL_STATUS 0x68
68#define ESDHC_TUNE_CTRL_STEP 1
69#define ESDHC_TUNE_CTRL_MIN 0
70#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
71
72/* strobe dll register */
73#define ESDHC_STROBE_DLL_CTRL 0x70
74#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
75#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
76#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
77#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
78
79#define ESDHC_STROBE_DLL_STATUS 0x74
80#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
81#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
82
83#define ESDHC_VEND_SPEC2 0xc8
84#define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
85
86#define ESDHC_TUNING_CTRL 0xcc
87#define ESDHC_STD_TUNING_EN (1 << 24)
88/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
89#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
90#define ESDHC_TUNING_START_TAP_MASK 0xff
91#define ESDHC_TUNING_STEP_MASK 0x00070000
92#define ESDHC_TUNING_STEP_SHIFT 16
93
94/* pinctrl state */
95#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
96#define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
97
98/*
99 * Our interpretation of the SDHCI_HOST_CONTROL register
100 */
101#define ESDHC_CTRL_4BITBUS (0x1 << 1)
102#define ESDHC_CTRL_8BITBUS (0x2 << 1)
103#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
104
105/*
106 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
107 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
108 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
109 * Define this macro DMA error INT for fsl eSDHC
110 */
111#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
112
113/* the address offset of CQHCI */
114#define ESDHC_CQHCI_ADDR_OFFSET 0x100
115
116/*
117 * The CMDTYPE of the CMD register (offset 0xE) should be set to
118 * "11" when the STOP CMD12 is issued on imx53 to abort one
119 * open ended multi-blk IO. Otherwise the TC INT wouldn't
120 * be generated.
121 * In exact block transfer, the controller doesn't complete the
122 * operations automatically as required at the end of the
123 * transfer and remains on hold if the abort command is not sent.
124 * As a result, the TC flag is not asserted and SW received timeout
125 * exception. Bit1 of Vendor Spec register is used to fix it.
126 */
127#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
128/*
129 * The flag tells that the ESDHC controller is an USDHC block that is
130 * integrated on the i.MX6 series.
131 */
132#define ESDHC_FLAG_USDHC BIT(3)
133/* The IP supports manual tuning process */
134#define ESDHC_FLAG_MAN_TUNING BIT(4)
135/* The IP supports standard tuning process */
136#define ESDHC_FLAG_STD_TUNING BIT(5)
137/* The IP has SDHCI_CAPABILITIES_1 register */
138#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
139/*
140 * The IP has erratum ERR004536
141 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
142 * when reading data from the card
143 * This flag is also set for i.MX25 and i.MX35 in order to get
144 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
145 */
146#define ESDHC_FLAG_ERR004536 BIT(7)
147/* The IP supports HS200 mode */
148#define ESDHC_FLAG_HS200 BIT(8)
149/* The IP supports HS400 mode */
150#define ESDHC_FLAG_HS400 BIT(9)
151/*
152 * The IP has errata ERR010450
153 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
154 * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
155 */
156#define ESDHC_FLAG_ERR010450 BIT(10)
157/* The IP supports HS400ES mode */
158#define ESDHC_FLAG_HS400_ES BIT(11)
159/* The IP has Host Controller Interface for Command Queuing */
160#define ESDHC_FLAG_CQHCI BIT(12)
161/* need request pmqos during low power */
162#define ESDHC_FLAG_PMQOS BIT(13)
163
164struct esdhc_soc_data {
165 u32 flags;
166};
167
168static const struct esdhc_soc_data esdhc_imx25_data = {
169 .flags = ESDHC_FLAG_ERR004536,
170};
171
172static const struct esdhc_soc_data esdhc_imx35_data = {
173 .flags = ESDHC_FLAG_ERR004536,
174};
175
176static const struct esdhc_soc_data esdhc_imx51_data = {
177 .flags = 0,
178};
179
180static const struct esdhc_soc_data esdhc_imx53_data = {
181 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
182};
183
184static const struct esdhc_soc_data usdhc_imx6q_data = {
185 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
186};
187
188static const struct esdhc_soc_data usdhc_imx6sl_data = {
189 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
190 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
191 | ESDHC_FLAG_HS200,
192};
193
194static const struct esdhc_soc_data usdhc_imx6sx_data = {
195 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
196 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
197};
198
199static const struct esdhc_soc_data usdhc_imx6ull_data = {
200 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
201 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
202 | ESDHC_FLAG_ERR010450,
203};
204
205static const struct esdhc_soc_data usdhc_imx7d_data = {
206 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
207 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
208 | ESDHC_FLAG_HS400,
209};
210
211static struct esdhc_soc_data usdhc_imx7ulp_data = {
212 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
213 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
214 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400,
215};
216
217static struct esdhc_soc_data usdhc_imx8qxp_data = {
218 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
219 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
220 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
221 | ESDHC_FLAG_CQHCI,
222};
223
224struct pltfm_imx_data {
225 u32 scratchpad;
226 struct pinctrl *pinctrl;
227 struct pinctrl_state *pins_default;
228 struct pinctrl_state *pins_100mhz;
229 struct pinctrl_state *pins_200mhz;
230 const struct esdhc_soc_data *socdata;
231 struct esdhc_platform_data boarddata;
232 struct clk *clk_ipg;
233 struct clk *clk_ahb;
234 struct clk *clk_per;
235 unsigned int actual_clock;
236 enum {
237 NO_CMD_PENDING, /* no multiblock command pending */
238 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
239 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
240 } multiblock_status;
241 u32 is_ddr;
242 struct pm_qos_request pm_qos_req;
243};
244
245static const struct platform_device_id imx_esdhc_devtype[] = {
246 {
247 .name = "sdhci-esdhc-imx25",
248 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
249 }, {
250 .name = "sdhci-esdhc-imx35",
251 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
252 }, {
253 .name = "sdhci-esdhc-imx51",
254 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
255 }, {
256 /* sentinel */
257 }
258};
259MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
260
261static const struct of_device_id imx_esdhc_dt_ids[] = {
262 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
263 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
264 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
265 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
266 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
267 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
268 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
269 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
270 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
271 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
272 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
273 { /* sentinel */ }
274};
275MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
276
277static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
278{
279 return data->socdata == &esdhc_imx25_data;
280}
281
282static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
283{
284 return data->socdata == &esdhc_imx53_data;
285}
286
287static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
288{
289 return data->socdata == &usdhc_imx6q_data;
290}
291
292static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
293{
294 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
295}
296
297static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
298{
299 void __iomem *base = host->ioaddr + (reg & ~0x3);
300 u32 shift = (reg & 0x3) * 8;
301
302 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
303}
304
305static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
306{
307 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
308 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
309 u32 val = readl(host->ioaddr + reg);
310
311 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
312 u32 fsl_prss = val;
313 /* save the least 20 bits */
314 val = fsl_prss & 0x000FFFFF;
315 /* move dat[0-3] bits */
316 val |= (fsl_prss & 0x0F000000) >> 4;
317 /* move cmd line bit */
318 val |= (fsl_prss & 0x00800000) << 1;
319 }
320
321 if (unlikely(reg == SDHCI_CAPABILITIES)) {
322 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
323 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
324 val &= 0xffff0000;
325
326 /* In FSL esdhc IC module, only bit20 is used to indicate the
327 * ADMA2 capability of esdhc, but this bit is messed up on
328 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
329 * don't actually support ADMA2). So set the BROKEN_ADMA
330 * quirk on MX25/35 platforms.
331 */
332
333 if (val & SDHCI_CAN_DO_ADMA1) {
334 val &= ~SDHCI_CAN_DO_ADMA1;
335 val |= SDHCI_CAN_DO_ADMA2;
336 }
337 }
338
339 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
340 if (esdhc_is_usdhc(imx_data)) {
341 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
342 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
343 else
344 /* imx6q/dl does not have cap_1 register, fake one */
345 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
346 | SDHCI_SUPPORT_SDR50
347 | SDHCI_USE_SDR50_TUNING
348 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
349
350 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
351 val |= SDHCI_SUPPORT_HS400;
352
353 /*
354 * Do not advertise faster UHS modes if there are no
355 * pinctrl states for 100MHz/200MHz.
356 */
357 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
358 IS_ERR_OR_NULL(imx_data->pins_200mhz))
359 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
360 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
361 }
362 }
363
364 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
365 val = 0;
366 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
367 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
368 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
369 }
370
371 if (unlikely(reg == SDHCI_INT_STATUS)) {
372 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
373 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
374 val |= SDHCI_INT_ADMA_ERROR;
375 }
376
377 /*
378 * mask off the interrupt we get in response to the manually
379 * sent CMD12
380 */
381 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
382 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
383 val &= ~SDHCI_INT_RESPONSE;
384 writel(SDHCI_INT_RESPONSE, host->ioaddr +
385 SDHCI_INT_STATUS);
386 imx_data->multiblock_status = NO_CMD_PENDING;
387 }
388 }
389
390 return val;
391}
392
393static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
394{
395 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
396 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
397 u32 data;
398
399 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
400 reg == SDHCI_INT_STATUS)) {
401 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
402 /*
403 * Clear and then set D3CD bit to avoid missing the
404 * card interrupt. This is an eSDHC controller problem
405 * so we need to apply the following workaround: clear
406 * and set D3CD bit will make eSDHC re-sample the card
407 * interrupt. In case a card interrupt was lost,
408 * re-sample it by the following steps.
409 */
410 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
411 data &= ~ESDHC_CTRL_D3CD;
412 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
413 data |= ESDHC_CTRL_D3CD;
414 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
415 }
416
417 if (val & SDHCI_INT_ADMA_ERROR) {
418 val &= ~SDHCI_INT_ADMA_ERROR;
419 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
420 }
421 }
422
423 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
424 && (reg == SDHCI_INT_STATUS)
425 && (val & SDHCI_INT_DATA_END))) {
426 u32 v;
427 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
428 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
429 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
430
431 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
432 {
433 /* send a manual CMD12 with RESPTYP=none */
434 data = MMC_STOP_TRANSMISSION << 24 |
435 SDHCI_CMD_ABORTCMD << 16;
436 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
437 imx_data->multiblock_status = WAIT_FOR_INT;
438 }
439 }
440
441 writel(val, host->ioaddr + reg);
442}
443
444static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
445{
446 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
447 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
448 u16 ret = 0;
449 u32 val;
450
451 if (unlikely(reg == SDHCI_HOST_VERSION)) {
452 reg ^= 2;
453 if (esdhc_is_usdhc(imx_data)) {
454 /*
455 * The usdhc register returns a wrong host version.
456 * Correct it here.
457 */
458 return SDHCI_SPEC_300;
459 }
460 }
461
462 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
463 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
464 if (val & ESDHC_VENDOR_SPEC_VSELECT)
465 ret |= SDHCI_CTRL_VDD_180;
466
467 if (esdhc_is_usdhc(imx_data)) {
468 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
469 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
470 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
471 /* the std tuning bits is in ACMD12_ERR for imx6sl */
472 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
473 }
474
475 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
476 ret |= SDHCI_CTRL_EXEC_TUNING;
477 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
478 ret |= SDHCI_CTRL_TUNED_CLK;
479
480 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
481
482 return ret;
483 }
484
485 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
486 if (esdhc_is_usdhc(imx_data)) {
487 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
488 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
489 /* Swap AC23 bit */
490 if (m & ESDHC_MIX_CTRL_AC23EN) {
491 ret &= ~ESDHC_MIX_CTRL_AC23EN;
492 ret |= SDHCI_TRNS_AUTO_CMD23;
493 }
494 } else {
495 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
496 }
497
498 return ret;
499 }
500
501 return readw(host->ioaddr + reg);
502}
503
504static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
505{
506 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
507 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
508 u32 new_val = 0;
509
510 switch (reg) {
511 case SDHCI_CLOCK_CONTROL:
512 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
513 if (val & SDHCI_CLOCK_CARD_EN)
514 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
515 else
516 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
517 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
518 return;
519 case SDHCI_HOST_CONTROL2:
520 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
521 if (val & SDHCI_CTRL_VDD_180)
522 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
523 else
524 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
525 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
526 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
527 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
528 if (val & SDHCI_CTRL_TUNED_CLK) {
529 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
530 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
531 } else {
532 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
533 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
534 }
535 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
536 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
537 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
538 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
539 if (val & SDHCI_CTRL_TUNED_CLK) {
540 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
541 } else {
542 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
543 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
544 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
545 }
546
547 if (val & SDHCI_CTRL_EXEC_TUNING) {
548 v |= ESDHC_MIX_CTRL_EXE_TUNE;
549 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
550 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
551 } else {
552 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
553 }
554
555 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
556 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
557 }
558 return;
559 case SDHCI_TRANSFER_MODE:
560 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
561 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
562 && (host->cmd->data->blocks > 1)
563 && (host->cmd->data->flags & MMC_DATA_READ)) {
564 u32 v;
565 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
566 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
567 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
568 }
569
570 if (esdhc_is_usdhc(imx_data)) {
571 u32 wml;
572 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
573 /* Swap AC23 bit */
574 if (val & SDHCI_TRNS_AUTO_CMD23) {
575 val &= ~SDHCI_TRNS_AUTO_CMD23;
576 val |= ESDHC_MIX_CTRL_AC23EN;
577 }
578 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
579 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
580
581 /* Set watermark levels for PIO access to maximum value
582 * (128 words) to accommodate full 512 bytes buffer.
583 * For DMA access restore the levels to default value.
584 */
585 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
586 if (val & SDHCI_TRNS_DMA)
587 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
588 else
589 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
590 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
591 ESDHC_WTMK_LVL_WR_WML_MASK);
592 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
593 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
594 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
595 } else {
596 /*
597 * Postpone this write, we must do it together with a
598 * command write that is down below.
599 */
600 imx_data->scratchpad = val;
601 }
602 return;
603 case SDHCI_COMMAND:
604 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
605 val |= SDHCI_CMD_ABORTCMD;
606
607 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
608 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
609 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
610
611 if (esdhc_is_usdhc(imx_data))
612 writel(val << 16,
613 host->ioaddr + SDHCI_TRANSFER_MODE);
614 else
615 writel(val << 16 | imx_data->scratchpad,
616 host->ioaddr + SDHCI_TRANSFER_MODE);
617 return;
618 case SDHCI_BLOCK_SIZE:
619 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
620 break;
621 }
622 esdhc_clrset_le(host, 0xffff, val, reg);
623}
624
625static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
626{
627 u8 ret;
628 u32 val;
629
630 switch (reg) {
631 case SDHCI_HOST_CONTROL:
632 val = readl(host->ioaddr + reg);
633
634 ret = val & SDHCI_CTRL_LED;
635 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
636 ret |= (val & ESDHC_CTRL_4BITBUS);
637 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
638 return ret;
639 }
640
641 return readb(host->ioaddr + reg);
642}
643
644static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
645{
646 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
647 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
648 u32 new_val = 0;
649 u32 mask;
650
651 switch (reg) {
652 case SDHCI_POWER_CONTROL:
653 /*
654 * FSL put some DMA bits here
655 * If your board has a regulator, code should be here
656 */
657 return;
658 case SDHCI_HOST_CONTROL:
659 /* FSL messed up here, so we need to manually compose it. */
660 new_val = val & SDHCI_CTRL_LED;
661 /* ensure the endianness */
662 new_val |= ESDHC_HOST_CONTROL_LE;
663 /* bits 8&9 are reserved on mx25 */
664 if (!is_imx25_esdhc(imx_data)) {
665 /* DMA mode bits are shifted */
666 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
667 }
668
669 /*
670 * Do not touch buswidth bits here. This is done in
671 * esdhc_pltfm_bus_width.
672 * Do not touch the D3CD bit either which is used for the
673 * SDIO interrupt erratum workaround.
674 */
675 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
676
677 esdhc_clrset_le(host, mask, new_val, reg);
678 return;
679 case SDHCI_SOFTWARE_RESET:
680 if (val & SDHCI_RESET_DATA)
681 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
682 break;
683 }
684 esdhc_clrset_le(host, 0xff, val, reg);
685
686 if (reg == SDHCI_SOFTWARE_RESET) {
687 if (val & SDHCI_RESET_ALL) {
688 /*
689 * The esdhc has a design violation to SDHC spec which
690 * tells that software reset should not affect card
691 * detection circuit. But esdhc clears its SYSCTL
692 * register bits [0..2] during the software reset. This
693 * will stop those clocks that card detection circuit
694 * relies on. To work around it, we turn the clocks on
695 * back to keep card detection circuit functional.
696 */
697 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
698 /*
699 * The reset on usdhc fails to clear MIX_CTRL register.
700 * Do it manually here.
701 */
702 if (esdhc_is_usdhc(imx_data)) {
703 /*
704 * the tuning bits should be kept during reset
705 */
706 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
707 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
708 host->ioaddr + ESDHC_MIX_CTRL);
709 imx_data->is_ddr = 0;
710 }
711 } else if (val & SDHCI_RESET_DATA) {
712 /*
713 * The eSDHC DAT line software reset clears at least the
714 * data transfer width on i.MX25, so make sure that the
715 * Host Control register is unaffected.
716 */
717 esdhc_clrset_le(host, 0xff, new_val,
718 SDHCI_HOST_CONTROL);
719 }
720 }
721}
722
723static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
724{
725 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
726
727 return pltfm_host->clock;
728}
729
730static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
731{
732 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
733
734 return pltfm_host->clock / 256 / 16;
735}
736
737static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
738 unsigned int clock)
739{
740 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
741 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
742 unsigned int host_clock = pltfm_host->clock;
743 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
744 int pre_div = 1;
745 int div = 1;
746 u32 temp, val;
747
748 if (esdhc_is_usdhc(imx_data)) {
749 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
750 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
751 host->ioaddr + ESDHC_VENDOR_SPEC);
752 }
753
754 if (clock == 0) {
755 host->mmc->actual_clock = 0;
756 return;
757 }
758
759 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
760 if (is_imx53_esdhc(imx_data)) {
761 /*
762 * According to the i.MX53 reference manual, if DLLCTRL[10] can
763 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
764 */
765 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
766 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
767 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
768 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
769 if (temp & BIT(10))
770 pre_div = 2;
771 }
772
773 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
774 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
775 | ESDHC_CLOCK_MASK);
776 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
777
778 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
779 unsigned int max_clock;
780
781 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
782
783 clock = min(clock, max_clock);
784 }
785
786 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
787 pre_div < 256)
788 pre_div *= 2;
789
790 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
791 div++;
792
793 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
794 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
795 clock, host->mmc->actual_clock);
796
797 pre_div >>= 1;
798 div--;
799
800 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
801 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
802 | (div << ESDHC_DIVIDER_SHIFT)
803 | (pre_div << ESDHC_PREDIV_SHIFT));
804 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
805
806 if (esdhc_is_usdhc(imx_data)) {
807 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
808 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
809 host->ioaddr + ESDHC_VENDOR_SPEC);
810 }
811
812 mdelay(1);
813}
814
815static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
816{
817 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
818 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
819 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
820
821 switch (boarddata->wp_type) {
822 case ESDHC_WP_GPIO:
823 return mmc_gpio_get_ro(host->mmc);
824 case ESDHC_WP_CONTROLLER:
825 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
826 SDHCI_WRITE_PROTECT);
827 case ESDHC_WP_NONE:
828 break;
829 }
830
831 return -ENOSYS;
832}
833
834static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
835{
836 u32 ctrl;
837
838 switch (width) {
839 case MMC_BUS_WIDTH_8:
840 ctrl = ESDHC_CTRL_8BITBUS;
841 break;
842 case MMC_BUS_WIDTH_4:
843 ctrl = ESDHC_CTRL_4BITBUS;
844 break;
845 default:
846 ctrl = 0;
847 break;
848 }
849
850 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
851 SDHCI_HOST_CONTROL);
852}
853
854static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
855{
856 struct sdhci_host *host = mmc_priv(mmc);
857
858 /*
859 * i.MX uSDHC internally already uses a fixed optimized timing for
860 * DDR50, normally does not require tuning for DDR50 mode.
861 */
862 if (host->timing == MMC_TIMING_UHS_DDR50)
863 return 0;
864
865 return sdhci_execute_tuning(mmc, opcode);
866}
867
868static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
869{
870 u32 reg;
871
872 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
873 mdelay(1);
874
875 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
876 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
877 ESDHC_MIX_CTRL_FBCLK_SEL;
878 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
879 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
880 dev_dbg(mmc_dev(host->mmc),
881 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
882 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
883}
884
885static void esdhc_post_tuning(struct sdhci_host *host)
886{
887 u32 reg;
888
889 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
890 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
891 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
892 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
893}
894
895static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
896{
897 int min, max, avg, ret;
898
899 /* find the mininum delay first which can pass tuning */
900 min = ESDHC_TUNE_CTRL_MIN;
901 while (min < ESDHC_TUNE_CTRL_MAX) {
902 esdhc_prepare_tuning(host, min);
903 if (!mmc_send_tuning(host->mmc, opcode, NULL))
904 break;
905 min += ESDHC_TUNE_CTRL_STEP;
906 }
907
908 /* find the maxinum delay which can not pass tuning */
909 max = min + ESDHC_TUNE_CTRL_STEP;
910 while (max < ESDHC_TUNE_CTRL_MAX) {
911 esdhc_prepare_tuning(host, max);
912 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
913 max -= ESDHC_TUNE_CTRL_STEP;
914 break;
915 }
916 max += ESDHC_TUNE_CTRL_STEP;
917 }
918
919 /* use average delay to get the best timing */
920 avg = (min + max) / 2;
921 esdhc_prepare_tuning(host, avg);
922 ret = mmc_send_tuning(host->mmc, opcode, NULL);
923 esdhc_post_tuning(host);
924
925 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
926 ret ? "failed" : "passed", avg, ret);
927
928 return ret;
929}
930
931static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
932{
933 struct sdhci_host *host = mmc_priv(mmc);
934 u32 m;
935
936 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
937 if (ios->enhanced_strobe)
938 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
939 else
940 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
941 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
942}
943
944static int esdhc_change_pinstate(struct sdhci_host *host,
945 unsigned int uhs)
946{
947 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
948 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
949 struct pinctrl_state *pinctrl;
950
951 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
952
953 if (IS_ERR(imx_data->pinctrl) ||
954 IS_ERR(imx_data->pins_default) ||
955 IS_ERR(imx_data->pins_100mhz) ||
956 IS_ERR(imx_data->pins_200mhz))
957 return -EINVAL;
958
959 switch (uhs) {
960 case MMC_TIMING_UHS_SDR50:
961 case MMC_TIMING_UHS_DDR50:
962 pinctrl = imx_data->pins_100mhz;
963 break;
964 case MMC_TIMING_UHS_SDR104:
965 case MMC_TIMING_MMC_HS200:
966 case MMC_TIMING_MMC_HS400:
967 pinctrl = imx_data->pins_200mhz;
968 break;
969 default:
970 /* back to default state for other legacy timing */
971 pinctrl = imx_data->pins_default;
972 }
973
974 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
975}
976
977/*
978 * For HS400 eMMC, there is a data_strobe line. This signal is generated
979 * by the device and used for data output and CRC status response output
980 * in HS400 mode. The frequency of this signal follows the frequency of
981 * CLK generated by host. The host receives the data which is aligned to the
982 * edge of data_strobe line. Due to the time delay between CLK line and
983 * data_strobe line, if the delay time is larger than one clock cycle,
984 * then CLK and data_strobe line will be misaligned, read error shows up.
985 */
986static void esdhc_set_strobe_dll(struct sdhci_host *host)
987{
988 u32 v;
989
990 /* disable clock before enabling strobe dll */
991 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
992 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
993 host->ioaddr + ESDHC_VENDOR_SPEC);
994
995 /* force a reset on strobe dll */
996 writel(ESDHC_STROBE_DLL_CTRL_RESET,
997 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
998 /* clear the reset bit on strobe dll before any setting */
999 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1000
1001 /*
1002 * enable strobe dll ctrl and adjust the delay target
1003 * for the uSDHC loopback read clock
1004 */
1005 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1006 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1007 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1008 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1009 /* wait 5us to make sure strobe dll status register stable */
1010 udelay(5);
1011 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
1012 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
1013 dev_warn(mmc_dev(host->mmc),
1014 "warning! HS400 strobe DLL status REF not lock!\n");
1015 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
1016 dev_warn(mmc_dev(host->mmc),
1017 "warning! HS400 strobe DLL status SLV not lock!\n");
1018}
1019
1020static void esdhc_reset_tuning(struct sdhci_host *host)
1021{
1022 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1023 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1024 u32 ctrl;
1025
1026 /* Reset the tuning circuit */
1027 if (esdhc_is_usdhc(imx_data)) {
1028 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1029 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1030 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1031 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1032 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1033 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1034 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1035 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1036 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1037 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1038 }
1039 }
1040}
1041
1042static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1043{
1044 u32 m;
1045 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1046 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1047 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1048
1049 /* disable ddr mode and disable HS400 mode */
1050 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1051 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1052 imx_data->is_ddr = 0;
1053
1054 switch (timing) {
1055 case MMC_TIMING_UHS_SDR12:
1056 case MMC_TIMING_UHS_SDR25:
1057 case MMC_TIMING_UHS_SDR50:
1058 case MMC_TIMING_UHS_SDR104:
1059 case MMC_TIMING_MMC_HS:
1060 case MMC_TIMING_MMC_HS200:
1061 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1062 break;
1063 case MMC_TIMING_UHS_DDR50:
1064 case MMC_TIMING_MMC_DDR52:
1065 m |= ESDHC_MIX_CTRL_DDREN;
1066 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1067 imx_data->is_ddr = 1;
1068 if (boarddata->delay_line) {
1069 u32 v;
1070 v = boarddata->delay_line <<
1071 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1072 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1073 if (is_imx53_esdhc(imx_data))
1074 v <<= 1;
1075 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1076 }
1077 break;
1078 case MMC_TIMING_MMC_HS400:
1079 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1080 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1081 imx_data->is_ddr = 1;
1082 /* update clock after enable DDR for strobe DLL lock */
1083 host->ops->set_clock(host, host->clock);
1084 esdhc_set_strobe_dll(host);
1085 break;
1086 case MMC_TIMING_LEGACY:
1087 default:
1088 esdhc_reset_tuning(host);
1089 break;
1090 }
1091
1092 esdhc_change_pinstate(host, timing);
1093}
1094
1095static void esdhc_reset(struct sdhci_host *host, u8 mask)
1096{
1097 sdhci_reset(host, mask);
1098
1099 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1100 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1101}
1102
1103static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1104{
1105 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1106 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1107
1108 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1109 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1110}
1111
1112static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1113{
1114 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1115 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1116
1117 /* use maximum timeout counter */
1118 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1119 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1120 SDHCI_TIMEOUT_CONTROL);
1121}
1122
1123static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1124{
1125 int cmd_error = 0;
1126 int data_error = 0;
1127
1128 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1129 return intmask;
1130
1131 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1132
1133 return 0;
1134}
1135
1136static struct sdhci_ops sdhci_esdhc_ops = {
1137 .read_l = esdhc_readl_le,
1138 .read_w = esdhc_readw_le,
1139 .read_b = esdhc_readb_le,
1140 .write_l = esdhc_writel_le,
1141 .write_w = esdhc_writew_le,
1142 .write_b = esdhc_writeb_le,
1143 .set_clock = esdhc_pltfm_set_clock,
1144 .get_max_clock = esdhc_pltfm_get_max_clock,
1145 .get_min_clock = esdhc_pltfm_get_min_clock,
1146 .get_max_timeout_count = esdhc_get_max_timeout_count,
1147 .get_ro = esdhc_pltfm_get_ro,
1148 .set_timeout = esdhc_set_timeout,
1149 .set_bus_width = esdhc_pltfm_set_bus_width,
1150 .set_uhs_signaling = esdhc_set_uhs_signaling,
1151 .reset = esdhc_reset,
1152 .irq = esdhc_cqhci_irq,
1153};
1154
1155static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1156 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1157 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1158 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1159 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1160 .ops = &sdhci_esdhc_ops,
1161};
1162
1163static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1164{
1165 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1166 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1167 int tmp;
1168
1169 if (esdhc_is_usdhc(imx_data)) {
1170 /*
1171 * The imx6q ROM code will change the default watermark
1172 * level setting to something insane. Change it back here.
1173 */
1174 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1175
1176 /*
1177 * ROM code will change the bit burst_length_enable setting
1178 * to zero if this usdhc is chosen to boot system. Change
1179 * it back here, otherwise it will impact the performance a
1180 * lot. This bit is used to enable/disable the burst length
1181 * for the external AHB2AXI bridge. It's useful especially
1182 * for INCR transfer because without burst length indicator,
1183 * the AHB2AXI bridge does not know the burst length in
1184 * advance. And without burst length indicator, AHB INCR
1185 * transfer can only be converted to singles on the AXI side.
1186 */
1187 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1188 | ESDHC_BURST_LEN_EN_INCR,
1189 host->ioaddr + SDHCI_HOST_CONTROL);
1190
1191 /*
1192 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1193 * TO1.1, it's harmless for MX6SL
1194 */
1195 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1196 host->ioaddr + 0x6c);
1197
1198 /* disable DLL_CTRL delay line settings */
1199 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1200
1201 /*
1202 * For the case of command with busy, if set the bit
1203 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1204 * transfer complete interrupt when busy is deasserted.
1205 * When CQHCI use DCMD to send a CMD need R1b respons,
1206 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1207 * otherwise DCMD will always meet timeout waiting for
1208 * hardware interrupt issue.
1209 */
1210 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1211 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1212 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1213 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1214
1215 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1216 }
1217
1218 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1219 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1220 tmp |= ESDHC_STD_TUNING_EN |
1221 ESDHC_TUNING_START_TAP_DEFAULT;
1222 if (imx_data->boarddata.tuning_start_tap) {
1223 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1224 tmp |= imx_data->boarddata.tuning_start_tap;
1225 }
1226
1227 if (imx_data->boarddata.tuning_step) {
1228 tmp &= ~ESDHC_TUNING_STEP_MASK;
1229 tmp |= imx_data->boarddata.tuning_step
1230 << ESDHC_TUNING_STEP_SHIFT;
1231 }
1232 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1233 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1234 /*
1235 * ESDHC_STD_TUNING_EN may be configed in bootloader
1236 * or ROM code, so clear this bit here to make sure
1237 * the manual tuning can work.
1238 */
1239 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1240 tmp &= ~ESDHC_STD_TUNING_EN;
1241 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1242 }
1243 }
1244}
1245
1246static void esdhc_cqe_enable(struct mmc_host *mmc)
1247{
1248 struct sdhci_host *host = mmc_priv(mmc);
1249 struct cqhci_host *cq_host = mmc->cqe_private;
1250 u32 reg;
1251 u16 mode;
1252 int count = 10;
1253
1254 /*
1255 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1256 * the case after tuning, so ensure the buffer is drained.
1257 */
1258 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1259 while (reg & SDHCI_DATA_AVAILABLE) {
1260 sdhci_readl(host, SDHCI_BUFFER);
1261 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1262 if (count-- == 0) {
1263 dev_warn(mmc_dev(host->mmc),
1264 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1265 break;
1266 }
1267 mdelay(1);
1268 }
1269
1270 /*
1271 * Runtime resume will reset the entire host controller, which
1272 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1273 * Here set DMAEN and BCEN when enable CMDQ.
1274 */
1275 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1276 if (host->flags & SDHCI_REQ_USE_DMA)
1277 mode |= SDHCI_TRNS_DMA;
1278 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1279 mode |= SDHCI_TRNS_BLK_CNT_EN;
1280 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1281
1282 /*
1283 * Though Runtime resume reset the entire host controller,
1284 * but do not impact the CQHCI side, need to clear the
1285 * HALT bit, avoid CQHCI stuck in the first request when
1286 * system resume back.
1287 */
1288 cqhci_writel(cq_host, 0, CQHCI_CTL);
1289 if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
1290 dev_err(mmc_dev(host->mmc),
1291 "failed to exit halt state when enable CQE\n");
1292
1293
1294 sdhci_cqe_enable(mmc);
1295}
1296
1297static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1298{
1299 sdhci_dumpregs(mmc_priv(mmc));
1300}
1301
1302static const struct cqhci_host_ops esdhc_cqhci_ops = {
1303 .enable = esdhc_cqe_enable,
1304 .disable = sdhci_cqe_disable,
1305 .dumpregs = esdhc_sdhci_dumpregs,
1306};
1307
1308#ifdef CONFIG_OF
1309static int
1310sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1311 struct sdhci_host *host,
1312 struct pltfm_imx_data *imx_data)
1313{
1314 struct device_node *np = pdev->dev.of_node;
1315 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1316 int ret;
1317
1318 if (of_get_property(np, "fsl,wp-controller", NULL))
1319 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1320
1321 /*
1322 * If we have this property, then activate WP check.
1323 * Retrieveing and requesting the actual WP GPIO will happen
1324 * in the call to mmc_of_parse().
1325 */
1326 if (of_property_read_bool(np, "wp-gpios"))
1327 boarddata->wp_type = ESDHC_WP_GPIO;
1328
1329 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1330 of_property_read_u32(np, "fsl,tuning-start-tap",
1331 &boarddata->tuning_start_tap);
1332
1333 if (of_find_property(np, "no-1-8-v", NULL))
1334 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1335
1336 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1337 boarddata->delay_line = 0;
1338
1339 mmc_of_parse_voltage(np, &host->ocr_mask);
1340
1341 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pins_default)) {
1342 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1343 ESDHC_PINCTRL_STATE_100MHZ);
1344 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1345 ESDHC_PINCTRL_STATE_200MHZ);
1346 }
1347
1348 /* call to generic mmc_of_parse to support additional capabilities */
1349 ret = mmc_of_parse(host->mmc);
1350 if (ret)
1351 return ret;
1352
1353 if (mmc_gpio_get_cd(host->mmc) >= 0)
1354 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1355
1356 return 0;
1357}
1358#else
1359static inline int
1360sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1361 struct sdhci_host *host,
1362 struct pltfm_imx_data *imx_data)
1363{
1364 return -ENODEV;
1365}
1366#endif
1367
1368static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1369 struct sdhci_host *host,
1370 struct pltfm_imx_data *imx_data)
1371{
1372 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1373 int err;
1374
1375 if (!host->mmc->parent->platform_data) {
1376 dev_err(mmc_dev(host->mmc), "no board data!\n");
1377 return -EINVAL;
1378 }
1379
1380 imx_data->boarddata = *((struct esdhc_platform_data *)
1381 host->mmc->parent->platform_data);
1382 /* write_protect */
1383 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1384 err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0, NULL);
1385 if (err) {
1386 dev_err(mmc_dev(host->mmc),
1387 "failed to request write-protect gpio!\n");
1388 return err;
1389 }
1390 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1391 }
1392
1393 /* card_detect */
1394 switch (boarddata->cd_type) {
1395 case ESDHC_CD_GPIO:
1396 err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0, NULL);
1397 if (err) {
1398 dev_err(mmc_dev(host->mmc),
1399 "failed to request card-detect gpio!\n");
1400 return err;
1401 }
1402 /* fall through */
1403
1404 case ESDHC_CD_CONTROLLER:
1405 /* we have a working card_detect back */
1406 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1407 break;
1408
1409 case ESDHC_CD_PERMANENT:
1410 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1411 break;
1412
1413 case ESDHC_CD_NONE:
1414 break;
1415 }
1416
1417 switch (boarddata->max_bus_width) {
1418 case 8:
1419 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1420 break;
1421 case 4:
1422 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1423 break;
1424 case 1:
1425 default:
1426 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1427 break;
1428 }
1429
1430 return 0;
1431}
1432
1433static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1434{
1435 const struct of_device_id *of_id =
1436 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1437 struct sdhci_pltfm_host *pltfm_host;
1438 struct sdhci_host *host;
1439 struct cqhci_host *cq_host;
1440 int err;
1441 struct pltfm_imx_data *imx_data;
1442
1443 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1444 sizeof(*imx_data));
1445 if (IS_ERR(host))
1446 return PTR_ERR(host);
1447
1448 pltfm_host = sdhci_priv(host);
1449
1450 imx_data = sdhci_pltfm_priv(pltfm_host);
1451
1452 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1453 pdev->id_entry->driver_data;
1454
1455 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1456 pm_qos_add_request(&imx_data->pm_qos_req,
1457 PM_QOS_CPU_DMA_LATENCY, 0);
1458
1459 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1460 if (IS_ERR(imx_data->clk_ipg)) {
1461 err = PTR_ERR(imx_data->clk_ipg);
1462 goto free_sdhci;
1463 }
1464
1465 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1466 if (IS_ERR(imx_data->clk_ahb)) {
1467 err = PTR_ERR(imx_data->clk_ahb);
1468 goto free_sdhci;
1469 }
1470
1471 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1472 if (IS_ERR(imx_data->clk_per)) {
1473 err = PTR_ERR(imx_data->clk_per);
1474 goto free_sdhci;
1475 }
1476
1477 pltfm_host->clk = imx_data->clk_per;
1478 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1479 err = clk_prepare_enable(imx_data->clk_per);
1480 if (err)
1481 goto free_sdhci;
1482 err = clk_prepare_enable(imx_data->clk_ipg);
1483 if (err)
1484 goto disable_per_clk;
1485 err = clk_prepare_enable(imx_data->clk_ahb);
1486 if (err)
1487 goto disable_ipg_clk;
1488
1489 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1490 if (IS_ERR(imx_data->pinctrl)) {
1491 err = PTR_ERR(imx_data->pinctrl);
1492 goto disable_ahb_clk;
1493 }
1494
1495 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1496 PINCTRL_STATE_DEFAULT);
1497 if (IS_ERR(imx_data->pins_default))
1498 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1499
1500 if (esdhc_is_usdhc(imx_data)) {
1501 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1502 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1503 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1504 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1505
1506 /* clear tuning bits in case ROM has set it already */
1507 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1508 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1509 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1510
1511 /*
1512 * Link usdhc specific mmc_host_ops execute_tuning function,
1513 * to replace the standard one in sdhci_ops.
1514 */
1515 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1516 }
1517
1518 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1519 sdhci_esdhc_ops.platform_execute_tuning =
1520 esdhc_executing_tuning;
1521
1522 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1523 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1524
1525 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1526 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1527
1528 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1529 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1530 host->mmc_host_ops.hs400_enhanced_strobe =
1531 esdhc_hs400_enhanced_strobe;
1532 }
1533
1534 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1535 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1536 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1537 if (!cq_host) {
1538 err = -ENOMEM;
1539 goto disable_ahb_clk;
1540 }
1541
1542 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1543 cq_host->ops = &esdhc_cqhci_ops;
1544
1545 err = cqhci_init(cq_host, host->mmc, false);
1546 if (err)
1547 goto disable_ahb_clk;
1548 }
1549
1550 if (of_id)
1551 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1552 else
1553 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1554 if (err)
1555 goto disable_ahb_clk;
1556
1557 host->tuning_delay = 1;
1558
1559 sdhci_esdhc_imx_hwinit(host);
1560
1561 err = sdhci_add_host(host);
1562 if (err)
1563 goto disable_ahb_clk;
1564
1565 pm_runtime_set_active(&pdev->dev);
1566 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1567 pm_runtime_use_autosuspend(&pdev->dev);
1568 pm_suspend_ignore_children(&pdev->dev, 1);
1569 pm_runtime_enable(&pdev->dev);
1570
1571 return 0;
1572
1573disable_ahb_clk:
1574 clk_disable_unprepare(imx_data->clk_ahb);
1575disable_ipg_clk:
1576 clk_disable_unprepare(imx_data->clk_ipg);
1577disable_per_clk:
1578 clk_disable_unprepare(imx_data->clk_per);
1579free_sdhci:
1580 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1581 pm_qos_remove_request(&imx_data->pm_qos_req);
1582 sdhci_pltfm_free(pdev);
1583 return err;
1584}
1585
1586static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1587{
1588 struct sdhci_host *host = platform_get_drvdata(pdev);
1589 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1590 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1591 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1592
1593 pm_runtime_get_sync(&pdev->dev);
1594 pm_runtime_disable(&pdev->dev);
1595 pm_runtime_put_noidle(&pdev->dev);
1596
1597 sdhci_remove_host(host, dead);
1598
1599 clk_disable_unprepare(imx_data->clk_per);
1600 clk_disable_unprepare(imx_data->clk_ipg);
1601 clk_disable_unprepare(imx_data->clk_ahb);
1602
1603 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1604 pm_qos_remove_request(&imx_data->pm_qos_req);
1605
1606 sdhci_pltfm_free(pdev);
1607
1608 return 0;
1609}
1610
1611#ifdef CONFIG_PM_SLEEP
1612static int sdhci_esdhc_suspend(struct device *dev)
1613{
1614 struct sdhci_host *host = dev_get_drvdata(dev);
1615 int ret;
1616
1617 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1618 ret = cqhci_suspend(host->mmc);
1619 if (ret)
1620 return ret;
1621 }
1622
1623 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1624 mmc_retune_needed(host->mmc);
1625
1626 return sdhci_suspend_host(host);
1627}
1628
1629static int sdhci_esdhc_resume(struct device *dev)
1630{
1631 struct sdhci_host *host = dev_get_drvdata(dev);
1632 int ret;
1633
1634 /* re-initialize hw state in case it's lost in low power mode */
1635 sdhci_esdhc_imx_hwinit(host);
1636
1637 ret = sdhci_resume_host(host);
1638 if (ret)
1639 return ret;
1640
1641 if (host->mmc->caps2 & MMC_CAP2_CQE)
1642 ret = cqhci_resume(host->mmc);
1643
1644 return ret;
1645}
1646#endif
1647
1648#ifdef CONFIG_PM
1649static int sdhci_esdhc_runtime_suspend(struct device *dev)
1650{
1651 struct sdhci_host *host = dev_get_drvdata(dev);
1652 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1653 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1654 int ret;
1655
1656 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1657 ret = cqhci_suspend(host->mmc);
1658 if (ret)
1659 return ret;
1660 }
1661
1662 ret = sdhci_runtime_suspend_host(host);
1663 if (ret)
1664 return ret;
1665
1666 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1667 mmc_retune_needed(host->mmc);
1668
1669 imx_data->actual_clock = host->mmc->actual_clock;
1670 esdhc_pltfm_set_clock(host, 0);
1671 clk_disable_unprepare(imx_data->clk_per);
1672 clk_disable_unprepare(imx_data->clk_ipg);
1673 clk_disable_unprepare(imx_data->clk_ahb);
1674
1675 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1676 pm_qos_remove_request(&imx_data->pm_qos_req);
1677
1678 return ret;
1679}
1680
1681static int sdhci_esdhc_runtime_resume(struct device *dev)
1682{
1683 struct sdhci_host *host = dev_get_drvdata(dev);
1684 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1685 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1686 int err;
1687
1688 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1689 pm_qos_add_request(&imx_data->pm_qos_req,
1690 PM_QOS_CPU_DMA_LATENCY, 0);
1691
1692 err = clk_prepare_enable(imx_data->clk_ahb);
1693 if (err)
1694 goto remove_pm_qos_request;
1695
1696 err = clk_prepare_enable(imx_data->clk_per);
1697 if (err)
1698 goto disable_ahb_clk;
1699
1700 err = clk_prepare_enable(imx_data->clk_ipg);
1701 if (err)
1702 goto disable_per_clk;
1703
1704 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1705
1706 err = sdhci_runtime_resume_host(host, 0);
1707 if (err)
1708 goto disable_ipg_clk;
1709
1710 if (host->mmc->caps2 & MMC_CAP2_CQE)
1711 err = cqhci_resume(host->mmc);
1712
1713 return err;
1714
1715disable_ipg_clk:
1716 clk_disable_unprepare(imx_data->clk_ipg);
1717disable_per_clk:
1718 clk_disable_unprepare(imx_data->clk_per);
1719disable_ahb_clk:
1720 clk_disable_unprepare(imx_data->clk_ahb);
1721remove_pm_qos_request:
1722 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1723 pm_qos_remove_request(&imx_data->pm_qos_req);
1724 return err;
1725}
1726#endif
1727
1728static const struct dev_pm_ops sdhci_esdhc_pmops = {
1729 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1730 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1731 sdhci_esdhc_runtime_resume, NULL)
1732};
1733
1734static struct platform_driver sdhci_esdhc_imx_driver = {
1735 .driver = {
1736 .name = "sdhci-esdhc-imx",
1737 .of_match_table = imx_esdhc_dt_ids,
1738 .pm = &sdhci_esdhc_pmops,
1739 },
1740 .id_table = imx_esdhc_devtype,
1741 .probe = sdhci_esdhc_imx_probe,
1742 .remove = sdhci_esdhc_imx_remove,
1743};
1744
1745module_platform_driver(sdhci_esdhc_imx_driver);
1746
1747MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1748MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1749MODULE_LICENSE("GPL v2");