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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Jerome Brunet <jbrunet@baylibre.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/irqchip.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#define NUM_CHANNEL 8
20#define MAX_INPUT_MUX 256
21
22#define REG_EDGE_POL 0x00
23#define REG_PIN_03_SEL 0x04
24#define REG_PIN_47_SEL 0x08
25#define REG_FILTER_SEL 0x0c
26
27/*
28 * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
29 * bits 24 to 31. Tests on the actual HW show that these bits are
30 * stuck at 0. Bits 8 to 15 are responsive and have the expected
31 * effect.
32 */
33#define REG_EDGE_POL_EDGE(x) BIT(x)
34#define REG_EDGE_POL_LOW(x) BIT(16 + (x))
35#define REG_BOTH_EDGE(x) BIT(8 + (x))
36#define REG_EDGE_POL_MASK(x) ( \
37 REG_EDGE_POL_EDGE(x) | \
38 REG_EDGE_POL_LOW(x) | \
39 REG_BOTH_EDGE(x))
40#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
41#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
42
43struct meson_gpio_irq_params {
44 unsigned int nr_hwirq;
45 bool support_edge_both;
46};
47
48static const struct meson_gpio_irq_params meson8_params = {
49 .nr_hwirq = 134,
50};
51
52static const struct meson_gpio_irq_params meson8b_params = {
53 .nr_hwirq = 119,
54};
55
56static const struct meson_gpio_irq_params gxbb_params = {
57 .nr_hwirq = 133,
58};
59
60static const struct meson_gpio_irq_params gxl_params = {
61 .nr_hwirq = 110,
62};
63
64static const struct meson_gpio_irq_params axg_params = {
65 .nr_hwirq = 100,
66};
67
68static const struct meson_gpio_irq_params sm1_params = {
69 .nr_hwirq = 100,
70 .support_edge_both = true,
71};
72
73static const struct of_device_id meson_irq_gpio_matches[] = {
74 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
75 { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
76 { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
77 { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
78 { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
79 { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
80 { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
81 { }
82};
83
84struct meson_gpio_irq_controller {
85 const struct meson_gpio_irq_params *params;
86 void __iomem *base;
87 u32 channel_irqs[NUM_CHANNEL];
88 DECLARE_BITMAP(channel_map, NUM_CHANNEL);
89 spinlock_t lock;
90};
91
92static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
93 unsigned int reg, u32 mask, u32 val)
94{
95 u32 tmp;
96
97 tmp = readl_relaxed(ctl->base + reg);
98 tmp &= ~mask;
99 tmp |= val;
100 writel_relaxed(tmp, ctl->base + reg);
101}
102
103static unsigned int meson_gpio_irq_channel_to_reg(unsigned int channel)
104{
105 return (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
106}
107
108static int
109meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
110 unsigned long hwirq,
111 u32 **channel_hwirq)
112{
113 unsigned int reg, idx;
114
115 spin_lock(&ctl->lock);
116
117 /* Find a free channel */
118 idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
119 if (idx >= NUM_CHANNEL) {
120 spin_unlock(&ctl->lock);
121 pr_err("No channel available\n");
122 return -ENOSPC;
123 }
124
125 /* Mark the channel as used */
126 set_bit(idx, ctl->channel_map);
127
128 /*
129 * Setup the mux of the channel to route the signal of the pad
130 * to the appropriate input of the GIC
131 */
132 reg = meson_gpio_irq_channel_to_reg(idx);
133 meson_gpio_irq_update_bits(ctl, reg,
134 0xff << REG_PIN_SEL_SHIFT(idx),
135 hwirq << REG_PIN_SEL_SHIFT(idx));
136
137 /*
138 * Get the hwirq number assigned to this channel through
139 * a pointer the channel_irq table. The added benifit of this
140 * method is that we can also retrieve the channel index with
141 * it, using the table base.
142 */
143 *channel_hwirq = &(ctl->channel_irqs[idx]);
144
145 spin_unlock(&ctl->lock);
146
147 pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
148 hwirq, idx, **channel_hwirq);
149
150 return 0;
151}
152
153static unsigned int
154meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
155 u32 *channel_hwirq)
156{
157 return channel_hwirq - ctl->channel_irqs;
158}
159
160static void
161meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
162 u32 *channel_hwirq)
163{
164 unsigned int idx;
165
166 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
167 clear_bit(idx, ctl->channel_map);
168}
169
170static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
171 unsigned int type,
172 u32 *channel_hwirq)
173{
174 u32 val = 0;
175 unsigned int idx;
176
177 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
178
179 /*
180 * The controller has a filter block to operate in either LEVEL or
181 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
182 * EDGE_FALLING support (which the GIC does not support), the filter
183 * block is also able to invert the input signal it gets before
184 * providing it to the GIC.
185 */
186 type &= IRQ_TYPE_SENSE_MASK;
187
188 /*
189 * New controller support EDGE_BOTH trigger. This setting takes
190 * precedence over the other edge/polarity settings
191 */
192 if (type == IRQ_TYPE_EDGE_BOTH) {
193 if (!ctl->params->support_edge_both)
194 return -EINVAL;
195
196 val |= REG_BOTH_EDGE(idx);
197 } else {
198 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
199 val |= REG_EDGE_POL_EDGE(idx);
200
201 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
202 val |= REG_EDGE_POL_LOW(idx);
203 }
204
205 spin_lock(&ctl->lock);
206
207 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
208 REG_EDGE_POL_MASK(idx), val);
209
210 spin_unlock(&ctl->lock);
211
212 return 0;
213}
214
215static unsigned int meson_gpio_irq_type_output(unsigned int type)
216{
217 unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
218
219 type &= ~IRQ_TYPE_SENSE_MASK;
220
221 /*
222 * The polarity of the signal provided to the GIC should always
223 * be high.
224 */
225 if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
226 type |= IRQ_TYPE_LEVEL_HIGH;
227 else
228 type |= IRQ_TYPE_EDGE_RISING;
229
230 return type;
231}
232
233static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
234{
235 struct meson_gpio_irq_controller *ctl = data->domain->host_data;
236 u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
237 int ret;
238
239 ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
240 if (ret)
241 return ret;
242
243 return irq_chip_set_type_parent(data,
244 meson_gpio_irq_type_output(type));
245}
246
247static struct irq_chip meson_gpio_irq_chip = {
248 .name = "meson-gpio-irqchip",
249 .irq_mask = irq_chip_mask_parent,
250 .irq_unmask = irq_chip_unmask_parent,
251 .irq_eoi = irq_chip_eoi_parent,
252 .irq_set_type = meson_gpio_irq_set_type,
253 .irq_retrigger = irq_chip_retrigger_hierarchy,
254#ifdef CONFIG_SMP
255 .irq_set_affinity = irq_chip_set_affinity_parent,
256#endif
257 .flags = IRQCHIP_SET_TYPE_MASKED,
258};
259
260static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
261 struct irq_fwspec *fwspec,
262 unsigned long *hwirq,
263 unsigned int *type)
264{
265 if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
266 *hwirq = fwspec->param[0];
267 *type = fwspec->param[1];
268 return 0;
269 }
270
271 return -EINVAL;
272}
273
274static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
275 unsigned int virq,
276 u32 hwirq,
277 unsigned int type)
278{
279 struct irq_fwspec fwspec;
280
281 fwspec.fwnode = domain->parent->fwnode;
282 fwspec.param_count = 3;
283 fwspec.param[0] = 0; /* SPI */
284 fwspec.param[1] = hwirq;
285 fwspec.param[2] = meson_gpio_irq_type_output(type);
286
287 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
288}
289
290static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
291 unsigned int virq,
292 unsigned int nr_irqs,
293 void *data)
294{
295 struct irq_fwspec *fwspec = data;
296 struct meson_gpio_irq_controller *ctl = domain->host_data;
297 unsigned long hwirq;
298 u32 *channel_hwirq;
299 unsigned int type;
300 int ret;
301
302 if (WARN_ON(nr_irqs != 1))
303 return -EINVAL;
304
305 ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
306 if (ret)
307 return ret;
308
309 ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
310 if (ret)
311 return ret;
312
313 ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
314 *channel_hwirq, type);
315 if (ret < 0) {
316 pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
317 meson_gpio_irq_release_channel(ctl, channel_hwirq);
318 return ret;
319 }
320
321 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
322 &meson_gpio_irq_chip, channel_hwirq);
323
324 return 0;
325}
326
327static void meson_gpio_irq_domain_free(struct irq_domain *domain,
328 unsigned int virq,
329 unsigned int nr_irqs)
330{
331 struct meson_gpio_irq_controller *ctl = domain->host_data;
332 struct irq_data *irq_data;
333 u32 *channel_hwirq;
334
335 if (WARN_ON(nr_irqs != 1))
336 return;
337
338 irq_domain_free_irqs_parent(domain, virq, 1);
339
340 irq_data = irq_domain_get_irq_data(domain, virq);
341 channel_hwirq = irq_data_get_irq_chip_data(irq_data);
342
343 meson_gpio_irq_release_channel(ctl, channel_hwirq);
344}
345
346static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
347 .alloc = meson_gpio_irq_domain_alloc,
348 .free = meson_gpio_irq_domain_free,
349 .translate = meson_gpio_irq_domain_translate,
350};
351
352static int __init meson_gpio_irq_parse_dt(struct device_node *node,
353 struct meson_gpio_irq_controller *ctl)
354{
355 const struct of_device_id *match;
356 int ret;
357
358 match = of_match_node(meson_irq_gpio_matches, node);
359 if (!match)
360 return -ENODEV;
361
362 ctl->params = match->data;
363
364 ret = of_property_read_variable_u32_array(node,
365 "amlogic,channel-interrupts",
366 ctl->channel_irqs,
367 NUM_CHANNEL,
368 NUM_CHANNEL);
369 if (ret < 0) {
370 pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
371 return ret;
372 }
373
374 return 0;
375}
376
377static int __init meson_gpio_irq_of_init(struct device_node *node,
378 struct device_node *parent)
379{
380 struct irq_domain *domain, *parent_domain;
381 struct meson_gpio_irq_controller *ctl;
382 int ret;
383
384 if (!parent) {
385 pr_err("missing parent interrupt node\n");
386 return -ENODEV;
387 }
388
389 parent_domain = irq_find_host(parent);
390 if (!parent_domain) {
391 pr_err("unable to obtain parent domain\n");
392 return -ENXIO;
393 }
394
395 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
396 if (!ctl)
397 return -ENOMEM;
398
399 spin_lock_init(&ctl->lock);
400
401 ctl->base = of_iomap(node, 0);
402 if (!ctl->base) {
403 ret = -ENOMEM;
404 goto free_ctl;
405 }
406
407 ret = meson_gpio_irq_parse_dt(node, ctl);
408 if (ret)
409 goto free_channel_irqs;
410
411 domain = irq_domain_create_hierarchy(parent_domain, 0,
412 ctl->params->nr_hwirq,
413 of_node_to_fwnode(node),
414 &meson_gpio_irq_domain_ops,
415 ctl);
416 if (!domain) {
417 pr_err("failed to add domain\n");
418 ret = -ENODEV;
419 goto free_channel_irqs;
420 }
421
422 pr_info("%d to %d gpio interrupt mux initialized\n",
423 ctl->params->nr_hwirq, NUM_CHANNEL);
424
425 return 0;
426
427free_channel_irqs:
428 iounmap(ctl->base);
429free_ctl:
430 kfree(ctl);
431
432 return ret;
433}
434
435IRQCHIP_DECLARE(meson_gpio_intc, "amlogic,meson-gpio-intc",
436 meson_gpio_irq_of_init);