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1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/* LCDC DRM driver, based on da8xx-fb */
19
20#include <linux/component.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/suspend.h>
23
24#include "tilcdc_drv.h"
25#include "tilcdc_regs.h"
26#include "tilcdc_tfp410.h"
27#include "tilcdc_panel.h"
28#include "tilcdc_external.h"
29
30#include "drm_fb_helper.h"
31
32static LIST_HEAD(module_list);
33
34void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
35 const struct tilcdc_module_ops *funcs)
36{
37 mod->name = name;
38 mod->funcs = funcs;
39 INIT_LIST_HEAD(&mod->list);
40 list_add(&mod->list, &module_list);
41}
42
43void tilcdc_module_cleanup(struct tilcdc_module *mod)
44{
45 list_del(&mod->list);
46}
47
48static struct of_device_id tilcdc_of_match[];
49
50static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
51 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
52{
53 return drm_fb_cma_create(dev, file_priv, mode_cmd);
54}
55
56static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
57{
58 struct tilcdc_drm_private *priv = dev->dev_private;
59 drm_fbdev_cma_hotplug_event(priv->fbdev);
60}
61
62static const struct drm_mode_config_funcs mode_config_funcs = {
63 .fb_create = tilcdc_fb_create,
64 .output_poll_changed = tilcdc_fb_output_poll_changed,
65};
66
67static int modeset_init(struct drm_device *dev)
68{
69 struct tilcdc_drm_private *priv = dev->dev_private;
70 struct tilcdc_module *mod;
71
72 drm_mode_config_init(dev);
73
74 priv->crtc = tilcdc_crtc_create(dev);
75
76 list_for_each_entry(mod, &module_list, list) {
77 DBG("loading module: %s", mod->name);
78 mod->funcs->modeset_init(mod, dev);
79 }
80
81 dev->mode_config.min_width = 0;
82 dev->mode_config.min_height = 0;
83 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
84 dev->mode_config.max_height = 2048;
85 dev->mode_config.funcs = &mode_config_funcs;
86
87 return 0;
88}
89
90#ifdef CONFIG_CPU_FREQ
91static int cpufreq_transition(struct notifier_block *nb,
92 unsigned long val, void *data)
93{
94 struct tilcdc_drm_private *priv = container_of(nb,
95 struct tilcdc_drm_private, freq_transition);
96 if (val == CPUFREQ_POSTCHANGE) {
97 if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
98 priv->lcd_fck_rate = clk_get_rate(priv->clk);
99 tilcdc_crtc_update_clk(priv->crtc);
100 }
101 }
102
103 return 0;
104}
105#endif
106
107/*
108 * DRM operations:
109 */
110
111static int tilcdc_unload(struct drm_device *dev)
112{
113 struct tilcdc_drm_private *priv = dev->dev_private;
114
115 tilcdc_crtc_dpms(priv->crtc, DRM_MODE_DPMS_OFF);
116
117 tilcdc_remove_external_encoders(dev);
118
119 drm_fbdev_cma_fini(priv->fbdev);
120 drm_kms_helper_poll_fini(dev);
121 drm_mode_config_cleanup(dev);
122 drm_vblank_cleanup(dev);
123
124 pm_runtime_get_sync(dev->dev);
125 drm_irq_uninstall(dev);
126 pm_runtime_put_sync(dev->dev);
127
128#ifdef CONFIG_CPU_FREQ
129 cpufreq_unregister_notifier(&priv->freq_transition,
130 CPUFREQ_TRANSITION_NOTIFIER);
131#endif
132
133 if (priv->clk)
134 clk_put(priv->clk);
135
136 if (priv->mmio)
137 iounmap(priv->mmio);
138
139 flush_workqueue(priv->wq);
140 destroy_workqueue(priv->wq);
141
142 dev->dev_private = NULL;
143
144 pm_runtime_disable(dev->dev);
145
146 return 0;
147}
148
149static size_t tilcdc_num_regs(void);
150
151static int tilcdc_load(struct drm_device *dev, unsigned long flags)
152{
153 struct platform_device *pdev = dev->platformdev;
154 struct device_node *node = pdev->dev.of_node;
155 struct tilcdc_drm_private *priv;
156 struct tilcdc_module *mod;
157 struct resource *res;
158 u32 bpp = 0;
159 int ret;
160
161 priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
162 if (priv)
163 priv->saved_register =
164 devm_kcalloc(dev->dev, tilcdc_num_regs(),
165 sizeof(*priv->saved_register), GFP_KERNEL);
166 if (!priv || !priv->saved_register) {
167 dev_err(dev->dev, "failed to allocate private data\n");
168 return -ENOMEM;
169 }
170
171 dev->dev_private = priv;
172
173 priv->is_componentized =
174 tilcdc_get_external_components(dev->dev, NULL) > 0;
175
176 priv->wq = alloc_ordered_workqueue("tilcdc", 0);
177 if (!priv->wq) {
178 ret = -ENOMEM;
179 goto fail_unset_priv;
180 }
181
182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
183 if (!res) {
184 dev_err(dev->dev, "failed to get memory resource\n");
185 ret = -EINVAL;
186 goto fail_free_wq;
187 }
188
189 priv->mmio = ioremap_nocache(res->start, resource_size(res));
190 if (!priv->mmio) {
191 dev_err(dev->dev, "failed to ioremap\n");
192 ret = -ENOMEM;
193 goto fail_free_wq;
194 }
195
196 priv->clk = clk_get(dev->dev, "fck");
197 if (IS_ERR(priv->clk)) {
198 dev_err(dev->dev, "failed to get functional clock\n");
199 ret = -ENODEV;
200 goto fail_iounmap;
201 }
202
203#ifdef CONFIG_CPU_FREQ
204 priv->lcd_fck_rate = clk_get_rate(priv->clk);
205 priv->freq_transition.notifier_call = cpufreq_transition;
206 ret = cpufreq_register_notifier(&priv->freq_transition,
207 CPUFREQ_TRANSITION_NOTIFIER);
208 if (ret) {
209 dev_err(dev->dev, "failed to register cpufreq notifier\n");
210 goto fail_put_clk;
211 }
212#endif
213
214 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
215 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
216
217 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
218
219 if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
220 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
221
222 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
223
224 if (of_property_read_u32(node, "ti,max-pixelclock",
225 &priv->max_pixelclock))
226 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
227
228 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
229
230 pm_runtime_enable(dev->dev);
231
232 /* Determine LCD IP Version */
233 pm_runtime_get_sync(dev->dev);
234 switch (tilcdc_read(dev, LCDC_PID_REG)) {
235 case 0x4c100102:
236 priv->rev = 1;
237 break;
238 case 0x4f200800:
239 case 0x4f201000:
240 priv->rev = 2;
241 break;
242 default:
243 dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
244 "defaulting to LCD revision 1\n",
245 tilcdc_read(dev, LCDC_PID_REG));
246 priv->rev = 1;
247 break;
248 }
249
250 pm_runtime_put_sync(dev->dev);
251
252 ret = modeset_init(dev);
253 if (ret < 0) {
254 dev_err(dev->dev, "failed to initialize mode setting\n");
255 goto fail_cpufreq_unregister;
256 }
257
258 platform_set_drvdata(pdev, dev);
259
260 if (priv->is_componentized) {
261 ret = component_bind_all(dev->dev, dev);
262 if (ret < 0)
263 goto fail_mode_config_cleanup;
264
265 ret = tilcdc_add_external_encoders(dev, &bpp);
266 if (ret < 0)
267 goto fail_component_cleanup;
268 }
269
270 if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
271 dev_err(dev->dev, "no encoders/connectors found\n");
272 ret = -ENXIO;
273 goto fail_external_cleanup;
274 }
275
276 ret = drm_vblank_init(dev, 1);
277 if (ret < 0) {
278 dev_err(dev->dev, "failed to initialize vblank\n");
279 goto fail_external_cleanup;
280 }
281
282 pm_runtime_get_sync(dev->dev);
283 ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
284 pm_runtime_put_sync(dev->dev);
285 if (ret < 0) {
286 dev_err(dev->dev, "failed to install IRQ handler\n");
287 goto fail_vblank_cleanup;
288 }
289
290 list_for_each_entry(mod, &module_list, list) {
291 DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
292 bpp = mod->preferred_bpp;
293 if (bpp > 0)
294 break;
295 }
296
297 drm_helper_disable_unused_functions(dev);
298 priv->fbdev = drm_fbdev_cma_init(dev, bpp,
299 dev->mode_config.num_crtc,
300 dev->mode_config.num_connector);
301 if (IS_ERR(priv->fbdev)) {
302 ret = PTR_ERR(priv->fbdev);
303 goto fail_irq_uninstall;
304 }
305
306 drm_kms_helper_poll_init(dev);
307
308 return 0;
309
310fail_irq_uninstall:
311 pm_runtime_get_sync(dev->dev);
312 drm_irq_uninstall(dev);
313 pm_runtime_put_sync(dev->dev);
314
315fail_vblank_cleanup:
316 drm_vblank_cleanup(dev);
317
318fail_mode_config_cleanup:
319 drm_mode_config_cleanup(dev);
320
321fail_component_cleanup:
322 if (priv->is_componentized)
323 component_unbind_all(dev->dev, dev);
324
325fail_external_cleanup:
326 tilcdc_remove_external_encoders(dev);
327
328fail_cpufreq_unregister:
329 pm_runtime_disable(dev->dev);
330#ifdef CONFIG_CPU_FREQ
331 cpufreq_unregister_notifier(&priv->freq_transition,
332 CPUFREQ_TRANSITION_NOTIFIER);
333
334fail_put_clk:
335#endif
336 clk_put(priv->clk);
337
338fail_iounmap:
339 iounmap(priv->mmio);
340
341fail_free_wq:
342 flush_workqueue(priv->wq);
343 destroy_workqueue(priv->wq);
344
345fail_unset_priv:
346 dev->dev_private = NULL;
347
348 return ret;
349}
350
351static void tilcdc_lastclose(struct drm_device *dev)
352{
353 struct tilcdc_drm_private *priv = dev->dev_private;
354 drm_fbdev_cma_restore_mode(priv->fbdev);
355}
356
357static irqreturn_t tilcdc_irq(int irq, void *arg)
358{
359 struct drm_device *dev = arg;
360 struct tilcdc_drm_private *priv = dev->dev_private;
361 return tilcdc_crtc_irq(priv->crtc);
362}
363
364static void tilcdc_irq_preinstall(struct drm_device *dev)
365{
366 tilcdc_clear_irqstatus(dev, 0xffffffff);
367}
368
369static int tilcdc_irq_postinstall(struct drm_device *dev)
370{
371 struct tilcdc_drm_private *priv = dev->dev_private;
372
373 /* enable FIFO underflow irq: */
374 if (priv->rev == 1) {
375 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
376 } else {
377 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
378 LCDC_V2_UNDERFLOW_INT_ENA |
379 LCDC_V2_END_OF_FRAME0_INT_ENA |
380 LCDC_FRAME_DONE | LCDC_SYNC_LOST);
381 }
382
383 return 0;
384}
385
386static void tilcdc_irq_uninstall(struct drm_device *dev)
387{
388 struct tilcdc_drm_private *priv = dev->dev_private;
389
390 /* disable irqs that we might have enabled: */
391 if (priv->rev == 1) {
392 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
393 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
394 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
395 } else {
396 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
397 LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
398 LCDC_V2_END_OF_FRAME0_INT_ENA |
399 LCDC_FRAME_DONE | LCDC_SYNC_LOST);
400 }
401}
402
403static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
404{
405 return 0;
406}
407
408static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
409{
410 return;
411}
412
413#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
414static const struct {
415 const char *name;
416 uint8_t rev;
417 uint8_t save;
418 uint32_t reg;
419} registers[] = {
420#define REG(rev, save, reg) { #reg, rev, save, reg }
421 /* exists in revision 1: */
422 REG(1, false, LCDC_PID_REG),
423 REG(1, true, LCDC_CTRL_REG),
424 REG(1, false, LCDC_STAT_REG),
425 REG(1, true, LCDC_RASTER_CTRL_REG),
426 REG(1, true, LCDC_RASTER_TIMING_0_REG),
427 REG(1, true, LCDC_RASTER_TIMING_1_REG),
428 REG(1, true, LCDC_RASTER_TIMING_2_REG),
429 REG(1, true, LCDC_DMA_CTRL_REG),
430 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
431 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
432 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
433 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
434 /* new in revision 2: */
435 REG(2, false, LCDC_RAW_STAT_REG),
436 REG(2, false, LCDC_MASKED_STAT_REG),
437 REG(2, true, LCDC_INT_ENABLE_SET_REG),
438 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
439 REG(2, false, LCDC_END_OF_INT_IND_REG),
440 REG(2, true, LCDC_CLK_ENABLE_REG),
441#undef REG
442};
443
444static size_t tilcdc_num_regs(void)
445{
446 return ARRAY_SIZE(registers);
447}
448#else
449static size_t tilcdc_num_regs(void)
450{
451 return 0;
452}
453#endif
454
455#ifdef CONFIG_DEBUG_FS
456static int tilcdc_regs_show(struct seq_file *m, void *arg)
457{
458 struct drm_info_node *node = (struct drm_info_node *) m->private;
459 struct drm_device *dev = node->minor->dev;
460 struct tilcdc_drm_private *priv = dev->dev_private;
461 unsigned i;
462
463 pm_runtime_get_sync(dev->dev);
464
465 seq_printf(m, "revision: %d\n", priv->rev);
466
467 for (i = 0; i < ARRAY_SIZE(registers); i++)
468 if (priv->rev >= registers[i].rev)
469 seq_printf(m, "%s:\t %08x\n", registers[i].name,
470 tilcdc_read(dev, registers[i].reg));
471
472 pm_runtime_put_sync(dev->dev);
473
474 return 0;
475}
476
477static int tilcdc_mm_show(struct seq_file *m, void *arg)
478{
479 struct drm_info_node *node = (struct drm_info_node *) m->private;
480 struct drm_device *dev = node->minor->dev;
481 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
482}
483
484static struct drm_info_list tilcdc_debugfs_list[] = {
485 { "regs", tilcdc_regs_show, 0 },
486 { "mm", tilcdc_mm_show, 0 },
487 { "fb", drm_fb_cma_debugfs_show, 0 },
488};
489
490static int tilcdc_debugfs_init(struct drm_minor *minor)
491{
492 struct drm_device *dev = minor->dev;
493 struct tilcdc_module *mod;
494 int ret;
495
496 ret = drm_debugfs_create_files(tilcdc_debugfs_list,
497 ARRAY_SIZE(tilcdc_debugfs_list),
498 minor->debugfs_root, minor);
499
500 list_for_each_entry(mod, &module_list, list)
501 if (mod->funcs->debugfs_init)
502 mod->funcs->debugfs_init(mod, minor);
503
504 if (ret) {
505 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
506 return ret;
507 }
508
509 return ret;
510}
511
512static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
513{
514 struct tilcdc_module *mod;
515 drm_debugfs_remove_files(tilcdc_debugfs_list,
516 ARRAY_SIZE(tilcdc_debugfs_list), minor);
517
518 list_for_each_entry(mod, &module_list, list)
519 if (mod->funcs->debugfs_cleanup)
520 mod->funcs->debugfs_cleanup(mod, minor);
521}
522#endif
523
524static const struct file_operations fops = {
525 .owner = THIS_MODULE,
526 .open = drm_open,
527 .release = drm_release,
528 .unlocked_ioctl = drm_ioctl,
529#ifdef CONFIG_COMPAT
530 .compat_ioctl = drm_compat_ioctl,
531#endif
532 .poll = drm_poll,
533 .read = drm_read,
534 .llseek = no_llseek,
535 .mmap = drm_gem_cma_mmap,
536};
537
538static struct drm_driver tilcdc_driver = {
539 .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
540 DRIVER_PRIME),
541 .load = tilcdc_load,
542 .unload = tilcdc_unload,
543 .lastclose = tilcdc_lastclose,
544 .set_busid = drm_platform_set_busid,
545 .irq_handler = tilcdc_irq,
546 .irq_preinstall = tilcdc_irq_preinstall,
547 .irq_postinstall = tilcdc_irq_postinstall,
548 .irq_uninstall = tilcdc_irq_uninstall,
549 .get_vblank_counter = drm_vblank_no_hw_counter,
550 .enable_vblank = tilcdc_enable_vblank,
551 .disable_vblank = tilcdc_disable_vblank,
552 .gem_free_object = drm_gem_cma_free_object,
553 .gem_vm_ops = &drm_gem_cma_vm_ops,
554 .dumb_create = drm_gem_cma_dumb_create,
555 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
556 .dumb_destroy = drm_gem_dumb_destroy,
557
558 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
559 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
560 .gem_prime_import = drm_gem_prime_import,
561 .gem_prime_export = drm_gem_prime_export,
562 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
563 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
564 .gem_prime_vmap = drm_gem_cma_prime_vmap,
565 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
566 .gem_prime_mmap = drm_gem_cma_prime_mmap,
567#ifdef CONFIG_DEBUG_FS
568 .debugfs_init = tilcdc_debugfs_init,
569 .debugfs_cleanup = tilcdc_debugfs_cleanup,
570#endif
571 .fops = &fops,
572 .name = "tilcdc",
573 .desc = "TI LCD Controller DRM",
574 .date = "20121205",
575 .major = 1,
576 .minor = 0,
577};
578
579/*
580 * Power management:
581 */
582
583#ifdef CONFIG_PM_SLEEP
584static int tilcdc_pm_suspend(struct device *dev)
585{
586 struct drm_device *ddev = dev_get_drvdata(dev);
587 struct tilcdc_drm_private *priv = ddev->dev_private;
588 unsigned i, n = 0;
589
590 drm_kms_helper_poll_disable(ddev);
591
592 /* Select sleep pin state */
593 pinctrl_pm_select_sleep_state(dev);
594
595 if (pm_runtime_suspended(dev)) {
596 priv->ctx_valid = false;
597 return 0;
598 }
599
600 /* Disable the LCDC controller, to avoid locking up the PRCM */
601 tilcdc_crtc_dpms(priv->crtc, DRM_MODE_DPMS_OFF);
602
603 /* Save register state: */
604 for (i = 0; i < ARRAY_SIZE(registers); i++)
605 if (registers[i].save && (priv->rev >= registers[i].rev))
606 priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
607
608 priv->ctx_valid = true;
609
610 return 0;
611}
612
613static int tilcdc_pm_resume(struct device *dev)
614{
615 struct drm_device *ddev = dev_get_drvdata(dev);
616 struct tilcdc_drm_private *priv = ddev->dev_private;
617 unsigned i, n = 0;
618
619 /* Select default pin state */
620 pinctrl_pm_select_default_state(dev);
621
622 if (priv->ctx_valid == true) {
623 /* Restore register state: */
624 for (i = 0; i < ARRAY_SIZE(registers); i++)
625 if (registers[i].save &&
626 (priv->rev >= registers[i].rev))
627 tilcdc_write(ddev, registers[i].reg,
628 priv->saved_register[n++]);
629 }
630
631 drm_kms_helper_poll_enable(ddev);
632
633 return 0;
634}
635#endif
636
637static const struct dev_pm_ops tilcdc_pm_ops = {
638 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
639};
640
641/*
642 * Platform driver:
643 */
644
645static int tilcdc_bind(struct device *dev)
646{
647 return drm_platform_init(&tilcdc_driver, to_platform_device(dev));
648}
649
650static void tilcdc_unbind(struct device *dev)
651{
652 drm_put_dev(dev_get_drvdata(dev));
653}
654
655static const struct component_master_ops tilcdc_comp_ops = {
656 .bind = tilcdc_bind,
657 .unbind = tilcdc_unbind,
658};
659
660static int tilcdc_pdev_probe(struct platform_device *pdev)
661{
662 struct component_match *match = NULL;
663 int ret;
664
665 /* bail out early if no DT data: */
666 if (!pdev->dev.of_node) {
667 dev_err(&pdev->dev, "device-tree data is missing\n");
668 return -ENXIO;
669 }
670
671 ret = tilcdc_get_external_components(&pdev->dev, &match);
672 if (ret < 0)
673 return ret;
674 else if (ret == 0)
675 return drm_platform_init(&tilcdc_driver, pdev);
676 else
677 return component_master_add_with_match(&pdev->dev,
678 &tilcdc_comp_ops,
679 match);
680}
681
682static int tilcdc_pdev_remove(struct platform_device *pdev)
683{
684 struct drm_device *ddev = dev_get_drvdata(&pdev->dev);
685 struct tilcdc_drm_private *priv = ddev->dev_private;
686
687 /* Check if a subcomponent has already triggered the unloading. */
688 if (!priv)
689 return 0;
690
691 if (priv->is_componentized)
692 component_master_del(&pdev->dev, &tilcdc_comp_ops);
693 else
694 drm_put_dev(platform_get_drvdata(pdev));
695
696 return 0;
697}
698
699static struct of_device_id tilcdc_of_match[] = {
700 { .compatible = "ti,am33xx-tilcdc", },
701 { },
702};
703MODULE_DEVICE_TABLE(of, tilcdc_of_match);
704
705static struct platform_driver tilcdc_platform_driver = {
706 .probe = tilcdc_pdev_probe,
707 .remove = tilcdc_pdev_remove,
708 .driver = {
709 .name = "tilcdc",
710 .pm = &tilcdc_pm_ops,
711 .of_match_table = tilcdc_of_match,
712 },
713};
714
715static int __init tilcdc_drm_init(void)
716{
717 DBG("init");
718 tilcdc_tfp410_init();
719 tilcdc_panel_init();
720 return platform_driver_register(&tilcdc_platform_driver);
721}
722
723static void __exit tilcdc_drm_fini(void)
724{
725 DBG("fini");
726 platform_driver_unregister(&tilcdc_platform_driver);
727 tilcdc_panel_fini();
728 tilcdc_tfp410_fini();
729}
730
731module_init(tilcdc_drm_init);
732module_exit(tilcdc_drm_fini);
733
734MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
735MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
736MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7/* LCDC DRM driver, based on da8xx-fb */
8
9#include <linux/component.h>
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/pinctrl/consumer.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_debugfs.h>
18#include <drm/drm_drv.h>
19#include <drm/drm_fb_helper.h>
20#include <drm/drm_fourcc.h>
21#include <drm/drm_gem_cma_helper.h>
22#include <drm/drm_gem_framebuffer_helper.h>
23#include <drm/drm_irq.h>
24#include <drm/drm_mm.h>
25#include <drm/drm_probe_helper.h>
26#include <drm/drm_vblank.h>
27
28
29#include "tilcdc_drv.h"
30#include "tilcdc_external.h"
31#include "tilcdc_panel.h"
32#include "tilcdc_regs.h"
33#include "tilcdc_tfp410.h"
34
35static LIST_HEAD(module_list);
36
37static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
38
39static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
40 DRM_FORMAT_BGR888,
41 DRM_FORMAT_XBGR8888 };
42
43static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
44 DRM_FORMAT_RGB888,
45 DRM_FORMAT_XRGB8888 };
46
47static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
48 DRM_FORMAT_RGB888,
49 DRM_FORMAT_XRGB8888 };
50
51void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
52 const struct tilcdc_module_ops *funcs)
53{
54 mod->name = name;
55 mod->funcs = funcs;
56 INIT_LIST_HEAD(&mod->list);
57 list_add(&mod->list, &module_list);
58}
59
60void tilcdc_module_cleanup(struct tilcdc_module *mod)
61{
62 list_del(&mod->list);
63}
64
65static struct of_device_id tilcdc_of_match[];
66
67static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
68 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
69{
70 return drm_gem_fb_create(dev, file_priv, mode_cmd);
71}
72
73static int tilcdc_atomic_check(struct drm_device *dev,
74 struct drm_atomic_state *state)
75{
76 int ret;
77
78 ret = drm_atomic_helper_check_modeset(dev, state);
79 if (ret)
80 return ret;
81
82 ret = drm_atomic_helper_check_planes(dev, state);
83 if (ret)
84 return ret;
85
86 /*
87 * tilcdc ->atomic_check can update ->mode_changed if pixel format
88 * changes, hence will we check modeset changes again.
89 */
90 ret = drm_atomic_helper_check_modeset(dev, state);
91 if (ret)
92 return ret;
93
94 return ret;
95}
96
97static int tilcdc_commit(struct drm_device *dev,
98 struct drm_atomic_state *state,
99 bool async)
100{
101 int ret;
102
103 ret = drm_atomic_helper_prepare_planes(dev, state);
104 if (ret)
105 return ret;
106
107 ret = drm_atomic_helper_swap_state(state, true);
108 if (ret) {
109 drm_atomic_helper_cleanup_planes(dev, state);
110 return ret;
111 }
112
113 /*
114 * Everything below can be run asynchronously without the need to grab
115 * any modeset locks at all under one condition: It must be guaranteed
116 * that the asynchronous work has either been cancelled (if the driver
117 * supports it, which at least requires that the framebuffers get
118 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
119 * before the new state gets committed on the software side with
120 * drm_atomic_helper_swap_state().
121 *
122 * This scheme allows new atomic state updates to be prepared and
123 * checked in parallel to the asynchronous completion of the previous
124 * update. Which is important since compositors need to figure out the
125 * composition of the next frame right after having submitted the
126 * current layout.
127 */
128
129 drm_atomic_helper_commit_modeset_disables(dev, state);
130
131 drm_atomic_helper_commit_planes(dev, state, 0);
132
133 drm_atomic_helper_commit_modeset_enables(dev, state);
134
135 drm_atomic_helper_wait_for_vblanks(dev, state);
136
137 drm_atomic_helper_cleanup_planes(dev, state);
138
139 return 0;
140}
141
142static const struct drm_mode_config_funcs mode_config_funcs = {
143 .fb_create = tilcdc_fb_create,
144 .atomic_check = tilcdc_atomic_check,
145 .atomic_commit = tilcdc_commit,
146};
147
148static void modeset_init(struct drm_device *dev)
149{
150 struct tilcdc_drm_private *priv = dev->dev_private;
151 struct tilcdc_module *mod;
152
153 list_for_each_entry(mod, &module_list, list) {
154 DBG("loading module: %s", mod->name);
155 mod->funcs->modeset_init(mod, dev);
156 }
157
158 dev->mode_config.min_width = 0;
159 dev->mode_config.min_height = 0;
160 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
161 dev->mode_config.max_height = 2048;
162 dev->mode_config.funcs = &mode_config_funcs;
163}
164
165#ifdef CONFIG_CPU_FREQ
166static int cpufreq_transition(struct notifier_block *nb,
167 unsigned long val, void *data)
168{
169 struct tilcdc_drm_private *priv = container_of(nb,
170 struct tilcdc_drm_private, freq_transition);
171
172 if (val == CPUFREQ_POSTCHANGE)
173 tilcdc_crtc_update_clk(priv->crtc);
174
175 return 0;
176}
177#endif
178
179/*
180 * DRM operations:
181 */
182
183static void tilcdc_fini(struct drm_device *dev)
184{
185 struct tilcdc_drm_private *priv = dev->dev_private;
186
187#ifdef CONFIG_CPU_FREQ
188 if (priv->freq_transition.notifier_call)
189 cpufreq_unregister_notifier(&priv->freq_transition,
190 CPUFREQ_TRANSITION_NOTIFIER);
191#endif
192
193 if (priv->crtc)
194 tilcdc_crtc_shutdown(priv->crtc);
195
196 if (priv->is_registered)
197 drm_dev_unregister(dev);
198
199 drm_kms_helper_poll_fini(dev);
200 drm_irq_uninstall(dev);
201 drm_mode_config_cleanup(dev);
202
203 if (priv->clk)
204 clk_put(priv->clk);
205
206 if (priv->mmio)
207 iounmap(priv->mmio);
208
209 if (priv->wq) {
210 flush_workqueue(priv->wq);
211 destroy_workqueue(priv->wq);
212 }
213
214 dev->dev_private = NULL;
215
216 pm_runtime_disable(dev->dev);
217
218 drm_dev_put(dev);
219}
220
221static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
222{
223 struct drm_device *ddev;
224 struct platform_device *pdev = to_platform_device(dev);
225 struct device_node *node = dev->of_node;
226 struct tilcdc_drm_private *priv;
227 struct resource *res;
228 u32 bpp = 0;
229 int ret;
230
231 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
232 if (!priv)
233 return -ENOMEM;
234
235 ddev = drm_dev_alloc(ddrv, dev);
236 if (IS_ERR(ddev))
237 return PTR_ERR(ddev);
238
239 ddev->dev_private = priv;
240 platform_set_drvdata(pdev, ddev);
241 drm_mode_config_init(ddev);
242
243 priv->is_componentized =
244 tilcdc_get_external_components(dev, NULL) > 0;
245
246 priv->wq = alloc_ordered_workqueue("tilcdc", 0);
247 if (!priv->wq) {
248 ret = -ENOMEM;
249 goto init_failed;
250 }
251
252 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
253 if (!res) {
254 dev_err(dev, "failed to get memory resource\n");
255 ret = -EINVAL;
256 goto init_failed;
257 }
258
259 priv->mmio = ioremap_nocache(res->start, resource_size(res));
260 if (!priv->mmio) {
261 dev_err(dev, "failed to ioremap\n");
262 ret = -ENOMEM;
263 goto init_failed;
264 }
265
266 priv->clk = clk_get(dev, "fck");
267 if (IS_ERR(priv->clk)) {
268 dev_err(dev, "failed to get functional clock\n");
269 ret = -ENODEV;
270 goto init_failed;
271 }
272
273 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
274 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
275
276 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
277
278 if (of_property_read_u32(node, "max-width", &priv->max_width))
279 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
280
281 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
282
283 if (of_property_read_u32(node, "max-pixelclock",
284 &priv->max_pixelclock))
285 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
286
287 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
288
289 pm_runtime_enable(dev);
290
291 /* Determine LCD IP Version */
292 pm_runtime_get_sync(dev);
293 switch (tilcdc_read(ddev, LCDC_PID_REG)) {
294 case 0x4c100102:
295 priv->rev = 1;
296 break;
297 case 0x4f200800:
298 case 0x4f201000:
299 priv->rev = 2;
300 break;
301 default:
302 dev_warn(dev, "Unknown PID Reg value 0x%08x, "
303 "defaulting to LCD revision 1\n",
304 tilcdc_read(ddev, LCDC_PID_REG));
305 priv->rev = 1;
306 break;
307 }
308
309 pm_runtime_put_sync(dev);
310
311 if (priv->rev == 1) {
312 DBG("Revision 1 LCDC supports only RGB565 format");
313 priv->pixelformats = tilcdc_rev1_formats;
314 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
315 bpp = 16;
316 } else {
317 const char *str = "\0";
318
319 of_property_read_string(node, "blue-and-red-wiring", &str);
320 if (0 == strcmp(str, "crossed")) {
321 DBG("Configured for crossed blue and red wires");
322 priv->pixelformats = tilcdc_crossed_formats;
323 priv->num_pixelformats =
324 ARRAY_SIZE(tilcdc_crossed_formats);
325 bpp = 32; /* Choose bpp with RGB support for fbdef */
326 } else if (0 == strcmp(str, "straight")) {
327 DBG("Configured for straight blue and red wires");
328 priv->pixelformats = tilcdc_straight_formats;
329 priv->num_pixelformats =
330 ARRAY_SIZE(tilcdc_straight_formats);
331 bpp = 16; /* Choose bpp with RGB support for fbdef */
332 } else {
333 DBG("Blue and red wiring '%s' unknown, use legacy mode",
334 str);
335 priv->pixelformats = tilcdc_legacy_formats;
336 priv->num_pixelformats =
337 ARRAY_SIZE(tilcdc_legacy_formats);
338 bpp = 16; /* This is just a guess */
339 }
340 }
341
342 ret = tilcdc_crtc_create(ddev);
343 if (ret < 0) {
344 dev_err(dev, "failed to create crtc\n");
345 goto init_failed;
346 }
347 modeset_init(ddev);
348
349#ifdef CONFIG_CPU_FREQ
350 priv->freq_transition.notifier_call = cpufreq_transition;
351 ret = cpufreq_register_notifier(&priv->freq_transition,
352 CPUFREQ_TRANSITION_NOTIFIER);
353 if (ret) {
354 dev_err(dev, "failed to register cpufreq notifier\n");
355 priv->freq_transition.notifier_call = NULL;
356 goto init_failed;
357 }
358#endif
359
360 if (priv->is_componentized) {
361 ret = component_bind_all(dev, ddev);
362 if (ret < 0)
363 goto init_failed;
364
365 ret = tilcdc_add_component_encoder(ddev);
366 if (ret < 0)
367 goto init_failed;
368 } else {
369 ret = tilcdc_attach_external_device(ddev);
370 if (ret)
371 goto init_failed;
372 }
373
374 if (!priv->external_connector &&
375 ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
376 dev_err(dev, "no encoders/connectors found\n");
377 ret = -EPROBE_DEFER;
378 goto init_failed;
379 }
380
381 ret = drm_vblank_init(ddev, 1);
382 if (ret < 0) {
383 dev_err(dev, "failed to initialize vblank\n");
384 goto init_failed;
385 }
386
387 ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
388 if (ret < 0) {
389 dev_err(dev, "failed to install IRQ handler\n");
390 goto init_failed;
391 }
392
393 drm_mode_config_reset(ddev);
394
395 drm_kms_helper_poll_init(ddev);
396
397 ret = drm_dev_register(ddev, 0);
398 if (ret)
399 goto init_failed;
400
401 drm_fbdev_generic_setup(ddev, bpp);
402
403 priv->is_registered = true;
404 return 0;
405
406init_failed:
407 tilcdc_fini(ddev);
408
409 return ret;
410}
411
412static irqreturn_t tilcdc_irq(int irq, void *arg)
413{
414 struct drm_device *dev = arg;
415 struct tilcdc_drm_private *priv = dev->dev_private;
416 return tilcdc_crtc_irq(priv->crtc);
417}
418
419#if defined(CONFIG_DEBUG_FS)
420static const struct {
421 const char *name;
422 uint8_t rev;
423 uint8_t save;
424 uint32_t reg;
425} registers[] = {
426#define REG(rev, save, reg) { #reg, rev, save, reg }
427 /* exists in revision 1: */
428 REG(1, false, LCDC_PID_REG),
429 REG(1, true, LCDC_CTRL_REG),
430 REG(1, false, LCDC_STAT_REG),
431 REG(1, true, LCDC_RASTER_CTRL_REG),
432 REG(1, true, LCDC_RASTER_TIMING_0_REG),
433 REG(1, true, LCDC_RASTER_TIMING_1_REG),
434 REG(1, true, LCDC_RASTER_TIMING_2_REG),
435 REG(1, true, LCDC_DMA_CTRL_REG),
436 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
437 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
438 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
439 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
440 /* new in revision 2: */
441 REG(2, false, LCDC_RAW_STAT_REG),
442 REG(2, false, LCDC_MASKED_STAT_REG),
443 REG(2, true, LCDC_INT_ENABLE_SET_REG),
444 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
445 REG(2, false, LCDC_END_OF_INT_IND_REG),
446 REG(2, true, LCDC_CLK_ENABLE_REG),
447#undef REG
448};
449
450#endif
451
452#ifdef CONFIG_DEBUG_FS
453static int tilcdc_regs_show(struct seq_file *m, void *arg)
454{
455 struct drm_info_node *node = (struct drm_info_node *) m->private;
456 struct drm_device *dev = node->minor->dev;
457 struct tilcdc_drm_private *priv = dev->dev_private;
458 unsigned i;
459
460 pm_runtime_get_sync(dev->dev);
461
462 seq_printf(m, "revision: %d\n", priv->rev);
463
464 for (i = 0; i < ARRAY_SIZE(registers); i++)
465 if (priv->rev >= registers[i].rev)
466 seq_printf(m, "%s:\t %08x\n", registers[i].name,
467 tilcdc_read(dev, registers[i].reg));
468
469 pm_runtime_put_sync(dev->dev);
470
471 return 0;
472}
473
474static int tilcdc_mm_show(struct seq_file *m, void *arg)
475{
476 struct drm_info_node *node = (struct drm_info_node *) m->private;
477 struct drm_device *dev = node->minor->dev;
478 struct drm_printer p = drm_seq_file_printer(m);
479 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
480 return 0;
481}
482
483static struct drm_info_list tilcdc_debugfs_list[] = {
484 { "regs", tilcdc_regs_show, 0 },
485 { "mm", tilcdc_mm_show, 0 },
486};
487
488static int tilcdc_debugfs_init(struct drm_minor *minor)
489{
490 struct drm_device *dev = minor->dev;
491 struct tilcdc_module *mod;
492 int ret;
493
494 ret = drm_debugfs_create_files(tilcdc_debugfs_list,
495 ARRAY_SIZE(tilcdc_debugfs_list),
496 minor->debugfs_root, minor);
497
498 list_for_each_entry(mod, &module_list, list)
499 if (mod->funcs->debugfs_init)
500 mod->funcs->debugfs_init(mod, minor);
501
502 if (ret) {
503 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
504 return ret;
505 }
506
507 return ret;
508}
509#endif
510
511DEFINE_DRM_GEM_CMA_FOPS(fops);
512
513static struct drm_driver tilcdc_driver = {
514 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
515 .irq_handler = tilcdc_irq,
516 .gem_free_object_unlocked = drm_gem_cma_free_object,
517 .gem_print_info = drm_gem_cma_print_info,
518 .gem_vm_ops = &drm_gem_cma_vm_ops,
519 .dumb_create = drm_gem_cma_dumb_create,
520
521 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
522 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
523 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
524 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
525 .gem_prime_vmap = drm_gem_cma_prime_vmap,
526 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
527 .gem_prime_mmap = drm_gem_cma_prime_mmap,
528#ifdef CONFIG_DEBUG_FS
529 .debugfs_init = tilcdc_debugfs_init,
530#endif
531 .fops = &fops,
532 .name = "tilcdc",
533 .desc = "TI LCD Controller DRM",
534 .date = "20121205",
535 .major = 1,
536 .minor = 0,
537};
538
539/*
540 * Power management:
541 */
542
543#ifdef CONFIG_PM_SLEEP
544static int tilcdc_pm_suspend(struct device *dev)
545{
546 struct drm_device *ddev = dev_get_drvdata(dev);
547 int ret = 0;
548
549 ret = drm_mode_config_helper_suspend(ddev);
550
551 /* Select sleep pin state */
552 pinctrl_pm_select_sleep_state(dev);
553
554 return ret;
555}
556
557static int tilcdc_pm_resume(struct device *dev)
558{
559 struct drm_device *ddev = dev_get_drvdata(dev);
560
561 /* Select default pin state */
562 pinctrl_pm_select_default_state(dev);
563 return drm_mode_config_helper_resume(ddev);
564}
565#endif
566
567static const struct dev_pm_ops tilcdc_pm_ops = {
568 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
569};
570
571/*
572 * Platform driver:
573 */
574static int tilcdc_bind(struct device *dev)
575{
576 return tilcdc_init(&tilcdc_driver, dev);
577}
578
579static void tilcdc_unbind(struct device *dev)
580{
581 struct drm_device *ddev = dev_get_drvdata(dev);
582
583 /* Check if a subcomponent has already triggered the unloading. */
584 if (!ddev->dev_private)
585 return;
586
587 tilcdc_fini(dev_get_drvdata(dev));
588}
589
590static const struct component_master_ops tilcdc_comp_ops = {
591 .bind = tilcdc_bind,
592 .unbind = tilcdc_unbind,
593};
594
595static int tilcdc_pdev_probe(struct platform_device *pdev)
596{
597 struct component_match *match = NULL;
598 int ret;
599
600 /* bail out early if no DT data: */
601 if (!pdev->dev.of_node) {
602 dev_err(&pdev->dev, "device-tree data is missing\n");
603 return -ENXIO;
604 }
605
606 ret = tilcdc_get_external_components(&pdev->dev, &match);
607 if (ret < 0)
608 return ret;
609 else if (ret == 0)
610 return tilcdc_init(&tilcdc_driver, &pdev->dev);
611 else
612 return component_master_add_with_match(&pdev->dev,
613 &tilcdc_comp_ops,
614 match);
615}
616
617static int tilcdc_pdev_remove(struct platform_device *pdev)
618{
619 int ret;
620
621 ret = tilcdc_get_external_components(&pdev->dev, NULL);
622 if (ret < 0)
623 return ret;
624 else if (ret == 0)
625 tilcdc_fini(platform_get_drvdata(pdev));
626 else
627 component_master_del(&pdev->dev, &tilcdc_comp_ops);
628
629 return 0;
630}
631
632static struct of_device_id tilcdc_of_match[] = {
633 { .compatible = "ti,am33xx-tilcdc", },
634 { .compatible = "ti,da850-tilcdc", },
635 { },
636};
637MODULE_DEVICE_TABLE(of, tilcdc_of_match);
638
639static struct platform_driver tilcdc_platform_driver = {
640 .probe = tilcdc_pdev_probe,
641 .remove = tilcdc_pdev_remove,
642 .driver = {
643 .name = "tilcdc",
644 .pm = &tilcdc_pm_ops,
645 .of_match_table = tilcdc_of_match,
646 },
647};
648
649static int __init tilcdc_drm_init(void)
650{
651 DBG("init");
652 tilcdc_tfp410_init();
653 tilcdc_panel_init();
654 return platform_driver_register(&tilcdc_platform_driver);
655}
656
657static void __exit tilcdc_drm_fini(void)
658{
659 DBG("fini");
660 platform_driver_unregister(&tilcdc_platform_driver);
661 tilcdc_panel_fini();
662 tilcdc_tfp410_fini();
663}
664
665module_init(tilcdc_drm_init);
666module_exit(tilcdc_drm_fini);
667
668MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
669MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
670MODULE_LICENSE("GPL");