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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef __ADRENO_GPU_H__
21#define __ADRENO_GPU_H__
22
23#include <linux/firmware.h>
24
25#include "msm_gpu.h"
26
27#include "adreno_common.xml.h"
28#include "adreno_pm4.xml.h"
29
30#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
31/**
32 * adreno_regs: List of registers that are used in across all
33 * 3D devices. Each device type has different offset value for the same
34 * register, so an array of register offsets are declared for every device
35 * and are indexed by the enumeration values defined in this enum
36 */
37enum adreno_regs {
38 REG_ADRENO_CP_DEBUG,
39 REG_ADRENO_CP_ME_RAM_WADDR,
40 REG_ADRENO_CP_ME_RAM_DATA,
41 REG_ADRENO_CP_PFP_UCODE_DATA,
42 REG_ADRENO_CP_PFP_UCODE_ADDR,
43 REG_ADRENO_CP_WFI_PEND_CTR,
44 REG_ADRENO_CP_RB_BASE,
45 REG_ADRENO_CP_RB_RPTR_ADDR,
46 REG_ADRENO_CP_RB_RPTR,
47 REG_ADRENO_CP_RB_WPTR,
48 REG_ADRENO_CP_PROTECT_CTRL,
49 REG_ADRENO_CP_ME_CNTL,
50 REG_ADRENO_CP_RB_CNTL,
51 REG_ADRENO_CP_IB1_BASE,
52 REG_ADRENO_CP_IB1_BUFSZ,
53 REG_ADRENO_CP_IB2_BASE,
54 REG_ADRENO_CP_IB2_BUFSZ,
55 REG_ADRENO_CP_TIMESTAMP,
56 REG_ADRENO_CP_ME_RAM_RADDR,
57 REG_ADRENO_CP_ROQ_ADDR,
58 REG_ADRENO_CP_ROQ_DATA,
59 REG_ADRENO_CP_MERCIU_ADDR,
60 REG_ADRENO_CP_MERCIU_DATA,
61 REG_ADRENO_CP_MERCIU_DATA2,
62 REG_ADRENO_CP_MEQ_ADDR,
63 REG_ADRENO_CP_MEQ_DATA,
64 REG_ADRENO_CP_HW_FAULT,
65 REG_ADRENO_CP_PROTECT_STATUS,
66 REG_ADRENO_SCRATCH_ADDR,
67 REG_ADRENO_SCRATCH_UMSK,
68 REG_ADRENO_SCRATCH_REG2,
69 REG_ADRENO_RBBM_STATUS,
70 REG_ADRENO_RBBM_PERFCTR_CTL,
71 REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
72 REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
73 REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2,
74 REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
75 REG_ADRENO_RBBM_INT_0_MASK,
76 REG_ADRENO_RBBM_INT_0_STATUS,
77 REG_ADRENO_RBBM_AHB_ERROR_STATUS,
78 REG_ADRENO_RBBM_PM_OVERRIDE2,
79 REG_ADRENO_RBBM_AHB_CMD,
80 REG_ADRENO_RBBM_INT_CLEAR_CMD,
81 REG_ADRENO_RBBM_SW_RESET_CMD,
82 REG_ADRENO_RBBM_CLOCK_CTL,
83 REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS,
84 REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS,
85 REG_ADRENO_VPC_DEBUG_RAM_SEL,
86 REG_ADRENO_VPC_DEBUG_RAM_READ,
87 REG_ADRENO_VSC_SIZE_ADDRESS,
88 REG_ADRENO_VFD_CONTROL_0,
89 REG_ADRENO_VFD_INDEX_MAX,
90 REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
91 REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
92 REG_ADRENO_SP_VS_OBJ_START_REG,
93 REG_ADRENO_SP_FS_OBJ_START_REG,
94 REG_ADRENO_PA_SC_AA_CONFIG,
95 REG_ADRENO_SQ_GPR_MANAGEMENT,
96 REG_ADRENO_SQ_INST_STORE_MANAGMENT,
97 REG_ADRENO_TP0_CHICKEN,
98 REG_ADRENO_RBBM_RBBM_CTL,
99 REG_ADRENO_UCHE_INVALIDATE0,
100 REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
101 REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
102 REG_ADRENO_REGISTER_MAX,
103};
104
105struct adreno_rev {
106 uint8_t core;
107 uint8_t major;
108 uint8_t minor;
109 uint8_t patchid;
110};
111
112#define ADRENO_REV(core, major, minor, patchid) \
113 ((struct adreno_rev){ core, major, minor, patchid })
114
115struct adreno_gpu_funcs {
116 struct msm_gpu_funcs base;
117 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
118};
119
120struct adreno_info {
121 struct adreno_rev rev;
122 uint32_t revn;
123 const char *name;
124 const char *pm4fw, *pfpfw;
125 uint32_t gmem;
126 struct msm_gpu *(*init)(struct drm_device *dev);
127};
128
129const struct adreno_info *adreno_info(struct adreno_rev rev);
130
131struct adreno_rbmemptrs {
132 volatile uint32_t rptr;
133 volatile uint32_t wptr;
134 volatile uint32_t fence;
135};
136
137struct adreno_gpu {
138 struct msm_gpu base;
139 struct adreno_rev rev;
140 const struct adreno_info *info;
141 uint32_t gmem; /* actual gmem size */
142 uint32_t revn; /* numeric revision name */
143 const struct adreno_gpu_funcs *funcs;
144
145 /* interesting register offsets to dump: */
146 const unsigned int *registers;
147
148 /* firmware: */
149 const struct firmware *pm4, *pfp;
150
151 /* ringbuffer rptr/wptr: */
152 // TODO should this be in msm_ringbuffer? I think it would be
153 // different for z180..
154 struct adreno_rbmemptrs *memptrs;
155 struct drm_gem_object *memptrs_bo;
156 uint32_t memptrs_iova;
157
158 /*
159 * Register offsets are different between some GPUs.
160 * GPU specific offsets will be exported by GPU specific
161 * code (a3xx_gpu.c) and stored in this common location.
162 */
163 const unsigned int *reg_offsets;
164};
165#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
166
167/* platform config data (ie. from DT, or pdata) */
168struct adreno_platform_config {
169 struct adreno_rev rev;
170 uint32_t fast_rate, slow_rate, bus_freq;
171#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
172 struct msm_bus_scale_pdata *bus_scale_table;
173#endif
174};
175
176#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
177
178#define spin_until(X) ({ \
179 int __ret = -ETIMEDOUT; \
180 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
181 do { \
182 if (X) { \
183 __ret = 0; \
184 break; \
185 } \
186 } while (time_before(jiffies, __t)); \
187 __ret; \
188})
189
190
191static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
192{
193 return (gpu->revn >= 300) && (gpu->revn < 400);
194}
195
196static inline bool adreno_is_a305(struct adreno_gpu *gpu)
197{
198 return gpu->revn == 305;
199}
200
201static inline bool adreno_is_a306(struct adreno_gpu *gpu)
202{
203 /* yes, 307, because a305c is 306 */
204 return gpu->revn == 307;
205}
206
207static inline bool adreno_is_a320(struct adreno_gpu *gpu)
208{
209 return gpu->revn == 320;
210}
211
212static inline bool adreno_is_a330(struct adreno_gpu *gpu)
213{
214 return gpu->revn == 330;
215}
216
217static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
218{
219 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
220}
221
222static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
223{
224 return (gpu->revn >= 400) && (gpu->revn < 500);
225}
226
227static inline int adreno_is_a420(struct adreno_gpu *gpu)
228{
229 return gpu->revn == 420;
230}
231
232static inline int adreno_is_a430(struct adreno_gpu *gpu)
233{
234 return gpu->revn == 430;
235}
236
237int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
238int adreno_hw_init(struct msm_gpu *gpu);
239uint32_t adreno_last_fence(struct msm_gpu *gpu);
240void adreno_recover(struct msm_gpu *gpu);
241int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
242 struct msm_file_private *ctx);
243void adreno_flush(struct msm_gpu *gpu);
244void adreno_idle(struct msm_gpu *gpu);
245#ifdef CONFIG_DEBUG_FS
246void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
247#endif
248void adreno_dump_info(struct msm_gpu *gpu);
249void adreno_dump(struct msm_gpu *gpu);
250void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
251
252int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
253 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs);
254void adreno_gpu_cleanup(struct adreno_gpu *gpu);
255
256
257/* ringbuffer helpers (the parts that are adreno specific) */
258
259static inline void
260OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
261{
262 adreno_wait_ring(ring->gpu, cnt+1);
263 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
264}
265
266/* no-op packet: */
267static inline void
268OUT_PKT2(struct msm_ringbuffer *ring)
269{
270 adreno_wait_ring(ring->gpu, 1);
271 OUT_RING(ring, CP_TYPE2_PKT);
272}
273
274static inline void
275OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
276{
277 adreno_wait_ring(ring->gpu, cnt+1);
278 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
279}
280
281/*
282 * adreno_checkreg_off() - Checks the validity of a register enum
283 * @gpu: Pointer to struct adreno_gpu
284 * @offset_name: The register enum that is checked
285 */
286static inline bool adreno_reg_check(struct adreno_gpu *gpu,
287 enum adreno_regs offset_name)
288{
289 if (offset_name >= REG_ADRENO_REGISTER_MAX ||
290 !gpu->reg_offsets[offset_name]) {
291 BUG();
292 }
293 return true;
294}
295
296static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
297 enum adreno_regs offset_name)
298{
299 u32 reg = gpu->reg_offsets[offset_name];
300 u32 val = 0;
301 if(adreno_reg_check(gpu,offset_name))
302 val = gpu_read(&gpu->base, reg - 1);
303 return val;
304}
305
306static inline void adreno_gpu_write(struct adreno_gpu *gpu,
307 enum adreno_regs offset_name, u32 data)
308{
309 u32 reg = gpu->reg_offsets[offset_name];
310 if(adreno_reg_check(gpu, offset_name))
311 gpu_write(&gpu->base, reg - 1, data);
312}
313
314#endif /* __ADRENO_GPU_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 */
8
9#ifndef __ADRENO_GPU_H__
10#define __ADRENO_GPU_H__
11
12#include <linux/firmware.h>
13#include <linux/iopoll.h>
14
15#include "msm_gpu.h"
16
17#include "adreno_common.xml.h"
18#include "adreno_pm4.xml.h"
19
20#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
21#define REG_SKIP ~0
22#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
23
24/**
25 * adreno_regs: List of registers that are used in across all
26 * 3D devices. Each device type has different offset value for the same
27 * register, so an array of register offsets are declared for every device
28 * and are indexed by the enumeration values defined in this enum
29 */
30enum adreno_regs {
31 REG_ADRENO_CP_RB_BASE,
32 REG_ADRENO_CP_RB_BASE_HI,
33 REG_ADRENO_CP_RB_RPTR_ADDR,
34 REG_ADRENO_CP_RB_RPTR_ADDR_HI,
35 REG_ADRENO_CP_RB_RPTR,
36 REG_ADRENO_CP_RB_WPTR,
37 REG_ADRENO_CP_RB_CNTL,
38 REG_ADRENO_REGISTER_MAX,
39};
40
41enum {
42 ADRENO_FW_PM4 = 0,
43 ADRENO_FW_SQE = 0, /* a6xx */
44 ADRENO_FW_PFP = 1,
45 ADRENO_FW_GMU = 1, /* a6xx */
46 ADRENO_FW_GPMU = 2,
47 ADRENO_FW_MAX,
48};
49
50enum adreno_quirks {
51 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
52 ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
53 ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
54};
55
56struct adreno_rev {
57 uint8_t core;
58 uint8_t major;
59 uint8_t minor;
60 uint8_t patchid;
61};
62
63#define ADRENO_REV(core, major, minor, patchid) \
64 ((struct adreno_rev){ core, major, minor, patchid })
65
66struct adreno_gpu_funcs {
67 struct msm_gpu_funcs base;
68 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
69};
70
71struct adreno_info {
72 struct adreno_rev rev;
73 uint32_t revn;
74 const char *name;
75 const char *fw[ADRENO_FW_MAX];
76 uint32_t gmem;
77 enum adreno_quirks quirks;
78 struct msm_gpu *(*init)(struct drm_device *dev);
79 const char *zapfw;
80 u32 inactive_period;
81};
82
83const struct adreno_info *adreno_info(struct adreno_rev rev);
84
85struct adreno_gpu {
86 struct msm_gpu base;
87 struct adreno_rev rev;
88 const struct adreno_info *info;
89 uint32_t gmem; /* actual gmem size */
90 uint32_t revn; /* numeric revision name */
91 const struct adreno_gpu_funcs *funcs;
92
93 /* interesting register offsets to dump: */
94 const unsigned int *registers;
95
96 /*
97 * Are we loading fw from legacy path? Prior to addition
98 * of gpu firmware to linux-firmware, the fw files were
99 * placed in toplevel firmware directory, following qcom's
100 * android kernel. But linux-firmware preferred they be
101 * placed in a 'qcom' subdirectory.
102 *
103 * For backwards compatibility, we try first to load from
104 * the new path, using request_firmware_direct() to avoid
105 * any potential timeout waiting for usermode helper, then
106 * fall back to the old path (with direct load). And
107 * finally fall back to request_firmware() with the new
108 * path to allow the usermode helper.
109 */
110 enum {
111 FW_LOCATION_UNKNOWN = 0,
112 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */
113 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */
114 FW_LOCATION_HELPER,
115 } fwloc;
116
117 /* firmware: */
118 const struct firmware *fw[ADRENO_FW_MAX];
119
120 /*
121 * Register offsets are different between some GPUs.
122 * GPU specific offsets will be exported by GPU specific
123 * code (a3xx_gpu.c) and stored in this common location.
124 */
125 const unsigned int *reg_offsets;
126};
127#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
128
129/* platform config data (ie. from DT, or pdata) */
130struct adreno_platform_config {
131 struct adreno_rev rev;
132};
133
134#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
135
136#define spin_until(X) ({ \
137 int __ret = -ETIMEDOUT; \
138 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
139 do { \
140 if (X) { \
141 __ret = 0; \
142 break; \
143 } \
144 } while (time_before(jiffies, __t)); \
145 __ret; \
146})
147
148static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
149{
150 return (gpu->revn < 300);
151}
152
153static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
154{
155 return (gpu->revn < 210);
156}
157
158static inline bool adreno_is_a225(struct adreno_gpu *gpu)
159{
160 return gpu->revn == 225;
161}
162
163static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
164{
165 return (gpu->revn >= 300) && (gpu->revn < 400);
166}
167
168static inline bool adreno_is_a305(struct adreno_gpu *gpu)
169{
170 return gpu->revn == 305;
171}
172
173static inline bool adreno_is_a306(struct adreno_gpu *gpu)
174{
175 /* yes, 307, because a305c is 306 */
176 return gpu->revn == 307;
177}
178
179static inline bool adreno_is_a320(struct adreno_gpu *gpu)
180{
181 return gpu->revn == 320;
182}
183
184static inline bool adreno_is_a330(struct adreno_gpu *gpu)
185{
186 return gpu->revn == 330;
187}
188
189static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
190{
191 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
192}
193
194static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
195{
196 return (gpu->revn >= 400) && (gpu->revn < 500);
197}
198
199static inline int adreno_is_a420(struct adreno_gpu *gpu)
200{
201 return gpu->revn == 420;
202}
203
204static inline int adreno_is_a430(struct adreno_gpu *gpu)
205{
206 return gpu->revn == 430;
207}
208
209static inline int adreno_is_a530(struct adreno_gpu *gpu)
210{
211 return gpu->revn == 530;
212}
213
214static inline int adreno_is_a540(struct adreno_gpu *gpu)
215{
216 return gpu->revn == 540;
217}
218
219int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
220const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
221 const char *fwname);
222struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
223 const struct firmware *fw, u64 *iova);
224int adreno_hw_init(struct msm_gpu *gpu);
225void adreno_recover(struct msm_gpu *gpu);
226void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
227 struct msm_file_private *ctx);
228void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
229bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
230#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
231void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
232 struct drm_printer *p);
233#endif
234void adreno_dump_info(struct msm_gpu *gpu);
235void adreno_dump(struct msm_gpu *gpu);
236void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
237struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
238
239int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
240 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
241 int nr_rings);
242void adreno_gpu_cleanup(struct adreno_gpu *gpu);
243int adreno_load_fw(struct adreno_gpu *adreno_gpu);
244
245void adreno_gpu_state_destroy(struct msm_gpu_state *state);
246
247int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
248int adreno_gpu_state_put(struct msm_gpu_state *state);
249
250/*
251 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
252 * out of secure mode
253 */
254int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
255
256/* ringbuffer helpers (the parts that are adreno specific) */
257
258static inline void
259OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
260{
261 adreno_wait_ring(ring, cnt+1);
262 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
263}
264
265/* no-op packet: */
266static inline void
267OUT_PKT2(struct msm_ringbuffer *ring)
268{
269 adreno_wait_ring(ring, 1);
270 OUT_RING(ring, CP_TYPE2_PKT);
271}
272
273static inline void
274OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
275{
276 adreno_wait_ring(ring, cnt+1);
277 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
278}
279
280static inline u32 PM4_PARITY(u32 val)
281{
282 return (0x9669 >> (0xF & (val ^
283 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
284 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
285 (val >> 28)))) & 1;
286}
287
288/* Maximum number of values that can be executed for one opcode */
289#define TYPE4_MAX_PAYLOAD 127
290
291#define PKT4(_reg, _cnt) \
292 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
293 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
294
295static inline void
296OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
297{
298 adreno_wait_ring(ring, cnt + 1);
299 OUT_RING(ring, PKT4(regindx, cnt));
300}
301
302static inline void
303OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
304{
305 adreno_wait_ring(ring, cnt + 1);
306 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
307 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
308}
309
310/*
311 * adreno_reg_check() - Checks the validity of a register enum
312 * @gpu: Pointer to struct adreno_gpu
313 * @offset_name: The register enum that is checked
314 */
315static inline bool adreno_reg_check(struct adreno_gpu *gpu,
316 enum adreno_regs offset_name)
317{
318 if (offset_name >= REG_ADRENO_REGISTER_MAX ||
319 !gpu->reg_offsets[offset_name]) {
320 BUG();
321 }
322
323 /*
324 * REG_SKIP is a special value that tell us that the register in
325 * question isn't implemented on target but don't trigger a BUG(). This
326 * is used to cleanly implement adreno_gpu_write64() and
327 * adreno_gpu_read64() in a generic fashion
328 */
329 if (gpu->reg_offsets[offset_name] == REG_SKIP)
330 return false;
331
332 return true;
333}
334
335static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
336 enum adreno_regs offset_name)
337{
338 u32 reg = gpu->reg_offsets[offset_name];
339 u32 val = 0;
340 if(adreno_reg_check(gpu,offset_name))
341 val = gpu_read(&gpu->base, reg - 1);
342 return val;
343}
344
345static inline void adreno_gpu_write(struct adreno_gpu *gpu,
346 enum adreno_regs offset_name, u32 data)
347{
348 u32 reg = gpu->reg_offsets[offset_name];
349 if(adreno_reg_check(gpu, offset_name))
350 gpu_write(&gpu->base, reg - 1, data);
351}
352
353struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
354struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
355struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
356struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
357struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
358
359static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
360 enum adreno_regs lo, enum adreno_regs hi, u64 data)
361{
362 adreno_gpu_write(gpu, lo, lower_32_bits(data));
363 adreno_gpu_write(gpu, hi, upper_32_bits(data));
364}
365
366static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
367{
368 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
369}
370
371/*
372 * Given a register and a count, return a value to program into
373 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
374 * registers starting at _reg.
375 *
376 * The register base needs to be a multiple of the length. If it is not, the
377 * hardware will quietly mask off the bits for you and shift the size. For
378 * example, if you intend the protection to start at 0x07 for a length of 4
379 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
380 * expose registers you intended to protect!
381 */
382#define ADRENO_PROTECT_RW(_reg, _len) \
383 ((1 << 30) | (1 << 29) | \
384 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
385
386/*
387 * Same as above, but allow reads over the range. For areas of mixed use (such
388 * as performance counters) this allows us to protect a much larger range with a
389 * single register
390 */
391#define ADRENO_PROTECT_RDONLY(_reg, _len) \
392 ((1 << 29) \
393 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
394
395
396#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
397 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
398 interval, timeout)
399
400#endif /* __ADRENO_GPU_H__ */