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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include "drmP.h"
27#include "amdgpu.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "atom.h"
34#include "amd_pcie.h"
35
36#include "gmc/gmc_8_1_d.h"
37#include "gmc/gmc_8_1_sh_mask.h"
38
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "gca/gfx_8_0_d.h"
46#include "gca/gfx_8_0_sh_mask.h"
47
48#include "smu/smu_7_1_1_d.h"
49#include "smu/smu_7_1_1_sh_mask.h"
50
51#include "uvd/uvd_5_0_d.h"
52#include "uvd/uvd_5_0_sh_mask.h"
53
54#include "vce/vce_3_0_d.h"
55#include "vce/vce_3_0_sh_mask.h"
56
57#include "dce/dce_10_0_d.h"
58#include "dce/dce_10_0_sh_mask.h"
59
60#include "vid.h"
61#include "vi.h"
62#include "vi_dpm.h"
63#include "gmc_v8_0.h"
64#include "gmc_v7_0.h"
65#include "gfx_v8_0.h"
66#include "sdma_v2_4.h"
67#include "sdma_v3_0.h"
68#include "dce_v10_0.h"
69#include "dce_v11_0.h"
70#include "iceland_ih.h"
71#include "tonga_ih.h"
72#include "cz_ih.h"
73#include "uvd_v5_0.h"
74#include "uvd_v6_0.h"
75#include "vce_v3_0.h"
76#include "amdgpu_powerplay.h"
77#if defined(CONFIG_DRM_AMD_ACP)
78#include "amdgpu_acp.h"
79#endif
80
81/*
82 * Indirect registers accessor
83 */
84static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
85{
86 unsigned long flags;
87 u32 r;
88
89 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
90 WREG32(mmPCIE_INDEX, reg);
91 (void)RREG32(mmPCIE_INDEX);
92 r = RREG32(mmPCIE_DATA);
93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
94 return r;
95}
96
97static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
98{
99 unsigned long flags;
100
101 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
102 WREG32(mmPCIE_INDEX, reg);
103 (void)RREG32(mmPCIE_INDEX);
104 WREG32(mmPCIE_DATA, v);
105 (void)RREG32(mmPCIE_DATA);
106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
107}
108
109static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
110{
111 unsigned long flags;
112 u32 r;
113
114 spin_lock_irqsave(&adev->smc_idx_lock, flags);
115 WREG32(mmSMC_IND_INDEX_0, (reg));
116 r = RREG32(mmSMC_IND_DATA_0);
117 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
118 return r;
119}
120
121static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
122{
123 unsigned long flags;
124
125 spin_lock_irqsave(&adev->smc_idx_lock, flags);
126 WREG32(mmSMC_IND_INDEX_0, (reg));
127 WREG32(mmSMC_IND_DATA_0, (v));
128 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
129}
130
131/* smu_8_0_d.h */
132#define mmMP0PUB_IND_INDEX 0x180
133#define mmMP0PUB_IND_DATA 0x181
134
135static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
136{
137 unsigned long flags;
138 u32 r;
139
140 spin_lock_irqsave(&adev->smc_idx_lock, flags);
141 WREG32(mmMP0PUB_IND_INDEX, (reg));
142 r = RREG32(mmMP0PUB_IND_DATA);
143 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
144 return r;
145}
146
147static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
148{
149 unsigned long flags;
150
151 spin_lock_irqsave(&adev->smc_idx_lock, flags);
152 WREG32(mmMP0PUB_IND_INDEX, (reg));
153 WREG32(mmMP0PUB_IND_DATA, (v));
154 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
155}
156
157static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
158{
159 unsigned long flags;
160 u32 r;
161
162 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
163 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
164 r = RREG32(mmUVD_CTX_DATA);
165 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
166 return r;
167}
168
169static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
170{
171 unsigned long flags;
172
173 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
174 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
175 WREG32(mmUVD_CTX_DATA, (v));
176 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
177}
178
179static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
180{
181 unsigned long flags;
182 u32 r;
183
184 spin_lock_irqsave(&adev->didt_idx_lock, flags);
185 WREG32(mmDIDT_IND_INDEX, (reg));
186 r = RREG32(mmDIDT_IND_DATA);
187 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
188 return r;
189}
190
191static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
192{
193 unsigned long flags;
194
195 spin_lock_irqsave(&adev->didt_idx_lock, flags);
196 WREG32(mmDIDT_IND_INDEX, (reg));
197 WREG32(mmDIDT_IND_DATA, (v));
198 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
199}
200
201static const u32 tonga_mgcg_cgcg_init[] =
202{
203 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
204 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
205 mmPCIE_DATA, 0x000f0000, 0x00000000,
206 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
207 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
208 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
209 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
210};
211
212static const u32 fiji_mgcg_cgcg_init[] =
213{
214 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
215 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
216 mmPCIE_DATA, 0x000f0000, 0x00000000,
217 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
218 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
219 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
220 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
221};
222
223static const u32 iceland_mgcg_cgcg_init[] =
224{
225 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
226 mmPCIE_DATA, 0x000f0000, 0x00000000,
227 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
228 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
229 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
230};
231
232static const u32 cz_mgcg_cgcg_init[] =
233{
234 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
235 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
236 mmPCIE_DATA, 0x000f0000, 0x00000000,
237 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
238 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
239};
240
241static const u32 stoney_mgcg_cgcg_init[] =
242{
243 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
244 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
245 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
246};
247
248static void vi_init_golden_registers(struct amdgpu_device *adev)
249{
250 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
251 mutex_lock(&adev->grbm_idx_mutex);
252
253 switch (adev->asic_type) {
254 case CHIP_TOPAZ:
255 amdgpu_program_register_sequence(adev,
256 iceland_mgcg_cgcg_init,
257 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
258 break;
259 case CHIP_FIJI:
260 amdgpu_program_register_sequence(adev,
261 fiji_mgcg_cgcg_init,
262 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
263 break;
264 case CHIP_TONGA:
265 amdgpu_program_register_sequence(adev,
266 tonga_mgcg_cgcg_init,
267 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
268 break;
269 case CHIP_CARRIZO:
270 amdgpu_program_register_sequence(adev,
271 cz_mgcg_cgcg_init,
272 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
273 break;
274 case CHIP_STONEY:
275 amdgpu_program_register_sequence(adev,
276 stoney_mgcg_cgcg_init,
277 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
278 break;
279 default:
280 break;
281 }
282 mutex_unlock(&adev->grbm_idx_mutex);
283}
284
285/**
286 * vi_get_xclk - get the xclk
287 *
288 * @adev: amdgpu_device pointer
289 *
290 * Returns the reference clock used by the gfx engine
291 * (VI).
292 */
293static u32 vi_get_xclk(struct amdgpu_device *adev)
294{
295 u32 reference_clock = adev->clock.spll.reference_freq;
296 u32 tmp;
297
298 if (adev->flags & AMD_IS_APU)
299 return reference_clock;
300
301 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
302 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
303 return 1000;
304
305 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
306 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
307 return reference_clock / 4;
308
309 return reference_clock;
310}
311
312/**
313 * vi_srbm_select - select specific register instances
314 *
315 * @adev: amdgpu_device pointer
316 * @me: selected ME (micro engine)
317 * @pipe: pipe
318 * @queue: queue
319 * @vmid: VMID
320 *
321 * Switches the currently active registers instances. Some
322 * registers are instanced per VMID, others are instanced per
323 * me/pipe/queue combination.
324 */
325void vi_srbm_select(struct amdgpu_device *adev,
326 u32 me, u32 pipe, u32 queue, u32 vmid)
327{
328 u32 srbm_gfx_cntl = 0;
329 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
330 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
331 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
332 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
333 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
334}
335
336static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
337{
338 /* todo */
339}
340
341static bool vi_read_disabled_bios(struct amdgpu_device *adev)
342{
343 u32 bus_cntl;
344 u32 d1vga_control = 0;
345 u32 d2vga_control = 0;
346 u32 vga_render_control = 0;
347 u32 rom_cntl;
348 bool r;
349
350 bus_cntl = RREG32(mmBUS_CNTL);
351 if (adev->mode_info.num_crtc) {
352 d1vga_control = RREG32(mmD1VGA_CONTROL);
353 d2vga_control = RREG32(mmD2VGA_CONTROL);
354 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
355 }
356 rom_cntl = RREG32_SMC(ixROM_CNTL);
357
358 /* enable the rom */
359 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
360 if (adev->mode_info.num_crtc) {
361 /* Disable VGA mode */
362 WREG32(mmD1VGA_CONTROL,
363 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
364 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
365 WREG32(mmD2VGA_CONTROL,
366 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
367 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
368 WREG32(mmVGA_RENDER_CONTROL,
369 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
370 }
371 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
372
373 r = amdgpu_read_bios(adev);
374
375 /* restore regs */
376 WREG32(mmBUS_CNTL, bus_cntl);
377 if (adev->mode_info.num_crtc) {
378 WREG32(mmD1VGA_CONTROL, d1vga_control);
379 WREG32(mmD2VGA_CONTROL, d2vga_control);
380 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
381 }
382 WREG32_SMC(ixROM_CNTL, rom_cntl);
383 return r;
384}
385
386static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
387 u8 *bios, u32 length_bytes)
388{
389 u32 *dw_ptr;
390 unsigned long flags;
391 u32 i, length_dw;
392
393 if (bios == NULL)
394 return false;
395 if (length_bytes == 0)
396 return false;
397 /* APU vbios image is part of sbios image */
398 if (adev->flags & AMD_IS_APU)
399 return false;
400
401 dw_ptr = (u32 *)bios;
402 length_dw = ALIGN(length_bytes, 4) / 4;
403 /* take the smc lock since we are using the smc index */
404 spin_lock_irqsave(&adev->smc_idx_lock, flags);
405 /* set rom index to 0 */
406 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
407 WREG32(mmSMC_IND_DATA_0, 0);
408 /* set index to data for continous read */
409 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
410 for (i = 0; i < length_dw; i++)
411 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
412 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
413
414 return true;
415}
416
417static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
418 {mmGB_MACROTILE_MODE7, true},
419};
420
421static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
422 {mmGB_TILE_MODE7, true},
423 {mmGB_TILE_MODE12, true},
424 {mmGB_TILE_MODE17, true},
425 {mmGB_TILE_MODE23, true},
426 {mmGB_MACROTILE_MODE7, true},
427};
428
429static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
430 {mmGRBM_STATUS, false},
431 {mmGRBM_STATUS2, false},
432 {mmGRBM_STATUS_SE0, false},
433 {mmGRBM_STATUS_SE1, false},
434 {mmGRBM_STATUS_SE2, false},
435 {mmGRBM_STATUS_SE3, false},
436 {mmSRBM_STATUS, false},
437 {mmSRBM_STATUS2, false},
438 {mmSRBM_STATUS3, false},
439 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
440 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
441 {mmCP_STAT, false},
442 {mmCP_STALLED_STAT1, false},
443 {mmCP_STALLED_STAT2, false},
444 {mmCP_STALLED_STAT3, false},
445 {mmCP_CPF_BUSY_STAT, false},
446 {mmCP_CPF_STALLED_STAT1, false},
447 {mmCP_CPF_STATUS, false},
448 {mmCP_CPC_BUSY_STAT, false},
449 {mmCP_CPC_STALLED_STAT1, false},
450 {mmCP_CPC_STATUS, false},
451 {mmGB_ADDR_CONFIG, false},
452 {mmMC_ARB_RAMCFG, false},
453 {mmGB_TILE_MODE0, false},
454 {mmGB_TILE_MODE1, false},
455 {mmGB_TILE_MODE2, false},
456 {mmGB_TILE_MODE3, false},
457 {mmGB_TILE_MODE4, false},
458 {mmGB_TILE_MODE5, false},
459 {mmGB_TILE_MODE6, false},
460 {mmGB_TILE_MODE7, false},
461 {mmGB_TILE_MODE8, false},
462 {mmGB_TILE_MODE9, false},
463 {mmGB_TILE_MODE10, false},
464 {mmGB_TILE_MODE11, false},
465 {mmGB_TILE_MODE12, false},
466 {mmGB_TILE_MODE13, false},
467 {mmGB_TILE_MODE14, false},
468 {mmGB_TILE_MODE15, false},
469 {mmGB_TILE_MODE16, false},
470 {mmGB_TILE_MODE17, false},
471 {mmGB_TILE_MODE18, false},
472 {mmGB_TILE_MODE19, false},
473 {mmGB_TILE_MODE20, false},
474 {mmGB_TILE_MODE21, false},
475 {mmGB_TILE_MODE22, false},
476 {mmGB_TILE_MODE23, false},
477 {mmGB_TILE_MODE24, false},
478 {mmGB_TILE_MODE25, false},
479 {mmGB_TILE_MODE26, false},
480 {mmGB_TILE_MODE27, false},
481 {mmGB_TILE_MODE28, false},
482 {mmGB_TILE_MODE29, false},
483 {mmGB_TILE_MODE30, false},
484 {mmGB_TILE_MODE31, false},
485 {mmGB_MACROTILE_MODE0, false},
486 {mmGB_MACROTILE_MODE1, false},
487 {mmGB_MACROTILE_MODE2, false},
488 {mmGB_MACROTILE_MODE3, false},
489 {mmGB_MACROTILE_MODE4, false},
490 {mmGB_MACROTILE_MODE5, false},
491 {mmGB_MACROTILE_MODE6, false},
492 {mmGB_MACROTILE_MODE7, false},
493 {mmGB_MACROTILE_MODE8, false},
494 {mmGB_MACROTILE_MODE9, false},
495 {mmGB_MACROTILE_MODE10, false},
496 {mmGB_MACROTILE_MODE11, false},
497 {mmGB_MACROTILE_MODE12, false},
498 {mmGB_MACROTILE_MODE13, false},
499 {mmGB_MACROTILE_MODE14, false},
500 {mmGB_MACROTILE_MODE15, false},
501 {mmCC_RB_BACKEND_DISABLE, false, true},
502 {mmGC_USER_RB_BACKEND_DISABLE, false, true},
503 {mmGB_BACKEND_MAP, false, false},
504 {mmPA_SC_RASTER_CONFIG, false, true},
505 {mmPA_SC_RASTER_CONFIG_1, false, true},
506};
507
508static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
509 u32 sh_num, u32 reg_offset)
510{
511 uint32_t val;
512
513 mutex_lock(&adev->grbm_idx_mutex);
514 if (se_num != 0xffffffff || sh_num != 0xffffffff)
515 gfx_v8_0_select_se_sh(adev, se_num, sh_num);
516
517 val = RREG32(reg_offset);
518
519 if (se_num != 0xffffffff || sh_num != 0xffffffff)
520 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
521 mutex_unlock(&adev->grbm_idx_mutex);
522 return val;
523}
524
525static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
526 u32 sh_num, u32 reg_offset, u32 *value)
527{
528 struct amdgpu_allowed_register_entry *asic_register_table = NULL;
529 struct amdgpu_allowed_register_entry *asic_register_entry;
530 uint32_t size, i;
531
532 *value = 0;
533 switch (adev->asic_type) {
534 case CHIP_TOPAZ:
535 asic_register_table = tonga_allowed_read_registers;
536 size = ARRAY_SIZE(tonga_allowed_read_registers);
537 break;
538 case CHIP_FIJI:
539 case CHIP_TONGA:
540 case CHIP_CARRIZO:
541 case CHIP_STONEY:
542 asic_register_table = cz_allowed_read_registers;
543 size = ARRAY_SIZE(cz_allowed_read_registers);
544 break;
545 default:
546 return -EINVAL;
547 }
548
549 if (asic_register_table) {
550 for (i = 0; i < size; i++) {
551 asic_register_entry = asic_register_table + i;
552 if (reg_offset != asic_register_entry->reg_offset)
553 continue;
554 if (!asic_register_entry->untouched)
555 *value = asic_register_entry->grbm_indexed ?
556 vi_read_indexed_register(adev, se_num,
557 sh_num, reg_offset) :
558 RREG32(reg_offset);
559 return 0;
560 }
561 }
562
563 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
564 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
565 continue;
566
567 if (!vi_allowed_read_registers[i].untouched)
568 *value = vi_allowed_read_registers[i].grbm_indexed ?
569 vi_read_indexed_register(adev, se_num,
570 sh_num, reg_offset) :
571 RREG32(reg_offset);
572 return 0;
573 }
574 return -EINVAL;
575}
576
577static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
578{
579 u32 i;
580
581 dev_info(adev->dev, "GPU pci config reset\n");
582
583 /* disable BM */
584 pci_clear_master(adev->pdev);
585 /* reset */
586 amdgpu_pci_config_reset(adev);
587
588 udelay(100);
589
590 /* wait for asic to come out of reset */
591 for (i = 0; i < adev->usec_timeout; i++) {
592 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
593 break;
594 udelay(1);
595 }
596
597}
598
599static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
600{
601 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
602
603 if (hung)
604 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
605 else
606 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
607
608 WREG32(mmBIOS_SCRATCH_3, tmp);
609}
610
611/**
612 * vi_asic_reset - soft reset GPU
613 *
614 * @adev: amdgpu_device pointer
615 *
616 * Look up which blocks are hung and attempt
617 * to reset them.
618 * Returns 0 for success.
619 */
620static int vi_asic_reset(struct amdgpu_device *adev)
621{
622 vi_set_bios_scratch_engine_hung(adev, true);
623
624 vi_gpu_pci_config_reset(adev);
625
626 vi_set_bios_scratch_engine_hung(adev, false);
627
628 return 0;
629}
630
631static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
632 u32 cntl_reg, u32 status_reg)
633{
634 int r, i;
635 struct atom_clock_dividers dividers;
636 uint32_t tmp;
637
638 r = amdgpu_atombios_get_clock_dividers(adev,
639 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
640 clock, false, ÷rs);
641 if (r)
642 return r;
643
644 tmp = RREG32_SMC(cntl_reg);
645 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
646 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
647 tmp |= dividers.post_divider;
648 WREG32_SMC(cntl_reg, tmp);
649
650 for (i = 0; i < 100; i++) {
651 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
652 break;
653 mdelay(10);
654 }
655 if (i == 100)
656 return -ETIMEDOUT;
657
658 return 0;
659}
660
661static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
662{
663 int r;
664
665 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
666 if (r)
667 return r;
668
669 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
670
671 return 0;
672}
673
674static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
675{
676 /* todo */
677
678 return 0;
679}
680
681static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
682{
683 if (pci_is_root_bus(adev->pdev->bus))
684 return;
685
686 if (amdgpu_pcie_gen2 == 0)
687 return;
688
689 if (adev->flags & AMD_IS_APU)
690 return;
691
692 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
693 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
694 return;
695
696 /* todo */
697}
698
699static void vi_program_aspm(struct amdgpu_device *adev)
700{
701
702 if (amdgpu_aspm == 0)
703 return;
704
705 /* todo */
706}
707
708static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
709 bool enable)
710{
711 u32 tmp;
712
713 /* not necessary on CZ */
714 if (adev->flags & AMD_IS_APU)
715 return;
716
717 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
718 if (enable)
719 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
720 else
721 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
722
723 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
724}
725
726/* topaz has no DCE, UVD, VCE */
727static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
728{
729 /* ORDER MATTERS! */
730 {
731 .type = AMD_IP_BLOCK_TYPE_COMMON,
732 .major = 2,
733 .minor = 0,
734 .rev = 0,
735 .funcs = &vi_common_ip_funcs,
736 },
737 {
738 .type = AMD_IP_BLOCK_TYPE_GMC,
739 .major = 7,
740 .minor = 4,
741 .rev = 0,
742 .funcs = &gmc_v7_0_ip_funcs,
743 },
744 {
745 .type = AMD_IP_BLOCK_TYPE_IH,
746 .major = 2,
747 .minor = 4,
748 .rev = 0,
749 .funcs = &iceland_ih_ip_funcs,
750 },
751 {
752 .type = AMD_IP_BLOCK_TYPE_SMC,
753 .major = 7,
754 .minor = 1,
755 .rev = 0,
756 .funcs = &amdgpu_pp_ip_funcs,
757 },
758 {
759 .type = AMD_IP_BLOCK_TYPE_GFX,
760 .major = 8,
761 .minor = 0,
762 .rev = 0,
763 .funcs = &gfx_v8_0_ip_funcs,
764 },
765 {
766 .type = AMD_IP_BLOCK_TYPE_SDMA,
767 .major = 2,
768 .minor = 4,
769 .rev = 0,
770 .funcs = &sdma_v2_4_ip_funcs,
771 },
772};
773
774static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
775{
776 /* ORDER MATTERS! */
777 {
778 .type = AMD_IP_BLOCK_TYPE_COMMON,
779 .major = 2,
780 .minor = 0,
781 .rev = 0,
782 .funcs = &vi_common_ip_funcs,
783 },
784 {
785 .type = AMD_IP_BLOCK_TYPE_GMC,
786 .major = 8,
787 .minor = 0,
788 .rev = 0,
789 .funcs = &gmc_v8_0_ip_funcs,
790 },
791 {
792 .type = AMD_IP_BLOCK_TYPE_IH,
793 .major = 3,
794 .minor = 0,
795 .rev = 0,
796 .funcs = &tonga_ih_ip_funcs,
797 },
798 {
799 .type = AMD_IP_BLOCK_TYPE_SMC,
800 .major = 7,
801 .minor = 1,
802 .rev = 0,
803 .funcs = &amdgpu_pp_ip_funcs,
804 },
805 {
806 .type = AMD_IP_BLOCK_TYPE_DCE,
807 .major = 10,
808 .minor = 0,
809 .rev = 0,
810 .funcs = &dce_v10_0_ip_funcs,
811 },
812 {
813 .type = AMD_IP_BLOCK_TYPE_GFX,
814 .major = 8,
815 .minor = 0,
816 .rev = 0,
817 .funcs = &gfx_v8_0_ip_funcs,
818 },
819 {
820 .type = AMD_IP_BLOCK_TYPE_SDMA,
821 .major = 3,
822 .minor = 0,
823 .rev = 0,
824 .funcs = &sdma_v3_0_ip_funcs,
825 },
826 {
827 .type = AMD_IP_BLOCK_TYPE_UVD,
828 .major = 5,
829 .minor = 0,
830 .rev = 0,
831 .funcs = &uvd_v5_0_ip_funcs,
832 },
833 {
834 .type = AMD_IP_BLOCK_TYPE_VCE,
835 .major = 3,
836 .minor = 0,
837 .rev = 0,
838 .funcs = &vce_v3_0_ip_funcs,
839 },
840};
841
842static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
843{
844 /* ORDER MATTERS! */
845 {
846 .type = AMD_IP_BLOCK_TYPE_COMMON,
847 .major = 2,
848 .minor = 0,
849 .rev = 0,
850 .funcs = &vi_common_ip_funcs,
851 },
852 {
853 .type = AMD_IP_BLOCK_TYPE_GMC,
854 .major = 8,
855 .minor = 5,
856 .rev = 0,
857 .funcs = &gmc_v8_0_ip_funcs,
858 },
859 {
860 .type = AMD_IP_BLOCK_TYPE_IH,
861 .major = 3,
862 .minor = 0,
863 .rev = 0,
864 .funcs = &tonga_ih_ip_funcs,
865 },
866 {
867 .type = AMD_IP_BLOCK_TYPE_SMC,
868 .major = 7,
869 .minor = 1,
870 .rev = 0,
871 .funcs = &amdgpu_pp_ip_funcs,
872 },
873 {
874 .type = AMD_IP_BLOCK_TYPE_DCE,
875 .major = 10,
876 .minor = 1,
877 .rev = 0,
878 .funcs = &dce_v10_0_ip_funcs,
879 },
880 {
881 .type = AMD_IP_BLOCK_TYPE_GFX,
882 .major = 8,
883 .minor = 0,
884 .rev = 0,
885 .funcs = &gfx_v8_0_ip_funcs,
886 },
887 {
888 .type = AMD_IP_BLOCK_TYPE_SDMA,
889 .major = 3,
890 .minor = 0,
891 .rev = 0,
892 .funcs = &sdma_v3_0_ip_funcs,
893 },
894 {
895 .type = AMD_IP_BLOCK_TYPE_UVD,
896 .major = 6,
897 .minor = 0,
898 .rev = 0,
899 .funcs = &uvd_v6_0_ip_funcs,
900 },
901 {
902 .type = AMD_IP_BLOCK_TYPE_VCE,
903 .major = 3,
904 .minor = 0,
905 .rev = 0,
906 .funcs = &vce_v3_0_ip_funcs,
907 },
908};
909
910static const struct amdgpu_ip_block_version cz_ip_blocks[] =
911{
912 /* ORDER MATTERS! */
913 {
914 .type = AMD_IP_BLOCK_TYPE_COMMON,
915 .major = 2,
916 .minor = 0,
917 .rev = 0,
918 .funcs = &vi_common_ip_funcs,
919 },
920 {
921 .type = AMD_IP_BLOCK_TYPE_GMC,
922 .major = 8,
923 .minor = 0,
924 .rev = 0,
925 .funcs = &gmc_v8_0_ip_funcs,
926 },
927 {
928 .type = AMD_IP_BLOCK_TYPE_IH,
929 .major = 3,
930 .minor = 0,
931 .rev = 0,
932 .funcs = &cz_ih_ip_funcs,
933 },
934 {
935 .type = AMD_IP_BLOCK_TYPE_SMC,
936 .major = 8,
937 .minor = 0,
938 .rev = 0,
939 .funcs = &amdgpu_pp_ip_funcs
940 },
941 {
942 .type = AMD_IP_BLOCK_TYPE_DCE,
943 .major = 11,
944 .minor = 0,
945 .rev = 0,
946 .funcs = &dce_v11_0_ip_funcs,
947 },
948 {
949 .type = AMD_IP_BLOCK_TYPE_GFX,
950 .major = 8,
951 .minor = 0,
952 .rev = 0,
953 .funcs = &gfx_v8_0_ip_funcs,
954 },
955 {
956 .type = AMD_IP_BLOCK_TYPE_SDMA,
957 .major = 3,
958 .minor = 0,
959 .rev = 0,
960 .funcs = &sdma_v3_0_ip_funcs,
961 },
962 {
963 .type = AMD_IP_BLOCK_TYPE_UVD,
964 .major = 6,
965 .minor = 0,
966 .rev = 0,
967 .funcs = &uvd_v6_0_ip_funcs,
968 },
969 {
970 .type = AMD_IP_BLOCK_TYPE_VCE,
971 .major = 3,
972 .minor = 0,
973 .rev = 0,
974 .funcs = &vce_v3_0_ip_funcs,
975 },
976#if defined(CONFIG_DRM_AMD_ACP)
977 {
978 .type = AMD_IP_BLOCK_TYPE_ACP,
979 .major = 2,
980 .minor = 2,
981 .rev = 0,
982 .funcs = &acp_ip_funcs,
983 },
984#endif
985};
986
987int vi_set_ip_blocks(struct amdgpu_device *adev)
988{
989 switch (adev->asic_type) {
990 case CHIP_TOPAZ:
991 adev->ip_blocks = topaz_ip_blocks;
992 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
993 break;
994 case CHIP_FIJI:
995 adev->ip_blocks = fiji_ip_blocks;
996 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
997 break;
998 case CHIP_TONGA:
999 adev->ip_blocks = tonga_ip_blocks;
1000 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1001 break;
1002 case CHIP_CARRIZO:
1003 case CHIP_STONEY:
1004 adev->ip_blocks = cz_ip_blocks;
1005 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1006 break;
1007 default:
1008 /* FIXME: not supported yet */
1009 return -EINVAL;
1010 }
1011
1012 return 0;
1013}
1014
1015#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1016#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1017#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1018
1019static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1020{
1021 if (adev->flags & AMD_IS_APU)
1022 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1023 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1024 else
1025 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1026 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1027}
1028
1029static const struct amdgpu_asic_funcs vi_asic_funcs =
1030{
1031 .read_disabled_bios = &vi_read_disabled_bios,
1032 .read_bios_from_rom = &vi_read_bios_from_rom,
1033 .read_register = &vi_read_register,
1034 .reset = &vi_asic_reset,
1035 .set_vga_state = &vi_vga_set_state,
1036 .get_xclk = &vi_get_xclk,
1037 .set_uvd_clocks = &vi_set_uvd_clocks,
1038 .set_vce_clocks = &vi_set_vce_clocks,
1039 .get_cu_info = &gfx_v8_0_get_cu_info,
1040 /* these should be moved to their own ip modules */
1041 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
1042 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
1043};
1044
1045static int vi_common_early_init(void *handle)
1046{
1047 bool smc_enabled = false;
1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1049
1050 if (adev->flags & AMD_IS_APU) {
1051 adev->smc_rreg = &cz_smc_rreg;
1052 adev->smc_wreg = &cz_smc_wreg;
1053 } else {
1054 adev->smc_rreg = &vi_smc_rreg;
1055 adev->smc_wreg = &vi_smc_wreg;
1056 }
1057 adev->pcie_rreg = &vi_pcie_rreg;
1058 adev->pcie_wreg = &vi_pcie_wreg;
1059 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1060 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1061 adev->didt_rreg = &vi_didt_rreg;
1062 adev->didt_wreg = &vi_didt_wreg;
1063
1064 adev->asic_funcs = &vi_asic_funcs;
1065
1066 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1067 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
1068 smc_enabled = true;
1069
1070 adev->rev_id = vi_get_rev_id(adev);
1071 adev->external_rev_id = 0xFF;
1072 switch (adev->asic_type) {
1073 case CHIP_TOPAZ:
1074 adev->cg_flags = 0;
1075 adev->pg_flags = 0;
1076 adev->external_rev_id = 0x1;
1077 break;
1078 case CHIP_FIJI:
1079 adev->cg_flags = 0;
1080 adev->pg_flags = 0;
1081 adev->external_rev_id = adev->rev_id + 0x3c;
1082 break;
1083 case CHIP_TONGA:
1084 adev->cg_flags = 0;
1085 adev->pg_flags = 0;
1086 adev->external_rev_id = adev->rev_id + 0x14;
1087 break;
1088 case CHIP_CARRIZO:
1089 case CHIP_STONEY:
1090 adev->cg_flags = 0;
1091 adev->pg_flags = 0;
1092 adev->external_rev_id = adev->rev_id + 0x1;
1093 break;
1094 default:
1095 /* FIXME: not supported yet */
1096 return -EINVAL;
1097 }
1098
1099 if (amdgpu_smc_load_fw && smc_enabled)
1100 adev->firmware.smu_load = true;
1101
1102 amdgpu_get_pcie_info(adev);
1103
1104 return 0;
1105}
1106
1107static int vi_common_sw_init(void *handle)
1108{
1109 return 0;
1110}
1111
1112static int vi_common_sw_fini(void *handle)
1113{
1114 return 0;
1115}
1116
1117static int vi_common_hw_init(void *handle)
1118{
1119 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120
1121 /* move the golden regs per IP block */
1122 vi_init_golden_registers(adev);
1123 /* enable pcie gen2/3 link */
1124 vi_pcie_gen3_enable(adev);
1125 /* enable aspm */
1126 vi_program_aspm(adev);
1127 /* enable the doorbell aperture */
1128 vi_enable_doorbell_aperture(adev, true);
1129
1130 return 0;
1131}
1132
1133static int vi_common_hw_fini(void *handle)
1134{
1135 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1136
1137 /* enable the doorbell aperture */
1138 vi_enable_doorbell_aperture(adev, false);
1139
1140 return 0;
1141}
1142
1143static int vi_common_suspend(void *handle)
1144{
1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1146
1147 return vi_common_hw_fini(adev);
1148}
1149
1150static int vi_common_resume(void *handle)
1151{
1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1153
1154 return vi_common_hw_init(adev);
1155}
1156
1157static bool vi_common_is_idle(void *handle)
1158{
1159 return true;
1160}
1161
1162static int vi_common_wait_for_idle(void *handle)
1163{
1164 return 0;
1165}
1166
1167static void vi_common_print_status(void *handle)
1168{
1169 return;
1170}
1171
1172static int vi_common_soft_reset(void *handle)
1173{
1174 return 0;
1175}
1176
1177static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1178 bool enable)
1179{
1180 uint32_t temp, data;
1181
1182 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1183
1184 if (enable)
1185 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1186 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1187 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1188 else
1189 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1190 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1191 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1192
1193 if (temp != data)
1194 WREG32_PCIE(ixPCIE_CNTL2, data);
1195}
1196
1197static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1198 bool enable)
1199{
1200 uint32_t temp, data;
1201
1202 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1203
1204 if (enable)
1205 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1206 else
1207 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1208
1209 if (temp != data)
1210 WREG32(mmHDP_HOST_PATH_CNTL, data);
1211}
1212
1213static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
1214 bool enable)
1215{
1216 uint32_t temp, data;
1217
1218 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1219
1220 if (enable)
1221 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1222 else
1223 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1224
1225 if (temp != data)
1226 WREG32(mmHDP_MEM_POWER_LS, data);
1227}
1228
1229static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1230 bool enable)
1231{
1232 uint32_t temp, data;
1233
1234 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1235
1236 if (enable)
1237 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1238 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1239 else
1240 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1241 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1242
1243 if (temp != data)
1244 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1245}
1246
1247static int vi_common_set_clockgating_state(void *handle,
1248 enum amd_clockgating_state state)
1249{
1250 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1251
1252 switch (adev->asic_type) {
1253 case CHIP_FIJI:
1254 fiji_update_bif_medium_grain_light_sleep(adev,
1255 state == AMD_CG_STATE_GATE ? true : false);
1256 fiji_update_hdp_medium_grain_clock_gating(adev,
1257 state == AMD_CG_STATE_GATE ? true : false);
1258 fiji_update_hdp_light_sleep(adev,
1259 state == AMD_CG_STATE_GATE ? true : false);
1260 fiji_update_rom_medium_grain_clock_gating(adev,
1261 state == AMD_CG_STATE_GATE ? true : false);
1262 break;
1263 default:
1264 break;
1265 }
1266 return 0;
1267}
1268
1269static int vi_common_set_powergating_state(void *handle,
1270 enum amd_powergating_state state)
1271{
1272 return 0;
1273}
1274
1275const struct amd_ip_funcs vi_common_ip_funcs = {
1276 .early_init = vi_common_early_init,
1277 .late_init = NULL,
1278 .sw_init = vi_common_sw_init,
1279 .sw_fini = vi_common_sw_fini,
1280 .hw_init = vi_common_hw_init,
1281 .hw_fini = vi_common_hw_fini,
1282 .suspend = vi_common_suspend,
1283 .resume = vi_common_resume,
1284 .is_idle = vi_common_is_idle,
1285 .wait_for_idle = vi_common_wait_for_idle,
1286 .soft_reset = vi_common_soft_reset,
1287 .print_status = vi_common_print_status,
1288 .set_clockgating_state = vi_common_set_clockgating_state,
1289 .set_powergating_state = vi_common_set_powergating_state,
1290};
1291
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25#include <linux/slab.h>
26
27#include "amdgpu.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "atom.h"
34#include "amd_pcie.h"
35
36#include "gmc/gmc_8_1_d.h"
37#include "gmc/gmc_8_1_sh_mask.h"
38
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "gca/gfx_8_0_d.h"
46#include "gca/gfx_8_0_sh_mask.h"
47
48#include "smu/smu_7_1_1_d.h"
49#include "smu/smu_7_1_1_sh_mask.h"
50
51#include "uvd/uvd_5_0_d.h"
52#include "uvd/uvd_5_0_sh_mask.h"
53
54#include "vce/vce_3_0_d.h"
55#include "vce/vce_3_0_sh_mask.h"
56
57#include "dce/dce_10_0_d.h"
58#include "dce/dce_10_0_sh_mask.h"
59
60#include "vid.h"
61#include "vi.h"
62#include "gmc_v8_0.h"
63#include "gmc_v7_0.h"
64#include "gfx_v8_0.h"
65#include "sdma_v2_4.h"
66#include "sdma_v3_0.h"
67#include "dce_v10_0.h"
68#include "dce_v11_0.h"
69#include "iceland_ih.h"
70#include "tonga_ih.h"
71#include "cz_ih.h"
72#include "uvd_v5_0.h"
73#include "uvd_v6_0.h"
74#include "vce_v3_0.h"
75#if defined(CONFIG_DRM_AMD_ACP)
76#include "amdgpu_acp.h"
77#endif
78#include "dce_virtual.h"
79#include "mxgpu_vi.h"
80#include "amdgpu_dm.h"
81
82/*
83 * Indirect registers accessor
84 */
85static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
86{
87 unsigned long flags;
88 u32 r;
89
90 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
91 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
92 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
93 r = RREG32_NO_KIQ(mmPCIE_DATA);
94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
95 return r;
96}
97
98static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
99{
100 unsigned long flags;
101
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
103 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
104 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
105 WREG32_NO_KIQ(mmPCIE_DATA, v);
106 (void)RREG32_NO_KIQ(mmPCIE_DATA);
107 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
108}
109
110static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
111{
112 unsigned long flags;
113 u32 r;
114
115 spin_lock_irqsave(&adev->smc_idx_lock, flags);
116 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
117 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
118 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
119 return r;
120}
121
122static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
123{
124 unsigned long flags;
125
126 spin_lock_irqsave(&adev->smc_idx_lock, flags);
127 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
128 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
129 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
130}
131
132/* smu_8_0_d.h */
133#define mmMP0PUB_IND_INDEX 0x180
134#define mmMP0PUB_IND_DATA 0x181
135
136static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
137{
138 unsigned long flags;
139 u32 r;
140
141 spin_lock_irqsave(&adev->smc_idx_lock, flags);
142 WREG32(mmMP0PUB_IND_INDEX, (reg));
143 r = RREG32(mmMP0PUB_IND_DATA);
144 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
145 return r;
146}
147
148static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&adev->smc_idx_lock, flags);
153 WREG32(mmMP0PUB_IND_INDEX, (reg));
154 WREG32(mmMP0PUB_IND_DATA, (v));
155 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
156}
157
158static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
159{
160 unsigned long flags;
161 u32 r;
162
163 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
164 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
165 r = RREG32(mmUVD_CTX_DATA);
166 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
167 return r;
168}
169
170static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
171{
172 unsigned long flags;
173
174 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
175 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
176 WREG32(mmUVD_CTX_DATA, (v));
177 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
178}
179
180static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
181{
182 unsigned long flags;
183 u32 r;
184
185 spin_lock_irqsave(&adev->didt_idx_lock, flags);
186 WREG32(mmDIDT_IND_INDEX, (reg));
187 r = RREG32(mmDIDT_IND_DATA);
188 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
189 return r;
190}
191
192static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
193{
194 unsigned long flags;
195
196 spin_lock_irqsave(&adev->didt_idx_lock, flags);
197 WREG32(mmDIDT_IND_INDEX, (reg));
198 WREG32(mmDIDT_IND_DATA, (v));
199 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
200}
201
202static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
203{
204 unsigned long flags;
205 u32 r;
206
207 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
208 WREG32(mmGC_CAC_IND_INDEX, (reg));
209 r = RREG32(mmGC_CAC_IND_DATA);
210 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
211 return r;
212}
213
214static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
215{
216 unsigned long flags;
217
218 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
219 WREG32(mmGC_CAC_IND_INDEX, (reg));
220 WREG32(mmGC_CAC_IND_DATA, (v));
221 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
222}
223
224
225static const u32 tonga_mgcg_cgcg_init[] =
226{
227 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
228 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
229 mmPCIE_DATA, 0x000f0000, 0x00000000,
230 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
231 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
232 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
233 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
234};
235
236static const u32 fiji_mgcg_cgcg_init[] =
237{
238 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
239 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
240 mmPCIE_DATA, 0x000f0000, 0x00000000,
241 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
242 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
243 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
244 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
245};
246
247static const u32 iceland_mgcg_cgcg_init[] =
248{
249 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
250 mmPCIE_DATA, 0x000f0000, 0x00000000,
251 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
252 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
253 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
254};
255
256static const u32 cz_mgcg_cgcg_init[] =
257{
258 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
259 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
260 mmPCIE_DATA, 0x000f0000, 0x00000000,
261 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
262 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
263};
264
265static const u32 stoney_mgcg_cgcg_init[] =
266{
267 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
268 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
269 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
270};
271
272static void vi_init_golden_registers(struct amdgpu_device *adev)
273{
274 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
275 mutex_lock(&adev->grbm_idx_mutex);
276
277 if (amdgpu_sriov_vf(adev)) {
278 xgpu_vi_init_golden_registers(adev);
279 mutex_unlock(&adev->grbm_idx_mutex);
280 return;
281 }
282
283 switch (adev->asic_type) {
284 case CHIP_TOPAZ:
285 amdgpu_device_program_register_sequence(adev,
286 iceland_mgcg_cgcg_init,
287 ARRAY_SIZE(iceland_mgcg_cgcg_init));
288 break;
289 case CHIP_FIJI:
290 amdgpu_device_program_register_sequence(adev,
291 fiji_mgcg_cgcg_init,
292 ARRAY_SIZE(fiji_mgcg_cgcg_init));
293 break;
294 case CHIP_TONGA:
295 amdgpu_device_program_register_sequence(adev,
296 tonga_mgcg_cgcg_init,
297 ARRAY_SIZE(tonga_mgcg_cgcg_init));
298 break;
299 case CHIP_CARRIZO:
300 amdgpu_device_program_register_sequence(adev,
301 cz_mgcg_cgcg_init,
302 ARRAY_SIZE(cz_mgcg_cgcg_init));
303 break;
304 case CHIP_STONEY:
305 amdgpu_device_program_register_sequence(adev,
306 stoney_mgcg_cgcg_init,
307 ARRAY_SIZE(stoney_mgcg_cgcg_init));
308 break;
309 case CHIP_POLARIS10:
310 case CHIP_POLARIS11:
311 case CHIP_POLARIS12:
312 case CHIP_VEGAM:
313 default:
314 break;
315 }
316 mutex_unlock(&adev->grbm_idx_mutex);
317}
318
319/**
320 * vi_get_xclk - get the xclk
321 *
322 * @adev: amdgpu_device pointer
323 *
324 * Returns the reference clock used by the gfx engine
325 * (VI).
326 */
327static u32 vi_get_xclk(struct amdgpu_device *adev)
328{
329 u32 reference_clock = adev->clock.spll.reference_freq;
330 u32 tmp;
331
332 if (adev->flags & AMD_IS_APU)
333 return reference_clock;
334
335 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
336 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
337 return 1000;
338
339 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
340 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
341 return reference_clock / 4;
342
343 return reference_clock;
344}
345
346/**
347 * vi_srbm_select - select specific register instances
348 *
349 * @adev: amdgpu_device pointer
350 * @me: selected ME (micro engine)
351 * @pipe: pipe
352 * @queue: queue
353 * @vmid: VMID
354 *
355 * Switches the currently active registers instances. Some
356 * registers are instanced per VMID, others are instanced per
357 * me/pipe/queue combination.
358 */
359void vi_srbm_select(struct amdgpu_device *adev,
360 u32 me, u32 pipe, u32 queue, u32 vmid)
361{
362 u32 srbm_gfx_cntl = 0;
363 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
364 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
365 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
366 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
367 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
368}
369
370static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
371{
372 /* todo */
373}
374
375static bool vi_read_disabled_bios(struct amdgpu_device *adev)
376{
377 u32 bus_cntl;
378 u32 d1vga_control = 0;
379 u32 d2vga_control = 0;
380 u32 vga_render_control = 0;
381 u32 rom_cntl;
382 bool r;
383
384 bus_cntl = RREG32(mmBUS_CNTL);
385 if (adev->mode_info.num_crtc) {
386 d1vga_control = RREG32(mmD1VGA_CONTROL);
387 d2vga_control = RREG32(mmD2VGA_CONTROL);
388 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
389 }
390 rom_cntl = RREG32_SMC(ixROM_CNTL);
391
392 /* enable the rom */
393 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
394 if (adev->mode_info.num_crtc) {
395 /* Disable VGA mode */
396 WREG32(mmD1VGA_CONTROL,
397 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
398 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
399 WREG32(mmD2VGA_CONTROL,
400 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
401 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
402 WREG32(mmVGA_RENDER_CONTROL,
403 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
404 }
405 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
406
407 r = amdgpu_read_bios(adev);
408
409 /* restore regs */
410 WREG32(mmBUS_CNTL, bus_cntl);
411 if (adev->mode_info.num_crtc) {
412 WREG32(mmD1VGA_CONTROL, d1vga_control);
413 WREG32(mmD2VGA_CONTROL, d2vga_control);
414 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
415 }
416 WREG32_SMC(ixROM_CNTL, rom_cntl);
417 return r;
418}
419
420static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
421 u8 *bios, u32 length_bytes)
422{
423 u32 *dw_ptr;
424 unsigned long flags;
425 u32 i, length_dw;
426
427 if (bios == NULL)
428 return false;
429 if (length_bytes == 0)
430 return false;
431 /* APU vbios image is part of sbios image */
432 if (adev->flags & AMD_IS_APU)
433 return false;
434
435 dw_ptr = (u32 *)bios;
436 length_dw = ALIGN(length_bytes, 4) / 4;
437 /* take the smc lock since we are using the smc index */
438 spin_lock_irqsave(&adev->smc_idx_lock, flags);
439 /* set rom index to 0 */
440 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
441 WREG32(mmSMC_IND_DATA_11, 0);
442 /* set index to data for continous read */
443 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
444 for (i = 0; i < length_dw; i++)
445 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
446 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
447
448 return true;
449}
450
451static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
452{
453 uint32_t reg = 0;
454
455 if (adev->asic_type == CHIP_TONGA ||
456 adev->asic_type == CHIP_FIJI) {
457 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
458 /* bit0: 0 means pf and 1 means vf */
459 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
460 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
461 /* bit31: 0 means disable IOV and 1 means enable */
462 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
463 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
464 }
465
466 if (reg == 0) {
467 if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
468 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
469 }
470}
471
472static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
473 {mmGRBM_STATUS},
474 {mmGRBM_STATUS2},
475 {mmGRBM_STATUS_SE0},
476 {mmGRBM_STATUS_SE1},
477 {mmGRBM_STATUS_SE2},
478 {mmGRBM_STATUS_SE3},
479 {mmSRBM_STATUS},
480 {mmSRBM_STATUS2},
481 {mmSRBM_STATUS3},
482 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
483 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
484 {mmCP_STAT},
485 {mmCP_STALLED_STAT1},
486 {mmCP_STALLED_STAT2},
487 {mmCP_STALLED_STAT3},
488 {mmCP_CPF_BUSY_STAT},
489 {mmCP_CPF_STALLED_STAT1},
490 {mmCP_CPF_STATUS},
491 {mmCP_CPC_BUSY_STAT},
492 {mmCP_CPC_STALLED_STAT1},
493 {mmCP_CPC_STATUS},
494 {mmGB_ADDR_CONFIG},
495 {mmMC_ARB_RAMCFG},
496 {mmGB_TILE_MODE0},
497 {mmGB_TILE_MODE1},
498 {mmGB_TILE_MODE2},
499 {mmGB_TILE_MODE3},
500 {mmGB_TILE_MODE4},
501 {mmGB_TILE_MODE5},
502 {mmGB_TILE_MODE6},
503 {mmGB_TILE_MODE7},
504 {mmGB_TILE_MODE8},
505 {mmGB_TILE_MODE9},
506 {mmGB_TILE_MODE10},
507 {mmGB_TILE_MODE11},
508 {mmGB_TILE_MODE12},
509 {mmGB_TILE_MODE13},
510 {mmGB_TILE_MODE14},
511 {mmGB_TILE_MODE15},
512 {mmGB_TILE_MODE16},
513 {mmGB_TILE_MODE17},
514 {mmGB_TILE_MODE18},
515 {mmGB_TILE_MODE19},
516 {mmGB_TILE_MODE20},
517 {mmGB_TILE_MODE21},
518 {mmGB_TILE_MODE22},
519 {mmGB_TILE_MODE23},
520 {mmGB_TILE_MODE24},
521 {mmGB_TILE_MODE25},
522 {mmGB_TILE_MODE26},
523 {mmGB_TILE_MODE27},
524 {mmGB_TILE_MODE28},
525 {mmGB_TILE_MODE29},
526 {mmGB_TILE_MODE30},
527 {mmGB_TILE_MODE31},
528 {mmGB_MACROTILE_MODE0},
529 {mmGB_MACROTILE_MODE1},
530 {mmGB_MACROTILE_MODE2},
531 {mmGB_MACROTILE_MODE3},
532 {mmGB_MACROTILE_MODE4},
533 {mmGB_MACROTILE_MODE5},
534 {mmGB_MACROTILE_MODE6},
535 {mmGB_MACROTILE_MODE7},
536 {mmGB_MACROTILE_MODE8},
537 {mmGB_MACROTILE_MODE9},
538 {mmGB_MACROTILE_MODE10},
539 {mmGB_MACROTILE_MODE11},
540 {mmGB_MACROTILE_MODE12},
541 {mmGB_MACROTILE_MODE13},
542 {mmGB_MACROTILE_MODE14},
543 {mmGB_MACROTILE_MODE15},
544 {mmCC_RB_BACKEND_DISABLE, true},
545 {mmGC_USER_RB_BACKEND_DISABLE, true},
546 {mmGB_BACKEND_MAP, false},
547 {mmPA_SC_RASTER_CONFIG, true},
548 {mmPA_SC_RASTER_CONFIG_1, true},
549};
550
551static uint32_t vi_get_register_value(struct amdgpu_device *adev,
552 bool indexed, u32 se_num,
553 u32 sh_num, u32 reg_offset)
554{
555 if (indexed) {
556 uint32_t val;
557 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
558 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
559
560 switch (reg_offset) {
561 case mmCC_RB_BACKEND_DISABLE:
562 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
563 case mmGC_USER_RB_BACKEND_DISABLE:
564 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
565 case mmPA_SC_RASTER_CONFIG:
566 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
567 case mmPA_SC_RASTER_CONFIG_1:
568 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
569 }
570
571 mutex_lock(&adev->grbm_idx_mutex);
572 if (se_num != 0xffffffff || sh_num != 0xffffffff)
573 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
574
575 val = RREG32(reg_offset);
576
577 if (se_num != 0xffffffff || sh_num != 0xffffffff)
578 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
579 mutex_unlock(&adev->grbm_idx_mutex);
580 return val;
581 } else {
582 unsigned idx;
583
584 switch (reg_offset) {
585 case mmGB_ADDR_CONFIG:
586 return adev->gfx.config.gb_addr_config;
587 case mmMC_ARB_RAMCFG:
588 return adev->gfx.config.mc_arb_ramcfg;
589 case mmGB_TILE_MODE0:
590 case mmGB_TILE_MODE1:
591 case mmGB_TILE_MODE2:
592 case mmGB_TILE_MODE3:
593 case mmGB_TILE_MODE4:
594 case mmGB_TILE_MODE5:
595 case mmGB_TILE_MODE6:
596 case mmGB_TILE_MODE7:
597 case mmGB_TILE_MODE8:
598 case mmGB_TILE_MODE9:
599 case mmGB_TILE_MODE10:
600 case mmGB_TILE_MODE11:
601 case mmGB_TILE_MODE12:
602 case mmGB_TILE_MODE13:
603 case mmGB_TILE_MODE14:
604 case mmGB_TILE_MODE15:
605 case mmGB_TILE_MODE16:
606 case mmGB_TILE_MODE17:
607 case mmGB_TILE_MODE18:
608 case mmGB_TILE_MODE19:
609 case mmGB_TILE_MODE20:
610 case mmGB_TILE_MODE21:
611 case mmGB_TILE_MODE22:
612 case mmGB_TILE_MODE23:
613 case mmGB_TILE_MODE24:
614 case mmGB_TILE_MODE25:
615 case mmGB_TILE_MODE26:
616 case mmGB_TILE_MODE27:
617 case mmGB_TILE_MODE28:
618 case mmGB_TILE_MODE29:
619 case mmGB_TILE_MODE30:
620 case mmGB_TILE_MODE31:
621 idx = (reg_offset - mmGB_TILE_MODE0);
622 return adev->gfx.config.tile_mode_array[idx];
623 case mmGB_MACROTILE_MODE0:
624 case mmGB_MACROTILE_MODE1:
625 case mmGB_MACROTILE_MODE2:
626 case mmGB_MACROTILE_MODE3:
627 case mmGB_MACROTILE_MODE4:
628 case mmGB_MACROTILE_MODE5:
629 case mmGB_MACROTILE_MODE6:
630 case mmGB_MACROTILE_MODE7:
631 case mmGB_MACROTILE_MODE8:
632 case mmGB_MACROTILE_MODE9:
633 case mmGB_MACROTILE_MODE10:
634 case mmGB_MACROTILE_MODE11:
635 case mmGB_MACROTILE_MODE12:
636 case mmGB_MACROTILE_MODE13:
637 case mmGB_MACROTILE_MODE14:
638 case mmGB_MACROTILE_MODE15:
639 idx = (reg_offset - mmGB_MACROTILE_MODE0);
640 return adev->gfx.config.macrotile_mode_array[idx];
641 default:
642 return RREG32(reg_offset);
643 }
644 }
645}
646
647static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
648 u32 sh_num, u32 reg_offset, u32 *value)
649{
650 uint32_t i;
651
652 *value = 0;
653 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
654 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
655
656 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
657 continue;
658
659 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
660 reg_offset);
661 return 0;
662 }
663 return -EINVAL;
664}
665
666static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
667{
668 u32 i;
669
670 dev_info(adev->dev, "GPU pci config reset\n");
671
672 /* disable BM */
673 pci_clear_master(adev->pdev);
674 /* reset */
675 amdgpu_device_pci_config_reset(adev);
676
677 udelay(100);
678
679 /* wait for asic to come out of reset */
680 for (i = 0; i < adev->usec_timeout; i++) {
681 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
682 /* enable BM */
683 pci_set_master(adev->pdev);
684 adev->has_hw_reset = true;
685 return 0;
686 }
687 udelay(1);
688 }
689 return -EINVAL;
690}
691
692/**
693 * vi_asic_reset - soft reset GPU
694 *
695 * @adev: amdgpu_device pointer
696 *
697 * Look up which blocks are hung and attempt
698 * to reset them.
699 * Returns 0 for success.
700 */
701static int vi_asic_reset(struct amdgpu_device *adev)
702{
703 int r;
704
705 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
706
707 r = vi_gpu_pci_config_reset(adev);
708
709 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
710
711 return r;
712}
713
714static enum amd_reset_method
715vi_asic_reset_method(struct amdgpu_device *adev)
716{
717 return AMD_RESET_METHOD_LEGACY;
718}
719
720static u32 vi_get_config_memsize(struct amdgpu_device *adev)
721{
722 return RREG32(mmCONFIG_MEMSIZE);
723}
724
725static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
726 u32 cntl_reg, u32 status_reg)
727{
728 int r, i;
729 struct atom_clock_dividers dividers;
730 uint32_t tmp;
731
732 r = amdgpu_atombios_get_clock_dividers(adev,
733 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
734 clock, false, ÷rs);
735 if (r)
736 return r;
737
738 tmp = RREG32_SMC(cntl_reg);
739
740 if (adev->flags & AMD_IS_APU)
741 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
742 else
743 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
744 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
745 tmp |= dividers.post_divider;
746 WREG32_SMC(cntl_reg, tmp);
747
748 for (i = 0; i < 100; i++) {
749 tmp = RREG32_SMC(status_reg);
750 if (adev->flags & AMD_IS_APU) {
751 if (tmp & 0x10000)
752 break;
753 } else {
754 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
755 break;
756 }
757 mdelay(10);
758 }
759 if (i == 100)
760 return -ETIMEDOUT;
761 return 0;
762}
763
764#define ixGNB_CLK1_DFS_CNTL 0xD82200F0
765#define ixGNB_CLK1_STATUS 0xD822010C
766#define ixGNB_CLK2_DFS_CNTL 0xD8220110
767#define ixGNB_CLK2_STATUS 0xD822012C
768#define ixGNB_CLK3_DFS_CNTL 0xD8220130
769#define ixGNB_CLK3_STATUS 0xD822014C
770
771static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
772{
773 int r;
774
775 if (adev->flags & AMD_IS_APU) {
776 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
777 if (r)
778 return r;
779
780 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
781 if (r)
782 return r;
783 } else {
784 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
785 if (r)
786 return r;
787
788 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
789 if (r)
790 return r;
791 }
792
793 return 0;
794}
795
796static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
797{
798 int r, i;
799 struct atom_clock_dividers dividers;
800 u32 tmp;
801 u32 reg_ctrl;
802 u32 reg_status;
803 u32 status_mask;
804 u32 reg_mask;
805
806 if (adev->flags & AMD_IS_APU) {
807 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
808 reg_status = ixGNB_CLK3_STATUS;
809 status_mask = 0x00010000;
810 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
811 } else {
812 reg_ctrl = ixCG_ECLK_CNTL;
813 reg_status = ixCG_ECLK_STATUS;
814 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
815 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
816 }
817
818 r = amdgpu_atombios_get_clock_dividers(adev,
819 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
820 ecclk, false, ÷rs);
821 if (r)
822 return r;
823
824 for (i = 0; i < 100; i++) {
825 if (RREG32_SMC(reg_status) & status_mask)
826 break;
827 mdelay(10);
828 }
829
830 if (i == 100)
831 return -ETIMEDOUT;
832
833 tmp = RREG32_SMC(reg_ctrl);
834 tmp &= ~reg_mask;
835 tmp |= dividers.post_divider;
836 WREG32_SMC(reg_ctrl, tmp);
837
838 for (i = 0; i < 100; i++) {
839 if (RREG32_SMC(reg_status) & status_mask)
840 break;
841 mdelay(10);
842 }
843
844 if (i == 100)
845 return -ETIMEDOUT;
846
847 return 0;
848}
849
850static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
851{
852 if (pci_is_root_bus(adev->pdev->bus))
853 return;
854
855 if (amdgpu_pcie_gen2 == 0)
856 return;
857
858 if (adev->flags & AMD_IS_APU)
859 return;
860
861 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
862 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
863 return;
864
865 /* todo */
866}
867
868static void vi_program_aspm(struct amdgpu_device *adev)
869{
870
871 if (amdgpu_aspm == 0)
872 return;
873
874 /* todo */
875}
876
877static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
878 bool enable)
879{
880 u32 tmp;
881
882 /* not necessary on CZ */
883 if (adev->flags & AMD_IS_APU)
884 return;
885
886 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
887 if (enable)
888 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
889 else
890 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
891
892 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
893}
894
895#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
896#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
897#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
898
899static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
900{
901 if (adev->flags & AMD_IS_APU)
902 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
903 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
904 else
905 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
906 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
907}
908
909static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
910{
911 if (!ring || !ring->funcs->emit_wreg) {
912 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
913 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
914 } else {
915 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
916 }
917}
918
919static void vi_invalidate_hdp(struct amdgpu_device *adev,
920 struct amdgpu_ring *ring)
921{
922 if (!ring || !ring->funcs->emit_wreg) {
923 WREG32(mmHDP_DEBUG0, 1);
924 RREG32(mmHDP_DEBUG0);
925 } else {
926 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
927 }
928}
929
930static bool vi_need_full_reset(struct amdgpu_device *adev)
931{
932 switch (adev->asic_type) {
933 case CHIP_CARRIZO:
934 case CHIP_STONEY:
935 /* CZ has hang issues with full reset at the moment */
936 return false;
937 case CHIP_FIJI:
938 case CHIP_TONGA:
939 /* XXX: soft reset should work on fiji and tonga */
940 return true;
941 case CHIP_POLARIS10:
942 case CHIP_POLARIS11:
943 case CHIP_POLARIS12:
944 case CHIP_TOPAZ:
945 default:
946 /* change this when we support soft reset */
947 return true;
948 }
949}
950
951static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
952 uint64_t *count1)
953{
954 uint32_t perfctr = 0;
955 uint64_t cnt0_of, cnt1_of;
956 int tmp;
957
958 /* This reports 0 on APUs, so return to avoid writing/reading registers
959 * that may or may not be different from their GPU counterparts
960 */
961 if (adev->flags & AMD_IS_APU)
962 return;
963
964 /* Set the 2 events that we wish to watch, defined above */
965 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
966 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
967 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
968
969 /* Write to enable desired perf counters */
970 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
971 /* Zero out and enable the perf counters
972 * Write 0x5:
973 * Bit 0 = Start all counters(1)
974 * Bit 2 = Global counter reset enable(1)
975 */
976 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
977
978 msleep(1000);
979
980 /* Load the shadow and disable the perf counters
981 * Write 0x2:
982 * Bit 0 = Stop counters(0)
983 * Bit 1 = Load the shadow counters(1)
984 */
985 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
986
987 /* Read register values to get any >32bit overflow */
988 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
989 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
990 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
991
992 /* Get the values and add the overflow */
993 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
994 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
995}
996
997static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
998{
999 uint64_t nak_r, nak_g;
1000
1001 /* Get the number of NAKs received and generated */
1002 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1003 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1004
1005 /* Add the total number of NAKs, i.e the number of replays */
1006 return (nak_r + nak_g);
1007}
1008
1009static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1010{
1011 u32 clock_cntl, pc;
1012
1013 if (adev->flags & AMD_IS_APU)
1014 return false;
1015
1016 /* check if the SMC is already running */
1017 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
1018 pc = RREG32_SMC(ixSMC_PC_C);
1019 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
1020 (0x20100 <= pc))
1021 return true;
1022
1023 return false;
1024}
1025
1026static const struct amdgpu_asic_funcs vi_asic_funcs =
1027{
1028 .read_disabled_bios = &vi_read_disabled_bios,
1029 .read_bios_from_rom = &vi_read_bios_from_rom,
1030 .read_register = &vi_read_register,
1031 .reset = &vi_asic_reset,
1032 .reset_method = &vi_asic_reset_method,
1033 .set_vga_state = &vi_vga_set_state,
1034 .get_xclk = &vi_get_xclk,
1035 .set_uvd_clocks = &vi_set_uvd_clocks,
1036 .set_vce_clocks = &vi_set_vce_clocks,
1037 .get_config_memsize = &vi_get_config_memsize,
1038 .flush_hdp = &vi_flush_hdp,
1039 .invalidate_hdp = &vi_invalidate_hdp,
1040 .need_full_reset = &vi_need_full_reset,
1041 .init_doorbell_index = &legacy_doorbell_index_init,
1042 .get_pcie_usage = &vi_get_pcie_usage,
1043 .need_reset_on_init = &vi_need_reset_on_init,
1044 .get_pcie_replay_count = &vi_get_pcie_replay_count,
1045};
1046
1047#define CZ_REV_BRISTOL(rev) \
1048 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
1049
1050static int vi_common_early_init(void *handle)
1051{
1052 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054 if (adev->flags & AMD_IS_APU) {
1055 adev->smc_rreg = &cz_smc_rreg;
1056 adev->smc_wreg = &cz_smc_wreg;
1057 } else {
1058 adev->smc_rreg = &vi_smc_rreg;
1059 adev->smc_wreg = &vi_smc_wreg;
1060 }
1061 adev->pcie_rreg = &vi_pcie_rreg;
1062 adev->pcie_wreg = &vi_pcie_wreg;
1063 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1064 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1065 adev->didt_rreg = &vi_didt_rreg;
1066 adev->didt_wreg = &vi_didt_wreg;
1067 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1068 adev->gc_cac_wreg = &vi_gc_cac_wreg;
1069
1070 adev->asic_funcs = &vi_asic_funcs;
1071
1072 adev->rev_id = vi_get_rev_id(adev);
1073 adev->external_rev_id = 0xFF;
1074 switch (adev->asic_type) {
1075 case CHIP_TOPAZ:
1076 adev->cg_flags = 0;
1077 adev->pg_flags = 0;
1078 adev->external_rev_id = 0x1;
1079 break;
1080 case CHIP_FIJI:
1081 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1082 AMD_CG_SUPPORT_GFX_MGLS |
1083 AMD_CG_SUPPORT_GFX_RLC_LS |
1084 AMD_CG_SUPPORT_GFX_CP_LS |
1085 AMD_CG_SUPPORT_GFX_CGTS |
1086 AMD_CG_SUPPORT_GFX_CGTS_LS |
1087 AMD_CG_SUPPORT_GFX_CGCG |
1088 AMD_CG_SUPPORT_GFX_CGLS |
1089 AMD_CG_SUPPORT_SDMA_MGCG |
1090 AMD_CG_SUPPORT_SDMA_LS |
1091 AMD_CG_SUPPORT_BIF_LS |
1092 AMD_CG_SUPPORT_HDP_MGCG |
1093 AMD_CG_SUPPORT_HDP_LS |
1094 AMD_CG_SUPPORT_ROM_MGCG |
1095 AMD_CG_SUPPORT_MC_MGCG |
1096 AMD_CG_SUPPORT_MC_LS |
1097 AMD_CG_SUPPORT_UVD_MGCG;
1098 adev->pg_flags = 0;
1099 adev->external_rev_id = adev->rev_id + 0x3c;
1100 break;
1101 case CHIP_TONGA:
1102 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1103 AMD_CG_SUPPORT_GFX_CGCG |
1104 AMD_CG_SUPPORT_GFX_CGLS |
1105 AMD_CG_SUPPORT_SDMA_MGCG |
1106 AMD_CG_SUPPORT_SDMA_LS |
1107 AMD_CG_SUPPORT_BIF_LS |
1108 AMD_CG_SUPPORT_HDP_MGCG |
1109 AMD_CG_SUPPORT_HDP_LS |
1110 AMD_CG_SUPPORT_ROM_MGCG |
1111 AMD_CG_SUPPORT_MC_MGCG |
1112 AMD_CG_SUPPORT_MC_LS |
1113 AMD_CG_SUPPORT_DRM_LS |
1114 AMD_CG_SUPPORT_UVD_MGCG;
1115 adev->pg_flags = 0;
1116 adev->external_rev_id = adev->rev_id + 0x14;
1117 break;
1118 case CHIP_POLARIS11:
1119 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1120 AMD_CG_SUPPORT_GFX_RLC_LS |
1121 AMD_CG_SUPPORT_GFX_CP_LS |
1122 AMD_CG_SUPPORT_GFX_CGCG |
1123 AMD_CG_SUPPORT_GFX_CGLS |
1124 AMD_CG_SUPPORT_GFX_3D_CGCG |
1125 AMD_CG_SUPPORT_GFX_3D_CGLS |
1126 AMD_CG_SUPPORT_SDMA_MGCG |
1127 AMD_CG_SUPPORT_SDMA_LS |
1128 AMD_CG_SUPPORT_BIF_MGCG |
1129 AMD_CG_SUPPORT_BIF_LS |
1130 AMD_CG_SUPPORT_HDP_MGCG |
1131 AMD_CG_SUPPORT_HDP_LS |
1132 AMD_CG_SUPPORT_ROM_MGCG |
1133 AMD_CG_SUPPORT_MC_MGCG |
1134 AMD_CG_SUPPORT_MC_LS |
1135 AMD_CG_SUPPORT_DRM_LS |
1136 AMD_CG_SUPPORT_UVD_MGCG |
1137 AMD_CG_SUPPORT_VCE_MGCG;
1138 adev->pg_flags = 0;
1139 adev->external_rev_id = adev->rev_id + 0x5A;
1140 break;
1141 case CHIP_POLARIS10:
1142 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1143 AMD_CG_SUPPORT_GFX_RLC_LS |
1144 AMD_CG_SUPPORT_GFX_CP_LS |
1145 AMD_CG_SUPPORT_GFX_CGCG |
1146 AMD_CG_SUPPORT_GFX_CGLS |
1147 AMD_CG_SUPPORT_GFX_3D_CGCG |
1148 AMD_CG_SUPPORT_GFX_3D_CGLS |
1149 AMD_CG_SUPPORT_SDMA_MGCG |
1150 AMD_CG_SUPPORT_SDMA_LS |
1151 AMD_CG_SUPPORT_BIF_MGCG |
1152 AMD_CG_SUPPORT_BIF_LS |
1153 AMD_CG_SUPPORT_HDP_MGCG |
1154 AMD_CG_SUPPORT_HDP_LS |
1155 AMD_CG_SUPPORT_ROM_MGCG |
1156 AMD_CG_SUPPORT_MC_MGCG |
1157 AMD_CG_SUPPORT_MC_LS |
1158 AMD_CG_SUPPORT_DRM_LS |
1159 AMD_CG_SUPPORT_UVD_MGCG |
1160 AMD_CG_SUPPORT_VCE_MGCG;
1161 adev->pg_flags = 0;
1162 adev->external_rev_id = adev->rev_id + 0x50;
1163 break;
1164 case CHIP_POLARIS12:
1165 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1166 AMD_CG_SUPPORT_GFX_RLC_LS |
1167 AMD_CG_SUPPORT_GFX_CP_LS |
1168 AMD_CG_SUPPORT_GFX_CGCG |
1169 AMD_CG_SUPPORT_GFX_CGLS |
1170 AMD_CG_SUPPORT_GFX_3D_CGCG |
1171 AMD_CG_SUPPORT_GFX_3D_CGLS |
1172 AMD_CG_SUPPORT_SDMA_MGCG |
1173 AMD_CG_SUPPORT_SDMA_LS |
1174 AMD_CG_SUPPORT_BIF_MGCG |
1175 AMD_CG_SUPPORT_BIF_LS |
1176 AMD_CG_SUPPORT_HDP_MGCG |
1177 AMD_CG_SUPPORT_HDP_LS |
1178 AMD_CG_SUPPORT_ROM_MGCG |
1179 AMD_CG_SUPPORT_MC_MGCG |
1180 AMD_CG_SUPPORT_MC_LS |
1181 AMD_CG_SUPPORT_DRM_LS |
1182 AMD_CG_SUPPORT_UVD_MGCG |
1183 AMD_CG_SUPPORT_VCE_MGCG;
1184 adev->pg_flags = 0;
1185 adev->external_rev_id = adev->rev_id + 0x64;
1186 break;
1187 case CHIP_VEGAM:
1188 adev->cg_flags = 0;
1189 /*AMD_CG_SUPPORT_GFX_MGCG |
1190 AMD_CG_SUPPORT_GFX_RLC_LS |
1191 AMD_CG_SUPPORT_GFX_CP_LS |
1192 AMD_CG_SUPPORT_GFX_CGCG |
1193 AMD_CG_SUPPORT_GFX_CGLS |
1194 AMD_CG_SUPPORT_GFX_3D_CGCG |
1195 AMD_CG_SUPPORT_GFX_3D_CGLS |
1196 AMD_CG_SUPPORT_SDMA_MGCG |
1197 AMD_CG_SUPPORT_SDMA_LS |
1198 AMD_CG_SUPPORT_BIF_MGCG |
1199 AMD_CG_SUPPORT_BIF_LS |
1200 AMD_CG_SUPPORT_HDP_MGCG |
1201 AMD_CG_SUPPORT_HDP_LS |
1202 AMD_CG_SUPPORT_ROM_MGCG |
1203 AMD_CG_SUPPORT_MC_MGCG |
1204 AMD_CG_SUPPORT_MC_LS |
1205 AMD_CG_SUPPORT_DRM_LS |
1206 AMD_CG_SUPPORT_UVD_MGCG |
1207 AMD_CG_SUPPORT_VCE_MGCG;*/
1208 adev->pg_flags = 0;
1209 adev->external_rev_id = adev->rev_id + 0x6E;
1210 break;
1211 case CHIP_CARRIZO:
1212 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1213 AMD_CG_SUPPORT_GFX_MGCG |
1214 AMD_CG_SUPPORT_GFX_MGLS |
1215 AMD_CG_SUPPORT_GFX_RLC_LS |
1216 AMD_CG_SUPPORT_GFX_CP_LS |
1217 AMD_CG_SUPPORT_GFX_CGTS |
1218 AMD_CG_SUPPORT_GFX_CGTS_LS |
1219 AMD_CG_SUPPORT_GFX_CGCG |
1220 AMD_CG_SUPPORT_GFX_CGLS |
1221 AMD_CG_SUPPORT_BIF_LS |
1222 AMD_CG_SUPPORT_HDP_MGCG |
1223 AMD_CG_SUPPORT_HDP_LS |
1224 AMD_CG_SUPPORT_SDMA_MGCG |
1225 AMD_CG_SUPPORT_SDMA_LS |
1226 AMD_CG_SUPPORT_VCE_MGCG;
1227 /* rev0 hardware requires workarounds to support PG */
1228 adev->pg_flags = 0;
1229 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1230 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1231 AMD_PG_SUPPORT_GFX_PIPELINE |
1232 AMD_PG_SUPPORT_CP |
1233 AMD_PG_SUPPORT_UVD |
1234 AMD_PG_SUPPORT_VCE;
1235 }
1236 adev->external_rev_id = adev->rev_id + 0x1;
1237 break;
1238 case CHIP_STONEY:
1239 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1240 AMD_CG_SUPPORT_GFX_MGCG |
1241 AMD_CG_SUPPORT_GFX_MGLS |
1242 AMD_CG_SUPPORT_GFX_RLC_LS |
1243 AMD_CG_SUPPORT_GFX_CP_LS |
1244 AMD_CG_SUPPORT_GFX_CGTS |
1245 AMD_CG_SUPPORT_GFX_CGTS_LS |
1246 AMD_CG_SUPPORT_GFX_CGLS |
1247 AMD_CG_SUPPORT_BIF_LS |
1248 AMD_CG_SUPPORT_HDP_MGCG |
1249 AMD_CG_SUPPORT_HDP_LS |
1250 AMD_CG_SUPPORT_SDMA_MGCG |
1251 AMD_CG_SUPPORT_SDMA_LS |
1252 AMD_CG_SUPPORT_VCE_MGCG;
1253 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1254 AMD_PG_SUPPORT_GFX_SMG |
1255 AMD_PG_SUPPORT_GFX_PIPELINE |
1256 AMD_PG_SUPPORT_CP |
1257 AMD_PG_SUPPORT_UVD |
1258 AMD_PG_SUPPORT_VCE;
1259 adev->external_rev_id = adev->rev_id + 0x61;
1260 break;
1261 default:
1262 /* FIXME: not supported yet */
1263 return -EINVAL;
1264 }
1265
1266 if (amdgpu_sriov_vf(adev)) {
1267 amdgpu_virt_init_setting(adev);
1268 xgpu_vi_mailbox_set_irq_funcs(adev);
1269 }
1270
1271 return 0;
1272}
1273
1274static int vi_common_late_init(void *handle)
1275{
1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277
1278 if (amdgpu_sriov_vf(adev))
1279 xgpu_vi_mailbox_get_irq(adev);
1280
1281 return 0;
1282}
1283
1284static int vi_common_sw_init(void *handle)
1285{
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287
1288 if (amdgpu_sriov_vf(adev))
1289 xgpu_vi_mailbox_add_irq_id(adev);
1290
1291 return 0;
1292}
1293
1294static int vi_common_sw_fini(void *handle)
1295{
1296 return 0;
1297}
1298
1299static int vi_common_hw_init(void *handle)
1300{
1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1302
1303 /* move the golden regs per IP block */
1304 vi_init_golden_registers(adev);
1305 /* enable pcie gen2/3 link */
1306 vi_pcie_gen3_enable(adev);
1307 /* enable aspm */
1308 vi_program_aspm(adev);
1309 /* enable the doorbell aperture */
1310 vi_enable_doorbell_aperture(adev, true);
1311
1312 return 0;
1313}
1314
1315static int vi_common_hw_fini(void *handle)
1316{
1317 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1318
1319 /* enable the doorbell aperture */
1320 vi_enable_doorbell_aperture(adev, false);
1321
1322 if (amdgpu_sriov_vf(adev))
1323 xgpu_vi_mailbox_put_irq(adev);
1324
1325 return 0;
1326}
1327
1328static int vi_common_suspend(void *handle)
1329{
1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331
1332 return vi_common_hw_fini(adev);
1333}
1334
1335static int vi_common_resume(void *handle)
1336{
1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338
1339 return vi_common_hw_init(adev);
1340}
1341
1342static bool vi_common_is_idle(void *handle)
1343{
1344 return true;
1345}
1346
1347static int vi_common_wait_for_idle(void *handle)
1348{
1349 return 0;
1350}
1351
1352static int vi_common_soft_reset(void *handle)
1353{
1354 return 0;
1355}
1356
1357static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1358 bool enable)
1359{
1360 uint32_t temp, data;
1361
1362 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1363
1364 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1365 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1366 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1367 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1368 else
1369 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1370 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1371 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1372
1373 if (temp != data)
1374 WREG32_PCIE(ixPCIE_CNTL2, data);
1375}
1376
1377static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1378 bool enable)
1379{
1380 uint32_t temp, data;
1381
1382 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1383
1384 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1385 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1386 else
1387 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1388
1389 if (temp != data)
1390 WREG32(mmHDP_HOST_PATH_CNTL, data);
1391}
1392
1393static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1394 bool enable)
1395{
1396 uint32_t temp, data;
1397
1398 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1399
1400 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1401 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1402 else
1403 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1404
1405 if (temp != data)
1406 WREG32(mmHDP_MEM_POWER_LS, data);
1407}
1408
1409static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1410 bool enable)
1411{
1412 uint32_t temp, data;
1413
1414 temp = data = RREG32(0x157a);
1415
1416 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1417 data |= 1;
1418 else
1419 data &= ~1;
1420
1421 if (temp != data)
1422 WREG32(0x157a, data);
1423}
1424
1425
1426static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1427 bool enable)
1428{
1429 uint32_t temp, data;
1430
1431 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1432
1433 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1434 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1435 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1436 else
1437 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1438 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1439
1440 if (temp != data)
1441 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1442}
1443
1444static int vi_common_set_clockgating_state_by_smu(void *handle,
1445 enum amd_clockgating_state state)
1446{
1447 uint32_t msg_id, pp_state = 0;
1448 uint32_t pp_support_state = 0;
1449 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1450
1451 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1452 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1453 pp_support_state = PP_STATE_SUPPORT_LS;
1454 pp_state = PP_STATE_LS;
1455 }
1456 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1457 pp_support_state |= PP_STATE_SUPPORT_CG;
1458 pp_state |= PP_STATE_CG;
1459 }
1460 if (state == AMD_CG_STATE_UNGATE)
1461 pp_state = 0;
1462 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1463 PP_BLOCK_SYS_MC,
1464 pp_support_state,
1465 pp_state);
1466 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1467 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1468 }
1469
1470 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1471 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1472 pp_support_state = PP_STATE_SUPPORT_LS;
1473 pp_state = PP_STATE_LS;
1474 }
1475 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1476 pp_support_state |= PP_STATE_SUPPORT_CG;
1477 pp_state |= PP_STATE_CG;
1478 }
1479 if (state == AMD_CG_STATE_UNGATE)
1480 pp_state = 0;
1481 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1482 PP_BLOCK_SYS_SDMA,
1483 pp_support_state,
1484 pp_state);
1485 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1486 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1487 }
1488
1489 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1490 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1491 pp_support_state = PP_STATE_SUPPORT_LS;
1492 pp_state = PP_STATE_LS;
1493 }
1494 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1495 pp_support_state |= PP_STATE_SUPPORT_CG;
1496 pp_state |= PP_STATE_CG;
1497 }
1498 if (state == AMD_CG_STATE_UNGATE)
1499 pp_state = 0;
1500 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1501 PP_BLOCK_SYS_HDP,
1502 pp_support_state,
1503 pp_state);
1504 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1505 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1506 }
1507
1508
1509 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1510 if (state == AMD_CG_STATE_UNGATE)
1511 pp_state = 0;
1512 else
1513 pp_state = PP_STATE_LS;
1514
1515 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1516 PP_BLOCK_SYS_BIF,
1517 PP_STATE_SUPPORT_LS,
1518 pp_state);
1519 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1520 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1521 }
1522 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1523 if (state == AMD_CG_STATE_UNGATE)
1524 pp_state = 0;
1525 else
1526 pp_state = PP_STATE_CG;
1527
1528 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1529 PP_BLOCK_SYS_BIF,
1530 PP_STATE_SUPPORT_CG,
1531 pp_state);
1532 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1533 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1534 }
1535
1536 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1537
1538 if (state == AMD_CG_STATE_UNGATE)
1539 pp_state = 0;
1540 else
1541 pp_state = PP_STATE_LS;
1542
1543 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1544 PP_BLOCK_SYS_DRM,
1545 PP_STATE_SUPPORT_LS,
1546 pp_state);
1547 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1548 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1549 }
1550
1551 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1552
1553 if (state == AMD_CG_STATE_UNGATE)
1554 pp_state = 0;
1555 else
1556 pp_state = PP_STATE_CG;
1557
1558 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1559 PP_BLOCK_SYS_ROM,
1560 PP_STATE_SUPPORT_CG,
1561 pp_state);
1562 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1563 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1564 }
1565 return 0;
1566}
1567
1568static int vi_common_set_clockgating_state(void *handle,
1569 enum amd_clockgating_state state)
1570{
1571 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1572
1573 if (amdgpu_sriov_vf(adev))
1574 return 0;
1575
1576 switch (adev->asic_type) {
1577 case CHIP_FIJI:
1578 vi_update_bif_medium_grain_light_sleep(adev,
1579 state == AMD_CG_STATE_GATE);
1580 vi_update_hdp_medium_grain_clock_gating(adev,
1581 state == AMD_CG_STATE_GATE);
1582 vi_update_hdp_light_sleep(adev,
1583 state == AMD_CG_STATE_GATE);
1584 vi_update_rom_medium_grain_clock_gating(adev,
1585 state == AMD_CG_STATE_GATE);
1586 break;
1587 case CHIP_CARRIZO:
1588 case CHIP_STONEY:
1589 vi_update_bif_medium_grain_light_sleep(adev,
1590 state == AMD_CG_STATE_GATE);
1591 vi_update_hdp_medium_grain_clock_gating(adev,
1592 state == AMD_CG_STATE_GATE);
1593 vi_update_hdp_light_sleep(adev,
1594 state == AMD_CG_STATE_GATE);
1595 vi_update_drm_light_sleep(adev,
1596 state == AMD_CG_STATE_GATE);
1597 break;
1598 case CHIP_TONGA:
1599 case CHIP_POLARIS10:
1600 case CHIP_POLARIS11:
1601 case CHIP_POLARIS12:
1602 case CHIP_VEGAM:
1603 vi_common_set_clockgating_state_by_smu(adev, state);
1604 default:
1605 break;
1606 }
1607 return 0;
1608}
1609
1610static int vi_common_set_powergating_state(void *handle,
1611 enum amd_powergating_state state)
1612{
1613 return 0;
1614}
1615
1616static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1617{
1618 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1619 int data;
1620
1621 if (amdgpu_sriov_vf(adev))
1622 *flags = 0;
1623
1624 /* AMD_CG_SUPPORT_BIF_LS */
1625 data = RREG32_PCIE(ixPCIE_CNTL2);
1626 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1627 *flags |= AMD_CG_SUPPORT_BIF_LS;
1628
1629 /* AMD_CG_SUPPORT_HDP_LS */
1630 data = RREG32(mmHDP_MEM_POWER_LS);
1631 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1632 *flags |= AMD_CG_SUPPORT_HDP_LS;
1633
1634 /* AMD_CG_SUPPORT_HDP_MGCG */
1635 data = RREG32(mmHDP_HOST_PATH_CNTL);
1636 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1637 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1638
1639 /* AMD_CG_SUPPORT_ROM_MGCG */
1640 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1641 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1642 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1643}
1644
1645static const struct amd_ip_funcs vi_common_ip_funcs = {
1646 .name = "vi_common",
1647 .early_init = vi_common_early_init,
1648 .late_init = vi_common_late_init,
1649 .sw_init = vi_common_sw_init,
1650 .sw_fini = vi_common_sw_fini,
1651 .hw_init = vi_common_hw_init,
1652 .hw_fini = vi_common_hw_fini,
1653 .suspend = vi_common_suspend,
1654 .resume = vi_common_resume,
1655 .is_idle = vi_common_is_idle,
1656 .wait_for_idle = vi_common_wait_for_idle,
1657 .soft_reset = vi_common_soft_reset,
1658 .set_clockgating_state = vi_common_set_clockgating_state,
1659 .set_powergating_state = vi_common_set_powergating_state,
1660 .get_clockgating_state = vi_common_get_clockgating_state,
1661};
1662
1663static const struct amdgpu_ip_block_version vi_common_ip_block =
1664{
1665 .type = AMD_IP_BLOCK_TYPE_COMMON,
1666 .major = 1,
1667 .minor = 0,
1668 .rev = 0,
1669 .funcs = &vi_common_ip_funcs,
1670};
1671
1672int vi_set_ip_blocks(struct amdgpu_device *adev)
1673{
1674 /* in early init stage, vbios code won't work */
1675 vi_detect_hw_virtualization(adev);
1676
1677 if (amdgpu_sriov_vf(adev))
1678 adev->virt.ops = &xgpu_vi_virt_ops;
1679
1680 switch (adev->asic_type) {
1681 case CHIP_TOPAZ:
1682 /* topaz has no DCE, UVD, VCE */
1683 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1684 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
1685 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
1686 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1687 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
1688 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1689 if (adev->enable_virtual_display)
1690 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1691 break;
1692 case CHIP_FIJI:
1693 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1694 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
1695 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1696 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1697 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1698 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1699 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1700 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1701#if defined(CONFIG_DRM_AMD_DC)
1702 else if (amdgpu_device_has_dc_support(adev))
1703 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1704#endif
1705 else
1706 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
1707 if (!amdgpu_sriov_vf(adev)) {
1708 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1709 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1710 }
1711 break;
1712 case CHIP_TONGA:
1713 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1714 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1715 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1716 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1717 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1718 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1719 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1720 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1721#if defined(CONFIG_DRM_AMD_DC)
1722 else if (amdgpu_device_has_dc_support(adev))
1723 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1724#endif
1725 else
1726 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
1727 if (!amdgpu_sriov_vf(adev)) {
1728 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
1729 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1730 }
1731 break;
1732 case CHIP_POLARIS10:
1733 case CHIP_POLARIS11:
1734 case CHIP_POLARIS12:
1735 case CHIP_VEGAM:
1736 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1737 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1738 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1739 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1740 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
1741 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1742 if (adev->enable_virtual_display)
1743 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1744#if defined(CONFIG_DRM_AMD_DC)
1745 else if (amdgpu_device_has_dc_support(adev))
1746 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1747#endif
1748 else
1749 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
1750 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
1751 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1752 break;
1753 case CHIP_CARRIZO:
1754 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1755 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1756 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1757 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1758 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1759 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1760 if (adev->enable_virtual_display)
1761 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1762#if defined(CONFIG_DRM_AMD_DC)
1763 else if (amdgpu_device_has_dc_support(adev))
1764 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1765#endif
1766 else
1767 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1768 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1769 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
1770#if defined(CONFIG_DRM_AMD_ACP)
1771 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1772#endif
1773 break;
1774 case CHIP_STONEY:
1775 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1776 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1777 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1778 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1779 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1780 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1781 if (adev->enable_virtual_display)
1782 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1783#if defined(CONFIG_DRM_AMD_DC)
1784 else if (amdgpu_device_has_dc_support(adev))
1785 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1786#endif
1787 else
1788 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1789 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
1790 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1791#if defined(CONFIG_DRM_AMD_ACP)
1792 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1793#endif
1794 break;
1795 default:
1796 /* FIXME: not supported yet */
1797 return -EINVAL;
1798 }
1799
1800 return 0;
1801}
1802
1803void legacy_doorbell_index_init(struct amdgpu_device *adev)
1804{
1805 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
1806 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
1807 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
1808 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
1809 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
1810 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
1811 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
1812 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
1813 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
1814 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
1815 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
1816 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
1817 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
1818 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
1819}