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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/debugfs.h>
25#include <linux/list.h>
26#include <linux/module.h>
27#include <linux/uaccess.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ras.h"
31#include "amdgpu_atomfirmware.h"
32
33const char *ras_error_string[] = {
34 "none",
35 "parity",
36 "single_correctable",
37 "multi_uncorrectable",
38 "poison",
39};
40
41const char *ras_block_string[] = {
42 "umc",
43 "sdma",
44 "gfx",
45 "mmhub",
46 "athub",
47 "pcie_bif",
48 "hdp",
49 "xgmi_wafl",
50 "df",
51 "smn",
52 "sem",
53 "mp0",
54 "mp1",
55 "fuse",
56};
57
58#define ras_err_str(i) (ras_error_string[ffs(i)])
59#define ras_block_str(i) (ras_block_string[i])
60
61#define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1
62#define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2
63#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
64
65/* inject address is 52 bits */
66#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
67
68static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
69 uint64_t offset, uint64_t size,
70 struct amdgpu_bo **bo_ptr);
71static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
72 struct amdgpu_bo **bo_ptr);
73
74static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
75 size_t size, loff_t *pos)
76{
77 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
78 struct ras_query_if info = {
79 .head = obj->head,
80 };
81 ssize_t s;
82 char val[128];
83
84 if (amdgpu_ras_error_query(obj->adev, &info))
85 return -EINVAL;
86
87 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
88 "ue", info.ue_count,
89 "ce", info.ce_count);
90 if (*pos >= s)
91 return 0;
92
93 s -= *pos;
94 s = min_t(u64, s, size);
95
96
97 if (copy_to_user(buf, &val[*pos], s))
98 return -EINVAL;
99
100 *pos += s;
101
102 return s;
103}
104
105static const struct file_operations amdgpu_ras_debugfs_ops = {
106 .owner = THIS_MODULE,
107 .read = amdgpu_ras_debugfs_read,
108 .write = NULL,
109 .llseek = default_llseek
110};
111
112static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
113{
114 int i;
115
116 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
117 *block_id = i;
118 if (strcmp(name, ras_block_str(i)) == 0)
119 return 0;
120 }
121 return -EINVAL;
122}
123
124static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
125 const char __user *buf, size_t size,
126 loff_t *pos, struct ras_debug_if *data)
127{
128 ssize_t s = min_t(u64, 64, size);
129 char str[65];
130 char block_name[33];
131 char err[9] = "ue";
132 int op = -1;
133 int block_id;
134 uint32_t sub_block;
135 u64 address, value;
136
137 if (*pos)
138 return -EINVAL;
139 *pos = size;
140
141 memset(str, 0, sizeof(str));
142 memset(data, 0, sizeof(*data));
143
144 if (copy_from_user(str, buf, s))
145 return -EINVAL;
146
147 if (sscanf(str, "disable %32s", block_name) == 1)
148 op = 0;
149 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
150 op = 1;
151 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
152 op = 2;
153 else if (str[0] && str[1] && str[2] && str[3])
154 /* ascii string, but commands are not matched. */
155 return -EINVAL;
156
157 if (op != -1) {
158 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
159 return -EINVAL;
160
161 data->head.block = block_id;
162 /* only ue and ce errors are supported */
163 if (!memcmp("ue", err, 2))
164 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
165 else if (!memcmp("ce", err, 2))
166 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
167 else
168 return -EINVAL;
169
170 data->op = op;
171
172 if (op == 2) {
173 if (sscanf(str, "%*s %*s %*s %u %llu %llu",
174 &sub_block, &address, &value) != 3)
175 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
176 &sub_block, &address, &value) != 3)
177 return -EINVAL;
178 data->head.sub_block_index = sub_block;
179 data->inject.address = address;
180 data->inject.value = value;
181 }
182 } else {
183 if (size < sizeof(*data))
184 return -EINVAL;
185
186 if (copy_from_user(data, buf, sizeof(*data)))
187 return -EINVAL;
188 }
189
190 return 0;
191}
192/**
193 * DOC: AMDGPU RAS debugfs control interface
194 *
195 * It accepts struct ras_debug_if who has two members.
196 *
197 * First member: ras_debug_if::head or ras_debug_if::inject.
198 *
199 * head is used to indicate which IP block will be under control.
200 *
201 * head has four members, they are block, type, sub_block_index, name.
202 * block: which IP will be under control.
203 * type: what kind of error will be enabled/disabled/injected.
204 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
205 * name: the name of IP.
206 *
207 * inject has two more members than head, they are address, value.
208 * As their names indicate, inject operation will write the
209 * value to the address.
210 *
211 * Second member: struct ras_debug_if::op.
212 * It has three kinds of operations.
213 * 0: disable RAS on the block. Take ::head as its data.
214 * 1: enable RAS on the block. Take ::head as its data.
215 * 2: inject errors on the block. Take ::inject as its data.
216 *
217 * How to use the interface?
218 * programs:
219 * copy the struct ras_debug_if in your codes and initialize it.
220 * write the struct to the control node.
221 *
222 * bash:
223 * echo op block [error [sub_blcok address value]] > .../ras/ras_ctrl
224 * op: disable, enable, inject
225 * disable: only block is needed
226 * enable: block and error are needed
227 * inject: error, address, value are needed
228 * block: umc, smda, gfx, .........
229 * see ras_block_string[] for details
230 * error: ue, ce
231 * ue: multi_uncorrectable
232 * ce: single_correctable
233 * sub_block: sub block index, pass 0 if there is no sub block
234 *
235 * here are some examples for bash commands,
236 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
237 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
238 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
239 *
240 * How to check the result?
241 *
242 * For disable/enable, please check ras features at
243 * /sys/class/drm/card[0/1/2...]/device/ras/features
244 *
245 * For inject, please check corresponding err count at
246 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
247 *
248 * NOTE: operation is only allowed on blocks which are supported.
249 * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
250 */
251static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
252 size_t size, loff_t *pos)
253{
254 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
255 struct ras_debug_if data;
256 int ret = 0;
257
258 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
259 if (ret)
260 return -EINVAL;
261
262 if (!amdgpu_ras_is_supported(adev, data.head.block))
263 return -EINVAL;
264
265 switch (data.op) {
266 case 0:
267 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
268 break;
269 case 1:
270 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
271 break;
272 case 2:
273 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
274 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
275 ret = -EINVAL;
276 break;
277 }
278
279 /* data.inject.address is offset instead of absolute gpu address */
280 ret = amdgpu_ras_error_inject(adev, &data.inject);
281 break;
282 default:
283 ret = -EINVAL;
284 break;
285 };
286
287 if (ret)
288 return -EINVAL;
289
290 return size;
291}
292
293static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
294 .owner = THIS_MODULE,
295 .read = NULL,
296 .write = amdgpu_ras_debugfs_ctrl_write,
297 .llseek = default_llseek
298};
299
300static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
301 struct device_attribute *attr, char *buf)
302{
303 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
304 struct ras_query_if info = {
305 .head = obj->head,
306 };
307
308 if (amdgpu_ras_error_query(obj->adev, &info))
309 return -EINVAL;
310
311 return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n",
312 "ue", info.ue_count,
313 "ce", info.ce_count);
314}
315
316/* obj begin */
317
318#define get_obj(obj) do { (obj)->use++; } while (0)
319#define alive_obj(obj) ((obj)->use)
320
321static inline void put_obj(struct ras_manager *obj)
322{
323 if (obj && --obj->use == 0)
324 list_del(&obj->node);
325 if (obj && obj->use < 0) {
326 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
327 }
328}
329
330/* make one obj and return it. */
331static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
332 struct ras_common_if *head)
333{
334 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
335 struct ras_manager *obj;
336
337 if (!con)
338 return NULL;
339
340 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
341 return NULL;
342
343 obj = &con->objs[head->block];
344 /* already exist. return obj? */
345 if (alive_obj(obj))
346 return NULL;
347
348 obj->head = *head;
349 obj->adev = adev;
350 list_add(&obj->node, &con->head);
351 get_obj(obj);
352
353 return obj;
354}
355
356/* return an obj equal to head, or the first when head is NULL */
357static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
358 struct ras_common_if *head)
359{
360 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
361 struct ras_manager *obj;
362 int i;
363
364 if (!con)
365 return NULL;
366
367 if (head) {
368 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
369 return NULL;
370
371 obj = &con->objs[head->block];
372
373 if (alive_obj(obj)) {
374 WARN_ON(head->block != obj->head.block);
375 return obj;
376 }
377 } else {
378 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
379 obj = &con->objs[i];
380 if (alive_obj(obj)) {
381 WARN_ON(i != obj->head.block);
382 return obj;
383 }
384 }
385 }
386
387 return NULL;
388}
389/* obj end */
390
391/* feature ctl begin */
392static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
393 struct ras_common_if *head)
394{
395 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
396
397 return con->hw_supported & BIT(head->block);
398}
399
400static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
401 struct ras_common_if *head)
402{
403 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
404
405 return con->features & BIT(head->block);
406}
407
408/*
409 * if obj is not created, then create one.
410 * set feature enable flag.
411 */
412static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
413 struct ras_common_if *head, int enable)
414{
415 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
416 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
417
418 /* If hardware does not support ras, then do not create obj.
419 * But if hardware support ras, we can create the obj.
420 * Ras framework checks con->hw_supported to see if it need do
421 * corresponding initialization.
422 * IP checks con->support to see if it need disable ras.
423 */
424 if (!amdgpu_ras_is_feature_allowed(adev, head))
425 return 0;
426 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
427 return 0;
428
429 if (enable) {
430 if (!obj) {
431 obj = amdgpu_ras_create_obj(adev, head);
432 if (!obj)
433 return -EINVAL;
434 } else {
435 /* In case we create obj somewhere else */
436 get_obj(obj);
437 }
438 con->features |= BIT(head->block);
439 } else {
440 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
441 con->features &= ~BIT(head->block);
442 put_obj(obj);
443 }
444 }
445
446 return 0;
447}
448
449/* wrapper of psp_ras_enable_features */
450int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
451 struct ras_common_if *head, bool enable)
452{
453 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
454 union ta_ras_cmd_input info;
455 int ret;
456
457 if (!con)
458 return -EINVAL;
459
460 if (!enable) {
461 info.disable_features = (struct ta_ras_disable_features_input) {
462 .block_id = amdgpu_ras_block_to_ta(head->block),
463 .error_type = amdgpu_ras_error_to_ta(head->type),
464 };
465 } else {
466 info.enable_features = (struct ta_ras_enable_features_input) {
467 .block_id = amdgpu_ras_block_to_ta(head->block),
468 .error_type = amdgpu_ras_error_to_ta(head->type),
469 };
470 }
471
472 /* Do not enable if it is not allowed. */
473 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
474 /* Are we alerady in that state we are going to set? */
475 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
476 return 0;
477
478 ret = psp_ras_enable_features(&adev->psp, &info, enable);
479 if (ret) {
480 DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
481 enable ? "enable":"disable",
482 ras_block_str(head->block),
483 ret);
484 if (ret == TA_RAS_STATUS__RESET_NEEDED)
485 return -EAGAIN;
486 return -EINVAL;
487 }
488
489 /* setup the obj */
490 __amdgpu_ras_feature_enable(adev, head, enable);
491
492 return 0;
493}
494
495/* Only used in device probe stage and called only once. */
496int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
497 struct ras_common_if *head, bool enable)
498{
499 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
500 int ret;
501
502 if (!con)
503 return -EINVAL;
504
505 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
506 if (enable) {
507 /* There is no harm to issue a ras TA cmd regardless of
508 * the currecnt ras state.
509 * If current state == target state, it will do nothing
510 * But sometimes it requests driver to reset and repost
511 * with error code -EAGAIN.
512 */
513 ret = amdgpu_ras_feature_enable(adev, head, 1);
514 /* With old ras TA, we might fail to enable ras.
515 * Log it and just setup the object.
516 * TODO need remove this WA in the future.
517 */
518 if (ret == -EINVAL) {
519 ret = __amdgpu_ras_feature_enable(adev, head, 1);
520 if (!ret)
521 DRM_INFO("RAS INFO: %s setup object\n",
522 ras_block_str(head->block));
523 }
524 } else {
525 /* setup the object then issue a ras TA disable cmd.*/
526 ret = __amdgpu_ras_feature_enable(adev, head, 1);
527 if (ret)
528 return ret;
529
530 ret = amdgpu_ras_feature_enable(adev, head, 0);
531 }
532 } else
533 ret = amdgpu_ras_feature_enable(adev, head, enable);
534
535 return ret;
536}
537
538static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
539 bool bypass)
540{
541 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
542 struct ras_manager *obj, *tmp;
543
544 list_for_each_entry_safe(obj, tmp, &con->head, node) {
545 /* bypass psp.
546 * aka just release the obj and corresponding flags
547 */
548 if (bypass) {
549 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
550 break;
551 } else {
552 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
553 break;
554 }
555 }
556
557 return con->features;
558}
559
560static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
561 bool bypass)
562{
563 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
564 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
565 int i;
566 const enum amdgpu_ras_error_type default_ras_type =
567 AMDGPU_RAS_ERROR__NONE;
568
569 for (i = 0; i < ras_block_count; i++) {
570 struct ras_common_if head = {
571 .block = i,
572 .type = default_ras_type,
573 .sub_block_index = 0,
574 };
575 strcpy(head.name, ras_block_str(i));
576 if (bypass) {
577 /*
578 * bypass psp. vbios enable ras for us.
579 * so just create the obj
580 */
581 if (__amdgpu_ras_feature_enable(adev, &head, 1))
582 break;
583 } else {
584 if (amdgpu_ras_feature_enable(adev, &head, 1))
585 break;
586 }
587 }
588
589 return con->features;
590}
591/* feature ctl end */
592
593/* query/inject/cure begin */
594int amdgpu_ras_error_query(struct amdgpu_device *adev,
595 struct ras_query_if *info)
596{
597 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
598 struct ras_err_data err_data = {0, 0, 0, NULL};
599
600 if (!obj)
601 return -EINVAL;
602
603 switch (info->head.block) {
604 case AMDGPU_RAS_BLOCK__UMC:
605 if (adev->umc.funcs->query_ras_error_count)
606 adev->umc.funcs->query_ras_error_count(adev, &err_data);
607 /* umc query_ras_error_address is also responsible for clearing
608 * error status
609 */
610 if (adev->umc.funcs->query_ras_error_address)
611 adev->umc.funcs->query_ras_error_address(adev, &err_data);
612 break;
613 case AMDGPU_RAS_BLOCK__GFX:
614 if (adev->gfx.funcs->query_ras_error_count)
615 adev->gfx.funcs->query_ras_error_count(adev, &err_data);
616 break;
617 case AMDGPU_RAS_BLOCK__MMHUB:
618 if (adev->mmhub_funcs->query_ras_error_count)
619 adev->mmhub_funcs->query_ras_error_count(adev, &err_data);
620 break;
621 default:
622 break;
623 }
624
625 obj->err_data.ue_count += err_data.ue_count;
626 obj->err_data.ce_count += err_data.ce_count;
627
628 info->ue_count = obj->err_data.ue_count;
629 info->ce_count = obj->err_data.ce_count;
630
631 if (err_data.ce_count)
632 dev_info(adev->dev, "%ld correctable errors detected in %s block\n",
633 obj->err_data.ce_count, ras_block_str(info->head.block));
634 if (err_data.ue_count)
635 dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n",
636 obj->err_data.ue_count, ras_block_str(info->head.block));
637
638 return 0;
639}
640
641/* wrapper of psp_ras_trigger_error */
642int amdgpu_ras_error_inject(struct amdgpu_device *adev,
643 struct ras_inject_if *info)
644{
645 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
646 struct ta_ras_trigger_error_input block_info = {
647 .block_id = amdgpu_ras_block_to_ta(info->head.block),
648 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
649 .sub_block_index = info->head.sub_block_index,
650 .address = info->address,
651 .value = info->value,
652 };
653 int ret = 0;
654
655 if (!obj)
656 return -EINVAL;
657
658 switch (info->head.block) {
659 case AMDGPU_RAS_BLOCK__GFX:
660 if (adev->gfx.funcs->ras_error_inject)
661 ret = adev->gfx.funcs->ras_error_inject(adev, info);
662 else
663 ret = -EINVAL;
664 break;
665 case AMDGPU_RAS_BLOCK__UMC:
666 case AMDGPU_RAS_BLOCK__MMHUB:
667 ret = psp_ras_trigger_error(&adev->psp, &block_info);
668 break;
669 default:
670 DRM_INFO("%s error injection is not supported yet\n",
671 ras_block_str(info->head.block));
672 ret = -EINVAL;
673 }
674
675 if (ret)
676 DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
677 ras_block_str(info->head.block),
678 ret);
679
680 return ret;
681}
682
683int amdgpu_ras_error_cure(struct amdgpu_device *adev,
684 struct ras_cure_if *info)
685{
686 /* psp fw has no cure interface for now. */
687 return 0;
688}
689
690/* get the total error counts on all IPs */
691unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
692 bool is_ce)
693{
694 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
695 struct ras_manager *obj;
696 struct ras_err_data data = {0, 0};
697
698 if (!con)
699 return 0;
700
701 list_for_each_entry(obj, &con->head, node) {
702 struct ras_query_if info = {
703 .head = obj->head,
704 };
705
706 if (amdgpu_ras_error_query(adev, &info))
707 return 0;
708
709 data.ce_count += info.ce_count;
710 data.ue_count += info.ue_count;
711 }
712
713 return is_ce ? data.ce_count : data.ue_count;
714}
715/* query/inject/cure end */
716
717
718/* sysfs begin */
719
720static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
721 struct ras_badpage **bps, unsigned int *count);
722
723static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
724{
725 switch (flags) {
726 case 0:
727 return "R";
728 case 1:
729 return "P";
730 case 2:
731 default:
732 return "F";
733 };
734}
735
736/*
737 * DOC: ras sysfs gpu_vram_bad_pages interface
738 *
739 * It allows user to read the bad pages of vram on the gpu through
740 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
741 *
742 * It outputs multiple lines, and each line stands for one gpu page.
743 *
744 * The format of one line is below,
745 * gpu pfn : gpu page size : flags
746 *
747 * gpu pfn and gpu page size are printed in hex format.
748 * flags can be one of below character,
749 * R: reserved, this gpu page is reserved and not able to use.
750 * P: pending for reserve, this gpu page is marked as bad, will be reserved
751 * in next window of page_reserve.
752 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
753 *
754 * examples:
755 * 0x00000001 : 0x00001000 : R
756 * 0x00000002 : 0x00001000 : P
757 */
758
759static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
760 struct kobject *kobj, struct bin_attribute *attr,
761 char *buf, loff_t ppos, size_t count)
762{
763 struct amdgpu_ras *con =
764 container_of(attr, struct amdgpu_ras, badpages_attr);
765 struct amdgpu_device *adev = con->adev;
766 const unsigned int element_size =
767 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
768 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
769 unsigned int end = div64_ul(ppos + count - 1, element_size);
770 ssize_t s = 0;
771 struct ras_badpage *bps = NULL;
772 unsigned int bps_count = 0;
773
774 memset(buf, 0, count);
775
776 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
777 return 0;
778
779 for (; start < end && start < bps_count; start++)
780 s += scnprintf(&buf[s], element_size + 1,
781 "0x%08x : 0x%08x : %1s\n",
782 bps[start].bp,
783 bps[start].size,
784 amdgpu_ras_badpage_flags_str(bps[start].flags));
785
786 kfree(bps);
787
788 return s;
789}
790
791static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
792 struct device_attribute *attr, char *buf)
793{
794 struct amdgpu_ras *con =
795 container_of(attr, struct amdgpu_ras, features_attr);
796
797 return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
798}
799
800static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev)
801{
802 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
803 struct attribute *attrs[] = {
804 &con->features_attr.attr,
805 NULL
806 };
807 struct bin_attribute *bin_attrs[] = {
808 &con->badpages_attr,
809 NULL
810 };
811 struct attribute_group group = {
812 .name = "ras",
813 .attrs = attrs,
814 .bin_attrs = bin_attrs,
815 };
816
817 con->features_attr = (struct device_attribute) {
818 .attr = {
819 .name = "features",
820 .mode = S_IRUGO,
821 },
822 .show = amdgpu_ras_sysfs_features_read,
823 };
824
825 con->badpages_attr = (struct bin_attribute) {
826 .attr = {
827 .name = "gpu_vram_bad_pages",
828 .mode = S_IRUGO,
829 },
830 .size = 0,
831 .private = NULL,
832 .read = amdgpu_ras_sysfs_badpages_read,
833 };
834
835 sysfs_attr_init(attrs[0]);
836 sysfs_bin_attr_init(bin_attrs[0]);
837
838 return sysfs_create_group(&adev->dev->kobj, &group);
839}
840
841static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
842{
843 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
844 struct attribute *attrs[] = {
845 &con->features_attr.attr,
846 NULL
847 };
848 struct bin_attribute *bin_attrs[] = {
849 &con->badpages_attr,
850 NULL
851 };
852 struct attribute_group group = {
853 .name = "ras",
854 .attrs = attrs,
855 .bin_attrs = bin_attrs,
856 };
857
858 sysfs_remove_group(&adev->dev->kobj, &group);
859
860 return 0;
861}
862
863int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
864 struct ras_fs_if *head)
865{
866 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
867
868 if (!obj || obj->attr_inuse)
869 return -EINVAL;
870
871 get_obj(obj);
872
873 memcpy(obj->fs_data.sysfs_name,
874 head->sysfs_name,
875 sizeof(obj->fs_data.sysfs_name));
876
877 obj->sysfs_attr = (struct device_attribute){
878 .attr = {
879 .name = obj->fs_data.sysfs_name,
880 .mode = S_IRUGO,
881 },
882 .show = amdgpu_ras_sysfs_read,
883 };
884 sysfs_attr_init(&obj->sysfs_attr.attr);
885
886 if (sysfs_add_file_to_group(&adev->dev->kobj,
887 &obj->sysfs_attr.attr,
888 "ras")) {
889 put_obj(obj);
890 return -EINVAL;
891 }
892
893 obj->attr_inuse = 1;
894
895 return 0;
896}
897
898int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
899 struct ras_common_if *head)
900{
901 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
902
903 if (!obj || !obj->attr_inuse)
904 return -EINVAL;
905
906 sysfs_remove_file_from_group(&adev->dev->kobj,
907 &obj->sysfs_attr.attr,
908 "ras");
909 obj->attr_inuse = 0;
910 put_obj(obj);
911
912 return 0;
913}
914
915static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
916{
917 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
918 struct ras_manager *obj, *tmp;
919
920 list_for_each_entry_safe(obj, tmp, &con->head, node) {
921 amdgpu_ras_sysfs_remove(adev, &obj->head);
922 }
923
924 amdgpu_ras_sysfs_remove_feature_node(adev);
925
926 return 0;
927}
928/* sysfs end */
929
930/* debugfs begin */
931static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
932{
933 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
934 struct drm_minor *minor = adev->ddev->primary;
935
936 con->dir = debugfs_create_dir("ras", minor->debugfs_root);
937 con->ent = debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir,
938 adev, &amdgpu_ras_debugfs_ctrl_ops);
939}
940
941void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
942 struct ras_fs_if *head)
943{
944 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
945 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
946
947 if (!obj || obj->ent)
948 return;
949
950 get_obj(obj);
951
952 memcpy(obj->fs_data.debugfs_name,
953 head->debugfs_name,
954 sizeof(obj->fs_data.debugfs_name));
955
956 obj->ent = debugfs_create_file(obj->fs_data.debugfs_name,
957 S_IWUGO | S_IRUGO, con->dir, obj,
958 &amdgpu_ras_debugfs_ops);
959}
960
961void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
962 struct ras_common_if *head)
963{
964 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
965
966 if (!obj || !obj->ent)
967 return;
968
969 debugfs_remove(obj->ent);
970 obj->ent = NULL;
971 put_obj(obj);
972}
973
974static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
975{
976 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
977 struct ras_manager *obj, *tmp;
978
979 list_for_each_entry_safe(obj, tmp, &con->head, node) {
980 amdgpu_ras_debugfs_remove(adev, &obj->head);
981 }
982
983 debugfs_remove(con->ent);
984 debugfs_remove(con->dir);
985 con->dir = NULL;
986 con->ent = NULL;
987}
988/* debugfs end */
989
990/* ras fs */
991
992static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
993{
994 amdgpu_ras_sysfs_create_feature_node(adev);
995 amdgpu_ras_debugfs_create_ctrl_node(adev);
996
997 return 0;
998}
999
1000static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1001{
1002 amdgpu_ras_debugfs_remove_all(adev);
1003 amdgpu_ras_sysfs_remove_all(adev);
1004 return 0;
1005}
1006/* ras fs end */
1007
1008/* ih begin */
1009static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1010{
1011 struct ras_ih_data *data = &obj->ih_data;
1012 struct amdgpu_iv_entry entry;
1013 int ret;
1014 struct ras_err_data err_data = {0, 0, 0, NULL};
1015
1016 while (data->rptr != data->wptr) {
1017 rmb();
1018 memcpy(&entry, &data->ring[data->rptr],
1019 data->element_size);
1020
1021 wmb();
1022 data->rptr = (data->aligned_element_size +
1023 data->rptr) % data->ring_size;
1024
1025 /* Let IP handle its data, maybe we need get the output
1026 * from the callback to udpate the error type/count, etc
1027 */
1028 if (data->cb) {
1029 ret = data->cb(obj->adev, &err_data, &entry);
1030 /* ue will trigger an interrupt, and in that case
1031 * we need do a reset to recovery the whole system.
1032 * But leave IP do that recovery, here we just dispatch
1033 * the error.
1034 */
1035 if (ret == AMDGPU_RAS_SUCCESS) {
1036 /* these counts could be left as 0 if
1037 * some blocks do not count error number
1038 */
1039 obj->err_data.ue_count += err_data.ue_count;
1040 obj->err_data.ce_count += err_data.ce_count;
1041 }
1042 }
1043 }
1044}
1045
1046static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1047{
1048 struct ras_ih_data *data =
1049 container_of(work, struct ras_ih_data, ih_work);
1050 struct ras_manager *obj =
1051 container_of(data, struct ras_manager, ih_data);
1052
1053 amdgpu_ras_interrupt_handler(obj);
1054}
1055
1056int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1057 struct ras_dispatch_if *info)
1058{
1059 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1060 struct ras_ih_data *data = &obj->ih_data;
1061
1062 if (!obj)
1063 return -EINVAL;
1064
1065 if (data->inuse == 0)
1066 return 0;
1067
1068 /* Might be overflow... */
1069 memcpy(&data->ring[data->wptr], info->entry,
1070 data->element_size);
1071
1072 wmb();
1073 data->wptr = (data->aligned_element_size +
1074 data->wptr) % data->ring_size;
1075
1076 schedule_work(&data->ih_work);
1077
1078 return 0;
1079}
1080
1081int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1082 struct ras_ih_if *info)
1083{
1084 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1085 struct ras_ih_data *data;
1086
1087 if (!obj)
1088 return -EINVAL;
1089
1090 data = &obj->ih_data;
1091 if (data->inuse == 0)
1092 return 0;
1093
1094 cancel_work_sync(&data->ih_work);
1095
1096 kfree(data->ring);
1097 memset(data, 0, sizeof(*data));
1098 put_obj(obj);
1099
1100 return 0;
1101}
1102
1103int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1104 struct ras_ih_if *info)
1105{
1106 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1107 struct ras_ih_data *data;
1108
1109 if (!obj) {
1110 /* in case we registe the IH before enable ras feature */
1111 obj = amdgpu_ras_create_obj(adev, &info->head);
1112 if (!obj)
1113 return -EINVAL;
1114 } else
1115 get_obj(obj);
1116
1117 data = &obj->ih_data;
1118 /* add the callback.etc */
1119 *data = (struct ras_ih_data) {
1120 .inuse = 0,
1121 .cb = info->cb,
1122 .element_size = sizeof(struct amdgpu_iv_entry),
1123 .rptr = 0,
1124 .wptr = 0,
1125 };
1126
1127 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1128
1129 data->aligned_element_size = ALIGN(data->element_size, 8);
1130 /* the ring can store 64 iv entries. */
1131 data->ring_size = 64 * data->aligned_element_size;
1132 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1133 if (!data->ring) {
1134 put_obj(obj);
1135 return -ENOMEM;
1136 }
1137
1138 /* IH is ready */
1139 data->inuse = 1;
1140
1141 return 0;
1142}
1143
1144static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1145{
1146 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1147 struct ras_manager *obj, *tmp;
1148
1149 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1150 struct ras_ih_if info = {
1151 .head = obj->head,
1152 };
1153 amdgpu_ras_interrupt_remove_handler(adev, &info);
1154 }
1155
1156 return 0;
1157}
1158/* ih end */
1159
1160/* recovery begin */
1161
1162/* return 0 on success.
1163 * caller need free bps.
1164 */
1165static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1166 struct ras_badpage **bps, unsigned int *count)
1167{
1168 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1169 struct ras_err_handler_data *data;
1170 int i = 0;
1171 int ret = 0;
1172
1173 if (!con || !con->eh_data || !bps || !count)
1174 return -EINVAL;
1175
1176 mutex_lock(&con->recovery_lock);
1177 data = con->eh_data;
1178 if (!data || data->count == 0) {
1179 *bps = NULL;
1180 goto out;
1181 }
1182
1183 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1184 if (!*bps) {
1185 ret = -ENOMEM;
1186 goto out;
1187 }
1188
1189 for (; i < data->count; i++) {
1190 (*bps)[i] = (struct ras_badpage){
1191 .bp = data->bps[i].bp,
1192 .size = AMDGPU_GPU_PAGE_SIZE,
1193 .flags = 0,
1194 };
1195
1196 if (data->last_reserved <= i)
1197 (*bps)[i].flags = 1;
1198 else if (data->bps[i].bo == NULL)
1199 (*bps)[i].flags = 2;
1200 }
1201
1202 *count = data->count;
1203out:
1204 mutex_unlock(&con->recovery_lock);
1205 return ret;
1206}
1207
1208static void amdgpu_ras_do_recovery(struct work_struct *work)
1209{
1210 struct amdgpu_ras *ras =
1211 container_of(work, struct amdgpu_ras, recovery_work);
1212
1213 amdgpu_device_gpu_recover(ras->adev, 0);
1214 atomic_set(&ras->in_recovery, 0);
1215}
1216
1217static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
1218 struct amdgpu_bo **bo_ptr)
1219{
1220 /* no need to free it actually. */
1221 amdgpu_bo_free_kernel(bo_ptr, NULL, NULL);
1222 return 0;
1223}
1224
1225/* reserve vram with size@offset */
1226static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
1227 uint64_t offset, uint64_t size,
1228 struct amdgpu_bo **bo_ptr)
1229{
1230 struct ttm_operation_ctx ctx = { false, false };
1231 struct amdgpu_bo_param bp;
1232 int r = 0;
1233 int i;
1234 struct amdgpu_bo *bo;
1235
1236 if (bo_ptr)
1237 *bo_ptr = NULL;
1238 memset(&bp, 0, sizeof(bp));
1239 bp.size = size;
1240 bp.byte_align = PAGE_SIZE;
1241 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1242 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
1243 AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
1244 bp.type = ttm_bo_type_kernel;
1245 bp.resv = NULL;
1246
1247 r = amdgpu_bo_create(adev, &bp, &bo);
1248 if (r)
1249 return -EINVAL;
1250
1251 r = amdgpu_bo_reserve(bo, false);
1252 if (r)
1253 goto error_reserve;
1254
1255 offset = ALIGN(offset, PAGE_SIZE);
1256 for (i = 0; i < bo->placement.num_placement; ++i) {
1257 bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1258 bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1259 }
1260
1261 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1262 r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, &ctx);
1263 if (r)
1264 goto error_pin;
1265
1266 r = amdgpu_bo_pin_restricted(bo,
1267 AMDGPU_GEM_DOMAIN_VRAM,
1268 offset,
1269 offset + size);
1270 if (r)
1271 goto error_pin;
1272
1273 if (bo_ptr)
1274 *bo_ptr = bo;
1275
1276 amdgpu_bo_unreserve(bo);
1277 return r;
1278
1279error_pin:
1280 amdgpu_bo_unreserve(bo);
1281error_reserve:
1282 amdgpu_bo_unref(&bo);
1283 return r;
1284}
1285
1286/* alloc/realloc bps array */
1287static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1288 struct ras_err_handler_data *data, int pages)
1289{
1290 unsigned int old_space = data->count + data->space_left;
1291 unsigned int new_space = old_space + pages;
1292 unsigned int align_space = ALIGN(new_space, 1024);
1293 void *tmp = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1294
1295 if (!tmp)
1296 return -ENOMEM;
1297
1298 if (data->bps) {
1299 memcpy(tmp, data->bps,
1300 data->count * sizeof(*data->bps));
1301 kfree(data->bps);
1302 }
1303
1304 data->bps = tmp;
1305 data->space_left += align_space - old_space;
1306 return 0;
1307}
1308
1309/* it deal with vram only. */
1310int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1311 unsigned long *bps, int pages)
1312{
1313 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1314 struct ras_err_handler_data *data;
1315 int i = pages;
1316 int ret = 0;
1317
1318 if (!con || !con->eh_data || !bps || pages <= 0)
1319 return 0;
1320
1321 mutex_lock(&con->recovery_lock);
1322 data = con->eh_data;
1323 if (!data)
1324 goto out;
1325
1326 if (data->space_left <= pages)
1327 if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) {
1328 ret = -ENOMEM;
1329 goto out;
1330 }
1331
1332 while (i--)
1333 data->bps[data->count++].bp = bps[i];
1334
1335 data->space_left -= pages;
1336out:
1337 mutex_unlock(&con->recovery_lock);
1338
1339 return ret;
1340}
1341
1342/* called in gpu recovery/init */
1343int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
1344{
1345 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1346 struct ras_err_handler_data *data;
1347 uint64_t bp;
1348 struct amdgpu_bo *bo;
1349 int i;
1350
1351 if (!con || !con->eh_data)
1352 return 0;
1353
1354 mutex_lock(&con->recovery_lock);
1355 data = con->eh_data;
1356 if (!data)
1357 goto out;
1358 /* reserve vram at driver post stage. */
1359 for (i = data->last_reserved; i < data->count; i++) {
1360 bp = data->bps[i].bp;
1361
1362 if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT,
1363 PAGE_SIZE, &bo))
1364 DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp);
1365
1366 data->bps[i].bo = bo;
1367 data->last_reserved = i + 1;
1368 }
1369out:
1370 mutex_unlock(&con->recovery_lock);
1371 return 0;
1372}
1373
1374/* called when driver unload */
1375static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
1376{
1377 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1378 struct ras_err_handler_data *data;
1379 struct amdgpu_bo *bo;
1380 int i;
1381
1382 if (!con || !con->eh_data)
1383 return 0;
1384
1385 mutex_lock(&con->recovery_lock);
1386 data = con->eh_data;
1387 if (!data)
1388 goto out;
1389
1390 for (i = data->last_reserved - 1; i >= 0; i--) {
1391 bo = data->bps[i].bo;
1392
1393 amdgpu_ras_release_vram(adev, &bo);
1394
1395 data->bps[i].bo = bo;
1396 data->last_reserved = i;
1397 }
1398out:
1399 mutex_unlock(&con->recovery_lock);
1400 return 0;
1401}
1402
1403static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1404{
1405 /* TODO
1406 * write the array to eeprom when SMU disabled.
1407 */
1408 return 0;
1409}
1410
1411static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1412{
1413 /* TODO
1414 * read the array to eeprom when SMU disabled.
1415 */
1416 return 0;
1417}
1418
1419static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1420{
1421 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1422 struct ras_err_handler_data **data = &con->eh_data;
1423
1424 *data = kmalloc(sizeof(**data),
1425 GFP_KERNEL|__GFP_ZERO);
1426 if (!*data)
1427 return -ENOMEM;
1428
1429 mutex_init(&con->recovery_lock);
1430 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1431 atomic_set(&con->in_recovery, 0);
1432 con->adev = adev;
1433
1434 amdgpu_ras_load_bad_pages(adev);
1435 amdgpu_ras_reserve_bad_pages(adev);
1436
1437 return 0;
1438}
1439
1440static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1441{
1442 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1443 struct ras_err_handler_data *data = con->eh_data;
1444
1445 cancel_work_sync(&con->recovery_work);
1446 amdgpu_ras_save_bad_pages(adev);
1447 amdgpu_ras_release_bad_pages(adev);
1448
1449 mutex_lock(&con->recovery_lock);
1450 con->eh_data = NULL;
1451 kfree(data->bps);
1452 kfree(data);
1453 mutex_unlock(&con->recovery_lock);
1454
1455 return 0;
1456}
1457/* recovery end */
1458
1459/* return 0 if ras will reset gpu and repost.*/
1460int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
1461 unsigned int block)
1462{
1463 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1464
1465 if (!ras)
1466 return -EINVAL;
1467
1468 ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1469 return 0;
1470}
1471
1472/*
1473 * check hardware's ras ability which will be saved in hw_supported.
1474 * if hardware does not support ras, we can skip some ras initializtion and
1475 * forbid some ras operations from IP.
1476 * if software itself, say boot parameter, limit the ras ability. We still
1477 * need allow IP do some limited operations, like disable. In such case,
1478 * we have to initialize ras as normal. but need check if operation is
1479 * allowed or not in each function.
1480 */
1481static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1482 uint32_t *hw_supported, uint32_t *supported)
1483{
1484 *hw_supported = 0;
1485 *supported = 0;
1486
1487 if (amdgpu_sriov_vf(adev) ||
1488 adev->asic_type != CHIP_VEGA20)
1489 return;
1490
1491 if (adev->is_atom_fw &&
1492 (amdgpu_atomfirmware_mem_ecc_supported(adev) ||
1493 amdgpu_atomfirmware_sram_ecc_supported(adev)))
1494 *hw_supported = AMDGPU_RAS_BLOCK_MASK;
1495
1496 *supported = amdgpu_ras_enable == 0 ?
1497 0 : *hw_supported & amdgpu_ras_mask;
1498}
1499
1500int amdgpu_ras_init(struct amdgpu_device *adev)
1501{
1502 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1503
1504 if (con)
1505 return 0;
1506
1507 con = kmalloc(sizeof(struct amdgpu_ras) +
1508 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
1509 GFP_KERNEL|__GFP_ZERO);
1510 if (!con)
1511 return -ENOMEM;
1512
1513 con->objs = (struct ras_manager *)(con + 1);
1514
1515 amdgpu_ras_set_context(adev, con);
1516
1517 amdgpu_ras_check_supported(adev, &con->hw_supported,
1518 &con->supported);
1519 if (!con->hw_supported) {
1520 amdgpu_ras_set_context(adev, NULL);
1521 kfree(con);
1522 return 0;
1523 }
1524
1525 con->features = 0;
1526 INIT_LIST_HEAD(&con->head);
1527 /* Might need get this flag from vbios. */
1528 con->flags = RAS_DEFAULT_FLAGS;
1529
1530 if (amdgpu_ras_recovery_init(adev))
1531 goto recovery_out;
1532
1533 amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
1534
1535 if (amdgpu_ras_fs_init(adev))
1536 goto fs_out;
1537
1538 /* ras init for each ras block */
1539 if (adev->umc.funcs->ras_init)
1540 adev->umc.funcs->ras_init(adev);
1541
1542 DRM_INFO("RAS INFO: ras initialized successfully, "
1543 "hardware ability[%x] ras_mask[%x]\n",
1544 con->hw_supported, con->supported);
1545 return 0;
1546fs_out:
1547 amdgpu_ras_recovery_fini(adev);
1548recovery_out:
1549 amdgpu_ras_set_context(adev, NULL);
1550 kfree(con);
1551
1552 return -EINVAL;
1553}
1554
1555/* do some init work after IP late init as dependence.
1556 * and it runs in resume/gpu reset/booting up cases.
1557 */
1558void amdgpu_ras_resume(struct amdgpu_device *adev)
1559{
1560 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1561 struct ras_manager *obj, *tmp;
1562
1563 if (!con)
1564 return;
1565
1566 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
1567 /* Set up all other IPs which are not implemented. There is a
1568 * tricky thing that IP's actual ras error type should be
1569 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
1570 * ERROR_NONE make sense anyway.
1571 */
1572 amdgpu_ras_enable_all_features(adev, 1);
1573
1574 /* We enable ras on all hw_supported block, but as boot
1575 * parameter might disable some of them and one or more IP has
1576 * not implemented yet. So we disable them on behalf.
1577 */
1578 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1579 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
1580 amdgpu_ras_feature_enable(adev, &obj->head, 0);
1581 /* there should be no any reference. */
1582 WARN_ON(alive_obj(obj));
1583 }
1584 }
1585 }
1586
1587 if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
1588 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1589 /* setup ras obj state as disabled.
1590 * for init_by_vbios case.
1591 * if we want to enable ras, just enable it in a normal way.
1592 * If we want do disable it, need setup ras obj as enabled,
1593 * then issue another TA disable cmd.
1594 * See feature_enable_on_boot
1595 */
1596 amdgpu_ras_disable_all_features(adev, 1);
1597 amdgpu_ras_reset_gpu(adev, 0);
1598 }
1599}
1600
1601void amdgpu_ras_suspend(struct amdgpu_device *adev)
1602{
1603 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1604
1605 if (!con)
1606 return;
1607
1608 amdgpu_ras_disable_all_features(adev, 0);
1609 /* Make sure all ras objects are disabled. */
1610 if (con->features)
1611 amdgpu_ras_disable_all_features(adev, 1);
1612}
1613
1614/* do some fini work before IP fini as dependence */
1615int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
1616{
1617 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1618
1619 if (!con)
1620 return 0;
1621
1622 /* Need disable ras on all IPs here before ip [hw/sw]fini */
1623 amdgpu_ras_disable_all_features(adev, 0);
1624 amdgpu_ras_recovery_fini(adev);
1625 return 0;
1626}
1627
1628int amdgpu_ras_fini(struct amdgpu_device *adev)
1629{
1630 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1631
1632 if (!con)
1633 return 0;
1634
1635 amdgpu_ras_fs_fini(adev);
1636 amdgpu_ras_interrupt_remove_all(adev);
1637
1638 WARN(con->features, "Feature mask is not cleared");
1639
1640 if (con->features)
1641 amdgpu_ras_disable_all_features(adev, 1);
1642
1643 amdgpu_ras_set_context(adev, NULL);
1644 kfree(con);
1645
1646 return 0;
1647}