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1/*
2 * GPIO driver for the WinSystems WS16C48
3 * Copyright (C) 2016 William Breathitt Gray
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 */
14#include <linux/bitops.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/gpio/driver.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/irqdesc.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27
28static unsigned ws16c48_base;
29module_param(ws16c48_base, uint, 0);
30MODULE_PARM_DESC(ws16c48_base, "WinSystems WS16C48 base address");
31static unsigned ws16c48_irq;
32module_param(ws16c48_irq, uint, 0);
33MODULE_PARM_DESC(ws16c48_irq, "WinSystems WS16C48 interrupt line number");
34
35/**
36 * struct ws16c48_gpio - GPIO device private data structure
37 * @chip: instance of the gpio_chip
38 * @io_state: bit I/O state (whether bit is set to input or output)
39 * @out_state: output bits state
40 * @lock: synchronization lock to prevent I/O race conditions
41 * @irq_mask: I/O bits affected by interrupts
42 * @flow_mask: IRQ flow type mask for the respective I/O bits
43 * @base: base port address of the GPIO device
44 * @irq: Interrupt line number
45 */
46struct ws16c48_gpio {
47 struct gpio_chip chip;
48 unsigned char io_state[6];
49 unsigned char out_state[6];
50 spinlock_t lock;
51 unsigned long irq_mask;
52 unsigned long flow_mask;
53 unsigned base;
54 unsigned irq;
55};
56
57static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
58{
59 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
60 const unsigned port = offset / 8;
61 const unsigned mask = BIT(offset % 8);
62
63 return !!(ws16c48gpio->io_state[port] & mask);
64}
65
66static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
67{
68 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
69 const unsigned port = offset / 8;
70 const unsigned mask = BIT(offset % 8);
71 unsigned long flags;
72
73 spin_lock_irqsave(&ws16c48gpio->lock, flags);
74
75 ws16c48gpio->io_state[port] |= mask;
76 ws16c48gpio->out_state[port] &= ~mask;
77 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
78
79 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
80
81 return 0;
82}
83
84static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
85 unsigned offset, int value)
86{
87 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
88 const unsigned port = offset / 8;
89 const unsigned mask = BIT(offset % 8);
90 unsigned long flags;
91
92 spin_lock_irqsave(&ws16c48gpio->lock, flags);
93
94 ws16c48gpio->io_state[port] &= ~mask;
95 if (value)
96 ws16c48gpio->out_state[port] |= mask;
97 else
98 ws16c48gpio->out_state[port] &= ~mask;
99 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
100
101 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
102
103 return 0;
104}
105
106static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
107{
108 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
109 const unsigned port = offset / 8;
110 const unsigned mask = BIT(offset % 8);
111 unsigned long flags;
112 unsigned port_state;
113
114 spin_lock_irqsave(&ws16c48gpio->lock, flags);
115
116 /* ensure that GPIO is set for input */
117 if (!(ws16c48gpio->io_state[port] & mask)) {
118 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
119 return -EINVAL;
120 }
121
122 port_state = inb(ws16c48gpio->base + port);
123
124 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
125
126 return !!(port_state & mask);
127}
128
129static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
130{
131 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
132 const unsigned port = offset / 8;
133 const unsigned mask = BIT(offset % 8);
134 unsigned long flags;
135
136 spin_lock_irqsave(&ws16c48gpio->lock, flags);
137
138 /* ensure that GPIO is set for output */
139 if (ws16c48gpio->io_state[port] & mask) {
140 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
141 return;
142 }
143
144 if (value)
145 ws16c48gpio->out_state[port] |= mask;
146 else
147 ws16c48gpio->out_state[port] &= ~mask;
148 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
149
150 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
151}
152
153static void ws16c48_irq_ack(struct irq_data *data)
154{
155 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
156 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
157 const unsigned long offset = irqd_to_hwirq(data);
158 const unsigned port = offset / 8;
159 const unsigned mask = BIT(offset % 8);
160 unsigned long flags;
161 unsigned port_state;
162
163 /* only the first 3 ports support interrupts */
164 if (port > 2)
165 return;
166
167 spin_lock_irqsave(&ws16c48gpio->lock, flags);
168
169 port_state = ws16c48gpio->irq_mask >> (8*port);
170
171 outb(0x80, ws16c48gpio->base + 7);
172 outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
173 outb(port_state | mask, ws16c48gpio->base + 8 + port);
174 outb(0xC0, ws16c48gpio->base + 7);
175
176 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
177}
178
179static void ws16c48_irq_mask(struct irq_data *data)
180{
181 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
182 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
183 const unsigned long offset = irqd_to_hwirq(data);
184 const unsigned long mask = BIT(offset);
185 const unsigned port = offset / 8;
186 unsigned long flags;
187
188 /* only the first 3 ports support interrupts */
189 if (port > 2)
190 return;
191
192 spin_lock_irqsave(&ws16c48gpio->lock, flags);
193
194 ws16c48gpio->irq_mask &= ~mask;
195
196 outb(0x80, ws16c48gpio->base + 7);
197 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
198 outb(0xC0, ws16c48gpio->base + 7);
199
200 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
201}
202
203static void ws16c48_irq_unmask(struct irq_data *data)
204{
205 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
206 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
207 const unsigned long offset = irqd_to_hwirq(data);
208 const unsigned long mask = BIT(offset);
209 const unsigned port = offset / 8;
210 unsigned long flags;
211
212 /* only the first 3 ports support interrupts */
213 if (port > 2)
214 return;
215
216 spin_lock_irqsave(&ws16c48gpio->lock, flags);
217
218 ws16c48gpio->irq_mask |= mask;
219
220 outb(0x80, ws16c48gpio->base + 7);
221 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
222 outb(0xC0, ws16c48gpio->base + 7);
223
224 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
225}
226
227static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
228{
229 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
230 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
231 const unsigned long offset = irqd_to_hwirq(data);
232 const unsigned long mask = BIT(offset);
233 const unsigned port = offset / 8;
234 unsigned long flags;
235
236 /* only the first 3 ports support interrupts */
237 if (port > 2)
238 return -EINVAL;
239
240 spin_lock_irqsave(&ws16c48gpio->lock, flags);
241
242 switch (flow_type) {
243 case IRQ_TYPE_NONE:
244 break;
245 case IRQ_TYPE_EDGE_RISING:
246 ws16c48gpio->flow_mask |= mask;
247 break;
248 case IRQ_TYPE_EDGE_FALLING:
249 ws16c48gpio->flow_mask &= ~mask;
250 break;
251 default:
252 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
253 return -EINVAL;
254 }
255
256 outb(0x40, ws16c48gpio->base + 7);
257 outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
258 outb(0xC0, ws16c48gpio->base + 7);
259
260 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
261
262 return 0;
263}
264
265static struct irq_chip ws16c48_irqchip = {
266 .name = "ws16c48",
267 .irq_ack = ws16c48_irq_ack,
268 .irq_mask = ws16c48_irq_mask,
269 .irq_unmask = ws16c48_irq_unmask,
270 .irq_set_type = ws16c48_irq_set_type
271};
272
273static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
274{
275 struct ws16c48_gpio *const ws16c48gpio = dev_id;
276 struct gpio_chip *const chip = &ws16c48gpio->chip;
277 unsigned long int_pending;
278 unsigned long port;
279 unsigned long int_id;
280 unsigned long gpio;
281
282 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
283 if (!int_pending)
284 return IRQ_NONE;
285
286 /* loop until all pending interrupts are handled */
287 do {
288 for_each_set_bit(port, &int_pending, 3) {
289 int_id = inb(ws16c48gpio->base + 8 + port);
290 for_each_set_bit(gpio, &int_id, 8)
291 generic_handle_irq(irq_find_mapping(
292 chip->irqdomain, gpio + 8*port));
293 }
294
295 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
296 } while (int_pending);
297
298 return IRQ_HANDLED;
299}
300
301static int __init ws16c48_probe(struct platform_device *pdev)
302{
303 struct device *dev = &pdev->dev;
304 struct ws16c48_gpio *ws16c48gpio;
305 const unsigned base = ws16c48_base;
306 const unsigned extent = 16;
307 const char *const name = dev_name(dev);
308 int err;
309 const unsigned irq = ws16c48_irq;
310
311 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
312 if (!ws16c48gpio)
313 return -ENOMEM;
314
315 if (!devm_request_region(dev, base, extent, name)) {
316 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
317 base, base + extent);
318 return -EBUSY;
319 }
320
321 ws16c48gpio->chip.label = name;
322 ws16c48gpio->chip.parent = dev;
323 ws16c48gpio->chip.owner = THIS_MODULE;
324 ws16c48gpio->chip.base = -1;
325 ws16c48gpio->chip.ngpio = 48;
326 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
327 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
328 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
329 ws16c48gpio->chip.get = ws16c48_gpio_get;
330 ws16c48gpio->chip.set = ws16c48_gpio_set;
331 ws16c48gpio->base = base;
332 ws16c48gpio->irq = irq;
333
334 spin_lock_init(&ws16c48gpio->lock);
335
336 dev_set_drvdata(dev, ws16c48gpio);
337
338 err = gpiochip_add_data(&ws16c48gpio->chip, ws16c48gpio);
339 if (err) {
340 dev_err(dev, "GPIO registering failed (%d)\n", err);
341 return err;
342 }
343
344 /* Disable IRQ by default */
345 outb(0x80, base + 7);
346 outb(0, base + 8);
347 outb(0, base + 9);
348 outb(0, base + 10);
349 outb(0xC0, base + 7);
350
351 err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
352 handle_edge_irq, IRQ_TYPE_NONE);
353 if (err) {
354 dev_err(dev, "Could not add irqchip (%d)\n", err);
355 goto err_gpiochip_remove;
356 }
357
358 err = request_irq(irq, ws16c48_irq_handler, IRQF_SHARED, name,
359 ws16c48gpio);
360 if (err) {
361 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
362 goto err_gpiochip_remove;
363 }
364
365 return 0;
366
367err_gpiochip_remove:
368 gpiochip_remove(&ws16c48gpio->chip);
369 return err;
370}
371
372static int ws16c48_remove(struct platform_device *pdev)
373{
374 struct ws16c48_gpio *const ws16c48gpio = platform_get_drvdata(pdev);
375
376 free_irq(ws16c48gpio->irq, ws16c48gpio);
377 gpiochip_remove(&ws16c48gpio->chip);
378
379 return 0;
380}
381
382static struct platform_device *ws16c48_device;
383
384static struct platform_driver ws16c48_driver = {
385 .driver = {
386 .name = "ws16c48"
387 },
388 .remove = ws16c48_remove
389};
390
391static void __exit ws16c48_exit(void)
392{
393 platform_device_unregister(ws16c48_device);
394 platform_driver_unregister(&ws16c48_driver);
395}
396
397static int __init ws16c48_init(void)
398{
399 int err;
400
401 ws16c48_device = platform_device_alloc(ws16c48_driver.driver.name, -1);
402 if (!ws16c48_device)
403 return -ENOMEM;
404
405 err = platform_device_add(ws16c48_device);
406 if (err)
407 goto err_platform_device;
408
409 err = platform_driver_probe(&ws16c48_driver, ws16c48_probe);
410 if (err)
411 goto err_platform_driver;
412
413 return 0;
414
415err_platform_driver:
416 platform_device_del(ws16c48_device);
417err_platform_device:
418 platform_device_put(ws16c48_device);
419 return err;
420}
421
422module_init(ws16c48_init);
423module_exit(ws16c48_exit);
424
425MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
426MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
427MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the WinSystems WS16C48
4 * Copyright (C) 2016 William Breathitt Gray
5 */
6#include <linux/bitmap.h>
7#include <linux/bitops.h>
8#include <linux/device.h>
9#include <linux/errno.h>
10#include <linux/gpio/driver.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <linux/interrupt.h>
14#include <linux/irqdesc.h>
15#include <linux/isa.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/spinlock.h>
20
21#define WS16C48_EXTENT 16
22#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
23
24static unsigned int base[MAX_NUM_WS16C48];
25static unsigned int num_ws16c48;
26module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
27MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
28
29static unsigned int irq[MAX_NUM_WS16C48];
30module_param_hw_array(irq, uint, irq, NULL, 0);
31MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
32
33/**
34 * struct ws16c48_gpio - GPIO device private data structure
35 * @chip: instance of the gpio_chip
36 * @io_state: bit I/O state (whether bit is set to input or output)
37 * @out_state: output bits state
38 * @lock: synchronization lock to prevent I/O race conditions
39 * @irq_mask: I/O bits affected by interrupts
40 * @flow_mask: IRQ flow type mask for the respective I/O bits
41 * @base: base port address of the GPIO device
42 */
43struct ws16c48_gpio {
44 struct gpio_chip chip;
45 unsigned char io_state[6];
46 unsigned char out_state[6];
47 raw_spinlock_t lock;
48 unsigned long irq_mask;
49 unsigned long flow_mask;
50 unsigned base;
51};
52
53static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
54{
55 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
56 const unsigned port = offset / 8;
57 const unsigned mask = BIT(offset % 8);
58
59 return !!(ws16c48gpio->io_state[port] & mask);
60}
61
62static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
63{
64 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
65 const unsigned port = offset / 8;
66 const unsigned mask = BIT(offset % 8);
67 unsigned long flags;
68
69 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
70
71 ws16c48gpio->io_state[port] |= mask;
72 ws16c48gpio->out_state[port] &= ~mask;
73 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
74
75 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
76
77 return 0;
78}
79
80static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
81 unsigned offset, int value)
82{
83 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
84 const unsigned port = offset / 8;
85 const unsigned mask = BIT(offset % 8);
86 unsigned long flags;
87
88 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
89
90 ws16c48gpio->io_state[port] &= ~mask;
91 if (value)
92 ws16c48gpio->out_state[port] |= mask;
93 else
94 ws16c48gpio->out_state[port] &= ~mask;
95 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
96
97 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
98
99 return 0;
100}
101
102static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
103{
104 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
105 const unsigned port = offset / 8;
106 const unsigned mask = BIT(offset % 8);
107 unsigned long flags;
108 unsigned port_state;
109
110 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
111
112 /* ensure that GPIO is set for input */
113 if (!(ws16c48gpio->io_state[port] & mask)) {
114 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
115 return -EINVAL;
116 }
117
118 port_state = inb(ws16c48gpio->base + port);
119
120 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
121
122 return !!(port_state & mask);
123}
124
125static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
126 unsigned long *mask, unsigned long *bits)
127{
128 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
129 const unsigned int gpio_reg_size = 8;
130 size_t i;
131 const size_t num_ports = chip->ngpio / gpio_reg_size;
132 unsigned int bits_offset;
133 size_t word_index;
134 unsigned int word_offset;
135 unsigned long word_mask;
136 const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
137 unsigned long port_state;
138
139 /* clear bits array to a clean slate */
140 bitmap_zero(bits, chip->ngpio);
141
142 /* get bits are evaluated a gpio port register at a time */
143 for (i = 0; i < num_ports; i++) {
144 /* gpio offset in bits array */
145 bits_offset = i * gpio_reg_size;
146
147 /* word index for bits array */
148 word_index = BIT_WORD(bits_offset);
149
150 /* gpio offset within current word of bits array */
151 word_offset = bits_offset % BITS_PER_LONG;
152
153 /* mask of get bits for current gpio within current word */
154 word_mask = mask[word_index] & (port_mask << word_offset);
155 if (!word_mask) {
156 /* no get bits in this port so skip to next one */
157 continue;
158 }
159
160 /* read bits from current gpio port */
161 port_state = inb(ws16c48gpio->base + i);
162
163 /* store acquired bits at respective bits array offset */
164 bits[word_index] |= (port_state << word_offset) & word_mask;
165 }
166
167 return 0;
168}
169
170static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
171{
172 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
173 const unsigned port = offset / 8;
174 const unsigned mask = BIT(offset % 8);
175 unsigned long flags;
176
177 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
178
179 /* ensure that GPIO is set for output */
180 if (ws16c48gpio->io_state[port] & mask) {
181 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
182 return;
183 }
184
185 if (value)
186 ws16c48gpio->out_state[port] |= mask;
187 else
188 ws16c48gpio->out_state[port] &= ~mask;
189 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
190
191 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
192}
193
194static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
195 unsigned long *mask, unsigned long *bits)
196{
197 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
198 unsigned int i;
199 const unsigned int gpio_reg_size = 8;
200 unsigned int port;
201 unsigned int iomask;
202 unsigned int bitmask;
203 unsigned long flags;
204
205 /* set bits are evaluated a gpio register size at a time */
206 for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
207 /* no more set bits in this mask word; skip to the next word */
208 if (!mask[BIT_WORD(i)]) {
209 i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
210 continue;
211 }
212
213 port = i / gpio_reg_size;
214
215 /* mask out GPIO configured for input */
216 iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port];
217 bitmask = iomask & bits[BIT_WORD(i)];
218
219 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
220
221 /* update output state data and set device gpio register */
222 ws16c48gpio->out_state[port] &= ~iomask;
223 ws16c48gpio->out_state[port] |= bitmask;
224 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
225
226 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
227
228 /* prepare for next gpio register set */
229 mask[BIT_WORD(i)] >>= gpio_reg_size;
230 bits[BIT_WORD(i)] >>= gpio_reg_size;
231 }
232}
233
234static void ws16c48_irq_ack(struct irq_data *data)
235{
236 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
237 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
238 const unsigned long offset = irqd_to_hwirq(data);
239 const unsigned port = offset / 8;
240 const unsigned mask = BIT(offset % 8);
241 unsigned long flags;
242 unsigned port_state;
243
244 /* only the first 3 ports support interrupts */
245 if (port > 2)
246 return;
247
248 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
249
250 port_state = ws16c48gpio->irq_mask >> (8*port);
251
252 outb(0x80, ws16c48gpio->base + 7);
253 outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
254 outb(port_state | mask, ws16c48gpio->base + 8 + port);
255 outb(0xC0, ws16c48gpio->base + 7);
256
257 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
258}
259
260static void ws16c48_irq_mask(struct irq_data *data)
261{
262 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
263 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
264 const unsigned long offset = irqd_to_hwirq(data);
265 const unsigned long mask = BIT(offset);
266 const unsigned port = offset / 8;
267 unsigned long flags;
268
269 /* only the first 3 ports support interrupts */
270 if (port > 2)
271 return;
272
273 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
274
275 ws16c48gpio->irq_mask &= ~mask;
276
277 outb(0x80, ws16c48gpio->base + 7);
278 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
279 outb(0xC0, ws16c48gpio->base + 7);
280
281 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
282}
283
284static void ws16c48_irq_unmask(struct irq_data *data)
285{
286 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
287 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
288 const unsigned long offset = irqd_to_hwirq(data);
289 const unsigned long mask = BIT(offset);
290 const unsigned port = offset / 8;
291 unsigned long flags;
292
293 /* only the first 3 ports support interrupts */
294 if (port > 2)
295 return;
296
297 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
298
299 ws16c48gpio->irq_mask |= mask;
300
301 outb(0x80, ws16c48gpio->base + 7);
302 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
303 outb(0xC0, ws16c48gpio->base + 7);
304
305 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
306}
307
308static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
309{
310 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
311 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
312 const unsigned long offset = irqd_to_hwirq(data);
313 const unsigned long mask = BIT(offset);
314 const unsigned port = offset / 8;
315 unsigned long flags;
316
317 /* only the first 3 ports support interrupts */
318 if (port > 2)
319 return -EINVAL;
320
321 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
322
323 switch (flow_type) {
324 case IRQ_TYPE_NONE:
325 break;
326 case IRQ_TYPE_EDGE_RISING:
327 ws16c48gpio->flow_mask |= mask;
328 break;
329 case IRQ_TYPE_EDGE_FALLING:
330 ws16c48gpio->flow_mask &= ~mask;
331 break;
332 default:
333 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
334 return -EINVAL;
335 }
336
337 outb(0x40, ws16c48gpio->base + 7);
338 outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
339 outb(0xC0, ws16c48gpio->base + 7);
340
341 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
342
343 return 0;
344}
345
346static struct irq_chip ws16c48_irqchip = {
347 .name = "ws16c48",
348 .irq_ack = ws16c48_irq_ack,
349 .irq_mask = ws16c48_irq_mask,
350 .irq_unmask = ws16c48_irq_unmask,
351 .irq_set_type = ws16c48_irq_set_type
352};
353
354static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
355{
356 struct ws16c48_gpio *const ws16c48gpio = dev_id;
357 struct gpio_chip *const chip = &ws16c48gpio->chip;
358 unsigned long int_pending;
359 unsigned long port;
360 unsigned long int_id;
361 unsigned long gpio;
362
363 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
364 if (!int_pending)
365 return IRQ_NONE;
366
367 /* loop until all pending interrupts are handled */
368 do {
369 for_each_set_bit(port, &int_pending, 3) {
370 int_id = inb(ws16c48gpio->base + 8 + port);
371 for_each_set_bit(gpio, &int_id, 8)
372 generic_handle_irq(irq_find_mapping(
373 chip->irq.domain, gpio + 8*port));
374 }
375
376 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
377 } while (int_pending);
378
379 return IRQ_HANDLED;
380}
381
382#define WS16C48_NGPIO 48
383static const char *ws16c48_names[WS16C48_NGPIO] = {
384 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
385 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
386 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
387 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
388 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
389 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
390 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
391 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
392 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
393 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
394 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
395 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
396};
397
398static int ws16c48_probe(struct device *dev, unsigned int id)
399{
400 struct ws16c48_gpio *ws16c48gpio;
401 const char *const name = dev_name(dev);
402 int err;
403
404 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
405 if (!ws16c48gpio)
406 return -ENOMEM;
407
408 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
409 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
410 base[id], base[id] + WS16C48_EXTENT);
411 return -EBUSY;
412 }
413
414 ws16c48gpio->chip.label = name;
415 ws16c48gpio->chip.parent = dev;
416 ws16c48gpio->chip.owner = THIS_MODULE;
417 ws16c48gpio->chip.base = -1;
418 ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
419 ws16c48gpio->chip.names = ws16c48_names;
420 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
421 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
422 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
423 ws16c48gpio->chip.get = ws16c48_gpio_get;
424 ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
425 ws16c48gpio->chip.set = ws16c48_gpio_set;
426 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
427 ws16c48gpio->base = base[id];
428
429 raw_spin_lock_init(&ws16c48gpio->lock);
430
431 err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
432 if (err) {
433 dev_err(dev, "GPIO registering failed (%d)\n", err);
434 return err;
435 }
436
437 /* Disable IRQ by default */
438 outb(0x80, base[id] + 7);
439 outb(0, base[id] + 8);
440 outb(0, base[id] + 9);
441 outb(0, base[id] + 10);
442 outb(0xC0, base[id] + 7);
443
444 err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
445 handle_edge_irq, IRQ_TYPE_NONE);
446 if (err) {
447 dev_err(dev, "Could not add irqchip (%d)\n", err);
448 return err;
449 }
450
451 err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
452 name, ws16c48gpio);
453 if (err) {
454 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
455 return err;
456 }
457
458 return 0;
459}
460
461static struct isa_driver ws16c48_driver = {
462 .probe = ws16c48_probe,
463 .driver = {
464 .name = "ws16c48"
465 },
466};
467
468module_isa_driver(ws16c48_driver, num_ws16c48);
469
470MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
471MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
472MODULE_LICENSE("GPL v2");