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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2015 IBM Corp.
4 *
5 * Joel Stanley <joel@jms.id.au>
6 */
7
8#include <asm/div64.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/gpio/aspeed.h>
12#include <linux/hashtable.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/platform_device.h>
19#include <linux/spinlock.h>
20#include <linux/string.h>
21
22/*
23 * These two headers aren't meant to be used by GPIO drivers. We need
24 * them in order to access gpio_chip_hwgpio() which we need to implement
25 * the aspeed specific API which allows the coprocessor to request
26 * access to some GPIOs and to arbitrate between coprocessor and ARM.
27 */
28#include <linux/gpio/consumer.h>
29#include "gpiolib.h"
30
31struct aspeed_bank_props {
32 unsigned int bank;
33 u32 input;
34 u32 output;
35};
36
37struct aspeed_gpio_config {
38 unsigned int nr_gpios;
39 const struct aspeed_bank_props *props;
40};
41
42/*
43 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
44 * @timer_users: Tracks the number of users for each timer
45 *
46 * The @timer_users has four elements but the first element is unused. This is
47 * to simplify accounting and indexing, as a zero value in @offset_timer
48 * represents disabled debouncing for the GPIO. Any other value for an element
49 * of @offset_timer is used as an index into @timer_users. This behaviour of
50 * the zero value aligns with the behaviour of zero built from the timer
51 * configuration registers (i.e. debouncing is disabled).
52 */
53struct aspeed_gpio {
54 struct gpio_chip chip;
55 struct irq_chip irqc;
56 spinlock_t lock;
57 void __iomem *base;
58 int irq;
59 const struct aspeed_gpio_config *config;
60
61 u8 *offset_timer;
62 unsigned int timer_users[4];
63 struct clk *clk;
64
65 u32 *dcache;
66 u8 *cf_copro_bankmap;
67};
68
69struct aspeed_gpio_bank {
70 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
71 * +4: Rd/Wr: Direction (0=in, 1=out)
72 */
73 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
74 uint16_t irq_regs;
75 uint16_t debounce_regs;
76 uint16_t tolerance_regs;
77 uint16_t cmdsrc_regs;
78 const char names[4][3];
79};
80
81/*
82 * Note: The "value" register returns the input value sampled on the
83 * line even when the GPIO is configured as an output. Since
84 * that input goes through synchronizers, writing, then reading
85 * back may not return the written value right away.
86 *
87 * The "rdata" register returns the content of the write latch
88 * and thus can be used to read back what was last written
89 * reliably.
90 */
91
92static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
93
94static const struct aspeed_gpio_copro_ops *copro_ops;
95static void *copro_data;
96
97static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
98 {
99 .val_regs = 0x0000,
100 .rdata_reg = 0x00c0,
101 .irq_regs = 0x0008,
102 .debounce_regs = 0x0040,
103 .tolerance_regs = 0x001c,
104 .cmdsrc_regs = 0x0060,
105 .names = { "A", "B", "C", "D" },
106 },
107 {
108 .val_regs = 0x0020,
109 .rdata_reg = 0x00c4,
110 .irq_regs = 0x0028,
111 .debounce_regs = 0x0048,
112 .tolerance_regs = 0x003c,
113 .cmdsrc_regs = 0x0068,
114 .names = { "E", "F", "G", "H" },
115 },
116 {
117 .val_regs = 0x0070,
118 .rdata_reg = 0x00c8,
119 .irq_regs = 0x0098,
120 .debounce_regs = 0x00b0,
121 .tolerance_regs = 0x00ac,
122 .cmdsrc_regs = 0x0090,
123 .names = { "I", "J", "K", "L" },
124 },
125 {
126 .val_regs = 0x0078,
127 .rdata_reg = 0x00cc,
128 .irq_regs = 0x00e8,
129 .debounce_regs = 0x0100,
130 .tolerance_regs = 0x00fc,
131 .cmdsrc_regs = 0x00e0,
132 .names = { "M", "N", "O", "P" },
133 },
134 {
135 .val_regs = 0x0080,
136 .rdata_reg = 0x00d0,
137 .irq_regs = 0x0118,
138 .debounce_regs = 0x0130,
139 .tolerance_regs = 0x012c,
140 .cmdsrc_regs = 0x0110,
141 .names = { "Q", "R", "S", "T" },
142 },
143 {
144 .val_regs = 0x0088,
145 .rdata_reg = 0x00d4,
146 .irq_regs = 0x0148,
147 .debounce_regs = 0x0160,
148 .tolerance_regs = 0x015c,
149 .cmdsrc_regs = 0x0140,
150 .names = { "U", "V", "W", "X" },
151 },
152 {
153 .val_regs = 0x01E0,
154 .rdata_reg = 0x00d8,
155 .irq_regs = 0x0178,
156 .debounce_regs = 0x0190,
157 .tolerance_regs = 0x018c,
158 .cmdsrc_regs = 0x0170,
159 .names = { "Y", "Z", "AA", "AB" },
160 },
161 {
162 .val_regs = 0x01e8,
163 .rdata_reg = 0x00dc,
164 .irq_regs = 0x01a8,
165 .debounce_regs = 0x01c0,
166 .tolerance_regs = 0x01bc,
167 .cmdsrc_regs = 0x01a0,
168 .names = { "AC", "", "", "" },
169 },
170};
171
172enum aspeed_gpio_reg {
173 reg_val,
174 reg_rdata,
175 reg_dir,
176 reg_irq_enable,
177 reg_irq_type0,
178 reg_irq_type1,
179 reg_irq_type2,
180 reg_irq_status,
181 reg_debounce_sel1,
182 reg_debounce_sel2,
183 reg_tolerance,
184 reg_cmdsrc0,
185 reg_cmdsrc1,
186};
187
188#define GPIO_VAL_VALUE 0x00
189#define GPIO_VAL_DIR 0x04
190
191#define GPIO_IRQ_ENABLE 0x00
192#define GPIO_IRQ_TYPE0 0x04
193#define GPIO_IRQ_TYPE1 0x08
194#define GPIO_IRQ_TYPE2 0x0c
195#define GPIO_IRQ_STATUS 0x10
196
197#define GPIO_DEBOUNCE_SEL1 0x00
198#define GPIO_DEBOUNCE_SEL2 0x04
199
200#define GPIO_CMDSRC_0 0x00
201#define GPIO_CMDSRC_1 0x04
202#define GPIO_CMDSRC_ARM 0
203#define GPIO_CMDSRC_LPC 1
204#define GPIO_CMDSRC_COLDFIRE 2
205#define GPIO_CMDSRC_RESERVED 3
206
207/* This will be resolved at compile time */
208static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
209 const struct aspeed_gpio_bank *bank,
210 const enum aspeed_gpio_reg reg)
211{
212 switch (reg) {
213 case reg_val:
214 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
215 case reg_rdata:
216 return gpio->base + bank->rdata_reg;
217 case reg_dir:
218 return gpio->base + bank->val_regs + GPIO_VAL_DIR;
219 case reg_irq_enable:
220 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
221 case reg_irq_type0:
222 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
223 case reg_irq_type1:
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
225 case reg_irq_type2:
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
227 case reg_irq_status:
228 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
229 case reg_debounce_sel1:
230 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
231 case reg_debounce_sel2:
232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
233 case reg_tolerance:
234 return gpio->base + bank->tolerance_regs;
235 case reg_cmdsrc0:
236 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
237 case reg_cmdsrc1:
238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
239 }
240 BUG();
241}
242
243#define GPIO_BANK(x) ((x) >> 5)
244#define GPIO_OFFSET(x) ((x) & 0x1f)
245#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
246
247#define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
248#define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
249#define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
250
251static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
252{
253 unsigned int bank = GPIO_BANK(offset);
254
255 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
256 return &aspeed_gpio_banks[bank];
257}
258
259static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
260{
261 return !(props->input || props->output);
262}
263
264static inline const struct aspeed_bank_props *find_bank_props(
265 struct aspeed_gpio *gpio, unsigned int offset)
266{
267 const struct aspeed_bank_props *props = gpio->config->props;
268
269 while (!is_bank_props_sentinel(props)) {
270 if (props->bank == GPIO_BANK(offset))
271 return props;
272 props++;
273 }
274
275 return NULL;
276}
277
278static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
279{
280 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
281 const struct aspeed_gpio_bank *bank = to_bank(offset);
282 unsigned int group = GPIO_OFFSET(offset) / 8;
283
284 return bank->names[group][0] != '\0' &&
285 (!props || ((props->input | props->output) & GPIO_BIT(offset)));
286}
287
288static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
289{
290 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
291
292 return !props || (props->input & GPIO_BIT(offset));
293}
294
295#define have_irq(g, o) have_input((g), (o))
296#define have_debounce(g, o) have_input((g), (o))
297
298static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
299{
300 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
301
302 return !props || (props->output & GPIO_BIT(offset));
303}
304
305static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
306 const struct aspeed_gpio_bank *bank,
307 int bindex, int cmdsrc)
308{
309 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
310 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
311 u32 bit, reg;
312
313 /*
314 * Each register controls 4 banks, so take the bottom 2
315 * bits of the bank index, and use them to select the
316 * right control bit (0, 8, 16 or 24).
317 */
318 bit = BIT((bindex & 3) << 3);
319
320 /* Source 1 first to avoid illegal 11 combination */
321 reg = ioread32(c1);
322 if (cmdsrc & 2)
323 reg |= bit;
324 else
325 reg &= ~bit;
326 iowrite32(reg, c1);
327
328 /* Then Source 0 */
329 reg = ioread32(c0);
330 if (cmdsrc & 1)
331 reg |= bit;
332 else
333 reg &= ~bit;
334 iowrite32(reg, c0);
335}
336
337static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
338 unsigned int offset)
339{
340 const struct aspeed_gpio_bank *bank = to_bank(offset);
341
342 if (!copro_ops || !gpio->cf_copro_bankmap)
343 return false;
344 if (!gpio->cf_copro_bankmap[offset >> 3])
345 return false;
346 if (!copro_ops->request_access)
347 return false;
348
349 /* Pause the coprocessor */
350 copro_ops->request_access(copro_data);
351
352 /* Change command source back to ARM */
353 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
354
355 /* Update cache */
356 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
357
358 return true;
359}
360
361static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
362 unsigned int offset)
363{
364 const struct aspeed_gpio_bank *bank = to_bank(offset);
365
366 if (!copro_ops || !gpio->cf_copro_bankmap)
367 return;
368 if (!gpio->cf_copro_bankmap[offset >> 3])
369 return;
370 if (!copro_ops->release_access)
371 return;
372
373 /* Change command source back to ColdFire */
374 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
375 GPIO_CMDSRC_COLDFIRE);
376
377 /* Restart the coprocessor */
378 copro_ops->release_access(copro_data);
379}
380
381static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
382{
383 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
384 const struct aspeed_gpio_bank *bank = to_bank(offset);
385
386 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
387}
388
389static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
390 int val)
391{
392 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
393 const struct aspeed_gpio_bank *bank = to_bank(offset);
394 void __iomem *addr;
395 u32 reg;
396
397 addr = bank_reg(gpio, bank, reg_val);
398 reg = gpio->dcache[GPIO_BANK(offset)];
399
400 if (val)
401 reg |= GPIO_BIT(offset);
402 else
403 reg &= ~GPIO_BIT(offset);
404 gpio->dcache[GPIO_BANK(offset)] = reg;
405
406 iowrite32(reg, addr);
407}
408
409static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
410 int val)
411{
412 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
413 unsigned long flags;
414 bool copro;
415
416 spin_lock_irqsave(&gpio->lock, flags);
417 copro = aspeed_gpio_copro_request(gpio, offset);
418
419 __aspeed_gpio_set(gc, offset, val);
420
421 if (copro)
422 aspeed_gpio_copro_release(gpio, offset);
423 spin_unlock_irqrestore(&gpio->lock, flags);
424}
425
426static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
427{
428 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
429 const struct aspeed_gpio_bank *bank = to_bank(offset);
430 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
431 unsigned long flags;
432 bool copro;
433 u32 reg;
434
435 if (!have_input(gpio, offset))
436 return -ENOTSUPP;
437
438 spin_lock_irqsave(&gpio->lock, flags);
439
440 reg = ioread32(addr);
441 reg &= ~GPIO_BIT(offset);
442
443 copro = aspeed_gpio_copro_request(gpio, offset);
444 iowrite32(reg, addr);
445 if (copro)
446 aspeed_gpio_copro_release(gpio, offset);
447
448 spin_unlock_irqrestore(&gpio->lock, flags);
449
450 return 0;
451}
452
453static int aspeed_gpio_dir_out(struct gpio_chip *gc,
454 unsigned int offset, int val)
455{
456 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
457 const struct aspeed_gpio_bank *bank = to_bank(offset);
458 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
459 unsigned long flags;
460 bool copro;
461 u32 reg;
462
463 if (!have_output(gpio, offset))
464 return -ENOTSUPP;
465
466 spin_lock_irqsave(&gpio->lock, flags);
467
468 reg = ioread32(addr);
469 reg |= GPIO_BIT(offset);
470
471 copro = aspeed_gpio_copro_request(gpio, offset);
472 __aspeed_gpio_set(gc, offset, val);
473 iowrite32(reg, addr);
474
475 if (copro)
476 aspeed_gpio_copro_release(gpio, offset);
477 spin_unlock_irqrestore(&gpio->lock, flags);
478
479 return 0;
480}
481
482static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
483{
484 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
485 const struct aspeed_gpio_bank *bank = to_bank(offset);
486 unsigned long flags;
487 u32 val;
488
489 if (!have_input(gpio, offset))
490 return 0;
491
492 if (!have_output(gpio, offset))
493 return 1;
494
495 spin_lock_irqsave(&gpio->lock, flags);
496
497 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
498
499 spin_unlock_irqrestore(&gpio->lock, flags);
500
501 return !val;
502
503}
504
505static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
506 struct aspeed_gpio **gpio,
507 const struct aspeed_gpio_bank **bank,
508 u32 *bit, int *offset)
509{
510 struct aspeed_gpio *internal;
511
512 *offset = irqd_to_hwirq(d);
513
514 internal = irq_data_get_irq_chip_data(d);
515
516 /* This might be a bit of a questionable place to check */
517 if (!have_irq(internal, *offset))
518 return -ENOTSUPP;
519
520 *gpio = internal;
521 *bank = to_bank(*offset);
522 *bit = GPIO_BIT(*offset);
523
524 return 0;
525}
526
527static void aspeed_gpio_irq_ack(struct irq_data *d)
528{
529 const struct aspeed_gpio_bank *bank;
530 struct aspeed_gpio *gpio;
531 unsigned long flags;
532 void __iomem *status_addr;
533 int rc, offset;
534 bool copro;
535 u32 bit;
536
537 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
538 if (rc)
539 return;
540
541 status_addr = bank_reg(gpio, bank, reg_irq_status);
542
543 spin_lock_irqsave(&gpio->lock, flags);
544 copro = aspeed_gpio_copro_request(gpio, offset);
545
546 iowrite32(bit, status_addr);
547
548 if (copro)
549 aspeed_gpio_copro_release(gpio, offset);
550 spin_unlock_irqrestore(&gpio->lock, flags);
551}
552
553static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
554{
555 const struct aspeed_gpio_bank *bank;
556 struct aspeed_gpio *gpio;
557 unsigned long flags;
558 u32 reg, bit;
559 void __iomem *addr;
560 int rc, offset;
561 bool copro;
562
563 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
564 if (rc)
565 return;
566
567 addr = bank_reg(gpio, bank, reg_irq_enable);
568
569 spin_lock_irqsave(&gpio->lock, flags);
570 copro = aspeed_gpio_copro_request(gpio, offset);
571
572 reg = ioread32(addr);
573 if (set)
574 reg |= bit;
575 else
576 reg &= ~bit;
577 iowrite32(reg, addr);
578
579 if (copro)
580 aspeed_gpio_copro_release(gpio, offset);
581 spin_unlock_irqrestore(&gpio->lock, flags);
582}
583
584static void aspeed_gpio_irq_mask(struct irq_data *d)
585{
586 aspeed_gpio_irq_set_mask(d, false);
587}
588
589static void aspeed_gpio_irq_unmask(struct irq_data *d)
590{
591 aspeed_gpio_irq_set_mask(d, true);
592}
593
594static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
595{
596 u32 type0 = 0;
597 u32 type1 = 0;
598 u32 type2 = 0;
599 u32 bit, reg;
600 const struct aspeed_gpio_bank *bank;
601 irq_flow_handler_t handler;
602 struct aspeed_gpio *gpio;
603 unsigned long flags;
604 void __iomem *addr;
605 int rc, offset;
606 bool copro;
607
608 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
609 if (rc)
610 return -EINVAL;
611
612 switch (type & IRQ_TYPE_SENSE_MASK) {
613 case IRQ_TYPE_EDGE_BOTH:
614 type2 |= bit;
615 /* fall through */
616 case IRQ_TYPE_EDGE_RISING:
617 type0 |= bit;
618 /* fall through */
619 case IRQ_TYPE_EDGE_FALLING:
620 handler = handle_edge_irq;
621 break;
622 case IRQ_TYPE_LEVEL_HIGH:
623 type0 |= bit;
624 /* fall through */
625 case IRQ_TYPE_LEVEL_LOW:
626 type1 |= bit;
627 handler = handle_level_irq;
628 break;
629 default:
630 return -EINVAL;
631 }
632
633 spin_lock_irqsave(&gpio->lock, flags);
634 copro = aspeed_gpio_copro_request(gpio, offset);
635
636 addr = bank_reg(gpio, bank, reg_irq_type0);
637 reg = ioread32(addr);
638 reg = (reg & ~bit) | type0;
639 iowrite32(reg, addr);
640
641 addr = bank_reg(gpio, bank, reg_irq_type1);
642 reg = ioread32(addr);
643 reg = (reg & ~bit) | type1;
644 iowrite32(reg, addr);
645
646 addr = bank_reg(gpio, bank, reg_irq_type2);
647 reg = ioread32(addr);
648 reg = (reg & ~bit) | type2;
649 iowrite32(reg, addr);
650
651 if (copro)
652 aspeed_gpio_copro_release(gpio, offset);
653 spin_unlock_irqrestore(&gpio->lock, flags);
654
655 irq_set_handler_locked(d, handler);
656
657 return 0;
658}
659
660static void aspeed_gpio_irq_handler(struct irq_desc *desc)
661{
662 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
663 struct irq_chip *ic = irq_desc_get_chip(desc);
664 struct aspeed_gpio *data = gpiochip_get_data(gc);
665 unsigned int i, p, girq, banks;
666 unsigned long reg;
667 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
668
669 chained_irq_enter(ic, desc);
670
671 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
672 for (i = 0; i < banks; i++) {
673 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
674
675 reg = ioread32(bank_reg(data, bank, reg_irq_status));
676
677 for_each_set_bit(p, ®, 32) {
678 girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
679 generic_handle_irq(girq);
680 }
681
682 }
683
684 chained_irq_exit(ic, desc);
685}
686
687static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
688 unsigned long *valid_mask,
689 unsigned int ngpios)
690{
691 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
692 const struct aspeed_bank_props *props = gpio->config->props;
693
694 while (!is_bank_props_sentinel(props)) {
695 unsigned int offset;
696 const unsigned long int input = props->input;
697
698 /* Pretty crummy approach, but similar to GPIO core */
699 for_each_clear_bit(offset, &input, 32) {
700 unsigned int i = props->bank * 32 + offset;
701
702 if (i >= gpio->chip.ngpio)
703 break;
704
705 clear_bit(i, valid_mask);
706 }
707
708 props++;
709 }
710}
711
712static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
713 unsigned int offset, bool enable)
714{
715 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
716 unsigned long flags;
717 void __iomem *treg;
718 bool copro;
719 u32 val;
720
721 treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
722
723 spin_lock_irqsave(&gpio->lock, flags);
724 copro = aspeed_gpio_copro_request(gpio, offset);
725
726 val = readl(treg);
727
728 if (enable)
729 val |= GPIO_BIT(offset);
730 else
731 val &= ~GPIO_BIT(offset);
732
733 writel(val, treg);
734
735 if (copro)
736 aspeed_gpio_copro_release(gpio, offset);
737 spin_unlock_irqrestore(&gpio->lock, flags);
738
739 return 0;
740}
741
742static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
743{
744 if (!have_gpio(gpiochip_get_data(chip), offset))
745 return -ENODEV;
746
747 return pinctrl_gpio_request(chip->base + offset);
748}
749
750static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
751{
752 pinctrl_gpio_free(chip->base + offset);
753}
754
755static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
756 u32 *cycles)
757{
758 u64 rate;
759 u64 n;
760 u32 r;
761
762 rate = clk_get_rate(gpio->clk);
763 if (!rate)
764 return -ENOTSUPP;
765
766 n = rate * usecs;
767 r = do_div(n, 1000000);
768
769 if (n >= U32_MAX)
770 return -ERANGE;
771
772 /* At least as long as the requested time */
773 *cycles = n + (!!r);
774
775 return 0;
776}
777
778/* Call under gpio->lock */
779static int register_allocated_timer(struct aspeed_gpio *gpio,
780 unsigned int offset, unsigned int timer)
781{
782 if (WARN(gpio->offset_timer[offset] != 0,
783 "Offset %d already allocated timer %d\n",
784 offset, gpio->offset_timer[offset]))
785 return -EINVAL;
786
787 if (WARN(gpio->timer_users[timer] == UINT_MAX,
788 "Timer user count would overflow\n"))
789 return -EPERM;
790
791 gpio->offset_timer[offset] = timer;
792 gpio->timer_users[timer]++;
793
794 return 0;
795}
796
797/* Call under gpio->lock */
798static int unregister_allocated_timer(struct aspeed_gpio *gpio,
799 unsigned int offset)
800{
801 if (WARN(gpio->offset_timer[offset] == 0,
802 "No timer allocated to offset %d\n", offset))
803 return -EINVAL;
804
805 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
806 "No users recorded for timer %d\n",
807 gpio->offset_timer[offset]))
808 return -EINVAL;
809
810 gpio->timer_users[gpio->offset_timer[offset]]--;
811 gpio->offset_timer[offset] = 0;
812
813 return 0;
814}
815
816/* Call under gpio->lock */
817static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
818 unsigned int offset)
819{
820 return gpio->offset_timer[offset] > 0;
821}
822
823/* Call under gpio->lock */
824static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
825 unsigned int timer)
826{
827 const struct aspeed_gpio_bank *bank = to_bank(offset);
828 const u32 mask = GPIO_BIT(offset);
829 void __iomem *addr;
830 u32 val;
831
832 /* Note: Debounce timer isn't under control of the command
833 * source registers, so no need to sync with the coprocessor
834 */
835 addr = bank_reg(gpio, bank, reg_debounce_sel1);
836 val = ioread32(addr);
837 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
838
839 addr = bank_reg(gpio, bank, reg_debounce_sel2);
840 val = ioread32(addr);
841 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
842}
843
844static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
845 unsigned long usecs)
846{
847 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
848 u32 requested_cycles;
849 unsigned long flags;
850 int rc;
851 int i;
852
853 if (!gpio->clk)
854 return -EINVAL;
855
856 rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
857 if (rc < 0) {
858 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
859 usecs, clk_get_rate(gpio->clk), rc);
860 return rc;
861 }
862
863 spin_lock_irqsave(&gpio->lock, flags);
864
865 if (timer_allocation_registered(gpio, offset)) {
866 rc = unregister_allocated_timer(gpio, offset);
867 if (rc < 0)
868 goto out;
869 }
870
871 /* Try to find a timer already configured for the debounce period */
872 for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
873 u32 cycles;
874
875 cycles = ioread32(gpio->base + debounce_timers[i]);
876 if (requested_cycles == cycles)
877 break;
878 }
879
880 if (i == ARRAY_SIZE(debounce_timers)) {
881 int j;
882
883 /*
884 * As there are no timers configured for the requested debounce
885 * period, find an unused timer instead
886 */
887 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
888 if (gpio->timer_users[j] == 0)
889 break;
890 }
891
892 if (j == ARRAY_SIZE(gpio->timer_users)) {
893 dev_warn(chip->parent,
894 "Debounce timers exhausted, cannot debounce for period %luus\n",
895 usecs);
896
897 rc = -EPERM;
898
899 /*
900 * We already adjusted the accounting to remove @offset
901 * as a user of its previous timer, so also configure
902 * the hardware so @offset has timers disabled for
903 * consistency.
904 */
905 configure_timer(gpio, offset, 0);
906 goto out;
907 }
908
909 i = j;
910
911 iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
912 }
913
914 if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
915 rc = -EINVAL;
916 goto out;
917 }
918
919 register_allocated_timer(gpio, offset, i);
920 configure_timer(gpio, offset, i);
921
922out:
923 spin_unlock_irqrestore(&gpio->lock, flags);
924
925 return rc;
926}
927
928static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
929{
930 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
931 unsigned long flags;
932 int rc;
933
934 spin_lock_irqsave(&gpio->lock, flags);
935
936 rc = unregister_allocated_timer(gpio, offset);
937 if (!rc)
938 configure_timer(gpio, offset, 0);
939
940 spin_unlock_irqrestore(&gpio->lock, flags);
941
942 return rc;
943}
944
945static int set_debounce(struct gpio_chip *chip, unsigned int offset,
946 unsigned long usecs)
947{
948 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
949
950 if (!have_debounce(gpio, offset))
951 return -ENOTSUPP;
952
953 if (usecs)
954 return enable_debounce(chip, offset, usecs);
955
956 return disable_debounce(chip, offset);
957}
958
959static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
960 unsigned long config)
961{
962 unsigned long param = pinconf_to_config_param(config);
963 u32 arg = pinconf_to_config_argument(config);
964
965 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
966 return set_debounce(chip, offset, arg);
967 else if (param == PIN_CONFIG_BIAS_DISABLE ||
968 param == PIN_CONFIG_BIAS_PULL_DOWN ||
969 param == PIN_CONFIG_DRIVE_STRENGTH)
970 return pinctrl_gpio_set_config(offset, config);
971 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
972 param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
973 /* Return -ENOTSUPP to trigger emulation, as per datasheet */
974 return -ENOTSUPP;
975 else if (param == PIN_CONFIG_PERSIST_STATE)
976 return aspeed_gpio_reset_tolerance(chip, offset, arg);
977
978 return -ENOTSUPP;
979}
980
981/**
982 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handhsaking with
983 * the coprocessor for shared GPIO banks
984 * @ops: The callbacks
985 * @data: Pointer passed back to the callbacks
986 */
987int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data)
988{
989 copro_data = data;
990 copro_ops = ops;
991
992 return 0;
993}
994EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops);
995
996/**
997 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
998 * bank gets marked and any access from the ARM will
999 * result in handshaking via callbacks.
1000 * @desc: The GPIO to be marked
1001 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
1002 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
1003 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
1004 */
1005int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
1006 u16 *vreg_offset, u16 *dreg_offset, u8 *bit)
1007{
1008 struct gpio_chip *chip = gpiod_to_chip(desc);
1009 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1010 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
1011 const struct aspeed_gpio_bank *bank = to_bank(offset);
1012 unsigned long flags;
1013
1014 if (!gpio->cf_copro_bankmap)
1015 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
1016 if (!gpio->cf_copro_bankmap)
1017 return -ENOMEM;
1018 if (offset < 0 || offset > gpio->chip.ngpio)
1019 return -EINVAL;
1020 bindex = offset >> 3;
1021
1022 spin_lock_irqsave(&gpio->lock, flags);
1023
1024 /* Sanity check, this shouldn't happen */
1025 if (gpio->cf_copro_bankmap[bindex] == 0xff) {
1026 rc = -EIO;
1027 goto bail;
1028 }
1029 gpio->cf_copro_bankmap[bindex]++;
1030
1031 /* Switch command source */
1032 if (gpio->cf_copro_bankmap[bindex] == 1)
1033 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1034 GPIO_CMDSRC_COLDFIRE);
1035
1036 if (vreg_offset)
1037 *vreg_offset = bank->val_regs;
1038 if (dreg_offset)
1039 *dreg_offset = bank->rdata_reg;
1040 if (bit)
1041 *bit = GPIO_OFFSET(offset);
1042 bail:
1043 spin_unlock_irqrestore(&gpio->lock, flags);
1044 return rc;
1045}
1046EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
1047
1048/**
1049 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1050 * @desc: The GPIO to be marked
1051 */
1052int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc)
1053{
1054 struct gpio_chip *chip = gpiod_to_chip(desc);
1055 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1056 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
1057 const struct aspeed_gpio_bank *bank = to_bank(offset);
1058 unsigned long flags;
1059
1060 if (!gpio->cf_copro_bankmap)
1061 return -ENXIO;
1062
1063 if (offset < 0 || offset > gpio->chip.ngpio)
1064 return -EINVAL;
1065 bindex = offset >> 3;
1066
1067 spin_lock_irqsave(&gpio->lock, flags);
1068
1069 /* Sanity check, this shouldn't happen */
1070 if (gpio->cf_copro_bankmap[bindex] == 0) {
1071 rc = -EIO;
1072 goto bail;
1073 }
1074 gpio->cf_copro_bankmap[bindex]--;
1075
1076 /* Switch command source */
1077 if (gpio->cf_copro_bankmap[bindex] == 0)
1078 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1079 GPIO_CMDSRC_ARM);
1080 bail:
1081 spin_unlock_irqrestore(&gpio->lock, flags);
1082 return rc;
1083}
1084EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
1085
1086/*
1087 * Any banks not specified in a struct aspeed_bank_props array are assumed to
1088 * have the properties:
1089 *
1090 * { .input = 0xffffffff, .output = 0xffffffff }
1091 */
1092
1093static const struct aspeed_bank_props ast2400_bank_props[] = {
1094 /* input output */
1095 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1096 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1097 { },
1098};
1099
1100static const struct aspeed_gpio_config ast2400_config =
1101 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1102 { .nr_gpios = 220, .props = ast2400_bank_props, };
1103
1104static const struct aspeed_bank_props ast2500_bank_props[] = {
1105 /* input output */
1106 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1107 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1108 { 7, 0x000000ff, 0x000000ff }, /* AC */
1109 { },
1110};
1111
1112static const struct aspeed_gpio_config ast2500_config =
1113 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1114 { .nr_gpios = 232, .props = ast2500_bank_props, };
1115
1116static const struct aspeed_bank_props ast2600_bank_props[] = {
1117 /* input output */
1118 {5, 0xffffffff, 0x0000ffff}, /* U/V/W/X */
1119 {6, 0xffff0000, 0x0fff0000}, /* Y/Z */
1120 { },
1121};
1122
1123static const struct aspeed_gpio_config ast2600_config =
1124 /*
1125 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
1126 * We expect ngpio being set in the device tree and this is a fallback
1127 * option.
1128 */
1129 { .nr_gpios = 208, .props = ast2600_bank_props, };
1130
1131static const struct of_device_id aspeed_gpio_of_table[] = {
1132 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1133 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1134 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1135 {}
1136};
1137MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
1138
1139static int __init aspeed_gpio_probe(struct platform_device *pdev)
1140{
1141 const struct of_device_id *gpio_id;
1142 struct aspeed_gpio *gpio;
1143 int rc, i, banks, err;
1144 u32 ngpio;
1145
1146 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
1147 if (!gpio)
1148 return -ENOMEM;
1149
1150 gpio->base = devm_platform_ioremap_resource(pdev, 0);
1151 if (IS_ERR(gpio->base))
1152 return PTR_ERR(gpio->base);
1153
1154 spin_lock_init(&gpio->lock);
1155
1156 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
1157 if (!gpio_id)
1158 return -EINVAL;
1159
1160 gpio->clk = of_clk_get(pdev->dev.of_node, 0);
1161 if (IS_ERR(gpio->clk)) {
1162 dev_warn(&pdev->dev,
1163 "Failed to get clock from devicetree, debouncing disabled\n");
1164 gpio->clk = NULL;
1165 }
1166
1167 gpio->config = gpio_id->data;
1168
1169 gpio->chip.parent = &pdev->dev;
1170 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio);
1171 gpio->chip.ngpio = (u16) ngpio;
1172 if (err)
1173 gpio->chip.ngpio = gpio->config->nr_gpios;
1174 gpio->chip.direction_input = aspeed_gpio_dir_in;
1175 gpio->chip.direction_output = aspeed_gpio_dir_out;
1176 gpio->chip.get_direction = aspeed_gpio_get_direction;
1177 gpio->chip.request = aspeed_gpio_request;
1178 gpio->chip.free = aspeed_gpio_free;
1179 gpio->chip.get = aspeed_gpio_get;
1180 gpio->chip.set = aspeed_gpio_set;
1181 gpio->chip.set_config = aspeed_gpio_set_config;
1182 gpio->chip.label = dev_name(&pdev->dev);
1183 gpio->chip.base = -1;
1184
1185 /* Allocate a cache of the output registers */
1186 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
1187 gpio->dcache = devm_kcalloc(&pdev->dev,
1188 banks, sizeof(u32), GFP_KERNEL);
1189 if (!gpio->dcache)
1190 return -ENOMEM;
1191
1192 /*
1193 * Populate it with initial values read from the HW and switch
1194 * all command sources to the ARM by default
1195 */
1196 for (i = 0; i < banks; i++) {
1197 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
1198 void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
1199 gpio->dcache[i] = ioread32(addr);
1200 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
1201 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
1202 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
1203 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
1204 }
1205
1206 /* Optionally set up an irqchip if there is an IRQ */
1207 rc = platform_get_irq(pdev, 0);
1208 if (rc > 0) {
1209 struct gpio_irq_chip *girq;
1210
1211 gpio->irq = rc;
1212 girq = &gpio->chip.irq;
1213 girq->chip = &gpio->irqc;
1214 girq->chip->name = dev_name(&pdev->dev);
1215 girq->chip->irq_ack = aspeed_gpio_irq_ack;
1216 girq->chip->irq_mask = aspeed_gpio_irq_mask;
1217 girq->chip->irq_unmask = aspeed_gpio_irq_unmask;
1218 girq->chip->irq_set_type = aspeed_gpio_set_type;
1219 girq->parent_handler = aspeed_gpio_irq_handler;
1220 girq->num_parents = 1;
1221 girq->parents = devm_kcalloc(&pdev->dev, 1,
1222 sizeof(*girq->parents),
1223 GFP_KERNEL);
1224 if (!girq->parents)
1225 return -ENOMEM;
1226 girq->parents[0] = gpio->irq;
1227 girq->default_type = IRQ_TYPE_NONE;
1228 girq->handler = handle_bad_irq;
1229 girq->init_valid_mask = aspeed_init_irq_valid_mask;
1230 }
1231
1232 gpio->offset_timer =
1233 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
1234 if (!gpio->offset_timer)
1235 return -ENOMEM;
1236
1237 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
1238 if (rc < 0)
1239 return rc;
1240
1241 return 0;
1242}
1243
1244static struct platform_driver aspeed_gpio_driver = {
1245 .driver = {
1246 .name = KBUILD_MODNAME,
1247 .of_match_table = aspeed_gpio_of_table,
1248 },
1249};
1250
1251module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
1252
1253MODULE_DESCRIPTION("Aspeed GPIO Driver");
1254MODULE_LICENSE("GPL");