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1/*
2 * This control block defines the PACA which defines the processor
3 * specific data for each logical processor on the system.
4 * There are some pointers defined that are utilized by PLIC.
5 *
6 * C 2001 PPC 64 Team, IBM Corp
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13#ifndef _ASM_POWERPC_PACA_H
14#define _ASM_POWERPC_PACA_H
15#ifdef __KERNEL__
16
17#ifdef CONFIG_PPC64
18
19#include <linux/string.h>
20#include <asm/types.h>
21#include <asm/lppaca.h>
22#include <asm/mmu.h>
23#include <asm/page.h>
24#include <asm/exception-64e.h>
25#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
26#include <asm/kvm_book3s_asm.h>
27#endif
28
29register struct paca_struct *local_paca asm("r13");
30
31#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
32extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
33/*
34 * Add standard checks that preemption cannot occur when using get_paca():
35 * otherwise the paca_struct it points to may be the wrong one just after.
36 */
37#define get_paca() ((void) debug_smp_processor_id(), local_paca)
38#else
39#define get_paca() local_paca
40#endif
41
42#define get_lppaca() (get_paca()->lppaca_ptr)
43#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
44
45struct task_struct;
46
47/*
48 * Defines the layout of the paca.
49 *
50 * This structure is not directly accessed by firmware or the service
51 * processor.
52 */
53struct paca_struct {
54#ifdef CONFIG_PPC_BOOK3S
55 /*
56 * Because hw_cpu_id, unlike other paca fields, is accessed
57 * routinely from other CPUs (from the IRQ code), we stick to
58 * read-only (after boot) fields in the first cacheline to
59 * avoid cacheline bouncing.
60 */
61
62 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
63#endif /* CONFIG_PPC_BOOK3S */
64 /*
65 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
66 * load lock_token and paca_index with a single lwz
67 * instruction. They must travel together and be properly
68 * aligned.
69 */
70#ifdef __BIG_ENDIAN__
71 u16 lock_token; /* Constant 0x8000, used in locks */
72 u16 paca_index; /* Logical processor number */
73#else
74 u16 paca_index; /* Logical processor number */
75 u16 lock_token; /* Constant 0x8000, used in locks */
76#endif
77
78 u64 kernel_toc; /* Kernel TOC address */
79 u64 kernelbase; /* Base address of kernel */
80 u64 kernel_msr; /* MSR while running in kernel */
81 void *emergency_sp; /* pointer to emergency stack */
82 u64 data_offset; /* per cpu data offset */
83 s16 hw_cpu_id; /* Physical processor number */
84 u8 cpu_start; /* At startup, processor spins until */
85 /* this becomes non-zero. */
86 u8 kexec_state; /* set when kexec down has irqs off */
87#ifdef CONFIG_PPC_STD_MMU_64
88 struct slb_shadow *slb_shadow_ptr;
89 struct dtl_entry *dispatch_log;
90 struct dtl_entry *dispatch_log_end;
91#endif /* CONFIG_PPC_STD_MMU_64 */
92 u64 dscr_default; /* per-CPU default DSCR */
93
94#ifdef CONFIG_PPC_STD_MMU_64
95 /*
96 * Now, starting in cacheline 2, the exception save areas
97 */
98 /* used for most interrupts/exceptions */
99 u64 exgen[13] __attribute__((aligned(0x80)));
100 u64 exmc[13]; /* used for machine checks */
101 u64 exslb[13]; /* used for SLB/segment table misses
102 * on the linear mapping */
103 /* SLB related definitions */
104 u16 vmalloc_sllp;
105 u16 slb_cache_ptr;
106 u32 slb_cache[SLB_CACHE_ENTRIES];
107#endif /* CONFIG_PPC_STD_MMU_64 */
108
109#ifdef CONFIG_PPC_BOOK3E
110 u64 exgen[8] __aligned(0x40);
111 /* Keep pgd in the same cacheline as the start of extlb */
112 pgd_t *pgd __aligned(0x40); /* Current PGD */
113 pgd_t *kernel_pgd; /* Kernel PGD */
114
115 /* Shared by all threads of a core -- points to tcd of first thread */
116 struct tlb_core_data *tcd_ptr;
117
118 /*
119 * We can have up to 3 levels of reentrancy in the TLB miss handler,
120 * in each of four exception levels (normal, crit, mcheck, debug).
121 */
122 u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
123 u64 exmc[8]; /* used for machine checks */
124 u64 excrit[8]; /* used for crit interrupts */
125 u64 exdbg[8]; /* used for debug interrupts */
126
127 /* Kernel stack pointers for use by special exceptions */
128 void *mc_kstack;
129 void *crit_kstack;
130 void *dbg_kstack;
131
132 struct tlb_core_data tcd;
133#endif /* CONFIG_PPC_BOOK3E */
134
135#ifdef CONFIG_PPC_BOOK3S
136 mm_context_id_t mm_ctx_id;
137#ifdef CONFIG_PPC_MM_SLICES
138 u64 mm_ctx_low_slices_psize;
139 unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
140#else
141 u16 mm_ctx_user_psize;
142 u16 mm_ctx_sllp;
143#endif
144#endif
145
146 /*
147 * then miscellaneous read-write fields
148 */
149 struct task_struct *__current; /* Pointer to current */
150 u64 kstack; /* Saved Kernel stack addr */
151 u64 stab_rr; /* stab/slb round-robin counter */
152 u64 saved_r1; /* r1 save for RTAS calls or PM */
153 u64 saved_msr; /* MSR saved here by enter_rtas */
154 u16 trap_save; /* Used when bad stack is encountered */
155 u8 soft_enabled; /* irq soft-enable flag */
156 u8 irq_happened; /* irq happened while soft-disabled */
157 u8 io_sync; /* writel() needs spin_unlock sync */
158 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
159 u8 nap_state_lost; /* NV GPR values lost in power7_idle */
160 u64 sprg_vdso; /* Saved user-visible sprg */
161#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
162 u64 tm_scratch; /* TM scratch area for reclaim */
163#endif
164
165#ifdef CONFIG_PPC_POWERNV
166 /* Per-core mask tracking idle threads and a lock bit-[L][TTTTTTTT] */
167 u32 *core_idle_state_ptr;
168 u8 thread_idle_state; /* PNV_THREAD_RUNNING/NAP/SLEEP */
169 /* Mask to indicate thread id in core */
170 u8 thread_mask;
171 /* Mask to denote subcore sibling threads */
172 u8 subcore_sibling_mask;
173#endif
174
175#ifdef CONFIG_PPC_BOOK3S_64
176 /* Exclusive emergency stack pointer for machine check exception. */
177 void *mc_emergency_sp;
178 /*
179 * Flag to check whether we are in machine check early handler
180 * and already using emergency stack.
181 */
182 u16 in_mce;
183 u8 hmi_event_available; /* HMI event is available */
184#endif
185
186 /* Stuff for accurate time accounting */
187 u64 user_time; /* accumulated usermode TB ticks */
188 u64 system_time; /* accumulated system TB ticks */
189 u64 user_time_scaled; /* accumulated usermode SPURR ticks */
190 u64 starttime; /* TB value snapshot */
191 u64 starttime_user; /* TB value on exit to usermode */
192 u64 startspurr; /* SPURR value snapshot */
193 u64 utime_sspurr; /* ->user_time when ->startspurr set */
194 u64 stolen_time; /* TB ticks taken by hypervisor */
195 u64 dtl_ridx; /* read index in dispatch log */
196 struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */
197
198#ifdef CONFIG_KVM_BOOK3S_HANDLER
199#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
200 /* We use this to store guest state in */
201 struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
202#endif
203 struct kvmppc_host_state kvm_hstate;
204#endif
205};
206
207#ifdef CONFIG_PPC_BOOK3S
208static inline void copy_mm_to_paca(mm_context_t *context)
209{
210 get_paca()->mm_ctx_id = context->id;
211#ifdef CONFIG_PPC_MM_SLICES
212 get_paca()->mm_ctx_low_slices_psize = context->low_slices_psize;
213 memcpy(&get_paca()->mm_ctx_high_slices_psize,
214 &context->high_slices_psize, SLICE_ARRAY_SIZE);
215#else
216 get_paca()->mm_ctx_user_psize = context->user_psize;
217 get_paca()->mm_ctx_sllp = context->sllp;
218#endif
219}
220#else
221static inline void copy_mm_to_paca(mm_context_t *context){}
222#endif
223
224extern struct paca_struct *paca;
225extern void initialise_paca(struct paca_struct *new_paca, int cpu);
226extern void setup_paca(struct paca_struct *new_paca);
227extern void allocate_pacas(void);
228extern void free_unused_pacas(void);
229
230#else /* CONFIG_PPC64 */
231
232static inline void allocate_pacas(void) { };
233static inline void free_unused_pacas(void) { };
234
235#endif /* CONFIG_PPC64 */
236
237#endif /* __KERNEL__ */
238#endif /* _ASM_POWERPC_PACA_H */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * This control block defines the PACA which defines the processor
4 * specific data for each logical processor on the system.
5 * There are some pointers defined that are utilized by PLIC.
6 *
7 * C 2001 PPC 64 Team, IBM Corp
8 */
9#ifndef _ASM_POWERPC_PACA_H
10#define _ASM_POWERPC_PACA_H
11#ifdef __KERNEL__
12
13#ifdef CONFIG_PPC64
14
15#include <linux/string.h>
16#include <asm/types.h>
17#include <asm/lppaca.h>
18#include <asm/mmu.h>
19#include <asm/page.h>
20#ifdef CONFIG_PPC_BOOK3E
21#include <asm/exception-64e.h>
22#else
23#include <asm/exception-64s.h>
24#endif
25#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
26#include <asm/kvm_book3s_asm.h>
27#endif
28#include <asm/accounting.h>
29#include <asm/hmi.h>
30#include <asm/cpuidle.h>
31#include <asm/atomic.h>
32
33#include <asm-generic/mmiowb_types.h>
34
35register struct paca_struct *local_paca asm("r13");
36
37#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
38extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
39/*
40 * Add standard checks that preemption cannot occur when using get_paca():
41 * otherwise the paca_struct it points to may be the wrong one just after.
42 */
43#define get_paca() ((void) debug_smp_processor_id(), local_paca)
44#else
45#define get_paca() local_paca
46#endif
47
48#ifdef CONFIG_PPC_PSERIES
49#define get_lppaca() (get_paca()->lppaca_ptr)
50#endif
51
52#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
53
54struct task_struct;
55
56/*
57 * Defines the layout of the paca.
58 *
59 * This structure is not directly accessed by firmware or the service
60 * processor.
61 */
62struct paca_struct {
63#ifdef CONFIG_PPC_PSERIES
64 /*
65 * Because hw_cpu_id, unlike other paca fields, is accessed
66 * routinely from other CPUs (from the IRQ code), we stick to
67 * read-only (after boot) fields in the first cacheline to
68 * avoid cacheline bouncing.
69 */
70
71 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
72#endif /* CONFIG_PPC_PSERIES */
73
74 /*
75 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
76 * load lock_token and paca_index with a single lwz
77 * instruction. They must travel together and be properly
78 * aligned.
79 */
80#ifdef __BIG_ENDIAN__
81 u16 lock_token; /* Constant 0x8000, used in locks */
82 u16 paca_index; /* Logical processor number */
83#else
84 u16 paca_index; /* Logical processor number */
85 u16 lock_token; /* Constant 0x8000, used in locks */
86#endif
87
88 u64 kernel_toc; /* Kernel TOC address */
89 u64 kernelbase; /* Base address of kernel */
90 u64 kernel_msr; /* MSR while running in kernel */
91 void *emergency_sp; /* pointer to emergency stack */
92 u64 data_offset; /* per cpu data offset */
93 s16 hw_cpu_id; /* Physical processor number */
94 u8 cpu_start; /* At startup, processor spins until */
95 /* this becomes non-zero. */
96 u8 kexec_state; /* set when kexec down has irqs off */
97#ifdef CONFIG_PPC_BOOK3S_64
98 struct slb_shadow *slb_shadow_ptr;
99 struct dtl_entry *dispatch_log;
100 struct dtl_entry *dispatch_log_end;
101#endif
102 u64 dscr_default; /* per-CPU default DSCR */
103
104#ifdef CONFIG_PPC_BOOK3S_64
105 /*
106 * Now, starting in cacheline 2, the exception save areas
107 */
108 /* used for most interrupts/exceptions */
109 u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
110 u64 exslb[EX_SIZE]; /* used for SLB/segment table misses
111 * on the linear mapping */
112 /* SLB related definitions */
113 u16 vmalloc_sllp;
114 u8 slb_cache_ptr;
115 u8 stab_rr; /* stab/slb round-robin counter */
116#ifdef CONFIG_DEBUG_VM
117 u8 in_kernel_slb_handler;
118#endif
119 u32 slb_used_bitmap; /* Bitmaps for first 32 SLB entries. */
120 u32 slb_kern_bitmap;
121 u32 slb_cache[SLB_CACHE_ENTRIES];
122#endif /* CONFIG_PPC_BOOK3S_64 */
123
124#ifdef CONFIG_PPC_BOOK3E
125 u64 exgen[8] __aligned(0x40);
126 /* Keep pgd in the same cacheline as the start of extlb */
127 pgd_t *pgd __aligned(0x40); /* Current PGD */
128 pgd_t *kernel_pgd; /* Kernel PGD */
129
130 /* Shared by all threads of a core -- points to tcd of first thread */
131 struct tlb_core_data *tcd_ptr;
132
133 /*
134 * We can have up to 3 levels of reentrancy in the TLB miss handler,
135 * in each of four exception levels (normal, crit, mcheck, debug).
136 */
137 u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
138 u64 exmc[8]; /* used for machine checks */
139 u64 excrit[8]; /* used for crit interrupts */
140 u64 exdbg[8]; /* used for debug interrupts */
141
142 /* Kernel stack pointers for use by special exceptions */
143 void *mc_kstack;
144 void *crit_kstack;
145 void *dbg_kstack;
146
147 struct tlb_core_data tcd;
148#endif /* CONFIG_PPC_BOOK3E */
149
150#ifdef CONFIG_PPC_BOOK3S
151 mm_context_id_t mm_ctx_id;
152#ifdef CONFIG_PPC_MM_SLICES
153 unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
154 unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
155 unsigned long mm_ctx_slb_addr_limit;
156#else
157 u16 mm_ctx_user_psize;
158 u16 mm_ctx_sllp;
159#endif
160#endif
161
162 /*
163 * then miscellaneous read-write fields
164 */
165 struct task_struct *__current; /* Pointer to current */
166 u64 kstack; /* Saved Kernel stack addr */
167 u64 saved_r1; /* r1 save for RTAS calls or PM or EE=0 */
168 u64 saved_msr; /* MSR saved here by enter_rtas */
169#ifdef CONFIG_PPC_BOOK3E
170 u16 trap_save; /* Used when bad stack is encountered */
171#endif
172 u8 irq_soft_mask; /* mask for irq soft masking */
173 u8 irq_happened; /* irq happened while soft-disabled */
174 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
175#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
176 u8 pmcregs_in_use; /* pseries puts this in lppaca */
177#endif
178 u64 sprg_vdso; /* Saved user-visible sprg */
179#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
180 u64 tm_scratch; /* TM scratch area for reclaim */
181#endif
182
183#ifdef CONFIG_PPC_POWERNV
184 /* PowerNV idle fields */
185 /* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */
186 unsigned long idle_state;
187 union {
188 /* P7/P8 specific fields */
189 struct {
190 /* PNV_THREAD_RUNNING/NAP/SLEEP */
191 u8 thread_idle_state;
192 /* Mask to denote subcore sibling threads */
193 u8 subcore_sibling_mask;
194 };
195
196 /* P9 specific fields */
197 struct {
198#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
199 /* The PSSCR value that the kernel requested before going to stop */
200 u64 requested_psscr;
201 /* Flag to request this thread not to stop */
202 atomic_t dont_stop;
203#endif
204 };
205 };
206#endif
207
208#ifdef CONFIG_PPC_BOOK3S_64
209 /* Non-maskable exceptions that are not performance critical */
210 u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */
211 u64 exmc[EX_SIZE]; /* used for machine checks */
212#endif
213#ifdef CONFIG_PPC_BOOK3S_64
214 /* Exclusive stacks for system reset and machine check exception. */
215 void *nmi_emergency_sp;
216 void *mc_emergency_sp;
217
218 u16 in_nmi; /* In nmi handler */
219
220 /*
221 * Flag to check whether we are in machine check early handler
222 * and already using emergency stack.
223 */
224 u16 in_mce;
225 u8 hmi_event_available; /* HMI event is available */
226 u8 hmi_p9_special_emu; /* HMI P9 special emulation */
227#endif
228 u8 ftrace_enabled; /* Hard disable ftrace */
229
230 /* Stuff for accurate time accounting */
231 struct cpu_accounting_data accounting;
232 u64 dtl_ridx; /* read index in dispatch log */
233 struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */
234
235#ifdef CONFIG_KVM_BOOK3S_HANDLER
236#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
237 /* We use this to store guest state in */
238 struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
239#endif
240 struct kvmppc_host_state kvm_hstate;
241#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
242 /*
243 * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
244 * more details
245 */
246 struct sibling_subcore_state *sibling_subcore_state;
247#endif
248#endif
249#ifdef CONFIG_PPC_BOOK3S_64
250 /*
251 * rfi fallback flush must be in its own cacheline to prevent
252 * other paca data leaking into the L1d
253 */
254 u64 exrfi[EX_SIZE] __aligned(0x80);
255 void *rfi_flush_fallback_area;
256 u64 l1d_flush_size;
257#endif
258#ifdef CONFIG_PPC_PSERIES
259 u8 *mce_data_buf; /* buffer to hold per cpu rtas errlog */
260#endif /* CONFIG_PPC_PSERIES */
261
262#ifdef CONFIG_PPC_BOOK3S_64
263 /* Capture SLB related old contents in MCE handler. */
264 struct slb_entry *mce_faulty_slbs;
265 u16 slb_save_cache_ptr;
266#endif /* CONFIG_PPC_BOOK3S_64 */
267#ifdef CONFIG_STACKPROTECTOR
268 unsigned long canary;
269#endif
270#ifdef CONFIG_MMIOWB
271 struct mmiowb_state mmiowb_state;
272#endif
273} ____cacheline_aligned;
274
275extern void copy_mm_to_paca(struct mm_struct *mm);
276extern struct paca_struct **paca_ptrs;
277extern void initialise_paca(struct paca_struct *new_paca, int cpu);
278extern void setup_paca(struct paca_struct *new_paca);
279extern void allocate_paca_ptrs(void);
280extern void allocate_paca(int cpu);
281extern void free_unused_pacas(void);
282
283#else /* CONFIG_PPC64 */
284
285static inline void allocate_paca_ptrs(void) { };
286static inline void allocate_paca(int cpu) { };
287static inline void free_unused_pacas(void) { };
288
289#endif /* CONFIG_PPC64 */
290
291#endif /* __KERNEL__ */
292#endif /* _ASM_POWERPC_PACA_H */