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1/*
2 * core.c - DesignWare HS OTG Controller common routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * The Core code provides basic services for accessing and managing the
39 * DWC_otg hardware. These services are used by both the Host Controller
40 * Driver and the Peripheral Controller Driver.
41 */
42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/moduleparam.h>
45#include <linux/spinlock.h>
46#include <linux/interrupt.h>
47#include <linux/dma-mapping.h>
48#include <linux/delay.h>
49#include <linux/io.h>
50#include <linux/slab.h>
51#include <linux/usb.h>
52
53#include <linux/usb/hcd.h>
54#include <linux/usb/ch11.h>
55
56#include "core.h"
57#include "hcd.h"
58
59/**
60 * dwc2_backup_global_registers() - Backup global controller registers.
61 * When suspending usb bus, registers needs to be backuped
62 * if controller power is disabled once suspended.
63 *
64 * @hsotg: Programming view of the DWC_otg controller
65 */
66static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
67{
68 struct dwc2_gregs_backup *gr;
69 int i;
70
71 /* Backup global regs */
72 gr = &hsotg->gr_backup;
73
74 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
75 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
76 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
77 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
78 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
79 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
80 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
81 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
82 for (i = 0; i < MAX_EPS_CHANNELS; i++)
83 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
84
85 gr->valid = true;
86 return 0;
87}
88
89/**
90 * dwc2_restore_global_registers() - Restore controller global registers.
91 * When resuming usb bus, device registers needs to be restored
92 * if controller power were disabled.
93 *
94 * @hsotg: Programming view of the DWC_otg controller
95 */
96static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
97{
98 struct dwc2_gregs_backup *gr;
99 int i;
100
101 dev_dbg(hsotg->dev, "%s\n", __func__);
102
103 /* Restore global regs */
104 gr = &hsotg->gr_backup;
105 if (!gr->valid) {
106 dev_err(hsotg->dev, "%s: no global registers to restore\n",
107 __func__);
108 return -EINVAL;
109 }
110 gr->valid = false;
111
112 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
113 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
114 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
115 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
116 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
117 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
118 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
119 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
120 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
121 for (i = 0; i < MAX_EPS_CHANNELS; i++)
122 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
123
124 return 0;
125}
126
127/**
128 * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
129 *
130 * @hsotg: Programming view of the DWC_otg controller
131 * @restore: Controller registers need to be restored
132 */
133int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
134{
135 u32 pcgcctl;
136 int ret = 0;
137
138 if (!hsotg->core_params->hibernation)
139 return -ENOTSUPP;
140
141 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
142 pcgcctl &= ~PCGCTL_STOPPCLK;
143 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
144
145 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
146 pcgcctl &= ~PCGCTL_PWRCLMP;
147 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
148
149 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
150 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
151 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
152
153 udelay(100);
154 if (restore) {
155 ret = dwc2_restore_global_registers(hsotg);
156 if (ret) {
157 dev_err(hsotg->dev, "%s: failed to restore registers\n",
158 __func__);
159 return ret;
160 }
161 if (dwc2_is_host_mode(hsotg)) {
162 ret = dwc2_restore_host_registers(hsotg);
163 if (ret) {
164 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
165 __func__);
166 return ret;
167 }
168 } else {
169 ret = dwc2_restore_device_registers(hsotg);
170 if (ret) {
171 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
172 __func__);
173 return ret;
174 }
175 }
176 }
177
178 return ret;
179}
180
181/**
182 * dwc2_enter_hibernation() - Put controller in Partial Power Down.
183 *
184 * @hsotg: Programming view of the DWC_otg controller
185 */
186int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
187{
188 u32 pcgcctl;
189 int ret = 0;
190
191 if (!hsotg->core_params->hibernation)
192 return -ENOTSUPP;
193
194 /* Backup all registers */
195 ret = dwc2_backup_global_registers(hsotg);
196 if (ret) {
197 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
198 __func__);
199 return ret;
200 }
201
202 if (dwc2_is_host_mode(hsotg)) {
203 ret = dwc2_backup_host_registers(hsotg);
204 if (ret) {
205 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
206 __func__);
207 return ret;
208 }
209 } else {
210 ret = dwc2_backup_device_registers(hsotg);
211 if (ret) {
212 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
213 __func__);
214 return ret;
215 }
216 }
217
218 /*
219 * Clear any pending interrupts since dwc2 will not be able to
220 * clear them after entering hibernation.
221 */
222 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
223
224 /* Put the controller in low power state */
225 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
226
227 pcgcctl |= PCGCTL_PWRCLMP;
228 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
229 ndelay(20);
230
231 pcgcctl |= PCGCTL_RSTPDWNMODULE;
232 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
233 ndelay(20);
234
235 pcgcctl |= PCGCTL_STOPPCLK;
236 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
237
238 return ret;
239}
240
241/*
242 * Do core a soft reset of the core. Be careful with this because it
243 * resets all the internal state machines of the core.
244 */
245int dwc2_core_reset(struct dwc2_hsotg *hsotg)
246{
247 u32 greset;
248 int count = 0;
249
250 dev_vdbg(hsotg->dev, "%s()\n", __func__);
251
252 /* Core Soft Reset */
253 greset = dwc2_readl(hsotg->regs + GRSTCTL);
254 greset |= GRSTCTL_CSFTRST;
255 dwc2_writel(greset, hsotg->regs + GRSTCTL);
256 do {
257 udelay(1);
258 greset = dwc2_readl(hsotg->regs + GRSTCTL);
259 if (++count > 50) {
260 dev_warn(hsotg->dev,
261 "%s() HANG! Soft Reset GRSTCTL=%0x\n",
262 __func__, greset);
263 return -EBUSY;
264 }
265 } while (greset & GRSTCTL_CSFTRST);
266
267 /* Wait for AHB master IDLE state */
268 count = 0;
269 do {
270 udelay(1);
271 greset = dwc2_readl(hsotg->regs + GRSTCTL);
272 if (++count > 50) {
273 dev_warn(hsotg->dev,
274 "%s() HANG! AHB Idle GRSTCTL=%0x\n",
275 __func__, greset);
276 return -EBUSY;
277 }
278 } while (!(greset & GRSTCTL_AHBIDLE));
279
280 return 0;
281}
282
283/*
284 * Force the mode of the controller.
285 *
286 * Forcing the mode is needed for two cases:
287 *
288 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
289 * controller to stay in a particular mode regardless of ID pin
290 * changes. We do this usually after a core reset.
291 *
292 * 2) During probe we want to read reset values of the hw
293 * configuration registers that are only available in either host or
294 * device mode. We may need to force the mode if the current mode does
295 * not allow us to access the register in the mode that we want.
296 *
297 * In either case it only makes sense to force the mode if the
298 * controller hardware is OTG capable.
299 *
300 * Checks are done in this function to determine whether doing a force
301 * would be valid or not.
302 *
303 * If a force is done, it requires a 25ms delay to take effect.
304 *
305 * Returns true if the mode was forced.
306 */
307static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
308{
309 u32 gusbcfg;
310 u32 set;
311 u32 clear;
312
313 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
314
315 /*
316 * Force mode has no effect if the hardware is not OTG.
317 */
318 if (!dwc2_hw_is_otg(hsotg))
319 return false;
320
321 /*
322 * If dr_mode is either peripheral or host only, there is no
323 * need to ever force the mode to the opposite mode.
324 */
325 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
326 return false;
327
328 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
329 return false;
330
331 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
332
333 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
334 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
335
336 gusbcfg &= ~clear;
337 gusbcfg |= set;
338 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
339
340 msleep(25);
341 return true;
342}
343
344/*
345 * Clears the force mode bits.
346 */
347static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
348{
349 u32 gusbcfg;
350
351 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
352 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
353 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
354 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
355
356 /*
357 * NOTE: This long sleep is _very_ important, otherwise the core will
358 * not stay in host mode after a connector ID change!
359 */
360 msleep(25);
361}
362
363/*
364 * Sets or clears force mode based on the dr_mode parameter.
365 */
366void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
367{
368 switch (hsotg->dr_mode) {
369 case USB_DR_MODE_HOST:
370 dwc2_force_mode(hsotg, true);
371 break;
372 case USB_DR_MODE_PERIPHERAL:
373 dwc2_force_mode(hsotg, false);
374 break;
375 case USB_DR_MODE_OTG:
376 dwc2_clear_force_mode(hsotg);
377 break;
378 default:
379 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
380 __func__, hsotg->dr_mode);
381 break;
382 }
383
384 /*
385 * NOTE: This is required for some rockchip soc based
386 * platforms.
387 */
388 msleep(50);
389}
390
391/*
392 * Do core a soft reset of the core. Be careful with this because it
393 * resets all the internal state machines of the core.
394 *
395 * Additionally this will apply force mode as per the hsotg->dr_mode
396 * parameter.
397 */
398int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
399{
400 int retval;
401
402 retval = dwc2_core_reset(hsotg);
403 if (retval)
404 return retval;
405
406 dwc2_force_dr_mode(hsotg);
407 return 0;
408}
409
410/**
411 * dwc2_dump_host_registers() - Prints the host registers
412 *
413 * @hsotg: Programming view of DWC_otg controller
414 *
415 * NOTE: This function will be removed once the peripheral controller code
416 * is integrated and the driver is stable
417 */
418void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
419{
420#ifdef DEBUG
421 u32 __iomem *addr;
422 int i;
423
424 dev_dbg(hsotg->dev, "Host Global Registers\n");
425 addr = hsotg->regs + HCFG;
426 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
427 (unsigned long)addr, dwc2_readl(addr));
428 addr = hsotg->regs + HFIR;
429 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
430 (unsigned long)addr, dwc2_readl(addr));
431 addr = hsotg->regs + HFNUM;
432 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
433 (unsigned long)addr, dwc2_readl(addr));
434 addr = hsotg->regs + HPTXSTS;
435 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
436 (unsigned long)addr, dwc2_readl(addr));
437 addr = hsotg->regs + HAINT;
438 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
439 (unsigned long)addr, dwc2_readl(addr));
440 addr = hsotg->regs + HAINTMSK;
441 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
442 (unsigned long)addr, dwc2_readl(addr));
443 if (hsotg->core_params->dma_desc_enable > 0) {
444 addr = hsotg->regs + HFLBADDR;
445 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
446 (unsigned long)addr, dwc2_readl(addr));
447 }
448
449 addr = hsotg->regs + HPRT0;
450 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
451 (unsigned long)addr, dwc2_readl(addr));
452
453 for (i = 0; i < hsotg->core_params->host_channels; i++) {
454 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
455 addr = hsotg->regs + HCCHAR(i);
456 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
457 (unsigned long)addr, dwc2_readl(addr));
458 addr = hsotg->regs + HCSPLT(i);
459 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
460 (unsigned long)addr, dwc2_readl(addr));
461 addr = hsotg->regs + HCINT(i);
462 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
463 (unsigned long)addr, dwc2_readl(addr));
464 addr = hsotg->regs + HCINTMSK(i);
465 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
466 (unsigned long)addr, dwc2_readl(addr));
467 addr = hsotg->regs + HCTSIZ(i);
468 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
469 (unsigned long)addr, dwc2_readl(addr));
470 addr = hsotg->regs + HCDMA(i);
471 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
472 (unsigned long)addr, dwc2_readl(addr));
473 if (hsotg->core_params->dma_desc_enable > 0) {
474 addr = hsotg->regs + HCDMAB(i);
475 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
476 (unsigned long)addr, dwc2_readl(addr));
477 }
478 }
479#endif
480}
481
482/**
483 * dwc2_dump_global_registers() - Prints the core global registers
484 *
485 * @hsotg: Programming view of DWC_otg controller
486 *
487 * NOTE: This function will be removed once the peripheral controller code
488 * is integrated and the driver is stable
489 */
490void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
491{
492#ifdef DEBUG
493 u32 __iomem *addr;
494
495 dev_dbg(hsotg->dev, "Core Global Registers\n");
496 addr = hsotg->regs + GOTGCTL;
497 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
498 (unsigned long)addr, dwc2_readl(addr));
499 addr = hsotg->regs + GOTGINT;
500 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
501 (unsigned long)addr, dwc2_readl(addr));
502 addr = hsotg->regs + GAHBCFG;
503 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
504 (unsigned long)addr, dwc2_readl(addr));
505 addr = hsotg->regs + GUSBCFG;
506 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
507 (unsigned long)addr, dwc2_readl(addr));
508 addr = hsotg->regs + GRSTCTL;
509 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
510 (unsigned long)addr, dwc2_readl(addr));
511 addr = hsotg->regs + GINTSTS;
512 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
513 (unsigned long)addr, dwc2_readl(addr));
514 addr = hsotg->regs + GINTMSK;
515 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
516 (unsigned long)addr, dwc2_readl(addr));
517 addr = hsotg->regs + GRXSTSR;
518 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
519 (unsigned long)addr, dwc2_readl(addr));
520 addr = hsotg->regs + GRXFSIZ;
521 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
522 (unsigned long)addr, dwc2_readl(addr));
523 addr = hsotg->regs + GNPTXFSIZ;
524 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
525 (unsigned long)addr, dwc2_readl(addr));
526 addr = hsotg->regs + GNPTXSTS;
527 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
528 (unsigned long)addr, dwc2_readl(addr));
529 addr = hsotg->regs + GI2CCTL;
530 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
531 (unsigned long)addr, dwc2_readl(addr));
532 addr = hsotg->regs + GPVNDCTL;
533 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
534 (unsigned long)addr, dwc2_readl(addr));
535 addr = hsotg->regs + GGPIO;
536 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
537 (unsigned long)addr, dwc2_readl(addr));
538 addr = hsotg->regs + GUID;
539 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
540 (unsigned long)addr, dwc2_readl(addr));
541 addr = hsotg->regs + GSNPSID;
542 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
543 (unsigned long)addr, dwc2_readl(addr));
544 addr = hsotg->regs + GHWCFG1;
545 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
546 (unsigned long)addr, dwc2_readl(addr));
547 addr = hsotg->regs + GHWCFG2;
548 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
549 (unsigned long)addr, dwc2_readl(addr));
550 addr = hsotg->regs + GHWCFG3;
551 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
552 (unsigned long)addr, dwc2_readl(addr));
553 addr = hsotg->regs + GHWCFG4;
554 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
555 (unsigned long)addr, dwc2_readl(addr));
556 addr = hsotg->regs + GLPMCFG;
557 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
558 (unsigned long)addr, dwc2_readl(addr));
559 addr = hsotg->regs + GPWRDN;
560 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
561 (unsigned long)addr, dwc2_readl(addr));
562 addr = hsotg->regs + GDFIFOCFG;
563 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
564 (unsigned long)addr, dwc2_readl(addr));
565 addr = hsotg->regs + HPTXFSIZ;
566 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
567 (unsigned long)addr, dwc2_readl(addr));
568
569 addr = hsotg->regs + PCGCTL;
570 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
571 (unsigned long)addr, dwc2_readl(addr));
572#endif
573}
574
575/**
576 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
577 *
578 * @hsotg: Programming view of DWC_otg controller
579 * @num: Tx FIFO to flush
580 */
581void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
582{
583 u32 greset;
584 int count = 0;
585
586 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
587
588 greset = GRSTCTL_TXFFLSH;
589 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
590 dwc2_writel(greset, hsotg->regs + GRSTCTL);
591
592 do {
593 greset = dwc2_readl(hsotg->regs + GRSTCTL);
594 if (++count > 10000) {
595 dev_warn(hsotg->dev,
596 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
597 __func__, greset,
598 dwc2_readl(hsotg->regs + GNPTXSTS));
599 break;
600 }
601 udelay(1);
602 } while (greset & GRSTCTL_TXFFLSH);
603
604 /* Wait for at least 3 PHY Clocks */
605 udelay(1);
606}
607
608/**
609 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
610 *
611 * @hsotg: Programming view of DWC_otg controller
612 */
613void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
614{
615 u32 greset;
616 int count = 0;
617
618 dev_vdbg(hsotg->dev, "%s()\n", __func__);
619
620 greset = GRSTCTL_RXFFLSH;
621 dwc2_writel(greset, hsotg->regs + GRSTCTL);
622
623 do {
624 greset = dwc2_readl(hsotg->regs + GRSTCTL);
625 if (++count > 10000) {
626 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
627 __func__, greset);
628 break;
629 }
630 udelay(1);
631 } while (greset & GRSTCTL_RXFFLSH);
632
633 /* Wait for at least 3 PHY Clocks */
634 udelay(1);
635}
636
637#define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c))
638
639/* Parameter access functions */
640void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
641{
642 int valid = 1;
643
644 switch (val) {
645 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
646 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
647 valid = 0;
648 break;
649 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
650 switch (hsotg->hw_params.op_mode) {
651 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
652 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
653 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
654 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
655 break;
656 default:
657 valid = 0;
658 break;
659 }
660 break;
661 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
662 /* always valid */
663 break;
664 default:
665 valid = 0;
666 break;
667 }
668
669 if (!valid) {
670 if (val >= 0)
671 dev_err(hsotg->dev,
672 "%d invalid for otg_cap parameter. Check HW configuration.\n",
673 val);
674 switch (hsotg->hw_params.op_mode) {
675 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
676 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
677 break;
678 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
679 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
680 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
681 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
682 break;
683 default:
684 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
685 break;
686 }
687 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
688 }
689
690 hsotg->core_params->otg_cap = val;
691}
692
693void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
694{
695 int valid = 1;
696
697 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
698 valid = 0;
699 if (val < 0)
700 valid = 0;
701
702 if (!valid) {
703 if (val >= 0)
704 dev_err(hsotg->dev,
705 "%d invalid for dma_enable parameter. Check HW configuration.\n",
706 val);
707 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
708 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
709 }
710
711 hsotg->core_params->dma_enable = val;
712}
713
714void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
715{
716 int valid = 1;
717
718 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
719 !hsotg->hw_params.dma_desc_enable))
720 valid = 0;
721 if (val < 0)
722 valid = 0;
723
724 if (!valid) {
725 if (val >= 0)
726 dev_err(hsotg->dev,
727 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
728 val);
729 val = (hsotg->core_params->dma_enable > 0 &&
730 hsotg->hw_params.dma_desc_enable);
731 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
732 }
733
734 hsotg->core_params->dma_desc_enable = val;
735}
736
737void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
738{
739 int valid = 1;
740
741 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
742 !hsotg->hw_params.dma_desc_enable))
743 valid = 0;
744 if (val < 0)
745 valid = 0;
746
747 if (!valid) {
748 if (val >= 0)
749 dev_err(hsotg->dev,
750 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
751 val);
752 val = (hsotg->core_params->dma_enable > 0 &&
753 hsotg->hw_params.dma_desc_enable);
754 }
755
756 hsotg->core_params->dma_desc_fs_enable = val;
757 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
758}
759
760void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
761 int val)
762{
763 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
764 if (val >= 0) {
765 dev_err(hsotg->dev,
766 "Wrong value for host_support_fs_low_power\n");
767 dev_err(hsotg->dev,
768 "host_support_fs_low_power must be 0 or 1\n");
769 }
770 val = 0;
771 dev_dbg(hsotg->dev,
772 "Setting host_support_fs_low_power to %d\n", val);
773 }
774
775 hsotg->core_params->host_support_fs_ls_low_power = val;
776}
777
778void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
779{
780 int valid = 1;
781
782 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
783 valid = 0;
784 if (val < 0)
785 valid = 0;
786
787 if (!valid) {
788 if (val >= 0)
789 dev_err(hsotg->dev,
790 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
791 val);
792 val = hsotg->hw_params.enable_dynamic_fifo;
793 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
794 }
795
796 hsotg->core_params->enable_dynamic_fifo = val;
797}
798
799void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
800{
801 int valid = 1;
802
803 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
804 valid = 0;
805
806 if (!valid) {
807 if (val >= 0)
808 dev_err(hsotg->dev,
809 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
810 val);
811 val = hsotg->hw_params.host_rx_fifo_size;
812 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
813 }
814
815 hsotg->core_params->host_rx_fifo_size = val;
816}
817
818void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
819{
820 int valid = 1;
821
822 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
823 valid = 0;
824
825 if (!valid) {
826 if (val >= 0)
827 dev_err(hsotg->dev,
828 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
829 val);
830 val = hsotg->hw_params.host_nperio_tx_fifo_size;
831 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
832 val);
833 }
834
835 hsotg->core_params->host_nperio_tx_fifo_size = val;
836}
837
838void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
839{
840 int valid = 1;
841
842 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
843 valid = 0;
844
845 if (!valid) {
846 if (val >= 0)
847 dev_err(hsotg->dev,
848 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
849 val);
850 val = hsotg->hw_params.host_perio_tx_fifo_size;
851 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
852 val);
853 }
854
855 hsotg->core_params->host_perio_tx_fifo_size = val;
856}
857
858void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
859{
860 int valid = 1;
861
862 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
863 valid = 0;
864
865 if (!valid) {
866 if (val >= 0)
867 dev_err(hsotg->dev,
868 "%d invalid for max_transfer_size. Check HW configuration.\n",
869 val);
870 val = hsotg->hw_params.max_transfer_size;
871 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
872 }
873
874 hsotg->core_params->max_transfer_size = val;
875}
876
877void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
878{
879 int valid = 1;
880
881 if (val < 15 || val > hsotg->hw_params.max_packet_count)
882 valid = 0;
883
884 if (!valid) {
885 if (val >= 0)
886 dev_err(hsotg->dev,
887 "%d invalid for max_packet_count. Check HW configuration.\n",
888 val);
889 val = hsotg->hw_params.max_packet_count;
890 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
891 }
892
893 hsotg->core_params->max_packet_count = val;
894}
895
896void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
897{
898 int valid = 1;
899
900 if (val < 1 || val > hsotg->hw_params.host_channels)
901 valid = 0;
902
903 if (!valid) {
904 if (val >= 0)
905 dev_err(hsotg->dev,
906 "%d invalid for host_channels. Check HW configuration.\n",
907 val);
908 val = hsotg->hw_params.host_channels;
909 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
910 }
911
912 hsotg->core_params->host_channels = val;
913}
914
915void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
916{
917 int valid = 0;
918 u32 hs_phy_type, fs_phy_type;
919
920 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
921 DWC2_PHY_TYPE_PARAM_ULPI)) {
922 if (val >= 0) {
923 dev_err(hsotg->dev, "Wrong value for phy_type\n");
924 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
925 }
926
927 valid = 0;
928 }
929
930 hs_phy_type = hsotg->hw_params.hs_phy_type;
931 fs_phy_type = hsotg->hw_params.fs_phy_type;
932 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
933 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
934 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
935 valid = 1;
936 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
937 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
938 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
939 valid = 1;
940 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
941 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
942 valid = 1;
943
944 if (!valid) {
945 if (val >= 0)
946 dev_err(hsotg->dev,
947 "%d invalid for phy_type. Check HW configuration.\n",
948 val);
949 val = DWC2_PHY_TYPE_PARAM_FS;
950 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
951 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
952 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
953 val = DWC2_PHY_TYPE_PARAM_UTMI;
954 else
955 val = DWC2_PHY_TYPE_PARAM_ULPI;
956 }
957 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
958 }
959
960 hsotg->core_params->phy_type = val;
961}
962
963static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
964{
965 return hsotg->core_params->phy_type;
966}
967
968void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
969{
970 int valid = 1;
971
972 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
973 if (val >= 0) {
974 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
975 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
976 }
977 valid = 0;
978 }
979
980 if (val == DWC2_SPEED_PARAM_HIGH &&
981 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
982 valid = 0;
983
984 if (!valid) {
985 if (val >= 0)
986 dev_err(hsotg->dev,
987 "%d invalid for speed parameter. Check HW configuration.\n",
988 val);
989 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
990 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
991 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
992 }
993
994 hsotg->core_params->speed = val;
995}
996
997void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
998{
999 int valid = 1;
1000
1001 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
1002 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
1003 if (val >= 0) {
1004 dev_err(hsotg->dev,
1005 "Wrong value for host_ls_low_power_phy_clk parameter\n");
1006 dev_err(hsotg->dev,
1007 "host_ls_low_power_phy_clk must be 0 or 1\n");
1008 }
1009 valid = 0;
1010 }
1011
1012 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
1013 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
1014 valid = 0;
1015
1016 if (!valid) {
1017 if (val >= 0)
1018 dev_err(hsotg->dev,
1019 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
1020 val);
1021 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
1022 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
1023 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
1024 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
1025 val);
1026 }
1027
1028 hsotg->core_params->host_ls_low_power_phy_clk = val;
1029}
1030
1031void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
1032{
1033 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1034 if (val >= 0) {
1035 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
1036 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
1037 }
1038 val = 0;
1039 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
1040 }
1041
1042 hsotg->core_params->phy_ulpi_ddr = val;
1043}
1044
1045void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
1046{
1047 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1048 if (val >= 0) {
1049 dev_err(hsotg->dev,
1050 "Wrong value for phy_ulpi_ext_vbus\n");
1051 dev_err(hsotg->dev,
1052 "phy_ulpi_ext_vbus must be 0 or 1\n");
1053 }
1054 val = 0;
1055 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
1056 }
1057
1058 hsotg->core_params->phy_ulpi_ext_vbus = val;
1059}
1060
1061void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
1062{
1063 int valid = 0;
1064
1065 switch (hsotg->hw_params.utmi_phy_data_width) {
1066 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
1067 valid = (val == 8);
1068 break;
1069 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
1070 valid = (val == 16);
1071 break;
1072 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
1073 valid = (val == 8 || val == 16);
1074 break;
1075 }
1076
1077 if (!valid) {
1078 if (val >= 0) {
1079 dev_err(hsotg->dev,
1080 "%d invalid for phy_utmi_width. Check HW configuration.\n",
1081 val);
1082 }
1083 val = (hsotg->hw_params.utmi_phy_data_width ==
1084 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
1085 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
1086 }
1087
1088 hsotg->core_params->phy_utmi_width = val;
1089}
1090
1091void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
1092{
1093 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1094 if (val >= 0) {
1095 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
1096 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
1097 }
1098 val = 0;
1099 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
1100 }
1101
1102 hsotg->core_params->ulpi_fs_ls = val;
1103}
1104
1105void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
1106{
1107 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1108 if (val >= 0) {
1109 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
1110 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
1111 }
1112 val = 0;
1113 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
1114 }
1115
1116 hsotg->core_params->ts_dline = val;
1117}
1118
1119void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
1120{
1121 int valid = 1;
1122
1123 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1124 if (val >= 0) {
1125 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
1126 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
1127 }
1128
1129 valid = 0;
1130 }
1131
1132 if (val == 1 && !(hsotg->hw_params.i2c_enable))
1133 valid = 0;
1134
1135 if (!valid) {
1136 if (val >= 0)
1137 dev_err(hsotg->dev,
1138 "%d invalid for i2c_enable. Check HW configuration.\n",
1139 val);
1140 val = hsotg->hw_params.i2c_enable;
1141 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
1142 }
1143
1144 hsotg->core_params->i2c_enable = val;
1145}
1146
1147void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
1148{
1149 int valid = 1;
1150
1151 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1152 if (val >= 0) {
1153 dev_err(hsotg->dev,
1154 "Wrong value for en_multiple_tx_fifo,\n");
1155 dev_err(hsotg->dev,
1156 "en_multiple_tx_fifo must be 0 or 1\n");
1157 }
1158 valid = 0;
1159 }
1160
1161 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
1162 valid = 0;
1163
1164 if (!valid) {
1165 if (val >= 0)
1166 dev_err(hsotg->dev,
1167 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
1168 val);
1169 val = hsotg->hw_params.en_multiple_tx_fifo;
1170 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
1171 }
1172
1173 hsotg->core_params->en_multiple_tx_fifo = val;
1174}
1175
1176void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
1177{
1178 int valid = 1;
1179
1180 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1181 if (val >= 0) {
1182 dev_err(hsotg->dev,
1183 "'%d' invalid for parameter reload_ctl\n", val);
1184 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
1185 }
1186 valid = 0;
1187 }
1188
1189 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
1190 valid = 0;
1191
1192 if (!valid) {
1193 if (val >= 0)
1194 dev_err(hsotg->dev,
1195 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
1196 val);
1197 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
1198 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
1199 }
1200
1201 hsotg->core_params->reload_ctl = val;
1202}
1203
1204void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
1205{
1206 if (val != -1)
1207 hsotg->core_params->ahbcfg = val;
1208 else
1209 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
1210 GAHBCFG_HBSTLEN_SHIFT;
1211}
1212
1213void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
1214{
1215 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1216 if (val >= 0) {
1217 dev_err(hsotg->dev,
1218 "'%d' invalid for parameter otg_ver\n", val);
1219 dev_err(hsotg->dev,
1220 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
1221 }
1222 val = 0;
1223 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
1224 }
1225
1226 hsotg->core_params->otg_ver = val;
1227}
1228
1229static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
1230{
1231 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1232 if (val >= 0) {
1233 dev_err(hsotg->dev,
1234 "'%d' invalid for parameter uframe_sched\n",
1235 val);
1236 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
1237 }
1238 val = 1;
1239 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
1240 }
1241
1242 hsotg->core_params->uframe_sched = val;
1243}
1244
1245static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
1246 int val)
1247{
1248 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1249 if (val >= 0) {
1250 dev_err(hsotg->dev,
1251 "'%d' invalid for parameter external_id_pin_ctl\n",
1252 val);
1253 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
1254 }
1255 val = 0;
1256 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
1257 }
1258
1259 hsotg->core_params->external_id_pin_ctl = val;
1260}
1261
1262static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
1263 int val)
1264{
1265 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1266 if (val >= 0) {
1267 dev_err(hsotg->dev,
1268 "'%d' invalid for parameter hibernation\n",
1269 val);
1270 dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
1271 }
1272 val = 0;
1273 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
1274 }
1275
1276 hsotg->core_params->hibernation = val;
1277}
1278
1279/*
1280 * This function is called during module intialization to pass module parameters
1281 * for the DWC_otg core.
1282 */
1283void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1284 const struct dwc2_core_params *params)
1285{
1286 dev_dbg(hsotg->dev, "%s()\n", __func__);
1287
1288 dwc2_set_param_otg_cap(hsotg, params->otg_cap);
1289 dwc2_set_param_dma_enable(hsotg, params->dma_enable);
1290 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
1291 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
1292 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
1293 params->host_support_fs_ls_low_power);
1294 dwc2_set_param_enable_dynamic_fifo(hsotg,
1295 params->enable_dynamic_fifo);
1296 dwc2_set_param_host_rx_fifo_size(hsotg,
1297 params->host_rx_fifo_size);
1298 dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
1299 params->host_nperio_tx_fifo_size);
1300 dwc2_set_param_host_perio_tx_fifo_size(hsotg,
1301 params->host_perio_tx_fifo_size);
1302 dwc2_set_param_max_transfer_size(hsotg,
1303 params->max_transfer_size);
1304 dwc2_set_param_max_packet_count(hsotg,
1305 params->max_packet_count);
1306 dwc2_set_param_host_channels(hsotg, params->host_channels);
1307 dwc2_set_param_phy_type(hsotg, params->phy_type);
1308 dwc2_set_param_speed(hsotg, params->speed);
1309 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
1310 params->host_ls_low_power_phy_clk);
1311 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
1312 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
1313 params->phy_ulpi_ext_vbus);
1314 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
1315 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
1316 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
1317 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
1318 dwc2_set_param_en_multiple_tx_fifo(hsotg,
1319 params->en_multiple_tx_fifo);
1320 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
1321 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
1322 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
1323 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
1324 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
1325 dwc2_set_param_hibernation(hsotg, params->hibernation);
1326}
1327
1328/*
1329 * Forces either host or device mode if the controller is not
1330 * currently in that mode.
1331 *
1332 * Returns true if the mode was forced.
1333 */
1334static bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
1335{
1336 if (host && dwc2_is_host_mode(hsotg))
1337 return false;
1338 else if (!host && dwc2_is_device_mode(hsotg))
1339 return false;
1340
1341 return dwc2_force_mode(hsotg, host);
1342}
1343
1344/*
1345 * Gets host hardware parameters. Forces host mode if not currently in
1346 * host mode. Should be called immediately after a core soft reset in
1347 * order to get the reset values.
1348 */
1349static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
1350{
1351 struct dwc2_hw_params *hw = &hsotg->hw_params;
1352 u32 gnptxfsiz;
1353 u32 hptxfsiz;
1354 bool forced;
1355
1356 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
1357 return;
1358
1359 forced = dwc2_force_mode_if_needed(hsotg, true);
1360
1361 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1362 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
1363 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1364 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
1365
1366 if (forced)
1367 dwc2_clear_force_mode(hsotg);
1368
1369 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1370 FIFOSIZE_DEPTH_SHIFT;
1371 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1372 FIFOSIZE_DEPTH_SHIFT;
1373}
1374
1375/*
1376 * Gets device hardware parameters. Forces device mode if not
1377 * currently in device mode. Should be called immediately after a core
1378 * soft reset in order to get the reset values.
1379 */
1380static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
1381{
1382 struct dwc2_hw_params *hw = &hsotg->hw_params;
1383 bool forced;
1384 u32 gnptxfsiz;
1385
1386 if (hsotg->dr_mode == USB_DR_MODE_HOST)
1387 return;
1388
1389 forced = dwc2_force_mode_if_needed(hsotg, false);
1390
1391 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1392 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1393
1394 if (forced)
1395 dwc2_clear_force_mode(hsotg);
1396
1397 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1398 FIFOSIZE_DEPTH_SHIFT;
1399}
1400
1401/**
1402 * During device initialization, read various hardware configuration
1403 * registers and interpret the contents.
1404 */
1405int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
1406{
1407 struct dwc2_hw_params *hw = &hsotg->hw_params;
1408 unsigned width;
1409 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
1410 u32 grxfsiz;
1411
1412 /*
1413 * Attempt to ensure this device is really a DWC_otg Controller.
1414 * Read and verify the GSNPSID register contents. The value should be
1415 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
1416 * as in "OTG version 2.xx" or "OTG version 3.xx".
1417 */
1418 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
1419 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
1420 (hw->snpsid & 0xfffff000) != 0x4f543000) {
1421 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
1422 hw->snpsid);
1423 return -ENODEV;
1424 }
1425
1426 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
1427 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
1428 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
1429
1430 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
1431 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
1432 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
1433 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
1434 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
1435
1436 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
1437 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
1438 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
1439 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
1440 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
1441
1442 /*
1443 * Host specific hardware parameters. Reading these parameters
1444 * requires the controller to be in host mode. The mode will
1445 * be forced, if necessary, to read these values.
1446 */
1447 dwc2_get_host_hwparams(hsotg);
1448 dwc2_get_dev_hwparams(hsotg);
1449
1450 /* hwcfg1 */
1451 hw->dev_ep_dirs = hwcfg1;
1452
1453 /* hwcfg2 */
1454 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
1455 GHWCFG2_OP_MODE_SHIFT;
1456 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
1457 GHWCFG2_ARCHITECTURE_SHIFT;
1458 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
1459 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
1460 GHWCFG2_NUM_HOST_CHAN_SHIFT);
1461 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
1462 GHWCFG2_HS_PHY_TYPE_SHIFT;
1463 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
1464 GHWCFG2_FS_PHY_TYPE_SHIFT;
1465 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
1466 GHWCFG2_NUM_DEV_EP_SHIFT;
1467 hw->nperio_tx_q_depth =
1468 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
1469 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
1470 hw->host_perio_tx_q_depth =
1471 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
1472 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
1473 hw->dev_token_q_depth =
1474 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
1475 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
1476
1477 /* hwcfg3 */
1478 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
1479 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
1480 hw->max_transfer_size = (1 << (width + 11)) - 1;
1481 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
1482 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
1483 hw->max_packet_count = (1 << (width + 4)) - 1;
1484 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
1485 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
1486 GHWCFG3_DFIFO_DEPTH_SHIFT;
1487
1488 /* hwcfg4 */
1489 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
1490 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
1491 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
1492 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
1493 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
1494 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
1495 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
1496
1497 /* fifo sizes */
1498 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
1499 GRXFSIZ_DEPTH_SHIFT;
1500
1501 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
1502 dev_dbg(hsotg->dev, " op_mode=%d\n",
1503 hw->op_mode);
1504 dev_dbg(hsotg->dev, " arch=%d\n",
1505 hw->arch);
1506 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
1507 hw->dma_desc_enable);
1508 dev_dbg(hsotg->dev, " power_optimized=%d\n",
1509 hw->power_optimized);
1510 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
1511 hw->i2c_enable);
1512 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
1513 hw->hs_phy_type);
1514 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
1515 hw->fs_phy_type);
1516 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
1517 hw->utmi_phy_data_width);
1518 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
1519 hw->num_dev_ep);
1520 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
1521 hw->num_dev_perio_in_ep);
1522 dev_dbg(hsotg->dev, " host_channels=%d\n",
1523 hw->host_channels);
1524 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
1525 hw->max_transfer_size);
1526 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
1527 hw->max_packet_count);
1528 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
1529 hw->nperio_tx_q_depth);
1530 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
1531 hw->host_perio_tx_q_depth);
1532 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
1533 hw->dev_token_q_depth);
1534 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
1535 hw->enable_dynamic_fifo);
1536 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
1537 hw->en_multiple_tx_fifo);
1538 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
1539 hw->total_fifo_size);
1540 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n",
1541 hw->host_rx_fifo_size);
1542 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
1543 hw->host_nperio_tx_fifo_size);
1544 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
1545 hw->host_perio_tx_fifo_size);
1546 dev_dbg(hsotg->dev, "\n");
1547
1548 return 0;
1549}
1550
1551/*
1552 * Sets all parameters to the given value.
1553 *
1554 * Assumes that the dwc2_core_params struct contains only integers.
1555 */
1556void dwc2_set_all_params(struct dwc2_core_params *params, int value)
1557{
1558 int *p = (int *)params;
1559 size_t size = sizeof(*params) / sizeof(*p);
1560 int i;
1561
1562 for (i = 0; i < size; i++)
1563 p[i] = value;
1564}
1565
1566
1567u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
1568{
1569 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;
1570}
1571
1572bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
1573{
1574 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
1575 return false;
1576 else
1577 return true;
1578}
1579
1580/**
1581 * dwc2_enable_global_interrupts() - Enables the controller's Global
1582 * Interrupt in the AHB Config register
1583 *
1584 * @hsotg: Programming view of DWC_otg controller
1585 */
1586void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
1587{
1588 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
1589
1590 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
1591 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
1592}
1593
1594/**
1595 * dwc2_disable_global_interrupts() - Disables the controller's Global
1596 * Interrupt in the AHB Config register
1597 *
1598 * @hsotg: Programming view of DWC_otg controller
1599 */
1600void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
1601{
1602 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
1603
1604 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
1605 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
1606}
1607
1608/* Returns the controller's GHWCFG2.OTG_MODE. */
1609unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg)
1610{
1611 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
1612
1613 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
1614 GHWCFG2_OP_MODE_SHIFT;
1615}
1616
1617/* Returns true if the controller is capable of DRD. */
1618bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
1619{
1620 unsigned op_mode = dwc2_op_mode(hsotg);
1621
1622 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
1623 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
1624 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
1625}
1626
1627/* Returns true if the controller is host-only. */
1628bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
1629{
1630 unsigned op_mode = dwc2_op_mode(hsotg);
1631
1632 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
1633 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
1634}
1635
1636/* Returns true if the controller is device-only. */
1637bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
1638{
1639 unsigned op_mode = dwc2_op_mode(hsotg);
1640
1641 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
1642 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
1643}
1644
1645MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1646MODULE_AUTHOR("Synopsys, Inc.");
1647MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * core.c - DesignWare HS OTG Controller common routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * The Core code provides basic services for accessing and managing the
40 * DWC_otg hardware. These services are used by both the Host Controller
41 * Driver and the Peripheral Controller Driver.
42 */
43#include <linux/kernel.h>
44#include <linux/module.h>
45#include <linux/moduleparam.h>
46#include <linux/spinlock.h>
47#include <linux/interrupt.h>
48#include <linux/dma-mapping.h>
49#include <linux/delay.h>
50#include <linux/io.h>
51#include <linux/slab.h>
52#include <linux/usb.h>
53
54#include <linux/usb/hcd.h>
55#include <linux/usb/ch11.h>
56
57#include "core.h"
58#include "hcd.h"
59
60/**
61 * dwc2_backup_global_registers() - Backup global controller registers.
62 * When suspending usb bus, registers needs to be backuped
63 * if controller power is disabled once suspended.
64 *
65 * @hsotg: Programming view of the DWC_otg controller
66 */
67int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
68{
69 struct dwc2_gregs_backup *gr;
70
71 dev_dbg(hsotg->dev, "%s\n", __func__);
72
73 /* Backup global regs */
74 gr = &hsotg->gr_backup;
75
76 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
77 gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
78 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
79 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
80 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
81 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
82 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
83 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
84 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
85 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
86 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
87
88 gr->valid = true;
89 return 0;
90}
91
92/**
93 * dwc2_restore_global_registers() - Restore controller global registers.
94 * When resuming usb bus, device registers needs to be restored
95 * if controller power were disabled.
96 *
97 * @hsotg: Programming view of the DWC_otg controller
98 */
99int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
100{
101 struct dwc2_gregs_backup *gr;
102
103 dev_dbg(hsotg->dev, "%s\n", __func__);
104
105 /* Restore global regs */
106 gr = &hsotg->gr_backup;
107 if (!gr->valid) {
108 dev_err(hsotg->dev, "%s: no global registers to restore\n",
109 __func__);
110 return -EINVAL;
111 }
112 gr->valid = false;
113
114 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
115 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
116 dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
117 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
118 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
119 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
120 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
121 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
122 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
123 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
124 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
125 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
126
127 return 0;
128}
129
130/**
131 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
132 *
133 * @hsotg: Programming view of the DWC_otg controller
134 * @rem_wakeup: indicates whether resume is initiated by Reset.
135 * @restore: Controller registers need to be restored
136 */
137int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
138 bool restore)
139{
140 struct dwc2_gregs_backup *gr;
141
142 gr = &hsotg->gr_backup;
143
144 /*
145 * Restore host or device regisers with the same mode core enterted
146 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup
147 * value of the "gotgctl" register.
148 */
149 if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
150 return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup,
151 restore);
152 else
153 return dwc2_gadget_exit_partial_power_down(hsotg, restore);
154}
155
156/**
157 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
158 *
159 * @hsotg: Programming view of the DWC_otg controller
160 */
161int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
162{
163 if (dwc2_is_host_mode(hsotg))
164 return dwc2_host_enter_partial_power_down(hsotg);
165 else
166 return dwc2_gadget_enter_partial_power_down(hsotg);
167}
168
169/**
170 * dwc2_restore_essential_regs() - Restore essiential regs of core.
171 *
172 * @hsotg: Programming view of the DWC_otg controller
173 * @rmode: Restore mode, enabled in case of remote-wakeup.
174 * @is_host: Host or device mode.
175 */
176static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
177 int is_host)
178{
179 u32 pcgcctl;
180 struct dwc2_gregs_backup *gr;
181 struct dwc2_dregs_backup *dr;
182 struct dwc2_hregs_backup *hr;
183
184 gr = &hsotg->gr_backup;
185 dr = &hsotg->dr_backup;
186 hr = &hsotg->hr_backup;
187
188 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
189
190 /* Load restore values for [31:14] bits */
191 pcgcctl = (gr->pcgcctl & 0xffffc000);
192 /* If High Speed */
193 if (is_host) {
194 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
195 pcgcctl |= BIT(17);
196 } else {
197 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
198 pcgcctl |= BIT(17);
199 }
200 dwc2_writel(hsotg, pcgcctl, PCGCTL);
201
202 /* Umnask global Interrupt in GAHBCFG and restore it */
203 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
204
205 /* Clear all pending interupts */
206 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
207
208 /* Unmask restore done interrupt */
209 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
210
211 /* Restore GUSBCFG and HCFG/DCFG */
212 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
213
214 if (is_host) {
215 dwc2_writel(hsotg, hr->hcfg, HCFG);
216 if (rmode)
217 pcgcctl |= PCGCTL_RESTOREMODE;
218 dwc2_writel(hsotg, pcgcctl, PCGCTL);
219 udelay(10);
220
221 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
222 dwc2_writel(hsotg, pcgcctl, PCGCTL);
223 udelay(10);
224 } else {
225 dwc2_writel(hsotg, dr->dcfg, DCFG);
226 if (!rmode)
227 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
228 dwc2_writel(hsotg, pcgcctl, PCGCTL);
229 udelay(10);
230
231 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
232 dwc2_writel(hsotg, pcgcctl, PCGCTL);
233 udelay(10);
234 }
235}
236
237/**
238 * dwc2_hib_restore_common() - Common part of restore routine.
239 *
240 * @hsotg: Programming view of the DWC_otg controller
241 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
242 * @is_host: Host or device mode.
243 */
244void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
245 int is_host)
246{
247 u32 gpwrdn;
248
249 /* Switch-on voltage to the core */
250 gpwrdn = dwc2_readl(hsotg, GPWRDN);
251 gpwrdn &= ~GPWRDN_PWRDNSWTCH;
252 dwc2_writel(hsotg, gpwrdn, GPWRDN);
253 udelay(10);
254
255 /* Reset core */
256 gpwrdn = dwc2_readl(hsotg, GPWRDN);
257 gpwrdn &= ~GPWRDN_PWRDNRSTN;
258 dwc2_writel(hsotg, gpwrdn, GPWRDN);
259 udelay(10);
260
261 /* Enable restore from PMU */
262 gpwrdn = dwc2_readl(hsotg, GPWRDN);
263 gpwrdn |= GPWRDN_RESTORE;
264 dwc2_writel(hsotg, gpwrdn, GPWRDN);
265 udelay(10);
266
267 /* Disable Power Down Clamp */
268 gpwrdn = dwc2_readl(hsotg, GPWRDN);
269 gpwrdn &= ~GPWRDN_PWRDNCLMP;
270 dwc2_writel(hsotg, gpwrdn, GPWRDN);
271 udelay(50);
272
273 if (!is_host && rem_wakeup)
274 udelay(70);
275
276 /* Deassert reset core */
277 gpwrdn = dwc2_readl(hsotg, GPWRDN);
278 gpwrdn |= GPWRDN_PWRDNRSTN;
279 dwc2_writel(hsotg, gpwrdn, GPWRDN);
280 udelay(10);
281
282 /* Disable PMU interrupt */
283 gpwrdn = dwc2_readl(hsotg, GPWRDN);
284 gpwrdn &= ~GPWRDN_PMUINTSEL;
285 dwc2_writel(hsotg, gpwrdn, GPWRDN);
286 udelay(10);
287
288 /* Set Restore Essential Regs bit in PCGCCTL register */
289 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
290
291 /*
292 * Wait For Restore_done Interrupt. This mechanism of polling the
293 * interrupt is introduced to avoid any possible race conditions
294 */
295 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
296 20000)) {
297 dev_dbg(hsotg->dev,
298 "%s: Restore Done wan't generated here\n",
299 __func__);
300 } else {
301 dev_dbg(hsotg->dev, "restore done generated here\n");
302
303 /*
304 * To avoid restore done interrupt storm after restore is
305 * generated clear GINTSTS_RESTOREDONE bit.
306 */
307 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS);
308 }
309}
310
311/**
312 * dwc2_wait_for_mode() - Waits for the controller mode.
313 * @hsotg: Programming view of the DWC_otg controller.
314 * @host_mode: If true, waits for host mode, otherwise device mode.
315 */
316static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
317 bool host_mode)
318{
319 ktime_t start;
320 ktime_t end;
321 unsigned int timeout = 110;
322
323 dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
324 host_mode ? "host" : "device");
325
326 start = ktime_get();
327
328 while (1) {
329 s64 ms;
330
331 if (dwc2_is_host_mode(hsotg) == host_mode) {
332 dev_vdbg(hsotg->dev, "%s mode set\n",
333 host_mode ? "Host" : "Device");
334 break;
335 }
336
337 end = ktime_get();
338 ms = ktime_to_ms(ktime_sub(end, start));
339
340 if (ms >= (s64)timeout) {
341 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
342 __func__, host_mode ? "host" : "device");
343 break;
344 }
345
346 usleep_range(1000, 2000);
347 }
348}
349
350/**
351 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
352 * filter is enabled.
353 *
354 * @hsotg: Programming view of DWC_otg controller
355 */
356static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
357{
358 u32 gsnpsid;
359 u32 ghwcfg4;
360
361 if (!dwc2_hw_is_otg(hsotg))
362 return false;
363
364 /* Check if core configuration includes the IDDIG filter. */
365 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
366 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
367 return false;
368
369 /*
370 * Check if the IDDIG debounce filter is bypassed. Available
371 * in core version >= 3.10a.
372 */
373 gsnpsid = dwc2_readl(hsotg, GSNPSID);
374 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
375 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
376
377 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
378 return false;
379 }
380
381 return true;
382}
383
384/*
385 * dwc2_enter_hibernation() - Common function to enter hibernation.
386 *
387 * @hsotg: Programming view of the DWC_otg controller
388 * @is_host: True if core is in host mode.
389 *
390 * Return: 0 if successful, negative error code otherwise
391 */
392int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
393{
394 if (is_host)
395 return dwc2_host_enter_hibernation(hsotg);
396 else
397 return dwc2_gadget_enter_hibernation(hsotg);
398}
399
400/*
401 * dwc2_exit_hibernation() - Common function to exit from hibernation.
402 *
403 * @hsotg: Programming view of the DWC_otg controller
404 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
405 * @reset: Enabled in case of restore with reset.
406 * @is_host: True if core is in host mode.
407 *
408 * Return: 0 if successful, negative error code otherwise
409 */
410int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
411 int reset, int is_host)
412{
413 if (is_host)
414 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
415 else
416 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
417}
418
419/*
420 * Do core a soft reset of the core. Be careful with this because it
421 * resets all the internal state machines of the core.
422 */
423int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
424{
425 u32 greset;
426 bool wait_for_host_mode = false;
427
428 dev_vdbg(hsotg->dev, "%s()\n", __func__);
429
430 /*
431 * If the current mode is host, either due to the force mode
432 * bit being set (which persists after core reset) or the
433 * connector id pin, a core soft reset will temporarily reset
434 * the mode to device. A delay from the IDDIG debounce filter
435 * will occur before going back to host mode.
436 *
437 * Determine whether we will go back into host mode after a
438 * reset and account for this delay after the reset.
439 */
440 if (dwc2_iddig_filter_enabled(hsotg)) {
441 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
442 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
443
444 if (!(gotgctl & GOTGCTL_CONID_B) ||
445 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
446 wait_for_host_mode = true;
447 }
448 }
449
450 /* Core Soft Reset */
451 greset = dwc2_readl(hsotg, GRSTCTL);
452 greset |= GRSTCTL_CSFTRST;
453 dwc2_writel(hsotg, greset, GRSTCTL);
454
455 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
456 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
457 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
458 GRSTCTL_CSFTRST, 10000)) {
459 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
460 __func__);
461 return -EBUSY;
462 }
463 } else {
464 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
465 GRSTCTL_CSFTRST_DONE, 10000)) {
466 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
467 __func__);
468 return -EBUSY;
469 }
470 greset = dwc2_readl(hsotg, GRSTCTL);
471 greset &= ~GRSTCTL_CSFTRST;
472 greset |= GRSTCTL_CSFTRST_DONE;
473 dwc2_writel(hsotg, greset, GRSTCTL);
474 }
475
476 /*
477 * Switching from device mode to host mode by disconnecting
478 * device cable core enters and exits form hibernation.
479 * However, the fifo map remains not cleared. It results
480 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/
481 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2])
482 * if in host mode we disconnect the micro a to b host
483 * cable. Because core reset occurs.
484 * To avoid the WARNING, fifo_map should be cleared
485 * in dwc2_core_reset() function by taking into account configs.
486 * fifo_map must be cleared only if driver is configured in
487 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE"
488 * mode.
489 */
490 dwc2_clear_fifo_map(hsotg);
491
492 /* Wait for AHB master IDLE state */
493 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
494 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
495 __func__);
496 return -EBUSY;
497 }
498
499 if (wait_for_host_mode && !skip_wait)
500 dwc2_wait_for_mode(hsotg, true);
501
502 return 0;
503}
504
505/**
506 * dwc2_force_mode() - Force the mode of the controller.
507 *
508 * Forcing the mode is needed for two cases:
509 *
510 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
511 * controller to stay in a particular mode regardless of ID pin
512 * changes. We do this once during probe.
513 *
514 * 2) During probe we want to read reset values of the hw
515 * configuration registers that are only available in either host or
516 * device mode. We may need to force the mode if the current mode does
517 * not allow us to access the register in the mode that we want.
518 *
519 * In either case it only makes sense to force the mode if the
520 * controller hardware is OTG capable.
521 *
522 * Checks are done in this function to determine whether doing a force
523 * would be valid or not.
524 *
525 * If a force is done, it requires a IDDIG debounce filter delay if
526 * the filter is configured and enabled. We poll the current mode of
527 * the controller to account for this delay.
528 *
529 * @hsotg: Programming view of DWC_otg controller
530 * @host: Host mode flag
531 */
532void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
533{
534 u32 gusbcfg;
535 u32 set;
536 u32 clear;
537
538 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
539
540 /*
541 * Force mode has no effect if the hardware is not OTG.
542 */
543 if (!dwc2_hw_is_otg(hsotg))
544 return;
545
546 /*
547 * If dr_mode is either peripheral or host only, there is no
548 * need to ever force the mode to the opposite mode.
549 */
550 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
551 return;
552
553 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
554 return;
555
556 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
557
558 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
559 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
560
561 gusbcfg &= ~clear;
562 gusbcfg |= set;
563 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
564
565 dwc2_wait_for_mode(hsotg, host);
566 return;
567}
568
569/**
570 * dwc2_clear_force_mode() - Clears the force mode bits.
571 *
572 * After clearing the bits, wait up to 100 ms to account for any
573 * potential IDDIG filter delay. We can't know if we expect this delay
574 * or not because the value of the connector ID status is affected by
575 * the force mode. We only need to call this once during probe if
576 * dr_mode == OTG.
577 *
578 * @hsotg: Programming view of DWC_otg controller
579 */
580static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
581{
582 u32 gusbcfg;
583
584 if (!dwc2_hw_is_otg(hsotg))
585 return;
586
587 dev_dbg(hsotg->dev, "Clearing force mode bits\n");
588
589 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
590 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
591 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
592 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
593
594 if (dwc2_iddig_filter_enabled(hsotg))
595 msleep(100);
596}
597
598/*
599 * Sets or clears force mode based on the dr_mode parameter.
600 */
601void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
602{
603 switch (hsotg->dr_mode) {
604 case USB_DR_MODE_HOST:
605 /*
606 * NOTE: This is required for some rockchip soc based
607 * platforms on their host-only dwc2.
608 */
609 if (!dwc2_hw_is_otg(hsotg))
610 msleep(50);
611
612 break;
613 case USB_DR_MODE_PERIPHERAL:
614 dwc2_force_mode(hsotg, false);
615 break;
616 case USB_DR_MODE_OTG:
617 dwc2_clear_force_mode(hsotg);
618 break;
619 default:
620 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
621 __func__, hsotg->dr_mode);
622 break;
623 }
624}
625
626/*
627 * dwc2_enable_acg - enable active clock gating feature
628 */
629void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
630{
631 if (hsotg->params.acg_enable) {
632 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
633
634 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
635 pcgcctl1 |= PCGCCTL1_GATEEN;
636 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
637 }
638}
639
640/**
641 * dwc2_dump_host_registers() - Prints the host registers
642 *
643 * @hsotg: Programming view of DWC_otg controller
644 *
645 * NOTE: This function will be removed once the peripheral controller code
646 * is integrated and the driver is stable
647 */
648void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
649{
650#ifdef DEBUG
651 u32 __iomem *addr;
652 int i;
653
654 dev_dbg(hsotg->dev, "Host Global Registers\n");
655 addr = hsotg->regs + HCFG;
656 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
657 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
658 addr = hsotg->regs + HFIR;
659 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
660 (unsigned long)addr, dwc2_readl(hsotg, HFIR));
661 addr = hsotg->regs + HFNUM;
662 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
663 (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
664 addr = hsotg->regs + HPTXSTS;
665 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
666 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
667 addr = hsotg->regs + HAINT;
668 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
669 (unsigned long)addr, dwc2_readl(hsotg, HAINT));
670 addr = hsotg->regs + HAINTMSK;
671 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
672 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
673 if (hsotg->params.dma_desc_enable) {
674 addr = hsotg->regs + HFLBADDR;
675 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
676 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
677 }
678
679 addr = hsotg->regs + HPRT0;
680 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
681 (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
682
683 for (i = 0; i < hsotg->params.host_channels; i++) {
684 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
685 addr = hsotg->regs + HCCHAR(i);
686 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
687 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
688 addr = hsotg->regs + HCSPLT(i);
689 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
690 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
691 addr = hsotg->regs + HCINT(i);
692 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
693 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
694 addr = hsotg->regs + HCINTMSK(i);
695 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
696 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
697 addr = hsotg->regs + HCTSIZ(i);
698 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
699 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
700 addr = hsotg->regs + HCDMA(i);
701 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
702 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
703 if (hsotg->params.dma_desc_enable) {
704 addr = hsotg->regs + HCDMAB(i);
705 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
706 (unsigned long)addr, dwc2_readl(hsotg,
707 HCDMAB(i)));
708 }
709 }
710#endif
711}
712
713/**
714 * dwc2_dump_global_registers() - Prints the core global registers
715 *
716 * @hsotg: Programming view of DWC_otg controller
717 *
718 * NOTE: This function will be removed once the peripheral controller code
719 * is integrated and the driver is stable
720 */
721void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
722{
723#ifdef DEBUG
724 u32 __iomem *addr;
725
726 dev_dbg(hsotg->dev, "Core Global Registers\n");
727 addr = hsotg->regs + GOTGCTL;
728 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
729 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
730 addr = hsotg->regs + GOTGINT;
731 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
732 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
733 addr = hsotg->regs + GAHBCFG;
734 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
735 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
736 addr = hsotg->regs + GUSBCFG;
737 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
738 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
739 addr = hsotg->regs + GRSTCTL;
740 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
741 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
742 addr = hsotg->regs + GINTSTS;
743 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
744 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
745 addr = hsotg->regs + GINTMSK;
746 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
747 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
748 addr = hsotg->regs + GRXSTSR;
749 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
750 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
751 addr = hsotg->regs + GRXFSIZ;
752 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
753 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
754 addr = hsotg->regs + GNPTXFSIZ;
755 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
756 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
757 addr = hsotg->regs + GNPTXSTS;
758 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
759 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
760 addr = hsotg->regs + GI2CCTL;
761 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
762 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
763 addr = hsotg->regs + GPVNDCTL;
764 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
765 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
766 addr = hsotg->regs + GGPIO;
767 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
768 (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
769 addr = hsotg->regs + GUID;
770 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
771 (unsigned long)addr, dwc2_readl(hsotg, GUID));
772 addr = hsotg->regs + GSNPSID;
773 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
774 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
775 addr = hsotg->regs + GHWCFG1;
776 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
777 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
778 addr = hsotg->regs + GHWCFG2;
779 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
780 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
781 addr = hsotg->regs + GHWCFG3;
782 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
783 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
784 addr = hsotg->regs + GHWCFG4;
785 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
786 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
787 addr = hsotg->regs + GLPMCFG;
788 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
789 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
790 addr = hsotg->regs + GPWRDN;
791 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
792 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
793 addr = hsotg->regs + GDFIFOCFG;
794 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
795 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
796 addr = hsotg->regs + HPTXFSIZ;
797 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
798 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
799
800 addr = hsotg->regs + PCGCTL;
801 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
802 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
803#endif
804}
805
806/**
807 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
808 *
809 * @hsotg: Programming view of DWC_otg controller
810 * @num: Tx FIFO to flush
811 */
812void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
813{
814 u32 greset;
815
816 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
817
818 /* Wait for AHB master IDLE state */
819 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
820 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
821 __func__);
822
823 greset = GRSTCTL_TXFFLSH;
824 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
825 dwc2_writel(hsotg, greset, GRSTCTL);
826
827 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
828 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
829 __func__);
830
831 /* Wait for at least 3 PHY Clocks */
832 udelay(1);
833}
834
835/**
836 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
837 *
838 * @hsotg: Programming view of DWC_otg controller
839 */
840void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
841{
842 u32 greset;
843
844 dev_vdbg(hsotg->dev, "%s()\n", __func__);
845
846 /* Wait for AHB master IDLE state */
847 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
848 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
849 __func__);
850
851 greset = GRSTCTL_RXFFLSH;
852 dwc2_writel(hsotg, greset, GRSTCTL);
853
854 /* Wait for RxFIFO flush done */
855 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
856 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
857 __func__);
858
859 /* Wait for at least 3 PHY Clocks */
860 udelay(1);
861}
862
863bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
864{
865 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
866 return false;
867 else
868 return true;
869}
870
871/**
872 * dwc2_enable_global_interrupts() - Enables the controller's Global
873 * Interrupt in the AHB Config register
874 *
875 * @hsotg: Programming view of DWC_otg controller
876 */
877void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
878{
879 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
880
881 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
882 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
883}
884
885/**
886 * dwc2_disable_global_interrupts() - Disables the controller's Global
887 * Interrupt in the AHB Config register
888 *
889 * @hsotg: Programming view of DWC_otg controller
890 */
891void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
892{
893 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
894
895 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
896 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
897}
898
899/* Returns the controller's GHWCFG2.OTG_MODE. */
900unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
901{
902 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
903
904 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
905 GHWCFG2_OP_MODE_SHIFT;
906}
907
908/* Returns true if the controller is capable of DRD. */
909bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
910{
911 unsigned int op_mode = dwc2_op_mode(hsotg);
912
913 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
914 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
915 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
916}
917
918/* Returns true if the controller is host-only. */
919bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
920{
921 unsigned int op_mode = dwc2_op_mode(hsotg);
922
923 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
924 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
925}
926
927/* Returns true if the controller is device-only. */
928bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
929{
930 unsigned int op_mode = dwc2_op_mode(hsotg);
931
932 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
933 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
934}
935
936/**
937 * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
938 * @hsotg: Programming view of DWC_otg controller.
939 * @offset: Register's offset where bit/bits must be set.
940 * @mask: Mask of the bit/bits which must be set.
941 * @timeout: Timeout to wait.
942 *
943 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
944 */
945int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
946 u32 timeout)
947{
948 u32 i;
949
950 for (i = 0; i < timeout; i++) {
951 if (dwc2_readl(hsotg, offset) & mask)
952 return 0;
953 udelay(1);
954 }
955
956 return -ETIMEDOUT;
957}
958
959/**
960 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
961 * @hsotg: Programming view of DWC_otg controller.
962 * @offset: Register's offset where bit/bits must be set.
963 * @mask: Mask of the bit/bits which must be set.
964 * @timeout: Timeout to wait.
965 *
966 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
967 */
968int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
969 u32 timeout)
970{
971 u32 i;
972
973 for (i = 0; i < timeout; i++) {
974 if (!(dwc2_readl(hsotg, offset) & mask))
975 return 0;
976 udelay(1);
977 }
978
979 return -ETIMEDOUT;
980}
981
982/*
983 * Initializes the FSLSPClkSel field of the HCFG register depending on the
984 * PHY type
985 */
986void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
987{
988 u32 hcfg, val;
989
990 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
991 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
992 hsotg->params.ulpi_fs_ls) ||
993 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
994 /* Full speed PHY */
995 val = HCFG_FSLSPCLKSEL_48_MHZ;
996 } else {
997 /* High speed PHY running at full speed or high speed */
998 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
999 }
1000
1001 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
1002 hcfg = dwc2_readl(hsotg, HCFG);
1003 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
1004 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
1005 dwc2_writel(hsotg, hcfg, HCFG);
1006}
1007
1008static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1009{
1010 u32 usbcfg, ggpio, i2cctl;
1011 int retval = 0;
1012
1013 /*
1014 * core_init() is now called on every switch so only call the
1015 * following for the first time through
1016 */
1017 if (select_phy) {
1018 dev_dbg(hsotg->dev, "FS PHY selected\n");
1019
1020 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1021 if (!(usbcfg & GUSBCFG_PHYSEL)) {
1022 usbcfg |= GUSBCFG_PHYSEL;
1023 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1024
1025 /* Reset after a PHY select */
1026 retval = dwc2_core_reset(hsotg, false);
1027
1028 if (retval) {
1029 dev_err(hsotg->dev,
1030 "%s: Reset failed, aborting", __func__);
1031 return retval;
1032 }
1033 }
1034
1035 if (hsotg->params.activate_stm_fs_transceiver) {
1036 ggpio = dwc2_readl(hsotg, GGPIO);
1037 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1038 dev_dbg(hsotg->dev, "Activating transceiver\n");
1039 /*
1040 * STM32F4x9 uses the GGPIO register as general
1041 * core configuration register.
1042 */
1043 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1044 dwc2_writel(hsotg, ggpio, GGPIO);
1045 }
1046 }
1047 }
1048
1049 /*
1050 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1051 * do this on HNP Dev/Host mode switches (done in dev_init and
1052 * host_init).
1053 */
1054 if (dwc2_is_host_mode(hsotg))
1055 dwc2_init_fs_ls_pclk_sel(hsotg);
1056
1057 if (hsotg->params.i2c_enable) {
1058 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1059
1060 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
1061 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1062 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1063 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1064
1065 /* Program GI2CCTL.I2CEn */
1066 i2cctl = dwc2_readl(hsotg, GI2CCTL);
1067 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1068 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1069 i2cctl &= ~GI2CCTL_I2CEN;
1070 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1071 i2cctl |= GI2CCTL_I2CEN;
1072 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1073 }
1074
1075 return retval;
1076}
1077
1078static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1079{
1080 u32 usbcfg, usbcfg_old;
1081 int retval = 0;
1082
1083 if (!select_phy)
1084 return 0;
1085
1086 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1087 usbcfg_old = usbcfg;
1088
1089 /*
1090 * HS PHY parameters. These parameters are preserved during soft reset
1091 * so only program the first time. Do a soft reset immediately after
1092 * setting phyif.
1093 */
1094 switch (hsotg->params.phy_type) {
1095 case DWC2_PHY_TYPE_PARAM_ULPI:
1096 /* ULPI interface */
1097 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1098 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1099 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1100 if (hsotg->params.phy_ulpi_ddr)
1101 usbcfg |= GUSBCFG_DDRSEL;
1102
1103 /* Set external VBUS indicator as needed. */
1104 if (hsotg->params.oc_disable)
1105 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1106 GUSBCFG_INDICATORPASSTHROUGH);
1107 break;
1108 case DWC2_PHY_TYPE_PARAM_UTMI:
1109 /* UTMI+ interface */
1110 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1111 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1112 if (hsotg->params.phy_utmi_width == 16)
1113 usbcfg |= GUSBCFG_PHYIF16;
1114 break;
1115 default:
1116 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1117 break;
1118 }
1119
1120 if (usbcfg != usbcfg_old) {
1121 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1122
1123 /* Reset after setting the PHY parameters */
1124 retval = dwc2_core_reset(hsotg, false);
1125 if (retval) {
1126 dev_err(hsotg->dev,
1127 "%s: Reset failed, aborting", __func__);
1128 return retval;
1129 }
1130 }
1131
1132 return retval;
1133}
1134
1135static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1136{
1137 u32 usbcfg;
1138
1139 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1140 return;
1141
1142 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1143
1144 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1145 if (hsotg->params.phy_utmi_width == 16)
1146 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1147 else
1148 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1149
1150 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1151}
1152
1153int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1154{
1155 u32 usbcfg;
1156 int retval = 0;
1157
1158 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1159 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1160 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1161 /* If FS/LS mode with FS/LS PHY */
1162 retval = dwc2_fs_phy_init(hsotg, select_phy);
1163 if (retval)
1164 return retval;
1165 } else {
1166 /* High speed PHY */
1167 retval = dwc2_hs_phy_init(hsotg, select_phy);
1168 if (retval)
1169 return retval;
1170
1171 if (dwc2_is_device_mode(hsotg))
1172 dwc2_set_turnaround_time(hsotg);
1173 }
1174
1175 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1176 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1177 hsotg->params.ulpi_fs_ls) {
1178 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1179 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1180 usbcfg |= GUSBCFG_ULPI_FS_LS;
1181 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1182 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1183 } else {
1184 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1185 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1186 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1187 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1188 }
1189
1190 return retval;
1191}
1192
1193MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1194MODULE_AUTHOR("Synopsys, Inc.");
1195MODULE_LICENSE("Dual BSD/GPL");