1/* SPDX-License-Identifier: GPL-2.0 */
 2/* Copyright (C) 2021, Intel Corporation. */
 3
 4#ifndef _ICE_PTP_HW_H_
 5#define _ICE_PTP_HW_H_
 6
 7enum ice_ptp_tmr_cmd {
 8	INIT_TIME,
 9	INIT_INCVAL,
10	ADJ_TIME,
11	ADJ_TIME_AT_TIME,
12	READ_TIME
13};
14
15/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
16 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
17 */
18#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
19
20/* Device agnostic functions */
21u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
22bool ice_ptp_lock(struct ice_hw *hw);
23void ice_ptp_unlock(struct ice_hw *hw);
24int ice_ptp_init_time(struct ice_hw *hw, u64 time);
25int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
26int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
27int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
28int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
29int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
30
31/* E810 family functions */
32int ice_ptp_init_phy_e810(struct ice_hw *hw);
33
34#define PFTSYN_SEM_BYTES	4
35
36/* PHY timer commands */
37#define SEL_CPK_SRC	8
38
39/* Time Sync command Definitions */
40#define GLTSYN_CMD_INIT_TIME		BIT(0)
41#define GLTSYN_CMD_INIT_INCVAL		BIT(1)
42#define GLTSYN_CMD_ADJ_TIME		BIT(2)
43#define GLTSYN_CMD_ADJ_INIT_TIME	(BIT(2) | BIT(3))
44#define GLTSYN_CMD_READ_TIME		BIT(7)
45
46#define TS_CMD_MASK_E810		0xFF
47#define SYNC_EXEC_CMD			0x3
48
49/* E810 timesync enable register */
50#define ETH_GLTSYN_ENA(_i)		(0x03000348 + ((_i) * 4))
51
52/* E810 shadow init time registers */
53#define ETH_GLTSYN_SHTIME_0(i)		(0x03000368 + ((i) * 32))
54#define ETH_GLTSYN_SHTIME_L(i)		(0x0300036C + ((i) * 32))
55
56/* E810 shadow time adjust registers */
57#define ETH_GLTSYN_SHADJ_L(_i)		(0x03000378 + ((_i) * 32))
58#define ETH_GLTSYN_SHADJ_H(_i)		(0x0300037C + ((_i) * 32))
59
60/* E810 timer command register */
61#define ETH_GLTSYN_CMD			0x03000344
62
63/* Source timer incval macros */
64#define INCVAL_HIGH_M			0xFF
65
66/* Timestamp block macros */
67#define TS_LOW_M			0xFFFFFFFF
68#define TS_HIGH_S			32
69
70#define BYTES_PER_IDX_ADDR_L_U		8
71
72/* External PHY timestamp address */
73#define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) +			\
74				 ((idx) * BYTES_PER_IDX_ADDR_L_U))
75
76#define LOW_TX_MEMORY_BANK_START	0x03090000
77#define HIGH_TX_MEMORY_BANK_START	0x03090004
78
79#endif /* _ICE_PTP_HW_H_ */