1/* Intel PRO/1000 Linux driver
   2 * Copyright(c) 1999 - 2015 Intel Corporation.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms and conditions of the GNU General Public License,
   6 * version 2, as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope it will be useful, but WITHOUT
   9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11 * more details.
  12 *
  13 * The full GNU General Public License is included in this distribution in
  14 * the file called "COPYING".
  15 *
  16 * Contact Information:
  17 * Linux NICS <linux.nics@intel.com>
  18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20 */
  21
  22/* 82571EB Gigabit Ethernet Controller
  23 * 82571EB Gigabit Ethernet Controller (Copper)
  24 * 82571EB Gigabit Ethernet Controller (Fiber)
  25 * 82571EB Dual Port Gigabit Mezzanine Adapter
  26 * 82571EB Quad Port Gigabit Mezzanine Adapter
  27 * 82571PT Gigabit PT Quad Port Server ExpressModule
  28 * 82572EI Gigabit Ethernet Controller (Copper)
  29 * 82572EI Gigabit Ethernet Controller (Fiber)
  30 * 82572EI Gigabit Ethernet Controller
  31 * 82573V Gigabit Ethernet Controller (Copper)
  32 * 82573E Gigabit Ethernet Controller (Copper)
  33 * 82573L Gigabit Ethernet Controller
  34 * 82574L Gigabit Network Connection
  35 * 82583V Gigabit Network Connection
  36 */
  37
  38#include "e1000.h"
  39
  40static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  41static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  42static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  43static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  44static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  45				      u16 words, u16 *data);
  46static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  47static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  48static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  49static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  50static s32 e1000_led_on_82574(struct e1000_hw *hw);
  51static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  52static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  53static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  54static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  55static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  56static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
  57static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
  58
  59/**
  60 *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  61 *  @hw: pointer to the HW structure
  62 **/
  63static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  64{
  65	struct e1000_phy_info *phy = &hw->phy;
  66	s32 ret_val;
  67
  68	if (hw->phy.media_type != e1000_media_type_copper) {
  69		phy->type = e1000_phy_none;
  70		return 0;
  71	}
  72
  73	phy->addr = 1;
  74	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  75	phy->reset_delay_us = 100;
  76
  77	phy->ops.power_up = e1000_power_up_phy_copper;
  78	phy->ops.power_down = e1000_power_down_phy_copper_82571;
  79
  80	switch (hw->mac.type) {
  81	case e1000_82571:
  82	case e1000_82572:
  83		phy->type = e1000_phy_igp_2;
  84		break;
  85	case e1000_82573:
  86		phy->type = e1000_phy_m88;
  87		break;
  88	case e1000_82574:
  89	case e1000_82583:
  90		phy->type = e1000_phy_bm;
  91		phy->ops.acquire = e1000_get_hw_semaphore_82574;
  92		phy->ops.release = e1000_put_hw_semaphore_82574;
  93		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
  94		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
  95		break;
  96	default:
  97		return -E1000_ERR_PHY;
  98	}
  99
 100	/* This can only be done after all function pointers are setup. */
 101	ret_val = e1000_get_phy_id_82571(hw);
 102	if (ret_val) {
 103		e_dbg("Error getting PHY ID\n");
 104		return ret_val;
 105	}
 106
 107	/* Verify phy id */
 108	switch (hw->mac.type) {
 109	case e1000_82571:
 110	case e1000_82572:
 111		if (phy->id != IGP01E1000_I_PHY_ID)
 112			ret_val = -E1000_ERR_PHY;
 113		break;
 114	case e1000_82573:
 115		if (phy->id != M88E1111_I_PHY_ID)
 116			ret_val = -E1000_ERR_PHY;
 117		break;
 118	case e1000_82574:
 119	case e1000_82583:
 120		if (phy->id != BME1000_E_PHY_ID_R2)
 121			ret_val = -E1000_ERR_PHY;
 122		break;
 123	default:
 124		ret_val = -E1000_ERR_PHY;
 125		break;
 126	}
 127
 128	if (ret_val)
 129		e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
 130
 131	return ret_val;
 132}
 133
 134/**
 135 *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 136 *  @hw: pointer to the HW structure
 137 **/
 138static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 139{
 140	struct e1000_nvm_info *nvm = &hw->nvm;
 141	u32 eecd = er32(EECD);
 142	u16 size;
 143
 144	nvm->opcode_bits = 8;
 145	nvm->delay_usec = 1;
 146	switch (nvm->override) {
 147	case e1000_nvm_override_spi_large:
 148		nvm->page_size = 32;
 149		nvm->address_bits = 16;
 150		break;
 151	case e1000_nvm_override_spi_small:
 152		nvm->page_size = 8;
 153		nvm->address_bits = 8;
 154		break;
 155	default:
 156		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 157		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 158		break;
 159	}
 160
 161	switch (hw->mac.type) {
 162	case e1000_82573:
 163	case e1000_82574:
 164	case e1000_82583:
 165		if (((eecd >> 15) & 0x3) == 0x3) {
 166			nvm->type = e1000_nvm_flash_hw;
 167			nvm->word_size = 2048;
 168			/* Autonomous Flash update bit must be cleared due
 169			 * to Flash update issue.
 170			 */
 171			eecd &= ~E1000_EECD_AUPDEN;
 172			ew32(EECD, eecd);
 173			break;
 174		}
 175		/* Fall Through */
 176	default:
 177		nvm->type = e1000_nvm_eeprom_spi;
 178		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 179			     E1000_EECD_SIZE_EX_SHIFT);
 180		/* Added to a constant, "size" becomes the left-shift value
 181		 * for setting word_size.
 182		 */
 183		size += NVM_WORD_SIZE_BASE_SHIFT;
 184
 185		/* EEPROM access above 16k is unsupported */
 186		if (size > 14)
 187			size = 14;
 188		nvm->word_size = 1 << size;
 189		break;
 190	}
 191
 192	/* Function Pointers */
 193	switch (hw->mac.type) {
 194	case e1000_82574:
 195	case e1000_82583:
 196		nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 197		nvm->ops.release = e1000_put_hw_semaphore_82574;
 198		break;
 199	default:
 200		break;
 201	}
 202
 203	return 0;
 204}
 205
 206/**
 207 *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 208 *  @hw: pointer to the HW structure
 209 **/
 210static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 211{
 212	struct e1000_mac_info *mac = &hw->mac;
 213	u32 swsm = 0;
 214	u32 swsm2 = 0;
 215	bool force_clear_smbi = false;
 216
 217	/* Set media type and media-dependent function pointers */
 218	switch (hw->adapter->pdev->device) {
 219	case E1000_DEV_ID_82571EB_FIBER:
 220	case E1000_DEV_ID_82572EI_FIBER:
 221	case E1000_DEV_ID_82571EB_QUAD_FIBER:
 222		hw->phy.media_type = e1000_media_type_fiber;
 223		mac->ops.setup_physical_interface =
 224		    e1000_setup_fiber_serdes_link_82571;
 225		mac->ops.check_for_link = e1000e_check_for_fiber_link;
 226		mac->ops.get_link_up_info =
 227		    e1000e_get_speed_and_duplex_fiber_serdes;
 228		break;
 229	case E1000_DEV_ID_82571EB_SERDES:
 230	case E1000_DEV_ID_82571EB_SERDES_DUAL:
 231	case E1000_DEV_ID_82571EB_SERDES_QUAD:
 232	case E1000_DEV_ID_82572EI_SERDES:
 233		hw->phy.media_type = e1000_media_type_internal_serdes;
 234		mac->ops.setup_physical_interface =
 235		    e1000_setup_fiber_serdes_link_82571;
 236		mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 237		mac->ops.get_link_up_info =
 238		    e1000e_get_speed_and_duplex_fiber_serdes;
 239		break;
 240	default:
 241		hw->phy.media_type = e1000_media_type_copper;
 242		mac->ops.setup_physical_interface =
 243		    e1000_setup_copper_link_82571;
 244		mac->ops.check_for_link = e1000e_check_for_copper_link;
 245		mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
 246		break;
 247	}
 248
 249	/* Set mta register count */
 250	mac->mta_reg_count = 128;
 251	/* Set rar entry count */
 252	mac->rar_entry_count = E1000_RAR_ENTRIES;
 253	/* Adaptive IFS supported */
 254	mac->adaptive_ifs = true;
 255
 256	/* MAC-specific function pointers */
 257	switch (hw->mac.type) {
 258	case e1000_82573:
 259		mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 260		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 261		mac->ops.led_on = e1000e_led_on_generic;
 262		mac->ops.blink_led = e1000e_blink_led_generic;
 263
 264		/* FWSM register */
 265		mac->has_fwsm = true;
 266		/* ARC supported; valid only if manageability features are
 267		 * enabled.
 268		 */
 269		mac->arc_subsystem_valid = !!(er32(FWSM) &
 270					      E1000_FWSM_MODE_MASK);
 271		break;
 272	case e1000_82574:
 273	case e1000_82583:
 274		mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 275		mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 276		mac->ops.led_on = e1000_led_on_82574;
 277		break;
 278	default:
 279		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 280		mac->ops.led_on = e1000e_led_on_generic;
 281		mac->ops.blink_led = e1000e_blink_led_generic;
 282
 283		/* FWSM register */
 284		mac->has_fwsm = true;
 285		break;
 286	}
 287
 288	/* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 289	 * first NVM or PHY access. This should be done for single-port
 290	 * devices, and for one port only on dual-port devices so that
 291	 * for those devices we can still use the SMBI lock to synchronize
 292	 * inter-port accesses to the PHY & NVM.
 293	 */
 294	switch (hw->mac.type) {
 295	case e1000_82571:
 296	case e1000_82572:
 297		swsm2 = er32(SWSM2);
 298
 299		if (!(swsm2 & E1000_SWSM2_LOCK)) {
 300			/* Only do this for the first interface on this card */
 301			ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
 302			force_clear_smbi = true;
 303		} else {
 304			force_clear_smbi = false;
 305		}
 306		break;
 307	default:
 308		force_clear_smbi = true;
 309		break;
 310	}
 311
 312	if (force_clear_smbi) {
 313		/* Make sure SWSM.SMBI is clear */
 314		swsm = er32(SWSM);
 315		if (swsm & E1000_SWSM_SMBI) {
 316			/* This bit should not be set on a first interface, and
 317			 * indicates that the bootagent or EFI code has
 318			 * improperly left this bit enabled
 319			 */
 320			e_dbg("Please update your 82571 Bootagent\n");
 321		}
 322		ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
 323	}
 324
 325	/* Initialize device specific counter of SMBI acquisition timeouts. */
 326	hw->dev_spec.e82571.smb_counter = 0;
 327
 328	return 0;
 329}
 330
 331static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 332{
 333	struct e1000_hw *hw = &adapter->hw;
 334	static int global_quad_port_a;	/* global port a indication */
 335	struct pci_dev *pdev = adapter->pdev;
 336	int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 337	s32 rc;
 338
 339	rc = e1000_init_mac_params_82571(hw);
 340	if (rc)
 341		return rc;
 342
 343	rc = e1000_init_nvm_params_82571(hw);
 344	if (rc)
 345		return rc;
 346
 347	rc = e1000_init_phy_params_82571(hw);
 348	if (rc)
 349		return rc;
 350
 351	/* tag quad port adapters first, it's used below */
 352	switch (pdev->device) {
 353	case E1000_DEV_ID_82571EB_QUAD_COPPER:
 354	case E1000_DEV_ID_82571EB_QUAD_FIBER:
 355	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 356	case E1000_DEV_ID_82571PT_QUAD_COPPER:
 357		adapter->flags |= FLAG_IS_QUAD_PORT;
 358		/* mark the first port */
 359		if (global_quad_port_a == 0)
 360			adapter->flags |= FLAG_IS_QUAD_PORT_A;
 361		/* Reset for multiple quad port adapters */
 362		global_quad_port_a++;
 363		if (global_quad_port_a == 4)
 364			global_quad_port_a = 0;
 365		break;
 366	default:
 367		break;
 368	}
 369
 370	switch (adapter->hw.mac.type) {
 371	case e1000_82571:
 372		/* these dual ports don't have WoL on port B at all */
 373		if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 374		     (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 375		     (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 376		    (is_port_b))
 377			adapter->flags &= ~FLAG_HAS_WOL;
 378		/* quad ports only support WoL on port A */
 379		if (adapter->flags & FLAG_IS_QUAD_PORT &&
 380		    (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 381			adapter->flags &= ~FLAG_HAS_WOL;
 382		/* Does not support WoL on any port */
 383		if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 384			adapter->flags &= ~FLAG_HAS_WOL;
 385		break;
 386	case e1000_82573:
 387		if (pdev->device == E1000_DEV_ID_82573L) {
 388			adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
 389			adapter->max_hw_frame_size = DEFAULT_JUMBO;
 390		}
 391		break;
 392	default:
 393		break;
 394	}
 395
 396	return 0;
 397}
 398
 399/**
 400 *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 401 *  @hw: pointer to the HW structure
 402 *
 403 *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 404 *  revision in the hardware structure.
 405 **/
 406static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 407{
 408	struct e1000_phy_info *phy = &hw->phy;
 409	s32 ret_val;
 410	u16 phy_id = 0;
 411
 412	switch (hw->mac.type) {
 413	case e1000_82571:
 414	case e1000_82572:
 415		/* The 82571 firmware may still be configuring the PHY.
 416		 * In this case, we cannot access the PHY until the
 417		 * configuration is done.  So we explicitly set the
 418		 * PHY ID.
 419		 */
 420		phy->id = IGP01E1000_I_PHY_ID;
 421		break;
 422	case e1000_82573:
 423		return e1000e_get_phy_id(hw);
 424	case e1000_82574:
 425	case e1000_82583:
 426		ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
 427		if (ret_val)
 428			return ret_val;
 429
 430		phy->id = (u32)(phy_id << 16);
 431		usleep_range(20, 40);
 432		ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
 433		if (ret_val)
 434			return ret_val;
 435
 436		phy->id |= (u32)(phy_id);
 437		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 438		break;
 439	default:
 440		return -E1000_ERR_PHY;
 441	}
 442
 443	return 0;
 444}
 445
 446/**
 447 *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 448 *  @hw: pointer to the HW structure
 449 *
 450 *  Acquire the HW semaphore to access the PHY or NVM
 451 **/
 452static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 453{
 454	u32 swsm;
 455	s32 sw_timeout = hw->nvm.word_size + 1;
 456	s32 fw_timeout = hw->nvm.word_size + 1;
 457	s32 i = 0;
 458
 459	/* If we have timedout 3 times on trying to acquire
 460	 * the inter-port SMBI semaphore, there is old code
 461	 * operating on the other port, and it is not
 462	 * releasing SMBI. Modify the number of times that
 463	 * we try for the semaphore to interwork with this
 464	 * older code.
 465	 */
 466	if (hw->dev_spec.e82571.smb_counter > 2)
 467		sw_timeout = 1;
 468
 469	/* Get the SW semaphore */
 470	while (i < sw_timeout) {
 471		swsm = er32(SWSM);
 472		if (!(swsm & E1000_SWSM_SMBI))
 473			break;
 474
 475		usleep_range(50, 100);
 476		i++;
 477	}
 478
 479	if (i == sw_timeout) {
 480		e_dbg("Driver can't access device - SMBI bit is set.\n");
 481		hw->dev_spec.e82571.smb_counter++;
 482	}
 483	/* Get the FW semaphore. */
 484	for (i = 0; i < fw_timeout; i++) {
 485		swsm = er32(SWSM);
 486		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 487
 488		/* Semaphore acquired if bit latched */
 489		if (er32(SWSM) & E1000_SWSM_SWESMBI)
 490			break;
 491
 492		usleep_range(50, 100);
 493	}
 494
 495	if (i == fw_timeout) {
 496		/* Release semaphores */
 497		e1000_put_hw_semaphore_82571(hw);
 498		e_dbg("Driver can't access the NVM\n");
 499		return -E1000_ERR_NVM;
 500	}
 501
 502	return 0;
 503}
 504
 505/**
 506 *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 507 *  @hw: pointer to the HW structure
 508 *
 509 *  Release hardware semaphore used to access the PHY or NVM
 510 **/
 511static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 512{
 513	u32 swsm;
 514
 515	swsm = er32(SWSM);
 516	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 517	ew32(SWSM, swsm);
 518}
 519
 520/**
 521 *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 522 *  @hw: pointer to the HW structure
 523 *
 524 *  Acquire the HW semaphore during reset.
 525 *
 526 **/
 527static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 528{
 529	u32 extcnf_ctrl;
 530	s32 i = 0;
 531
 532	extcnf_ctrl = er32(EXTCNF_CTRL);
 533	do {
 534		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 535		ew32(EXTCNF_CTRL, extcnf_ctrl);
 536		extcnf_ctrl = er32(EXTCNF_CTRL);
 537
 538		if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 539			break;
 540
 541		usleep_range(2000, 4000);
 542		i++;
 543	} while (i < MDIO_OWNERSHIP_TIMEOUT);
 544
 545	if (i == MDIO_OWNERSHIP_TIMEOUT) {
 546		/* Release semaphores */
 547		e1000_put_hw_semaphore_82573(hw);
 548		e_dbg("Driver can't access the PHY\n");
 549		return -E1000_ERR_PHY;
 550	}
 551
 552	return 0;
 553}
 554
 555/**
 556 *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 557 *  @hw: pointer to the HW structure
 558 *
 559 *  Release hardware semaphore used during reset.
 560 *
 561 **/
 562static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 563{
 564	u32 extcnf_ctrl;
 565
 566	extcnf_ctrl = er32(EXTCNF_CTRL);
 567	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 568	ew32(EXTCNF_CTRL, extcnf_ctrl);
 569}
 570
 571static DEFINE_MUTEX(swflag_mutex);
 572
 573/**
 574 *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 575 *  @hw: pointer to the HW structure
 576 *
 577 *  Acquire the HW semaphore to access the PHY or NVM.
 578 *
 579 **/
 580static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 581{
 582	s32 ret_val;
 583
 584	mutex_lock(&swflag_mutex);
 585	ret_val = e1000_get_hw_semaphore_82573(hw);
 586	if (ret_val)
 587		mutex_unlock(&swflag_mutex);
 588	return ret_val;
 589}
 590
 591/**
 592 *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 593 *  @hw: pointer to the HW structure
 594 *
 595 *  Release hardware semaphore used to access the PHY or NVM
 596 *
 597 **/
 598static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 599{
 600	e1000_put_hw_semaphore_82573(hw);
 601	mutex_unlock(&swflag_mutex);
 602}
 603
 604/**
 605 *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 606 *  @hw: pointer to the HW structure
 607 *  @active: true to enable LPLU, false to disable
 608 *
 609 *  Sets the LPLU D0 state according to the active flag.
 610 *  LPLU will not be activated unless the
 611 *  device autonegotiation advertisement meets standards of
 612 *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 613 *  This is a function pointer entry point only called by
 614 *  PHY setup routines.
 615 **/
 616static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 617{
 618	u32 data = er32(POEMB);
 619
 620	if (active)
 621		data |= E1000_PHY_CTRL_D0A_LPLU;
 622	else
 623		data &= ~E1000_PHY_CTRL_D0A_LPLU;
 624
 625	ew32(POEMB, data);
 626	return 0;
 627}
 628
 629/**
 630 *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 631 *  @hw: pointer to the HW structure
 632 *  @active: boolean used to enable/disable lplu
 633 *
 634 *  The low power link up (lplu) state is set to the power management level D3
 635 *  when active is true, else clear lplu for D3. LPLU
 636 *  is used during Dx states where the power conservation is most important.
 637 *  During driver activity, SmartSpeed should be enabled so performance is
 638 *  maintained.
 639 **/
 640static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 641{
 642	u32 data = er32(POEMB);
 643
 644	if (!active) {
 645		data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 646	} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 647		   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 648		   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 649		data |= E1000_PHY_CTRL_NOND0A_LPLU;
 650	}
 651
 652	ew32(POEMB, data);
 653	return 0;
 654}
 655
 656/**
 657 *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 658 *  @hw: pointer to the HW structure
 659 *
 660 *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 661 *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 662 *  for EEPROM access grant bit.  If the access grant bit is not set, release
 663 *  hardware semaphore.
 664 **/
 665static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 666{
 667	s32 ret_val;
 668
 669	ret_val = e1000_get_hw_semaphore_82571(hw);
 670	if (ret_val)
 671		return ret_val;
 672
 673	switch (hw->mac.type) {
 674	case e1000_82573:
 675		break;
 676	default:
 677		ret_val = e1000e_acquire_nvm(hw);
 678		break;
 679	}
 680
 681	if (ret_val)
 682		e1000_put_hw_semaphore_82571(hw);
 683
 684	return ret_val;
 685}
 686
 687/**
 688 *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 689 *  @hw: pointer to the HW structure
 690 *
 691 *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 692 **/
 693static void e1000_release_nvm_82571(struct e1000_hw *hw)
 694{
 695	e1000e_release_nvm(hw);
 696	e1000_put_hw_semaphore_82571(hw);
 697}
 698
 699/**
 700 *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 701 *  @hw: pointer to the HW structure
 702 *  @offset: offset within the EEPROM to be written to
 703 *  @words: number of words to write
 704 *  @data: 16 bit word(s) to be written to the EEPROM
 705 *
 706 *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 707 *
 708 *  If e1000e_update_nvm_checksum is not called after this function, the
 709 *  EEPROM will most likely contain an invalid checksum.
 710 **/
 711static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 712				 u16 *data)
 713{
 714	s32 ret_val;
 715
 716	switch (hw->mac.type) {
 717	case e1000_82573:
 718	case e1000_82574:
 719	case e1000_82583:
 720		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 721		break;
 722	case e1000_82571:
 723	case e1000_82572:
 724		ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 725		break;
 726	default:
 727		ret_val = -E1000_ERR_NVM;
 728		break;
 729	}
 730
 731	return ret_val;
 732}
 733
 734/**
 735 *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 736 *  @hw: pointer to the HW structure
 737 *
 738 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 739 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 740 *  value to the EEPROM.
 741 **/
 742static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 743{
 744	u32 eecd;
 745	s32 ret_val;
 746	u16 i;
 747
 748	ret_val = e1000e_update_nvm_checksum_generic(hw);
 749	if (ret_val)
 750		return ret_val;
 751
 752	/* If our nvm is an EEPROM, then we're done
 753	 * otherwise, commit the checksum to the flash NVM.
 754	 */
 755	if (hw->nvm.type != e1000_nvm_flash_hw)
 756		return 0;
 757
 758	/* Check for pending operations. */
 759	for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 760		usleep_range(1000, 2000);
 761		if (!(er32(EECD) & E1000_EECD_FLUPD))
 762			break;
 763	}
 764
 765	if (i == E1000_FLASH_UPDATES)
 766		return -E1000_ERR_NVM;
 767
 768	/* Reset the firmware if using STM opcode. */
 769	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 770		/* The enabling of and the actual reset must be done
 771		 * in two write cycles.
 772		 */
 773		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 774		e1e_flush();
 775		ew32(HICR, E1000_HICR_FW_RESET);
 776	}
 777
 778	/* Commit the write to flash */
 779	eecd = er32(EECD) | E1000_EECD_FLUPD;
 780	ew32(EECD, eecd);
 781
 782	for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 783		usleep_range(1000, 2000);
 784		if (!(er32(EECD) & E1000_EECD_FLUPD))
 785			break;
 786	}
 787
 788	if (i == E1000_FLASH_UPDATES)
 789		return -E1000_ERR_NVM;
 790
 791	return 0;
 792}
 793
 794/**
 795 *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 796 *  @hw: pointer to the HW structure
 797 *
 798 *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 799 *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 800 **/
 801static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 802{
 803	if (hw->nvm.type == e1000_nvm_flash_hw)
 804		e1000_fix_nvm_checksum_82571(hw);
 805
 806	return e1000e_validate_nvm_checksum_generic(hw);
 807}
 808
 809/**
 810 *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 811 *  @hw: pointer to the HW structure
 812 *  @offset: offset within the EEPROM to be written to
 813 *  @words: number of words to write
 814 *  @data: 16 bit word(s) to be written to the EEPROM
 815 *
 816 *  After checking for invalid values, poll the EEPROM to ensure the previous
 817 *  command has completed before trying to write the next word.  After write
 818 *  poll for completion.
 819 *
 820 *  If e1000e_update_nvm_checksum is not called after this function, the
 821 *  EEPROM will most likely contain an invalid checksum.
 822 **/
 823static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 824				      u16 words, u16 *data)
 825{
 826	struct e1000_nvm_info *nvm = &hw->nvm;
 827	u32 i, eewr = 0;
 828	s32 ret_val = 0;
 829
 830	/* A check for invalid values:  offset too large, too many words,
 831	 * and not enough words.
 832	 */
 833	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 834	    (words == 0)) {
 835		e_dbg("nvm parameter(s) out of bounds\n");
 836		return -E1000_ERR_NVM;
 837	}
 838
 839	for (i = 0; i < words; i++) {
 840		eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
 841			((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
 842			E1000_NVM_RW_REG_START);
 843
 844		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 845		if (ret_val)
 846			break;
 847
 848		ew32(EEWR, eewr);
 849
 850		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 851		if (ret_val)
 852			break;
 853	}
 854
 855	return ret_val;
 856}
 857
 858/**
 859 *  e1000_get_cfg_done_82571 - Poll for configuration done
 860 *  @hw: pointer to the HW structure
 861 *
 862 *  Reads the management control register for the config done bit to be set.
 863 **/
 864static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 865{
 866	s32 timeout = PHY_CFG_TIMEOUT;
 867
 868	while (timeout) {
 869		if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
 870			break;
 871		usleep_range(1000, 2000);
 872		timeout--;
 873	}
 874	if (!timeout) {
 875		e_dbg("MNG configuration cycle has not completed.\n");
 876		return -E1000_ERR_RESET;
 877	}
 878
 879	return 0;
 880}
 881
 882/**
 883 *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 884 *  @hw: pointer to the HW structure
 885 *  @active: true to enable LPLU, false to disable
 886 *
 887 *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 888 *  this function also disables smart speed and vice versa.  LPLU will not be
 889 *  activated unless the device autonegotiation advertisement meets standards
 890 *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 891 *  pointer entry point only called by PHY setup routines.
 892 **/
 893static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 894{
 895	struct e1000_phy_info *phy = &hw->phy;
 896	s32 ret_val;
 897	u16 data;
 898
 899	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 900	if (ret_val)
 901		return ret_val;
 902
 903	if (active) {
 904		data |= IGP02E1000_PM_D0_LPLU;
 905		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 906		if (ret_val)
 907			return ret_val;
 908
 909		/* When LPLU is enabled, we should disable SmartSpeed */
 910		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 911		if (ret_val)
 912			return ret_val;
 913		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 914		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 915		if (ret_val)
 916			return ret_val;
 917	} else {
 918		data &= ~IGP02E1000_PM_D0_LPLU;
 919		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 
 
 920		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 921		 * during Dx states where the power conservation is most
 922		 * important.  During driver activity we should enable
 923		 * SmartSpeed, so performance is maintained.
 924		 */
 925		if (phy->smart_speed == e1000_smart_speed_on) {
 926			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 927					   &data);
 928			if (ret_val)
 929				return ret_val;
 930
 931			data |= IGP01E1000_PSCFR_SMART_SPEED;
 932			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 933					   data);
 934			if (ret_val)
 935				return ret_val;
 936		} else if (phy->smart_speed == e1000_smart_speed_off) {
 937			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 938					   &data);
 939			if (ret_val)
 940				return ret_val;
 941
 942			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 943			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 944					   data);
 945			if (ret_val)
 946				return ret_val;
 947		}
 948	}
 949
 950	return 0;
 951}
 952
 953/**
 954 *  e1000_reset_hw_82571 - Reset hardware
 955 *  @hw: pointer to the HW structure
 956 *
 957 *  This resets the hardware into a known state.
 958 **/
 959static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 960{
 961	u32 ctrl, ctrl_ext, eecd, tctl;
 962	s32 ret_val;
 963
 964	/* Prevent the PCI-E bus from sticking if there is no TLP connection
 965	 * on the last TLP read/write transaction when MAC is reset.
 966	 */
 967	ret_val = e1000e_disable_pcie_master(hw);
 968	if (ret_val)
 969		e_dbg("PCI-E Master disable polling has failed.\n");
 970
 971	e_dbg("Masking off all interrupts\n");
 972	ew32(IMC, 0xffffffff);
 973
 974	ew32(RCTL, 0);
 975	tctl = er32(TCTL);
 976	tctl &= ~E1000_TCTL_EN;
 977	ew32(TCTL, tctl);
 978	e1e_flush();
 979
 980	usleep_range(10000, 20000);
 981
 982	/* Must acquire the MDIO ownership before MAC reset.
 983	 * Ownership defaults to firmware after a reset.
 984	 */
 985	switch (hw->mac.type) {
 986	case e1000_82573:
 987		ret_val = e1000_get_hw_semaphore_82573(hw);
 988		break;
 989	case e1000_82574:
 990	case e1000_82583:
 991		ret_val = e1000_get_hw_semaphore_82574(hw);
 992		break;
 993	default:
 994		break;
 995	}
 996
 997	ctrl = er32(CTRL);
 998
 999	e_dbg("Issuing a global reset to MAC\n");
1000	ew32(CTRL, ctrl | E1000_CTRL_RST);
1001
1002	/* Must release MDIO ownership and mutex after MAC reset. */
1003	switch (hw->mac.type) {
1004	case e1000_82573:
1005		/* Release mutex only if the hw semaphore is acquired */
1006		if (!ret_val)
1007			e1000_put_hw_semaphore_82573(hw);
1008		break;
1009	case e1000_82574:
1010	case e1000_82583:
1011		/* Release mutex only if the hw semaphore is acquired */
1012		if (!ret_val)
1013			e1000_put_hw_semaphore_82574(hw);
1014		break;
1015	default:
1016		break;
1017	}
1018
1019	if (hw->nvm.type == e1000_nvm_flash_hw) {
1020		usleep_range(10, 20);
1021		ctrl_ext = er32(CTRL_EXT);
1022		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1023		ew32(CTRL_EXT, ctrl_ext);
1024		e1e_flush();
1025	}
1026
1027	ret_val = e1000e_get_auto_rd_done(hw);
1028	if (ret_val)
1029		/* We don't want to continue accessing MAC registers. */
1030		return ret_val;
1031
1032	/* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1033	 * Need to wait for Phy configuration completion before accessing
1034	 * NVM and Phy.
1035	 */
1036
1037	switch (hw->mac.type) {
1038	case e1000_82571:
1039	case e1000_82572:
1040		/* REQ and GNT bits need to be cleared when using AUTO_RD
1041		 * to access the EEPROM.
1042		 */
1043		eecd = er32(EECD);
1044		eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1045		ew32(EECD, eecd);
1046		break;
1047	case e1000_82573:
1048	case e1000_82574:
1049	case e1000_82583:
1050		msleep(25);
1051		break;
1052	default:
1053		break;
1054	}
1055
1056	/* Clear any pending interrupt events. */
1057	ew32(IMC, 0xffffffff);
1058	er32(ICR);
1059
1060	if (hw->mac.type == e1000_82571) {
1061		/* Install any alternate MAC address into RAR0 */
1062		ret_val = e1000_check_alt_mac_addr_generic(hw);
1063		if (ret_val)
1064			return ret_val;
1065
1066		e1000e_set_laa_state_82571(hw, true);
1067	}
1068
1069	/* Reinitialize the 82571 serdes link state machine */
1070	if (hw->phy.media_type == e1000_media_type_internal_serdes)
1071		hw->mac.serdes_link_state = e1000_serdes_link_down;
1072
1073	return 0;
1074}
1075
1076/**
1077 *  e1000_init_hw_82571 - Initialize hardware
1078 *  @hw: pointer to the HW structure
1079 *
1080 *  This inits the hardware readying it for operation.
1081 **/
1082static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1083{
1084	struct e1000_mac_info *mac = &hw->mac;
1085	u32 reg_data;
1086	s32 ret_val;
1087	u16 i, rar_count = mac->rar_entry_count;
1088
1089	e1000_initialize_hw_bits_82571(hw);
1090
1091	/* Initialize identification LED */
1092	ret_val = mac->ops.id_led_init(hw);
1093	/* An error is not fatal and we should not stop init due to this */
1094	if (ret_val)
1095		e_dbg("Error initializing identification LED\n");
1096
1097	/* Disabling VLAN filtering */
1098	e_dbg("Initializing the IEEE VLAN\n");
1099	mac->ops.clear_vfta(hw);
1100
1101	/* Setup the receive address.
1102	 * If, however, a locally administered address was assigned to the
1103	 * 82571, we must reserve a RAR for it to work around an issue where
1104	 * resetting one port will reload the MAC on the other port.
1105	 */
1106	if (e1000e_get_laa_state_82571(hw))
1107		rar_count--;
1108	e1000e_init_rx_addrs(hw, rar_count);
1109
1110	/* Zero out the Multicast HASH table */
1111	e_dbg("Zeroing the MTA\n");
1112	for (i = 0; i < mac->mta_reg_count; i++)
1113		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1114
1115	/* Setup link and flow control */
1116	ret_val = mac->ops.setup_link(hw);
1117
1118	/* Set the transmit descriptor write-back policy */
1119	reg_data = er32(TXDCTL(0));
1120	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1121		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1122	ew32(TXDCTL(0), reg_data);
1123
1124	/* ...for both queues. */
1125	switch (mac->type) {
1126	case e1000_82573:
1127		e1000e_enable_tx_pkt_filtering(hw);
1128		/* fall through */
1129	case e1000_82574:
1130	case e1000_82583:
1131		reg_data = er32(GCR);
1132		reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1133		ew32(GCR, reg_data);
1134		break;
1135	default:
1136		reg_data = er32(TXDCTL(1));
1137		reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1138			    E1000_TXDCTL_FULL_TX_DESC_WB |
1139			    E1000_TXDCTL_COUNT_DESC);
1140		ew32(TXDCTL(1), reg_data);
1141		break;
1142	}
1143
1144	/* Clear all of the statistics registers (clear on read).  It is
1145	 * important that we do this after we have tried to establish link
1146	 * because the symbol error count will increment wildly if there
1147	 * is no link.
1148	 */
1149	e1000_clear_hw_cntrs_82571(hw);
1150
1151	return ret_val;
1152}
1153
1154/**
1155 *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1156 *  @hw: pointer to the HW structure
1157 *
1158 *  Initializes required hardware-dependent bits needed for normal operation.
1159 **/
1160static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1161{
1162	u32 reg;
1163
1164	/* Transmit Descriptor Control 0 */
1165	reg = er32(TXDCTL(0));
1166	reg |= (1 << 22);
1167	ew32(TXDCTL(0), reg);
1168
1169	/* Transmit Descriptor Control 1 */
1170	reg = er32(TXDCTL(1));
1171	reg |= (1 << 22);
1172	ew32(TXDCTL(1), reg);
1173
1174	/* Transmit Arbitration Control 0 */
1175	reg = er32(TARC(0));
1176	reg &= ~(0xF << 27);	/* 30:27 */
1177	switch (hw->mac.type) {
1178	case e1000_82571:
1179	case e1000_82572:
1180		reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1181		break;
1182	case e1000_82574:
1183	case e1000_82583:
1184		reg |= (1 << 26);
1185		break;
1186	default:
1187		break;
1188	}
1189	ew32(TARC(0), reg);
1190
1191	/* Transmit Arbitration Control 1 */
1192	reg = er32(TARC(1));
1193	switch (hw->mac.type) {
1194	case e1000_82571:
1195	case e1000_82572:
1196		reg &= ~((1 << 29) | (1 << 30));
1197		reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1198		if (er32(TCTL) & E1000_TCTL_MULR)
1199			reg &= ~(1 << 28);
1200		else
1201			reg |= (1 << 28);
1202		ew32(TARC(1), reg);
1203		break;
1204	default:
1205		break;
1206	}
1207
1208	/* Device Control */
1209	switch (hw->mac.type) {
1210	case e1000_82573:
1211	case e1000_82574:
1212	case e1000_82583:
1213		reg = er32(CTRL);
1214		reg &= ~(1 << 29);
1215		ew32(CTRL, reg);
1216		break;
1217	default:
1218		break;
1219	}
1220
1221	/* Extended Device Control */
1222	switch (hw->mac.type) {
1223	case e1000_82573:
1224	case e1000_82574:
1225	case e1000_82583:
1226		reg = er32(CTRL_EXT);
1227		reg &= ~(1 << 23);
1228		reg |= (1 << 22);
1229		ew32(CTRL_EXT, reg);
1230		break;
1231	default:
1232		break;
1233	}
1234
1235	if (hw->mac.type == e1000_82571) {
1236		reg = er32(PBA_ECC);
1237		reg |= E1000_PBA_ECC_CORR_EN;
1238		ew32(PBA_ECC, reg);
1239	}
1240
1241	/* Workaround for hardware errata.
1242	 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1243	 */
1244	if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1245		reg = er32(CTRL_EXT);
1246		reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1247		ew32(CTRL_EXT, reg);
1248	}
1249
1250	/* Disable IPv6 extension header parsing because some malformed
1251	 * IPv6 headers can hang the Rx.
1252	 */
1253	if (hw->mac.type <= e1000_82573) {
1254		reg = er32(RFCTL);
1255		reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1256		ew32(RFCTL, reg);
1257	}
1258
1259	/* PCI-Ex Control Registers */
1260	switch (hw->mac.type) {
1261	case e1000_82574:
1262	case e1000_82583:
1263		reg = er32(GCR);
1264		reg |= (1 << 22);
1265		ew32(GCR, reg);
1266
1267		/* Workaround for hardware errata.
1268		 * apply workaround for hardware errata documented in errata
1269		 * docs Fixes issue where some error prone or unreliable PCIe
1270		 * completions are occurring, particularly with ASPM enabled.
1271		 * Without fix, issue can cause Tx timeouts.
1272		 */
1273		reg = er32(GCR2);
1274		reg |= 1;
1275		ew32(GCR2, reg);
1276		break;
1277	default:
1278		break;
1279	}
1280}
1281
1282/**
1283 *  e1000_clear_vfta_82571 - Clear VLAN filter table
1284 *  @hw: pointer to the HW structure
1285 *
1286 *  Clears the register array which contains the VLAN filter table by
1287 *  setting all the values to 0.
1288 **/
1289static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1290{
1291	u32 offset;
1292	u32 vfta_value = 0;
1293	u32 vfta_offset = 0;
1294	u32 vfta_bit_in_reg = 0;
1295
1296	switch (hw->mac.type) {
1297	case e1000_82573:
1298	case e1000_82574:
1299	case e1000_82583:
1300		if (hw->mng_cookie.vlan_id != 0) {
1301			/* The VFTA is a 4096b bit-field, each identifying
1302			 * a single VLAN ID.  The following operations
1303			 * determine which 32b entry (i.e. offset) into the
1304			 * array we want to set the VLAN ID (i.e. bit) of
1305			 * the manageability unit.
1306			 */
1307			vfta_offset = (hw->mng_cookie.vlan_id >>
1308				       E1000_VFTA_ENTRY_SHIFT) &
1309			    E1000_VFTA_ENTRY_MASK;
1310			vfta_bit_in_reg =
1311			    1 << (hw->mng_cookie.vlan_id &
1312				  E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1313		}
1314		break;
1315	default:
1316		break;
1317	}
1318	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1319		/* If the offset we want to clear is the same offset of the
1320		 * manageability VLAN ID, then clear all bits except that of
1321		 * the manageability unit.
1322		 */
1323		vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1324		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1325		e1e_flush();
1326	}
1327}
1328
1329/**
1330 *  e1000_check_mng_mode_82574 - Check manageability is enabled
1331 *  @hw: pointer to the HW structure
1332 *
1333 *  Reads the NVM Initialization Control Word 2 and returns true
1334 *  (>0) if any manageability is enabled, else false (0).
1335 **/
1336static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1337{
1338	u16 data;
1339
1340	e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1341	return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1342}
1343
1344/**
1345 *  e1000_led_on_82574 - Turn LED on
1346 *  @hw: pointer to the HW structure
1347 *
1348 *  Turn LED on.
1349 **/
1350static s32 e1000_led_on_82574(struct e1000_hw *hw)
1351{
1352	u32 ctrl;
1353	u32 i;
1354
1355	ctrl = hw->mac.ledctl_mode2;
1356	if (!(E1000_STATUS_LU & er32(STATUS))) {
1357		/* If no link, then turn LED on by setting the invert bit
1358		 * for each LED that's "on" (0x0E) in ledctl_mode2.
1359		 */
1360		for (i = 0; i < 4; i++)
1361			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1362			    E1000_LEDCTL_MODE_LED_ON)
1363				ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1364	}
1365	ew32(LEDCTL, ctrl);
1366
1367	return 0;
1368}
1369
1370/**
1371 *  e1000_check_phy_82574 - check 82574 phy hung state
1372 *  @hw: pointer to the HW structure
1373 *
1374 *  Returns whether phy is hung or not
1375 **/
1376bool e1000_check_phy_82574(struct e1000_hw *hw)
1377{
1378	u16 status_1kbt = 0;
1379	u16 receive_errors = 0;
1380	s32 ret_val;
1381
1382	/* Read PHY Receive Error counter first, if its is max - all F's then
1383	 * read the Base1000T status register If both are max then PHY is hung.
1384	 */
1385	ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1386	if (ret_val)
1387		return false;
1388	if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1389		ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1390		if (ret_val)
1391			return false;
1392		if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1393		    E1000_IDLE_ERROR_COUNT_MASK)
1394			return true;
1395	}
1396
1397	return false;
1398}
1399
1400/**
1401 *  e1000_setup_link_82571 - Setup flow control and link settings
1402 *  @hw: pointer to the HW structure
1403 *
1404 *  Determines which flow control settings to use, then configures flow
1405 *  control.  Calls the appropriate media-specific link configuration
1406 *  function.  Assuming the adapter has a valid link partner, a valid link
1407 *  should be established.  Assumes the hardware has previously been reset
1408 *  and the transmitter and receiver are not enabled.
1409 **/
1410static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1411{
1412	/* 82573 does not have a word in the NVM to determine
1413	 * the default flow control setting, so we explicitly
1414	 * set it to full.
1415	 */
1416	switch (hw->mac.type) {
1417	case e1000_82573:
1418	case e1000_82574:
1419	case e1000_82583:
1420		if (hw->fc.requested_mode == e1000_fc_default)
1421			hw->fc.requested_mode = e1000_fc_full;
1422		break;
1423	default:
1424		break;
1425	}
1426
1427	return e1000e_setup_link_generic(hw);
1428}
1429
1430/**
1431 *  e1000_setup_copper_link_82571 - Configure copper link settings
1432 *  @hw: pointer to the HW structure
1433 *
1434 *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1435 *  for link, once link is established calls to configure collision distance
1436 *  and flow control are called.
1437 **/
1438static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1439{
1440	u32 ctrl;
1441	s32 ret_val;
1442
1443	ctrl = er32(CTRL);
1444	ctrl |= E1000_CTRL_SLU;
1445	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1446	ew32(CTRL, ctrl);
1447
1448	switch (hw->phy.type) {
1449	case e1000_phy_m88:
1450	case e1000_phy_bm:
1451		ret_val = e1000e_copper_link_setup_m88(hw);
1452		break;
1453	case e1000_phy_igp_2:
1454		ret_val = e1000e_copper_link_setup_igp(hw);
1455		break;
1456	default:
1457		return -E1000_ERR_PHY;
1458	}
1459
1460	if (ret_val)
1461		return ret_val;
1462
1463	return e1000e_setup_copper_link(hw);
1464}
1465
1466/**
1467 *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1468 *  @hw: pointer to the HW structure
1469 *
1470 *  Configures collision distance and flow control for fiber and serdes links.
1471 *  Upon successful setup, poll for link.
1472 **/
1473static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1474{
1475	switch (hw->mac.type) {
1476	case e1000_82571:
1477	case e1000_82572:
1478		/* If SerDes loopback mode is entered, there is no form
1479		 * of reset to take the adapter out of that mode.  So we
1480		 * have to explicitly take the adapter out of loopback
1481		 * mode.  This prevents drivers from twiddling their thumbs
1482		 * if another tool failed to take it out of loopback mode.
1483		 */
1484		ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1485		break;
1486	default:
1487		break;
1488	}
1489
1490	return e1000e_setup_fiber_serdes_link(hw);
1491}
1492
1493/**
1494 *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1495 *  @hw: pointer to the HW structure
1496 *
1497 *  Reports the link state as up or down.
1498 *
1499 *  If autonegotiation is supported by the link partner, the link state is
1500 *  determined by the result of autonegotiation. This is the most likely case.
1501 *  If autonegotiation is not supported by the link partner, and the link
1502 *  has a valid signal, force the link up.
1503 *
1504 *  The link state is represented internally here by 4 states:
1505 *
1506 *  1) down
1507 *  2) autoneg_progress
1508 *  3) autoneg_complete (the link successfully autonegotiated)
1509 *  4) forced_up (the link has been forced up, it did not autonegotiate)
1510 *
1511 **/
1512static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1513{
1514	struct e1000_mac_info *mac = &hw->mac;
1515	u32 rxcw;
1516	u32 ctrl;
1517	u32 status;
1518	u32 txcw;
1519	u32 i;
1520	s32 ret_val = 0;
1521
1522	ctrl = er32(CTRL);
1523	status = er32(STATUS);
1524	er32(RXCW);
1525	/* SYNCH bit and IV bit are sticky */
1526	usleep_range(10, 20);
1527	rxcw = er32(RXCW);
1528
1529	if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1530		/* Receiver is synchronized with no invalid bits.  */
1531		switch (mac->serdes_link_state) {
1532		case e1000_serdes_link_autoneg_complete:
1533			if (!(status & E1000_STATUS_LU)) {
1534				/* We have lost link, retry autoneg before
1535				 * reporting link failure
1536				 */
1537				mac->serdes_link_state =
1538				    e1000_serdes_link_autoneg_progress;
1539				mac->serdes_has_link = false;
1540				e_dbg("AN_UP     -> AN_PROG\n");
1541			} else {
1542				mac->serdes_has_link = true;
1543			}
1544			break;
1545
1546		case e1000_serdes_link_forced_up:
1547			/* If we are receiving /C/ ordered sets, re-enable
1548			 * auto-negotiation in the TXCW register and disable
1549			 * forced link in the Device Control register in an
1550			 * attempt to auto-negotiate with our link partner.
1551			 */
1552			if (rxcw & E1000_RXCW_C) {
1553				/* Enable autoneg, and unforce link up */
1554				ew32(TXCW, mac->txcw);
1555				ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1556				mac->serdes_link_state =
1557				    e1000_serdes_link_autoneg_progress;
1558				mac->serdes_has_link = false;
1559				e_dbg("FORCED_UP -> AN_PROG\n");
1560			} else {
1561				mac->serdes_has_link = true;
1562			}
1563			break;
1564
1565		case e1000_serdes_link_autoneg_progress:
1566			if (rxcw & E1000_RXCW_C) {
1567				/* We received /C/ ordered sets, meaning the
1568				 * link partner has autonegotiated, and we can
1569				 * trust the Link Up (LU) status bit.
1570				 */
1571				if (status & E1000_STATUS_LU) {
1572					mac->serdes_link_state =
1573					    e1000_serdes_link_autoneg_complete;
1574					e_dbg("AN_PROG   -> AN_UP\n");
1575					mac->serdes_has_link = true;
1576				} else {
1577					/* Autoneg completed, but failed. */
1578					mac->serdes_link_state =
1579					    e1000_serdes_link_down;
1580					e_dbg("AN_PROG   -> DOWN\n");
1581				}
1582			} else {
1583				/* The link partner did not autoneg.
1584				 * Force link up and full duplex, and change
1585				 * state to forced.
1586				 */
1587				ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1588				ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1589				ew32(CTRL, ctrl);
1590
1591				/* Configure Flow Control after link up. */
1592				ret_val = e1000e_config_fc_after_link_up(hw);
1593				if (ret_val) {
1594					e_dbg("Error config flow control\n");
1595					break;
1596				}
1597				mac->serdes_link_state =
1598				    e1000_serdes_link_forced_up;
1599				mac->serdes_has_link = true;
1600				e_dbg("AN_PROG   -> FORCED_UP\n");
1601			}
1602			break;
1603
1604		case e1000_serdes_link_down:
1605		default:
1606			/* The link was down but the receiver has now gained
1607			 * valid sync, so lets see if we can bring the link
1608			 * up.
1609			 */
1610			ew32(TXCW, mac->txcw);
1611			ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1612			mac->serdes_link_state =
1613			    e1000_serdes_link_autoneg_progress;
1614			mac->serdes_has_link = false;
1615			e_dbg("DOWN      -> AN_PROG\n");
1616			break;
1617		}
1618	} else {
1619		if (!(rxcw & E1000_RXCW_SYNCH)) {
1620			mac->serdes_has_link = false;
1621			mac->serdes_link_state = e1000_serdes_link_down;
1622			e_dbg("ANYSTATE  -> DOWN\n");
1623		} else {
1624			/* Check several times, if SYNCH bit and CONFIG
1625			 * bit both are consistently 1 then simply ignore
1626			 * the IV bit and restart Autoneg
1627			 */
1628			for (i = 0; i < AN_RETRY_COUNT; i++) {
1629				usleep_range(10, 20);
1630				rxcw = er32(RXCW);
1631				if ((rxcw & E1000_RXCW_SYNCH) &&
1632				    (rxcw & E1000_RXCW_C))
1633					continue;
1634
1635				if (rxcw & E1000_RXCW_IV) {
1636					mac->serdes_has_link = false;
1637					mac->serdes_link_state =
1638					    e1000_serdes_link_down;
1639					e_dbg("ANYSTATE  -> DOWN\n");
1640					break;
1641				}
1642			}
1643
1644			if (i == AN_RETRY_COUNT) {
1645				txcw = er32(TXCW);
1646				txcw |= E1000_TXCW_ANE;
1647				ew32(TXCW, txcw);
1648				mac->serdes_link_state =
1649				    e1000_serdes_link_autoneg_progress;
1650				mac->serdes_has_link = false;
1651				e_dbg("ANYSTATE  -> AN_PROG\n");
1652			}
1653		}
1654	}
1655
1656	return ret_val;
1657}
1658
1659/**
1660 *  e1000_valid_led_default_82571 - Verify a valid default LED config
1661 *  @hw: pointer to the HW structure
1662 *  @data: pointer to the NVM (EEPROM)
1663 *
1664 *  Read the EEPROM for the current default LED configuration.  If the
1665 *  LED configuration is not valid, set to a valid LED configuration.
1666 **/
1667static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1668{
1669	s32 ret_val;
1670
1671	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1672	if (ret_val) {
1673		e_dbg("NVM Read Error\n");
1674		return ret_val;
1675	}
1676
1677	switch (hw->mac.type) {
1678	case e1000_82573:
1679	case e1000_82574:
1680	case e1000_82583:
1681		if (*data == ID_LED_RESERVED_F746)
1682			*data = ID_LED_DEFAULT_82573;
1683		break;
1684	default:
1685		if (*data == ID_LED_RESERVED_0000 ||
1686		    *data == ID_LED_RESERVED_FFFF)
1687			*data = ID_LED_DEFAULT;
1688		break;
1689	}
1690
1691	return 0;
1692}
1693
1694/**
1695 *  e1000e_get_laa_state_82571 - Get locally administered address state
1696 *  @hw: pointer to the HW structure
1697 *
1698 *  Retrieve and return the current locally administered address state.
1699 **/
1700bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1701{
1702	if (hw->mac.type != e1000_82571)
1703		return false;
1704
1705	return hw->dev_spec.e82571.laa_is_present;
1706}
1707
1708/**
1709 *  e1000e_set_laa_state_82571 - Set locally administered address state
1710 *  @hw: pointer to the HW structure
1711 *  @state: enable/disable locally administered address
1712 *
1713 *  Enable/Disable the current locally administered address state.
1714 **/
1715void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1716{
1717	if (hw->mac.type != e1000_82571)
1718		return;
1719
1720	hw->dev_spec.e82571.laa_is_present = state;
1721
1722	/* If workaround is activated... */
1723	if (state)
1724		/* Hold a copy of the LAA in RAR[14] This is done so that
1725		 * between the time RAR[0] gets clobbered and the time it
1726		 * gets fixed, the actual LAA is in one of the RARs and no
1727		 * incoming packets directed to this port are dropped.
1728		 * Eventually the LAA will be in RAR[0] and RAR[14].
1729		 */
1730		hw->mac.ops.rar_set(hw, hw->mac.addr,
1731				    hw->mac.rar_entry_count - 1);
1732}
1733
1734/**
1735 *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1736 *  @hw: pointer to the HW structure
1737 *
1738 *  Verifies that the EEPROM has completed the update.  After updating the
1739 *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1740 *  the checksum fix is not implemented, we need to set the bit and update
1741 *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1742 *  we need to return bad checksum.
1743 **/
1744static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1745{
1746	struct e1000_nvm_info *nvm = &hw->nvm;
1747	s32 ret_val;
1748	u16 data;
1749
1750	if (nvm->type != e1000_nvm_flash_hw)
1751		return 0;
1752
1753	/* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1754	 * 10h-12h.  Checksum may need to be fixed.
1755	 */
1756	ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1757	if (ret_val)
1758		return ret_val;
1759
1760	if (!(data & 0x10)) {
1761		/* Read 0x23 and check bit 15.  This bit is a 1
1762		 * when the checksum has already been fixed.  If
1763		 * the checksum is still wrong and this bit is a
1764		 * 1, we need to return bad checksum.  Otherwise,
1765		 * we need to set this bit to a 1 and update the
1766		 * checksum.
1767		 */
1768		ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1769		if (ret_val)
1770			return ret_val;
1771
1772		if (!(data & 0x8000)) {
1773			data |= 0x8000;
1774			ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1775			if (ret_val)
1776				return ret_val;
1777			ret_val = e1000e_update_nvm_checksum(hw);
1778			if (ret_val)
1779				return ret_val;
1780		}
1781	}
1782
1783	return 0;
1784}
1785
1786/**
1787 *  e1000_read_mac_addr_82571 - Read device MAC address
1788 *  @hw: pointer to the HW structure
1789 **/
1790static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1791{
1792	if (hw->mac.type == e1000_82571) {
1793		s32 ret_val;
1794
1795		/* If there's an alternate MAC address place it in RAR0
1796		 * so that it will override the Si installed default perm
1797		 * address.
1798		 */
1799		ret_val = e1000_check_alt_mac_addr_generic(hw);
1800		if (ret_val)
1801			return ret_val;
1802	}
1803
1804	return e1000_read_mac_addr_generic(hw);
1805}
1806
1807/**
1808 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1809 * @hw: pointer to the HW structure
1810 *
1811 * In the case of a PHY power down to save power, or to turn off link during a
1812 * driver unload, or wake on lan is not enabled, remove the link.
1813 **/
1814static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1815{
1816	struct e1000_phy_info *phy = &hw->phy;
1817	struct e1000_mac_info *mac = &hw->mac;
1818
1819	if (!phy->ops.check_reset_block)
1820		return;
1821
1822	/* If the management interface is not enabled, then power down */
1823	if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1824		e1000_power_down_phy_copper(hw);
1825}
1826
1827/**
1828 *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1829 *  @hw: pointer to the HW structure
1830 *
1831 *  Clears the hardware counters by reading the counter registers.
1832 **/
1833static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1834{
1835	e1000e_clear_hw_cntrs_base(hw);
1836
1837	er32(PRC64);
1838	er32(PRC127);
1839	er32(PRC255);
1840	er32(PRC511);
1841	er32(PRC1023);
1842	er32(PRC1522);
1843	er32(PTC64);
1844	er32(PTC127);
1845	er32(PTC255);
1846	er32(PTC511);
1847	er32(PTC1023);
1848	er32(PTC1522);
1849
1850	er32(ALGNERRC);
1851	er32(RXERRC);
1852	er32(TNCRS);
1853	er32(CEXTERR);
1854	er32(TSCTC);
1855	er32(TSCTFC);
1856
1857	er32(MGTPRC);
1858	er32(MGTPDC);
1859	er32(MGTPTC);
1860
1861	er32(IAC);
1862	er32(ICRXOC);
1863
1864	er32(ICRXPTC);
1865	er32(ICRXATC);
1866	er32(ICTXPTC);
1867	er32(ICTXATC);
1868	er32(ICTXQEC);
1869	er32(ICTXQMTC);
1870	er32(ICRXDMTC);
1871}
1872
1873static const struct e1000_mac_operations e82571_mac_ops = {
1874	/* .check_mng_mode: mac type dependent */
1875	/* .check_for_link: media type dependent */
1876	.id_led_init		= e1000e_id_led_init_generic,
1877	.cleanup_led		= e1000e_cleanup_led_generic,
1878	.clear_hw_cntrs		= e1000_clear_hw_cntrs_82571,
1879	.get_bus_info		= e1000e_get_bus_info_pcie,
1880	.set_lan_id		= e1000_set_lan_id_multi_port_pcie,
1881	/* .get_link_up_info: media type dependent */
1882	/* .led_on: mac type dependent */
1883	.led_off		= e1000e_led_off_generic,
1884	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
1885	.write_vfta		= e1000_write_vfta_generic,
1886	.clear_vfta		= e1000_clear_vfta_82571,
1887	.reset_hw		= e1000_reset_hw_82571,
1888	.init_hw		= e1000_init_hw_82571,
1889	.setup_link		= e1000_setup_link_82571,
1890	/* .setup_physical_interface: media type dependent */
1891	.setup_led		= e1000e_setup_led_generic,
1892	.config_collision_dist	= e1000e_config_collision_dist_generic,
1893	.read_mac_addr		= e1000_read_mac_addr_82571,
1894	.rar_set		= e1000e_rar_set_generic,
1895	.rar_get_count		= e1000e_rar_get_count_generic,
1896};
1897
1898static const struct e1000_phy_operations e82_phy_ops_igp = {
1899	.acquire		= e1000_get_hw_semaphore_82571,
1900	.check_polarity		= e1000_check_polarity_igp,
1901	.check_reset_block	= e1000e_check_reset_block_generic,
1902	.commit			= NULL,
1903	.force_speed_duplex	= e1000e_phy_force_speed_duplex_igp,
1904	.get_cfg_done		= e1000_get_cfg_done_82571,
1905	.get_cable_length	= e1000e_get_cable_length_igp_2,
1906	.get_info		= e1000e_get_phy_info_igp,
1907	.read_reg		= e1000e_read_phy_reg_igp,
1908	.release		= e1000_put_hw_semaphore_82571,
1909	.reset			= e1000e_phy_hw_reset_generic,
1910	.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571,
1911	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
1912	.write_reg		= e1000e_write_phy_reg_igp,
1913	.cfg_on_link_up		= NULL,
1914};
1915
1916static const struct e1000_phy_operations e82_phy_ops_m88 = {
1917	.acquire		= e1000_get_hw_semaphore_82571,
1918	.check_polarity		= e1000_check_polarity_m88,
1919	.check_reset_block	= e1000e_check_reset_block_generic,
1920	.commit			= e1000e_phy_sw_reset,
1921	.force_speed_duplex	= e1000e_phy_force_speed_duplex_m88,
1922	.get_cfg_done		= e1000e_get_cfg_done_generic,
1923	.get_cable_length	= e1000e_get_cable_length_m88,
1924	.get_info		= e1000e_get_phy_info_m88,
1925	.read_reg		= e1000e_read_phy_reg_m88,
1926	.release		= e1000_put_hw_semaphore_82571,
1927	.reset			= e1000e_phy_hw_reset_generic,
1928	.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571,
1929	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
1930	.write_reg		= e1000e_write_phy_reg_m88,
1931	.cfg_on_link_up		= NULL,
1932};
1933
1934static const struct e1000_phy_operations e82_phy_ops_bm = {
1935	.acquire		= e1000_get_hw_semaphore_82571,
1936	.check_polarity		= e1000_check_polarity_m88,
1937	.check_reset_block	= e1000e_check_reset_block_generic,
1938	.commit			= e1000e_phy_sw_reset,
1939	.force_speed_duplex	= e1000e_phy_force_speed_duplex_m88,
1940	.get_cfg_done		= e1000e_get_cfg_done_generic,
1941	.get_cable_length	= e1000e_get_cable_length_m88,
1942	.get_info		= e1000e_get_phy_info_m88,
1943	.read_reg		= e1000e_read_phy_reg_bm2,
1944	.release		= e1000_put_hw_semaphore_82571,
1945	.reset			= e1000e_phy_hw_reset_generic,
1946	.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571,
1947	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
1948	.write_reg		= e1000e_write_phy_reg_bm2,
1949	.cfg_on_link_up		= NULL,
1950};
1951
1952static const struct e1000_nvm_operations e82571_nvm_ops = {
1953	.acquire		= e1000_acquire_nvm_82571,
1954	.read			= e1000e_read_nvm_eerd,
1955	.release		= e1000_release_nvm_82571,
1956	.reload			= e1000e_reload_nvm_generic,
1957	.update			= e1000_update_nvm_checksum_82571,
1958	.valid_led_default	= e1000_valid_led_default_82571,
1959	.validate		= e1000_validate_nvm_checksum_82571,
1960	.write			= e1000_write_nvm_82571,
1961};
1962
1963const struct e1000_info e1000_82571_info = {
1964	.mac			= e1000_82571,
1965	.flags			= FLAG_HAS_HW_VLAN_FILTER
1966				  | FLAG_HAS_JUMBO_FRAMES
1967				  | FLAG_HAS_WOL
1968				  | FLAG_APME_IN_CTRL3
1969				  | FLAG_HAS_CTRLEXT_ON_LOAD
1970				  | FLAG_HAS_SMART_POWER_DOWN
1971				  | FLAG_RESET_OVERWRITES_LAA /* errata */
1972				  | FLAG_TARC_SPEED_MODE_BIT /* errata */
1973				  | FLAG_APME_CHECK_PORT_B,
1974	.flags2			= FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1975				  | FLAG2_DMA_BURST,
1976	.pba			= 38,
1977	.max_hw_frame_size	= DEFAULT_JUMBO,
1978	.get_variants		= e1000_get_variants_82571,
1979	.mac_ops		= &e82571_mac_ops,
1980	.phy_ops		= &e82_phy_ops_igp,
1981	.nvm_ops		= &e82571_nvm_ops,
1982};
1983
1984const struct e1000_info e1000_82572_info = {
1985	.mac			= e1000_82572,
1986	.flags			= FLAG_HAS_HW_VLAN_FILTER
1987				  | FLAG_HAS_JUMBO_FRAMES
1988				  | FLAG_HAS_WOL
1989				  | FLAG_APME_IN_CTRL3
1990				  | FLAG_HAS_CTRLEXT_ON_LOAD
1991				  | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1992	.flags2			= FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1993				  | FLAG2_DMA_BURST,
1994	.pba			= 38,
1995	.max_hw_frame_size	= DEFAULT_JUMBO,
1996	.get_variants		= e1000_get_variants_82571,
1997	.mac_ops		= &e82571_mac_ops,
1998	.phy_ops		= &e82_phy_ops_igp,
1999	.nvm_ops		= &e82571_nvm_ops,
2000};
2001
2002const struct e1000_info e1000_82573_info = {
2003	.mac			= e1000_82573,
2004	.flags			= FLAG_HAS_HW_VLAN_FILTER
2005				  | FLAG_HAS_WOL
2006				  | FLAG_APME_IN_CTRL3
2007				  | FLAG_HAS_SMART_POWER_DOWN
2008				  | FLAG_HAS_AMT
2009				  | FLAG_HAS_SWSM_ON_LOAD,
2010	.flags2			= FLAG2_DISABLE_ASPM_L1
2011				  | FLAG2_DISABLE_ASPM_L0S,
2012	.pba			= 20,
2013	.max_hw_frame_size	= VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
2014	.get_variants		= e1000_get_variants_82571,
2015	.mac_ops		= &e82571_mac_ops,
2016	.phy_ops		= &e82_phy_ops_m88,
2017	.nvm_ops		= &e82571_nvm_ops,
2018};
2019
2020const struct e1000_info e1000_82574_info = {
2021	.mac			= e1000_82574,
2022	.flags			= FLAG_HAS_HW_VLAN_FILTER
2023				  | FLAG_HAS_MSIX
2024				  | FLAG_HAS_JUMBO_FRAMES
2025				  | FLAG_HAS_WOL
2026				  | FLAG_HAS_HW_TIMESTAMP
2027				  | FLAG_APME_IN_CTRL3
2028				  | FLAG_HAS_SMART_POWER_DOWN
2029				  | FLAG_HAS_AMT
2030				  | FLAG_HAS_CTRLEXT_ON_LOAD,
2031	.flags2			 = FLAG2_CHECK_PHY_HANG
2032				  | FLAG2_DISABLE_ASPM_L0S
2033				  | FLAG2_DISABLE_ASPM_L1
2034				  | FLAG2_NO_DISABLE_RX
2035				  | FLAG2_DMA_BURST,
 
2036	.pba			= 32,
2037	.max_hw_frame_size	= DEFAULT_JUMBO,
2038	.get_variants		= e1000_get_variants_82571,
2039	.mac_ops		= &e82571_mac_ops,
2040	.phy_ops		= &e82_phy_ops_bm,
2041	.nvm_ops		= &e82571_nvm_ops,
2042};
2043
2044const struct e1000_info e1000_82583_info = {
2045	.mac			= e1000_82583,
2046	.flags			= FLAG_HAS_HW_VLAN_FILTER
2047				  | FLAG_HAS_WOL
2048				  | FLAG_HAS_HW_TIMESTAMP
2049				  | FLAG_APME_IN_CTRL3
2050				  | FLAG_HAS_SMART_POWER_DOWN
2051				  | FLAG_HAS_AMT
2052				  | FLAG_HAS_JUMBO_FRAMES
2053				  | FLAG_HAS_CTRLEXT_ON_LOAD,
2054	.flags2			= FLAG2_DISABLE_ASPM_L0S
2055				  | FLAG2_DISABLE_ASPM_L1
2056				  | FLAG2_NO_DISABLE_RX,
 
2057	.pba			= 32,
2058	.max_hw_frame_size	= DEFAULT_JUMBO,
2059	.get_variants		= e1000_get_variants_82571,
2060	.mac_ops		= &e82571_mac_ops,
2061	.phy_ops		= &e82_phy_ops_bm,
2062	.nvm_ops		= &e82571_nvm_ops,
2063};