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1/*******************************************************************************
2*
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 */
28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33#include "e1000.h"
34
35static s32 e1000_check_downshift(struct e1000_hw *hw);
36static s32 e1000_check_polarity(struct e1000_hw *hw,
37 e1000_rev_polarity *polarity);
38static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
39static void e1000_clear_vfta(struct e1000_hw *hw);
40static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
41 bool link_up);
42static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
43static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
44static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
45static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
46 u16 *max_length);
47static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
48static s32 e1000_id_led_init(struct e1000_hw *hw);
49static void e1000_init_rx_addrs(struct e1000_hw *hw);
50static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
51 struct e1000_phy_info *phy_info);
52static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
53 struct e1000_phy_info *phy_info);
54static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
55static s32 e1000_wait_autoneg(struct e1000_hw *hw);
56static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
57static s32 e1000_set_phy_type(struct e1000_hw *hw);
58static void e1000_phy_init_script(struct e1000_hw *hw);
59static s32 e1000_setup_copper_link(struct e1000_hw *hw);
60static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
61static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
62static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
64static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
65static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
66static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
67static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
68static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
69static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
70 u16 words, u16 *data);
71static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
72 u16 words, u16 *data);
73static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
74static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
75static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
76static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
77static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
78 u16 phy_data);
79static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
80 u16 *phy_data);
81static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
82static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
83static void e1000_release_eeprom(struct e1000_hw *hw);
84static void e1000_standby_eeprom(struct e1000_hw *hw);
85static s32 e1000_set_vco_speed(struct e1000_hw *hw);
86static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
87static s32 e1000_set_phy_mode(struct e1000_hw *hw);
88static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
89 u16 *data);
90static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
91 u16 *data);
92
93/* IGP cable length table */
94static const
95u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
102 100,
103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
104 110, 110,
105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
106 120, 120
107};
108
109static DEFINE_MUTEX(e1000_eeprom_lock);
110static DEFINE_SPINLOCK(e1000_phy_lock);
111
112/**
113 * e1000_set_phy_type - Set the phy type member in the hw struct.
114 * @hw: Struct containing variables accessed by shared code
115 */
116static s32 e1000_set_phy_type(struct e1000_hw *hw)
117{
118 if (hw->mac_type == e1000_undefined)
119 return -E1000_ERR_PHY_TYPE;
120
121 switch (hw->phy_id) {
122 case M88E1000_E_PHY_ID:
123 case M88E1000_I_PHY_ID:
124 case M88E1011_I_PHY_ID:
125 case M88E1111_I_PHY_ID:
126 case M88E1118_E_PHY_ID:
127 hw->phy_type = e1000_phy_m88;
128 break;
129 case IGP01E1000_I_PHY_ID:
130 if (hw->mac_type == e1000_82541 ||
131 hw->mac_type == e1000_82541_rev_2 ||
132 hw->mac_type == e1000_82547 ||
133 hw->mac_type == e1000_82547_rev_2)
134 hw->phy_type = e1000_phy_igp;
135 break;
136 case RTL8211B_PHY_ID:
137 hw->phy_type = e1000_phy_8211;
138 break;
139 case RTL8201N_PHY_ID:
140 hw->phy_type = e1000_phy_8201;
141 break;
142 default:
143 /* Should never have loaded on this device */
144 hw->phy_type = e1000_phy_undefined;
145 return -E1000_ERR_PHY_TYPE;
146 }
147
148 return E1000_SUCCESS;
149}
150
151/**
152 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
153 * @hw: Struct containing variables accessed by shared code
154 */
155static void e1000_phy_init_script(struct e1000_hw *hw)
156{
157 u32 ret_val;
158 u16 phy_saved_data;
159
160 if (hw->phy_init_script) {
161 msleep(20);
162
163 /* Save off the current value of register 0x2F5B to be restored
164 * at the end of this routine.
165 */
166 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
167
168 /* Disabled the PHY transmitter */
169 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
170 msleep(20);
171
172 e1000_write_phy_reg(hw, 0x0000, 0x0140);
173 msleep(5);
174
175 switch (hw->mac_type) {
176 case e1000_82541:
177 case e1000_82547:
178 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
179 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
180 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
181 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
182 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
183 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
184 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
185 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
186 e1000_write_phy_reg(hw, 0x2010, 0x0008);
187 break;
188
189 case e1000_82541_rev_2:
190 case e1000_82547_rev_2:
191 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
192 break;
193 default:
194 break;
195 }
196
197 e1000_write_phy_reg(hw, 0x0000, 0x3300);
198 msleep(20);
199
200 /* Now enable the transmitter */
201 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
202
203 if (hw->mac_type == e1000_82547) {
204 u16 fused, fine, coarse;
205
206 /* Move to analog registers page */
207 e1000_read_phy_reg(hw,
208 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
209 &fused);
210
211 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
212 e1000_read_phy_reg(hw,
213 IGP01E1000_ANALOG_FUSE_STATUS,
214 &fused);
215
216 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
217 coarse =
218 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
219
220 if (coarse >
221 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
222 coarse -=
223 IGP01E1000_ANALOG_FUSE_COARSE_10;
224 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
225 } else if (coarse ==
226 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
227 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
228
229 fused =
230 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
231 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
232 (coarse &
233 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
234
235 e1000_write_phy_reg(hw,
236 IGP01E1000_ANALOG_FUSE_CONTROL,
237 fused);
238 e1000_write_phy_reg(hw,
239 IGP01E1000_ANALOG_FUSE_BYPASS,
240 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
241 }
242 }
243 }
244}
245
246/**
247 * e1000_set_mac_type - Set the mac type member in the hw struct.
248 * @hw: Struct containing variables accessed by shared code
249 */
250s32 e1000_set_mac_type(struct e1000_hw *hw)
251{
252 switch (hw->device_id) {
253 case E1000_DEV_ID_82542:
254 switch (hw->revision_id) {
255 case E1000_82542_2_0_REV_ID:
256 hw->mac_type = e1000_82542_rev2_0;
257 break;
258 case E1000_82542_2_1_REV_ID:
259 hw->mac_type = e1000_82542_rev2_1;
260 break;
261 default:
262 /* Invalid 82542 revision ID */
263 return -E1000_ERR_MAC_TYPE;
264 }
265 break;
266 case E1000_DEV_ID_82543GC_FIBER:
267 case E1000_DEV_ID_82543GC_COPPER:
268 hw->mac_type = e1000_82543;
269 break;
270 case E1000_DEV_ID_82544EI_COPPER:
271 case E1000_DEV_ID_82544EI_FIBER:
272 case E1000_DEV_ID_82544GC_COPPER:
273 case E1000_DEV_ID_82544GC_LOM:
274 hw->mac_type = e1000_82544;
275 break;
276 case E1000_DEV_ID_82540EM:
277 case E1000_DEV_ID_82540EM_LOM:
278 case E1000_DEV_ID_82540EP:
279 case E1000_DEV_ID_82540EP_LOM:
280 case E1000_DEV_ID_82540EP_LP:
281 hw->mac_type = e1000_82540;
282 break;
283 case E1000_DEV_ID_82545EM_COPPER:
284 case E1000_DEV_ID_82545EM_FIBER:
285 hw->mac_type = e1000_82545;
286 break;
287 case E1000_DEV_ID_82545GM_COPPER:
288 case E1000_DEV_ID_82545GM_FIBER:
289 case E1000_DEV_ID_82545GM_SERDES:
290 hw->mac_type = e1000_82545_rev_3;
291 break;
292 case E1000_DEV_ID_82546EB_COPPER:
293 case E1000_DEV_ID_82546EB_FIBER:
294 case E1000_DEV_ID_82546EB_QUAD_COPPER:
295 hw->mac_type = e1000_82546;
296 break;
297 case E1000_DEV_ID_82546GB_COPPER:
298 case E1000_DEV_ID_82546GB_FIBER:
299 case E1000_DEV_ID_82546GB_SERDES:
300 case E1000_DEV_ID_82546GB_PCIE:
301 case E1000_DEV_ID_82546GB_QUAD_COPPER:
302 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
303 hw->mac_type = e1000_82546_rev_3;
304 break;
305 case E1000_DEV_ID_82541EI:
306 case E1000_DEV_ID_82541EI_MOBILE:
307 case E1000_DEV_ID_82541ER_LOM:
308 hw->mac_type = e1000_82541;
309 break;
310 case E1000_DEV_ID_82541ER:
311 case E1000_DEV_ID_82541GI:
312 case E1000_DEV_ID_82541GI_LF:
313 case E1000_DEV_ID_82541GI_MOBILE:
314 hw->mac_type = e1000_82541_rev_2;
315 break;
316 case E1000_DEV_ID_82547EI:
317 case E1000_DEV_ID_82547EI_MOBILE:
318 hw->mac_type = e1000_82547;
319 break;
320 case E1000_DEV_ID_82547GI:
321 hw->mac_type = e1000_82547_rev_2;
322 break;
323 case E1000_DEV_ID_INTEL_CE4100_GBE:
324 hw->mac_type = e1000_ce4100;
325 break;
326 default:
327 /* Should never have loaded on this device */
328 return -E1000_ERR_MAC_TYPE;
329 }
330
331 switch (hw->mac_type) {
332 case e1000_82541:
333 case e1000_82547:
334 case e1000_82541_rev_2:
335 case e1000_82547_rev_2:
336 hw->asf_firmware_present = true;
337 break;
338 default:
339 break;
340 }
341
342 /* The 82543 chip does not count tx_carrier_errors properly in
343 * FD mode
344 */
345 if (hw->mac_type == e1000_82543)
346 hw->bad_tx_carr_stats_fd = true;
347
348 if (hw->mac_type > e1000_82544)
349 hw->has_smbus = true;
350
351 return E1000_SUCCESS;
352}
353
354/**
355 * e1000_set_media_type - Set media type and TBI compatibility.
356 * @hw: Struct containing variables accessed by shared code
357 */
358void e1000_set_media_type(struct e1000_hw *hw)
359{
360 u32 status;
361
362 if (hw->mac_type != e1000_82543) {
363 /* tbi_compatibility is only valid on 82543 */
364 hw->tbi_compatibility_en = false;
365 }
366
367 switch (hw->device_id) {
368 case E1000_DEV_ID_82545GM_SERDES:
369 case E1000_DEV_ID_82546GB_SERDES:
370 hw->media_type = e1000_media_type_internal_serdes;
371 break;
372 default:
373 switch (hw->mac_type) {
374 case e1000_82542_rev2_0:
375 case e1000_82542_rev2_1:
376 hw->media_type = e1000_media_type_fiber;
377 break;
378 case e1000_ce4100:
379 hw->media_type = e1000_media_type_copper;
380 break;
381 default:
382 status = er32(STATUS);
383 if (status & E1000_STATUS_TBIMODE) {
384 hw->media_type = e1000_media_type_fiber;
385 /* tbi_compatibility not valid on fiber */
386 hw->tbi_compatibility_en = false;
387 } else {
388 hw->media_type = e1000_media_type_copper;
389 }
390 break;
391 }
392 }
393}
394
395/**
396 * e1000_reset_hw - reset the hardware completely
397 * @hw: Struct containing variables accessed by shared code
398 *
399 * Reset the transmit and receive units; mask and clear all interrupts.
400 */
401s32 e1000_reset_hw(struct e1000_hw *hw)
402{
403 u32 ctrl;
404 u32 ctrl_ext;
405 u32 icr;
406 u32 manc;
407 u32 led_ctrl;
408 s32 ret_val;
409
410 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
411 if (hw->mac_type == e1000_82542_rev2_0) {
412 e_dbg("Disabling MWI on 82542 rev 2.0\n");
413 e1000_pci_clear_mwi(hw);
414 }
415
416 /* Clear interrupt mask to stop board from generating interrupts */
417 e_dbg("Masking off all interrupts\n");
418 ew32(IMC, 0xffffffff);
419
420 /* Disable the Transmit and Receive units. Then delay to allow
421 * any pending transactions to complete before we hit the MAC with
422 * the global reset.
423 */
424 ew32(RCTL, 0);
425 ew32(TCTL, E1000_TCTL_PSP);
426 E1000_WRITE_FLUSH();
427
428 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
429 hw->tbi_compatibility_on = false;
430
431 /* Delay to allow any outstanding PCI transactions to complete before
432 * resetting the device
433 */
434 msleep(10);
435
436 ctrl = er32(CTRL);
437
438 /* Must reset the PHY before resetting the MAC */
439 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
440 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
441 E1000_WRITE_FLUSH();
442 msleep(5);
443 }
444
445 /* Issue a global reset to the MAC. This will reset the chip's
446 * transmit, receive, DMA, and link units. It will not effect
447 * the current PCI configuration. The global reset bit is self-
448 * clearing, and should clear within a microsecond.
449 */
450 e_dbg("Issuing a global reset to MAC\n");
451
452 switch (hw->mac_type) {
453 case e1000_82544:
454 case e1000_82540:
455 case e1000_82545:
456 case e1000_82546:
457 case e1000_82541:
458 case e1000_82541_rev_2:
459 /* These controllers can't ack the 64-bit write when issuing the
460 * reset, so use IO-mapping as a workaround to issue the reset
461 */
462 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
463 break;
464 case e1000_82545_rev_3:
465 case e1000_82546_rev_3:
466 /* Reset is performed on a shadow of the control register */
467 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
468 break;
469 case e1000_ce4100:
470 default:
471 ew32(CTRL, (ctrl | E1000_CTRL_RST));
472 break;
473 }
474
475 /* After MAC reset, force reload of EEPROM to restore power-on settings
476 * to device. Later controllers reload the EEPROM automatically, so
477 * just wait for reload to complete.
478 */
479 switch (hw->mac_type) {
480 case e1000_82542_rev2_0:
481 case e1000_82542_rev2_1:
482 case e1000_82543:
483 case e1000_82544:
484 /* Wait for reset to complete */
485 udelay(10);
486 ctrl_ext = er32(CTRL_EXT);
487 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
488 ew32(CTRL_EXT, ctrl_ext);
489 E1000_WRITE_FLUSH();
490 /* Wait for EEPROM reload */
491 msleep(2);
492 break;
493 case e1000_82541:
494 case e1000_82541_rev_2:
495 case e1000_82547:
496 case e1000_82547_rev_2:
497 /* Wait for EEPROM reload */
498 msleep(20);
499 break;
500 default:
501 /* Auto read done will delay 5ms or poll based on mac type */
502 ret_val = e1000_get_auto_rd_done(hw);
503 if (ret_val)
504 return ret_val;
505 break;
506 }
507
508 /* Disable HW ARPs on ASF enabled adapters */
509 if (hw->mac_type >= e1000_82540) {
510 manc = er32(MANC);
511 manc &= ~(E1000_MANC_ARP_EN);
512 ew32(MANC, manc);
513 }
514
515 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
516 e1000_phy_init_script(hw);
517
518 /* Configure activity LED after PHY reset */
519 led_ctrl = er32(LEDCTL);
520 led_ctrl &= IGP_ACTIVITY_LED_MASK;
521 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
522 ew32(LEDCTL, led_ctrl);
523 }
524
525 /* Clear interrupt mask to stop board from generating interrupts */
526 e_dbg("Masking off all interrupts\n");
527 ew32(IMC, 0xffffffff);
528
529 /* Clear any pending interrupt events. */
530 icr = er32(ICR);
531
532 /* If MWI was previously enabled, reenable it. */
533 if (hw->mac_type == e1000_82542_rev2_0) {
534 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
535 e1000_pci_set_mwi(hw);
536 }
537
538 return E1000_SUCCESS;
539}
540
541/**
542 * e1000_init_hw - Performs basic configuration of the adapter.
543 * @hw: Struct containing variables accessed by shared code
544 *
545 * Assumes that the controller has previously been reset and is in a
546 * post-reset uninitialized state. Initializes the receive address registers,
547 * multicast table, and VLAN filter table. Calls routines to setup link
548 * configuration and flow control settings. Clears all on-chip counters. Leaves
549 * the transmit and receive units disabled and uninitialized.
550 */
551s32 e1000_init_hw(struct e1000_hw *hw)
552{
553 u32 ctrl;
554 u32 i;
555 s32 ret_val;
556 u32 mta_size;
557 u32 ctrl_ext;
558
559 /* Initialize Identification LED */
560 ret_val = e1000_id_led_init(hw);
561 if (ret_val) {
562 e_dbg("Error Initializing Identification LED\n");
563 return ret_val;
564 }
565
566 /* Set the media type and TBI compatibility */
567 e1000_set_media_type(hw);
568
569 /* Disabling VLAN filtering. */
570 e_dbg("Initializing the IEEE VLAN\n");
571 if (hw->mac_type < e1000_82545_rev_3)
572 ew32(VET, 0);
573 e1000_clear_vfta(hw);
574
575 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
576 if (hw->mac_type == e1000_82542_rev2_0) {
577 e_dbg("Disabling MWI on 82542 rev 2.0\n");
578 e1000_pci_clear_mwi(hw);
579 ew32(RCTL, E1000_RCTL_RST);
580 E1000_WRITE_FLUSH();
581 msleep(5);
582 }
583
584 /* Setup the receive address. This involves initializing all of the
585 * Receive Address Registers (RARs 0 - 15).
586 */
587 e1000_init_rx_addrs(hw);
588
589 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
590 if (hw->mac_type == e1000_82542_rev2_0) {
591 ew32(RCTL, 0);
592 E1000_WRITE_FLUSH();
593 msleep(1);
594 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
595 e1000_pci_set_mwi(hw);
596 }
597
598 /* Zero out the Multicast HASH table */
599 e_dbg("Zeroing the MTA\n");
600 mta_size = E1000_MC_TBL_SIZE;
601 for (i = 0; i < mta_size; i++) {
602 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
603 /* use write flush to prevent Memory Write Block (MWB) from
604 * occurring when accessing our register space
605 */
606 E1000_WRITE_FLUSH();
607 }
608
609 /* Set the PCI priority bit correctly in the CTRL register. This
610 * determines if the adapter gives priority to receives, or if it
611 * gives equal priority to transmits and receives. Valid only on
612 * 82542 and 82543 silicon.
613 */
614 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
615 ctrl = er32(CTRL);
616 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
617 }
618
619 switch (hw->mac_type) {
620 case e1000_82545_rev_3:
621 case e1000_82546_rev_3:
622 break;
623 default:
624 /* Workaround for PCI-X problem when BIOS sets MMRBC
625 * incorrectly.
626 */
627 if (hw->bus_type == e1000_bus_type_pcix &&
628 e1000_pcix_get_mmrbc(hw) > 2048)
629 e1000_pcix_set_mmrbc(hw, 2048);
630 break;
631 }
632
633 /* Call a subroutine to configure the link and setup flow control. */
634 ret_val = e1000_setup_link(hw);
635
636 /* Set the transmit descriptor write-back policy */
637 if (hw->mac_type > e1000_82544) {
638 ctrl = er32(TXDCTL);
639 ctrl =
640 (ctrl & ~E1000_TXDCTL_WTHRESH) |
641 E1000_TXDCTL_FULL_TX_DESC_WB;
642 ew32(TXDCTL, ctrl);
643 }
644
645 /* Clear all of the statistics registers (clear on read). It is
646 * important that we do this after we have tried to establish link
647 * because the symbol error count will increment wildly if there
648 * is no link.
649 */
650 e1000_clear_hw_cntrs(hw);
651
652 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
653 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
654 ctrl_ext = er32(CTRL_EXT);
655 /* Relaxed ordering must be disabled to avoid a parity
656 * error crash in a PCI slot.
657 */
658 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
659 ew32(CTRL_EXT, ctrl_ext);
660 }
661
662 return ret_val;
663}
664
665/**
666 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
667 * @hw: Struct containing variables accessed by shared code.
668 */
669static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
670{
671 u16 eeprom_data;
672 s32 ret_val;
673
674 if (hw->media_type != e1000_media_type_internal_serdes)
675 return E1000_SUCCESS;
676
677 switch (hw->mac_type) {
678 case e1000_82545_rev_3:
679 case e1000_82546_rev_3:
680 break;
681 default:
682 return E1000_SUCCESS;
683 }
684
685 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
686 &eeprom_data);
687 if (ret_val)
688 return ret_val;
689
690 if (eeprom_data != EEPROM_RESERVED_WORD) {
691 /* Adjust SERDES output amplitude only. */
692 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
693 ret_val =
694 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
695 if (ret_val)
696 return ret_val;
697 }
698
699 return E1000_SUCCESS;
700}
701
702/**
703 * e1000_setup_link - Configures flow control and link settings.
704 * @hw: Struct containing variables accessed by shared code
705 *
706 * Determines which flow control settings to use. Calls the appropriate media-
707 * specific link configuration function. Configures the flow control settings.
708 * Assuming the adapter has a valid link partner, a valid link should be
709 * established. Assumes the hardware has previously been reset and the
710 * transmitter and receiver are not enabled.
711 */
712s32 e1000_setup_link(struct e1000_hw *hw)
713{
714 u32 ctrl_ext;
715 s32 ret_val;
716 u16 eeprom_data;
717
718 /* Read and store word 0x0F of the EEPROM. This word contains bits
719 * that determine the hardware's default PAUSE (flow control) mode,
720 * a bit that determines whether the HW defaults to enabling or
721 * disabling auto-negotiation, and the direction of the
722 * SW defined pins. If there is no SW over-ride of the flow
723 * control setting, then the variable hw->fc will
724 * be initialized based on a value in the EEPROM.
725 */
726 if (hw->fc == E1000_FC_DEFAULT) {
727 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
728 1, &eeprom_data);
729 if (ret_val) {
730 e_dbg("EEPROM Read Error\n");
731 return -E1000_ERR_EEPROM;
732 }
733 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
734 hw->fc = E1000_FC_NONE;
735 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
736 EEPROM_WORD0F_ASM_DIR)
737 hw->fc = E1000_FC_TX_PAUSE;
738 else
739 hw->fc = E1000_FC_FULL;
740 }
741
742 /* We want to save off the original Flow Control configuration just
743 * in case we get disconnected and then reconnected into a different
744 * hub or switch with different Flow Control capabilities.
745 */
746 if (hw->mac_type == e1000_82542_rev2_0)
747 hw->fc &= (~E1000_FC_TX_PAUSE);
748
749 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
750 hw->fc &= (~E1000_FC_RX_PAUSE);
751
752 hw->original_fc = hw->fc;
753
754 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
755
756 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
757 * polarity value for the SW controlled pins, and setup the
758 * Extended Device Control reg with that info.
759 * This is needed because one of the SW controlled pins is used for
760 * signal detection. So this should be done before e1000_setup_pcs_link()
761 * or e1000_phy_setup() is called.
762 */
763 if (hw->mac_type == e1000_82543) {
764 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
765 1, &eeprom_data);
766 if (ret_val) {
767 e_dbg("EEPROM Read Error\n");
768 return -E1000_ERR_EEPROM;
769 }
770 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
771 SWDPIO__EXT_SHIFT);
772 ew32(CTRL_EXT, ctrl_ext);
773 }
774
775 /* Call the necessary subroutine to configure the link. */
776 ret_val = (hw->media_type == e1000_media_type_copper) ?
777 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
778
779 /* Initialize the flow control address, type, and PAUSE timer
780 * registers to their default values. This is done even if flow
781 * control is disabled, because it does not hurt anything to
782 * initialize these registers.
783 */
784 e_dbg("Initializing the Flow Control address, type and timer regs\n");
785
786 ew32(FCT, FLOW_CONTROL_TYPE);
787 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
788 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
789
790 ew32(FCTTV, hw->fc_pause_time);
791
792 /* Set the flow control receive threshold registers. Normally,
793 * these registers will be set to a default threshold that may be
794 * adjusted later by the driver's runtime code. However, if the
795 * ability to transmit pause frames in not enabled, then these
796 * registers will be set to 0.
797 */
798 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
799 ew32(FCRTL, 0);
800 ew32(FCRTH, 0);
801 } else {
802 /* We need to set up the Receive Threshold high and low water
803 * marks as well as (optionally) enabling the transmission of
804 * XON frames.
805 */
806 if (hw->fc_send_xon) {
807 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
808 ew32(FCRTH, hw->fc_high_water);
809 } else {
810 ew32(FCRTL, hw->fc_low_water);
811 ew32(FCRTH, hw->fc_high_water);
812 }
813 }
814 return ret_val;
815}
816
817/**
818 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
819 * @hw: Struct containing variables accessed by shared code
820 *
821 * Manipulates Physical Coding Sublayer functions in order to configure
822 * link. Assumes the hardware has been previously reset and the transmitter
823 * and receiver are not enabled.
824 */
825static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
826{
827 u32 ctrl;
828 u32 status;
829 u32 txcw = 0;
830 u32 i;
831 u32 signal = 0;
832 s32 ret_val;
833
834 /* On adapters with a MAC newer than 82544, SWDP 1 will be
835 * set when the optics detect a signal. On older adapters, it will be
836 * cleared when there is a signal. This applies to fiber media only.
837 * If we're on serdes media, adjust the output amplitude to value
838 * set in the EEPROM.
839 */
840 ctrl = er32(CTRL);
841 if (hw->media_type == e1000_media_type_fiber)
842 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
843
844 ret_val = e1000_adjust_serdes_amplitude(hw);
845 if (ret_val)
846 return ret_val;
847
848 /* Take the link out of reset */
849 ctrl &= ~(E1000_CTRL_LRST);
850
851 /* Adjust VCO speed to improve BER performance */
852 ret_val = e1000_set_vco_speed(hw);
853 if (ret_val)
854 return ret_val;
855
856 e1000_config_collision_dist(hw);
857
858 /* Check for a software override of the flow control settings, and setup
859 * the device accordingly. If auto-negotiation is enabled, then
860 * software will have to set the "PAUSE" bits to the correct value in
861 * the Tranmsit Config Word Register (TXCW) and re-start
862 * auto-negotiation. However, if auto-negotiation is disabled, then
863 * software will have to manually configure the two flow control enable
864 * bits in the CTRL register.
865 *
866 * The possible values of the "fc" parameter are:
867 * 0: Flow control is completely disabled
868 * 1: Rx flow control is enabled (we can receive pause frames, but
869 * not send pause frames).
870 * 2: Tx flow control is enabled (we can send pause frames but we do
871 * not support receiving pause frames).
872 * 3: Both Rx and TX flow control (symmetric) are enabled.
873 */
874 switch (hw->fc) {
875 case E1000_FC_NONE:
876 /* Flow ctrl is completely disabled by a software over-ride */
877 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
878 break;
879 case E1000_FC_RX_PAUSE:
880 /* Rx Flow control is enabled and Tx Flow control is disabled by
881 * a software over-ride. Since there really isn't a way to
882 * advertise that we are capable of Rx Pause ONLY, we will
883 * advertise that we support both symmetric and asymmetric Rx
884 * PAUSE. Later, we will disable the adapter's ability to send
885 * PAUSE frames.
886 */
887 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
888 break;
889 case E1000_FC_TX_PAUSE:
890 /* Tx Flow control is enabled, and Rx Flow control is disabled,
891 * by a software over-ride.
892 */
893 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
894 break;
895 case E1000_FC_FULL:
896 /* Flow control (both Rx and Tx) is enabled by a software
897 * over-ride.
898 */
899 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
900 break;
901 default:
902 e_dbg("Flow control param set incorrectly\n");
903 return -E1000_ERR_CONFIG;
904 }
905
906 /* Since auto-negotiation is enabled, take the link out of reset (the
907 * link will be in reset, because we previously reset the chip). This
908 * will restart auto-negotiation. If auto-negotiation is successful
909 * then the link-up status bit will be set and the flow control enable
910 * bits (RFCE and TFCE) will be set according to their negotiated value.
911 */
912 e_dbg("Auto-negotiation enabled\n");
913
914 ew32(TXCW, txcw);
915 ew32(CTRL, ctrl);
916 E1000_WRITE_FLUSH();
917
918 hw->txcw = txcw;
919 msleep(1);
920
921 /* If we have a signal (the cable is plugged in) then poll for a
922 * "Link-Up" indication in the Device Status Register. Time-out if a
923 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should
924 * complete in less than 500 milliseconds even if the other end is doing
925 * it in SW). For internal serdes, we just assume a signal is present,
926 * then poll.
927 */
928 if (hw->media_type == e1000_media_type_internal_serdes ||
929 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
930 e_dbg("Looking for Link\n");
931 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
932 msleep(10);
933 status = er32(STATUS);
934 if (status & E1000_STATUS_LU)
935 break;
936 }
937 if (i == (LINK_UP_TIMEOUT / 10)) {
938 e_dbg("Never got a valid link from auto-neg!!!\n");
939 hw->autoneg_failed = 1;
940 /* AutoNeg failed to achieve a link, so we'll call
941 * e1000_check_for_link. This routine will force the
942 * link up if we detect a signal. This will allow us to
943 * communicate with non-autonegotiating link partners.
944 */
945 ret_val = e1000_check_for_link(hw);
946 if (ret_val) {
947 e_dbg("Error while checking for link\n");
948 return ret_val;
949 }
950 hw->autoneg_failed = 0;
951 } else {
952 hw->autoneg_failed = 0;
953 e_dbg("Valid Link Found\n");
954 }
955 } else {
956 e_dbg("No Signal Detected\n");
957 }
958 return E1000_SUCCESS;
959}
960
961/**
962 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
963 * @hw: Struct containing variables accessed by shared code
964 *
965 * Commits changes to PHY configuration by calling e1000_phy_reset().
966 */
967static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
968{
969 s32 ret_val;
970
971 /* SW reset the PHY so all changes take effect */
972 ret_val = e1000_phy_reset(hw);
973 if (ret_val) {
974 e_dbg("Error Resetting the PHY\n");
975 return ret_val;
976 }
977
978 return E1000_SUCCESS;
979}
980
981static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
982{
983 s32 ret_val;
984 u32 ctrl_aux;
985
986 switch (hw->phy_type) {
987 case e1000_phy_8211:
988 ret_val = e1000_copper_link_rtl_setup(hw);
989 if (ret_val) {
990 e_dbg("e1000_copper_link_rtl_setup failed!\n");
991 return ret_val;
992 }
993 break;
994 case e1000_phy_8201:
995 /* Set RMII mode */
996 ctrl_aux = er32(CTL_AUX);
997 ctrl_aux |= E1000_CTL_AUX_RMII;
998 ew32(CTL_AUX, ctrl_aux);
999 E1000_WRITE_FLUSH();
1000
1001 /* Disable the J/K bits required for receive */
1002 ctrl_aux = er32(CTL_AUX);
1003 ctrl_aux |= 0x4;
1004 ctrl_aux &= ~0x2;
1005 ew32(CTL_AUX, ctrl_aux);
1006 E1000_WRITE_FLUSH();
1007 ret_val = e1000_copper_link_rtl_setup(hw);
1008
1009 if (ret_val) {
1010 e_dbg("e1000_copper_link_rtl_setup failed!\n");
1011 return ret_val;
1012 }
1013 break;
1014 default:
1015 e_dbg("Error Resetting the PHY\n");
1016 return E1000_ERR_PHY_TYPE;
1017 }
1018
1019 return E1000_SUCCESS;
1020}
1021
1022/**
1023 * e1000_copper_link_preconfig - early configuration for copper
1024 * @hw: Struct containing variables accessed by shared code
1025 *
1026 * Make sure we have a valid PHY and change PHY mode before link setup.
1027 */
1028static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1029{
1030 u32 ctrl;
1031 s32 ret_val;
1032 u16 phy_data;
1033
1034 ctrl = er32(CTRL);
1035 /* With 82543, we need to force speed and duplex on the MAC equal to
1036 * what the PHY speed and duplex configuration is. In addition, we need
1037 * to perform a hardware reset on the PHY to take it out of reset.
1038 */
1039 if (hw->mac_type > e1000_82543) {
1040 ctrl |= E1000_CTRL_SLU;
1041 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1042 ew32(CTRL, ctrl);
1043 } else {
1044 ctrl |=
1045 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1046 ew32(CTRL, ctrl);
1047 ret_val = e1000_phy_hw_reset(hw);
1048 if (ret_val)
1049 return ret_val;
1050 }
1051
1052 /* Make sure we have a valid PHY */
1053 ret_val = e1000_detect_gig_phy(hw);
1054 if (ret_val) {
1055 e_dbg("Error, did not detect valid phy.\n");
1056 return ret_val;
1057 }
1058 e_dbg("Phy ID = %x\n", hw->phy_id);
1059
1060 /* Set PHY to class A mode (if necessary) */
1061 ret_val = e1000_set_phy_mode(hw);
1062 if (ret_val)
1063 return ret_val;
1064
1065 if ((hw->mac_type == e1000_82545_rev_3) ||
1066 (hw->mac_type == e1000_82546_rev_3)) {
1067 ret_val =
1068 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1069 phy_data |= 0x00000008;
1070 ret_val =
1071 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1072 }
1073
1074 if (hw->mac_type <= e1000_82543 ||
1075 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1076 hw->mac_type == e1000_82541_rev_2 ||
1077 hw->mac_type == e1000_82547_rev_2)
1078 hw->phy_reset_disable = false;
1079
1080 return E1000_SUCCESS;
1081}
1082
1083/**
1084 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1085 * @hw: Struct containing variables accessed by shared code
1086 */
1087static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1088{
1089 u32 led_ctrl;
1090 s32 ret_val;
1091 u16 phy_data;
1092
1093 if (hw->phy_reset_disable)
1094 return E1000_SUCCESS;
1095
1096 ret_val = e1000_phy_reset(hw);
1097 if (ret_val) {
1098 e_dbg("Error Resetting the PHY\n");
1099 return ret_val;
1100 }
1101
1102 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1103 msleep(15);
1104 /* Configure activity LED after PHY reset */
1105 led_ctrl = er32(LEDCTL);
1106 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1107 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1108 ew32(LEDCTL, led_ctrl);
1109
1110 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1111 if (hw->phy_type == e1000_phy_igp) {
1112 /* disable lplu d3 during driver init */
1113 ret_val = e1000_set_d3_lplu_state(hw, false);
1114 if (ret_val) {
1115 e_dbg("Error Disabling LPLU D3\n");
1116 return ret_val;
1117 }
1118 }
1119
1120 /* Configure mdi-mdix settings */
1121 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1122 if (ret_val)
1123 return ret_val;
1124
1125 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1126 hw->dsp_config_state = e1000_dsp_config_disabled;
1127 /* Force MDI for earlier revs of the IGP PHY */
1128 phy_data &=
1129 ~(IGP01E1000_PSCR_AUTO_MDIX |
1130 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1131 hw->mdix = 1;
1132
1133 } else {
1134 hw->dsp_config_state = e1000_dsp_config_enabled;
1135 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1136
1137 switch (hw->mdix) {
1138 case 1:
1139 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1140 break;
1141 case 2:
1142 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1143 break;
1144 case 0:
1145 default:
1146 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1147 break;
1148 }
1149 }
1150 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1151 if (ret_val)
1152 return ret_val;
1153
1154 /* set auto-master slave resolution settings */
1155 if (hw->autoneg) {
1156 e1000_ms_type phy_ms_setting = hw->master_slave;
1157
1158 if (hw->ffe_config_state == e1000_ffe_config_active)
1159 hw->ffe_config_state = e1000_ffe_config_enabled;
1160
1161 if (hw->dsp_config_state == e1000_dsp_config_activated)
1162 hw->dsp_config_state = e1000_dsp_config_enabled;
1163
1164 /* when autonegotiation advertisement is only 1000Mbps then we
1165 * should disable SmartSpeed and enable Auto MasterSlave
1166 * resolution as hardware default.
1167 */
1168 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1169 /* Disable SmartSpeed */
1170 ret_val =
1171 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1172 &phy_data);
1173 if (ret_val)
1174 return ret_val;
1175 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1176 ret_val =
1177 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1178 phy_data);
1179 if (ret_val)
1180 return ret_val;
1181 /* Set auto Master/Slave resolution process */
1182 ret_val =
1183 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1184 if (ret_val)
1185 return ret_val;
1186 phy_data &= ~CR_1000T_MS_ENABLE;
1187 ret_val =
1188 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1189 if (ret_val)
1190 return ret_val;
1191 }
1192
1193 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1194 if (ret_val)
1195 return ret_val;
1196
1197 /* load defaults for future use */
1198 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1199 ((phy_data & CR_1000T_MS_VALUE) ?
1200 e1000_ms_force_master :
1201 e1000_ms_force_slave) : e1000_ms_auto;
1202
1203 switch (phy_ms_setting) {
1204 case e1000_ms_force_master:
1205 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1206 break;
1207 case e1000_ms_force_slave:
1208 phy_data |= CR_1000T_MS_ENABLE;
1209 phy_data &= ~(CR_1000T_MS_VALUE);
1210 break;
1211 case e1000_ms_auto:
1212 phy_data &= ~CR_1000T_MS_ENABLE;
1213 default:
1214 break;
1215 }
1216 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1217 if (ret_val)
1218 return ret_val;
1219 }
1220
1221 return E1000_SUCCESS;
1222}
1223
1224/**
1225 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1226 * @hw: Struct containing variables accessed by shared code
1227 */
1228static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1229{
1230 s32 ret_val;
1231 u16 phy_data;
1232
1233 if (hw->phy_reset_disable)
1234 return E1000_SUCCESS;
1235
1236 /* Enable CRS on TX. This must be set for half-duplex operation. */
1237 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1238 if (ret_val)
1239 return ret_val;
1240
1241 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1242
1243 /* Options:
1244 * MDI/MDI-X = 0 (default)
1245 * 0 - Auto for all speeds
1246 * 1 - MDI mode
1247 * 2 - MDI-X mode
1248 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1249 */
1250 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1251
1252 switch (hw->mdix) {
1253 case 1:
1254 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1255 break;
1256 case 2:
1257 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1258 break;
1259 case 3:
1260 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1261 break;
1262 case 0:
1263 default:
1264 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1265 break;
1266 }
1267
1268 /* Options:
1269 * disable_polarity_correction = 0 (default)
1270 * Automatic Correction for Reversed Cable Polarity
1271 * 0 - Disabled
1272 * 1 - Enabled
1273 */
1274 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1275 if (hw->disable_polarity_correction == 1)
1276 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1277 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1278 if (ret_val)
1279 return ret_val;
1280
1281 if (hw->phy_revision < M88E1011_I_REV_4) {
1282 /* Force TX_CLK in the Extended PHY Specific Control Register
1283 * to 25MHz clock.
1284 */
1285 ret_val =
1286 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1287 &phy_data);
1288 if (ret_val)
1289 return ret_val;
1290
1291 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1292
1293 if ((hw->phy_revision == E1000_REVISION_2) &&
1294 (hw->phy_id == M88E1111_I_PHY_ID)) {
1295 /* Vidalia Phy, set the downshift counter to 5x */
1296 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1297 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1298 ret_val = e1000_write_phy_reg(hw,
1299 M88E1000_EXT_PHY_SPEC_CTRL,
1300 phy_data);
1301 if (ret_val)
1302 return ret_val;
1303 } else {
1304 /* Configure Master and Slave downshift values */
1305 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1306 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1307 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1308 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1309 ret_val = e1000_write_phy_reg(hw,
1310 M88E1000_EXT_PHY_SPEC_CTRL,
1311 phy_data);
1312 if (ret_val)
1313 return ret_val;
1314 }
1315 }
1316
1317 /* SW Reset the PHY so all changes take effect */
1318 ret_val = e1000_phy_reset(hw);
1319 if (ret_val) {
1320 e_dbg("Error Resetting the PHY\n");
1321 return ret_val;
1322 }
1323
1324 return E1000_SUCCESS;
1325}
1326
1327/**
1328 * e1000_copper_link_autoneg - setup auto-neg
1329 * @hw: Struct containing variables accessed by shared code
1330 *
1331 * Setup auto-negotiation and flow control advertisements,
1332 * and then perform auto-negotiation.
1333 */
1334static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1335{
1336 s32 ret_val;
1337 u16 phy_data;
1338
1339 /* Perform some bounds checking on the hw->autoneg_advertised
1340 * parameter. If this variable is zero, then set it to the default.
1341 */
1342 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1343
1344 /* If autoneg_advertised is zero, we assume it was not defaulted
1345 * by the calling code so we set to advertise full capability.
1346 */
1347 if (hw->autoneg_advertised == 0)
1348 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1349
1350 /* IFE/RTL8201N PHY only supports 10/100 */
1351 if (hw->phy_type == e1000_phy_8201)
1352 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1353
1354 e_dbg("Reconfiguring auto-neg advertisement params\n");
1355 ret_val = e1000_phy_setup_autoneg(hw);
1356 if (ret_val) {
1357 e_dbg("Error Setting up Auto-Negotiation\n");
1358 return ret_val;
1359 }
1360 e_dbg("Restarting Auto-Neg\n");
1361
1362 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1363 * the Auto Neg Restart bit in the PHY control register.
1364 */
1365 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1366 if (ret_val)
1367 return ret_val;
1368
1369 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1370 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1371 if (ret_val)
1372 return ret_val;
1373
1374 /* Does the user want to wait for Auto-Neg to complete here, or
1375 * check at a later time (for example, callback routine).
1376 */
1377 if (hw->wait_autoneg_complete) {
1378 ret_val = e1000_wait_autoneg(hw);
1379 if (ret_val) {
1380 e_dbg
1381 ("Error while waiting for autoneg to complete\n");
1382 return ret_val;
1383 }
1384 }
1385
1386 hw->get_link_status = true;
1387
1388 return E1000_SUCCESS;
1389}
1390
1391/**
1392 * e1000_copper_link_postconfig - post link setup
1393 * @hw: Struct containing variables accessed by shared code
1394 *
1395 * Config the MAC and the PHY after link is up.
1396 * 1) Set up the MAC to the current PHY speed/duplex
1397 * if we are on 82543. If we
1398 * are on newer silicon, we only need to configure
1399 * collision distance in the Transmit Control Register.
1400 * 2) Set up flow control on the MAC to that established with
1401 * the link partner.
1402 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1403 */
1404static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1405{
1406 s32 ret_val;
1407
1408 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1409 e1000_config_collision_dist(hw);
1410 } else {
1411 ret_val = e1000_config_mac_to_phy(hw);
1412 if (ret_val) {
1413 e_dbg("Error configuring MAC to PHY settings\n");
1414 return ret_val;
1415 }
1416 }
1417 ret_val = e1000_config_fc_after_link_up(hw);
1418 if (ret_val) {
1419 e_dbg("Error Configuring Flow Control\n");
1420 return ret_val;
1421 }
1422
1423 /* Config DSP to improve Giga link quality */
1424 if (hw->phy_type == e1000_phy_igp) {
1425 ret_val = e1000_config_dsp_after_link_change(hw, true);
1426 if (ret_val) {
1427 e_dbg("Error Configuring DSP after link up\n");
1428 return ret_val;
1429 }
1430 }
1431
1432 return E1000_SUCCESS;
1433}
1434
1435/**
1436 * e1000_setup_copper_link - phy/speed/duplex setting
1437 * @hw: Struct containing variables accessed by shared code
1438 *
1439 * Detects which PHY is present and sets up the speed and duplex
1440 */
1441static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1442{
1443 s32 ret_val;
1444 u16 i;
1445 u16 phy_data;
1446
1447 /* Check if it is a valid PHY and set PHY mode if necessary. */
1448 ret_val = e1000_copper_link_preconfig(hw);
1449 if (ret_val)
1450 return ret_val;
1451
1452 if (hw->phy_type == e1000_phy_igp) {
1453 ret_val = e1000_copper_link_igp_setup(hw);
1454 if (ret_val)
1455 return ret_val;
1456 } else if (hw->phy_type == e1000_phy_m88) {
1457 ret_val = e1000_copper_link_mgp_setup(hw);
1458 if (ret_val)
1459 return ret_val;
1460 } else {
1461 ret_val = gbe_dhg_phy_setup(hw);
1462 if (ret_val) {
1463 e_dbg("gbe_dhg_phy_setup failed!\n");
1464 return ret_val;
1465 }
1466 }
1467
1468 if (hw->autoneg) {
1469 /* Setup autoneg and flow control advertisement
1470 * and perform autonegotiation
1471 */
1472 ret_val = e1000_copper_link_autoneg(hw);
1473 if (ret_val)
1474 return ret_val;
1475 } else {
1476 /* PHY will be set to 10H, 10F, 100H,or 100F
1477 * depending on value from forced_speed_duplex.
1478 */
1479 e_dbg("Forcing speed and duplex\n");
1480 ret_val = e1000_phy_force_speed_duplex(hw);
1481 if (ret_val) {
1482 e_dbg("Error Forcing Speed and Duplex\n");
1483 return ret_val;
1484 }
1485 }
1486
1487 /* Check link status. Wait up to 100 microseconds for link to become
1488 * valid.
1489 */
1490 for (i = 0; i < 10; i++) {
1491 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1492 if (ret_val)
1493 return ret_val;
1494 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1495 if (ret_val)
1496 return ret_val;
1497
1498 if (phy_data & MII_SR_LINK_STATUS) {
1499 /* Config the MAC and PHY after link is up */
1500 ret_val = e1000_copper_link_postconfig(hw);
1501 if (ret_val)
1502 return ret_val;
1503
1504 e_dbg("Valid link established!!!\n");
1505 return E1000_SUCCESS;
1506 }
1507 udelay(10);
1508 }
1509
1510 e_dbg("Unable to establish link!!!\n");
1511 return E1000_SUCCESS;
1512}
1513
1514/**
1515 * e1000_phy_setup_autoneg - phy settings
1516 * @hw: Struct containing variables accessed by shared code
1517 *
1518 * Configures PHY autoneg and flow control advertisement settings
1519 */
1520s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1521{
1522 s32 ret_val;
1523 u16 mii_autoneg_adv_reg;
1524 u16 mii_1000t_ctrl_reg;
1525
1526 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1527 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1528 if (ret_val)
1529 return ret_val;
1530
1531 /* Read the MII 1000Base-T Control Register (Address 9). */
1532 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1533 if (ret_val)
1534 return ret_val;
1535 else if (hw->phy_type == e1000_phy_8201)
1536 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1537
1538 /* Need to parse both autoneg_advertised and fc and set up
1539 * the appropriate PHY registers. First we will parse for
1540 * autoneg_advertised software override. Since we can advertise
1541 * a plethora of combinations, we need to check each bit
1542 * individually.
1543 */
1544
1545 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1546 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1547 * the 1000Base-T Control Register (Address 9).
1548 */
1549 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1550 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1551
1552 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1553
1554 /* Do we want to advertise 10 Mb Half Duplex? */
1555 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1556 e_dbg("Advertise 10mb Half duplex\n");
1557 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1558 }
1559
1560 /* Do we want to advertise 10 Mb Full Duplex? */
1561 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1562 e_dbg("Advertise 10mb Full duplex\n");
1563 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1564 }
1565
1566 /* Do we want to advertise 100 Mb Half Duplex? */
1567 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1568 e_dbg("Advertise 100mb Half duplex\n");
1569 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1570 }
1571
1572 /* Do we want to advertise 100 Mb Full Duplex? */
1573 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1574 e_dbg("Advertise 100mb Full duplex\n");
1575 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1576 }
1577
1578 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1579 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1580 e_dbg
1581 ("Advertise 1000mb Half duplex requested, request denied!\n");
1582 }
1583
1584 /* Do we want to advertise 1000 Mb Full Duplex? */
1585 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1586 e_dbg("Advertise 1000mb Full duplex\n");
1587 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1588 }
1589
1590 /* Check for a software override of the flow control settings, and
1591 * setup the PHY advertisement registers accordingly. If
1592 * auto-negotiation is enabled, then software will have to set the
1593 * "PAUSE" bits to the correct value in the Auto-Negotiation
1594 * Advertisement Register (PHY_AUTONEG_ADV) and re-start
1595 * auto-negotiation.
1596 *
1597 * The possible values of the "fc" parameter are:
1598 * 0: Flow control is completely disabled
1599 * 1: Rx flow control is enabled (we can receive pause frames
1600 * but not send pause frames).
1601 * 2: Tx flow control is enabled (we can send pause frames
1602 * but we do not support receiving pause frames).
1603 * 3: Both Rx and TX flow control (symmetric) are enabled.
1604 * other: No software override. The flow control configuration
1605 * in the EEPROM is used.
1606 */
1607 switch (hw->fc) {
1608 case E1000_FC_NONE: /* 0 */
1609 /* Flow control (RX & TX) is completely disabled by a
1610 * software over-ride.
1611 */
1612 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1613 break;
1614 case E1000_FC_RX_PAUSE: /* 1 */
1615 /* RX Flow control is enabled, and TX Flow control is
1616 * disabled, by a software over-ride.
1617 */
1618 /* Since there really isn't a way to advertise that we are
1619 * capable of RX Pause ONLY, we will advertise that we
1620 * support both symmetric and asymmetric RX PAUSE. Later
1621 * (in e1000_config_fc_after_link_up) we will disable the
1622 * hw's ability to send PAUSE frames.
1623 */
1624 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1625 break;
1626 case E1000_FC_TX_PAUSE: /* 2 */
1627 /* TX Flow control is enabled, and RX Flow control is
1628 * disabled, by a software over-ride.
1629 */
1630 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1631 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1632 break;
1633 case E1000_FC_FULL: /* 3 */
1634 /* Flow control (both RX and TX) is enabled by a software
1635 * over-ride.
1636 */
1637 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1638 break;
1639 default:
1640 e_dbg("Flow control param set incorrectly\n");
1641 return -E1000_ERR_CONFIG;
1642 }
1643
1644 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1645 if (ret_val)
1646 return ret_val;
1647
1648 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1649
1650 if (hw->phy_type == e1000_phy_8201) {
1651 mii_1000t_ctrl_reg = 0;
1652 } else {
1653 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1654 mii_1000t_ctrl_reg);
1655 if (ret_val)
1656 return ret_val;
1657 }
1658
1659 return E1000_SUCCESS;
1660}
1661
1662/**
1663 * e1000_phy_force_speed_duplex - force link settings
1664 * @hw: Struct containing variables accessed by shared code
1665 *
1666 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1667 */
1668static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1669{
1670 u32 ctrl;
1671 s32 ret_val;
1672 u16 mii_ctrl_reg;
1673 u16 mii_status_reg;
1674 u16 phy_data;
1675 u16 i;
1676
1677 /* Turn off Flow control if we are forcing speed and duplex. */
1678 hw->fc = E1000_FC_NONE;
1679
1680 e_dbg("hw->fc = %d\n", hw->fc);
1681
1682 /* Read the Device Control Register. */
1683 ctrl = er32(CTRL);
1684
1685 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1686 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1687 ctrl &= ~(DEVICE_SPEED_MASK);
1688
1689 /* Clear the Auto Speed Detect Enable bit. */
1690 ctrl &= ~E1000_CTRL_ASDE;
1691
1692 /* Read the MII Control Register. */
1693 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1694 if (ret_val)
1695 return ret_val;
1696
1697 /* We need to disable autoneg in order to force link and duplex. */
1698
1699 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1700
1701 /* Are we forcing Full or Half Duplex? */
1702 if (hw->forced_speed_duplex == e1000_100_full ||
1703 hw->forced_speed_duplex == e1000_10_full) {
1704 /* We want to force full duplex so we SET the full duplex bits
1705 * in the Device and MII Control Registers.
1706 */
1707 ctrl |= E1000_CTRL_FD;
1708 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1709 e_dbg("Full Duplex\n");
1710 } else {
1711 /* We want to force half duplex so we CLEAR the full duplex bits
1712 * in the Device and MII Control Registers.
1713 */
1714 ctrl &= ~E1000_CTRL_FD;
1715 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1716 e_dbg("Half Duplex\n");
1717 }
1718
1719 /* Are we forcing 100Mbps??? */
1720 if (hw->forced_speed_duplex == e1000_100_full ||
1721 hw->forced_speed_duplex == e1000_100_half) {
1722 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1723 ctrl |= E1000_CTRL_SPD_100;
1724 mii_ctrl_reg |= MII_CR_SPEED_100;
1725 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1726 e_dbg("Forcing 100mb ");
1727 } else {
1728 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1729 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1730 mii_ctrl_reg |= MII_CR_SPEED_10;
1731 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1732 e_dbg("Forcing 10mb ");
1733 }
1734
1735 e1000_config_collision_dist(hw);
1736
1737 /* Write the configured values back to the Device Control Reg. */
1738 ew32(CTRL, ctrl);
1739
1740 if (hw->phy_type == e1000_phy_m88) {
1741 ret_val =
1742 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1743 if (ret_val)
1744 return ret_val;
1745
1746 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires
1747 * MDI forced whenever speed are duplex are forced.
1748 */
1749 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1750 ret_val =
1751 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1752 if (ret_val)
1753 return ret_val;
1754
1755 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1756
1757 /* Need to reset the PHY or these changes will be ignored */
1758 mii_ctrl_reg |= MII_CR_RESET;
1759
1760 /* Disable MDI-X support for 10/100 */
1761 } else {
1762 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1763 * forced whenever speed or duplex are forced.
1764 */
1765 ret_val =
1766 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1767 if (ret_val)
1768 return ret_val;
1769
1770 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1771 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1772
1773 ret_val =
1774 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1775 if (ret_val)
1776 return ret_val;
1777 }
1778
1779 /* Write back the modified PHY MII control register. */
1780 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1781 if (ret_val)
1782 return ret_val;
1783
1784 udelay(1);
1785
1786 /* The wait_autoneg_complete flag may be a little misleading here.
1787 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1788 * But we do want to delay for a period while forcing only so we
1789 * don't generate false No Link messages. So we will wait here
1790 * only if the user has set wait_autoneg_complete to 1, which is
1791 * the default.
1792 */
1793 if (hw->wait_autoneg_complete) {
1794 /* We will wait for autoneg to complete. */
1795 e_dbg("Waiting for forced speed/duplex link.\n");
1796 mii_status_reg = 0;
1797
1798 /* Wait for autoneg to complete or 4.5 seconds to expire */
1799 for (i = PHY_FORCE_TIME; i > 0; i--) {
1800 /* Read the MII Status Register and wait for Auto-Neg
1801 * Complete bit to be set.
1802 */
1803 ret_val =
1804 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1805 if (ret_val)
1806 return ret_val;
1807
1808 ret_val =
1809 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1810 if (ret_val)
1811 return ret_val;
1812
1813 if (mii_status_reg & MII_SR_LINK_STATUS)
1814 break;
1815 msleep(100);
1816 }
1817 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1818 /* We didn't get link. Reset the DSP and wait again
1819 * for link.
1820 */
1821 ret_val = e1000_phy_reset_dsp(hw);
1822 if (ret_val) {
1823 e_dbg("Error Resetting PHY DSP\n");
1824 return ret_val;
1825 }
1826 }
1827 /* This loop will early-out if the link condition has been
1828 * met
1829 */
1830 for (i = PHY_FORCE_TIME; i > 0; i--) {
1831 if (mii_status_reg & MII_SR_LINK_STATUS)
1832 break;
1833 msleep(100);
1834 /* Read the MII Status Register and wait for Auto-Neg
1835 * Complete bit to be set.
1836 */
1837 ret_val =
1838 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1839 if (ret_val)
1840 return ret_val;
1841
1842 ret_val =
1843 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1844 if (ret_val)
1845 return ret_val;
1846 }
1847 }
1848
1849 if (hw->phy_type == e1000_phy_m88) {
1850 /* Because we reset the PHY above, we need to re-force TX_CLK in
1851 * the Extended PHY Specific Control Register to 25MHz clock.
1852 * This value defaults back to a 2.5MHz clock when the PHY is
1853 * reset.
1854 */
1855 ret_val =
1856 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1857 &phy_data);
1858 if (ret_val)
1859 return ret_val;
1860
1861 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1862 ret_val =
1863 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1864 phy_data);
1865 if (ret_val)
1866 return ret_val;
1867
1868 /* In addition, because of the s/w reset above, we need to
1869 * enable CRS on Tx. This must be set for both full and half
1870 * duplex operation.
1871 */
1872 ret_val =
1873 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1874 if (ret_val)
1875 return ret_val;
1876
1877 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1878 ret_val =
1879 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1880 if (ret_val)
1881 return ret_val;
1882
1883 if ((hw->mac_type == e1000_82544 ||
1884 hw->mac_type == e1000_82543) &&
1885 (!hw->autoneg) &&
1886 (hw->forced_speed_duplex == e1000_10_full ||
1887 hw->forced_speed_duplex == e1000_10_half)) {
1888 ret_val = e1000_polarity_reversal_workaround(hw);
1889 if (ret_val)
1890 return ret_val;
1891 }
1892 }
1893 return E1000_SUCCESS;
1894}
1895
1896/**
1897 * e1000_config_collision_dist - set collision distance register
1898 * @hw: Struct containing variables accessed by shared code
1899 *
1900 * Sets the collision distance in the Transmit Control register.
1901 * Link should have been established previously. Reads the speed and duplex
1902 * information from the Device Status register.
1903 */
1904void e1000_config_collision_dist(struct e1000_hw *hw)
1905{
1906 u32 tctl, coll_dist;
1907
1908 if (hw->mac_type < e1000_82543)
1909 coll_dist = E1000_COLLISION_DISTANCE_82542;
1910 else
1911 coll_dist = E1000_COLLISION_DISTANCE;
1912
1913 tctl = er32(TCTL);
1914
1915 tctl &= ~E1000_TCTL_COLD;
1916 tctl |= coll_dist << E1000_COLD_SHIFT;
1917
1918 ew32(TCTL, tctl);
1919 E1000_WRITE_FLUSH();
1920}
1921
1922/**
1923 * e1000_config_mac_to_phy - sync phy and mac settings
1924 * @hw: Struct containing variables accessed by shared code
1925 * @mii_reg: data to write to the MII control register
1926 *
1927 * Sets MAC speed and duplex settings to reflect the those in the PHY
1928 * The contents of the PHY register containing the needed information need to
1929 * be passed in.
1930 */
1931static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1932{
1933 u32 ctrl;
1934 s32 ret_val;
1935 u16 phy_data;
1936
1937 /* 82544 or newer MAC, Auto Speed Detection takes care of
1938 * MAC speed/duplex configuration.
1939 */
1940 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1941 return E1000_SUCCESS;
1942
1943 /* Read the Device Control Register and set the bits to Force Speed
1944 * and Duplex.
1945 */
1946 ctrl = er32(CTRL);
1947 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1948 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1949
1950 switch (hw->phy_type) {
1951 case e1000_phy_8201:
1952 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1953 if (ret_val)
1954 return ret_val;
1955
1956 if (phy_data & RTL_PHY_CTRL_FD)
1957 ctrl |= E1000_CTRL_FD;
1958 else
1959 ctrl &= ~E1000_CTRL_FD;
1960
1961 if (phy_data & RTL_PHY_CTRL_SPD_100)
1962 ctrl |= E1000_CTRL_SPD_100;
1963 else
1964 ctrl |= E1000_CTRL_SPD_10;
1965
1966 e1000_config_collision_dist(hw);
1967 break;
1968 default:
1969 /* Set up duplex in the Device Control and Transmit Control
1970 * registers depending on negotiated values.
1971 */
1972 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1973 &phy_data);
1974 if (ret_val)
1975 return ret_val;
1976
1977 if (phy_data & M88E1000_PSSR_DPLX)
1978 ctrl |= E1000_CTRL_FD;
1979 else
1980 ctrl &= ~E1000_CTRL_FD;
1981
1982 e1000_config_collision_dist(hw);
1983
1984 /* Set up speed in the Device Control register depending on
1985 * negotiated values.
1986 */
1987 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1988 ctrl |= E1000_CTRL_SPD_1000;
1989 else if ((phy_data & M88E1000_PSSR_SPEED) ==
1990 M88E1000_PSSR_100MBS)
1991 ctrl |= E1000_CTRL_SPD_100;
1992 }
1993
1994 /* Write the configured values back to the Device Control Reg. */
1995 ew32(CTRL, ctrl);
1996 return E1000_SUCCESS;
1997}
1998
1999/**
2000 * e1000_force_mac_fc - force flow control settings
2001 * @hw: Struct containing variables accessed by shared code
2002 *
2003 * Forces the MAC's flow control settings.
2004 * Sets the TFCE and RFCE bits in the device control register to reflect
2005 * the adapter settings. TFCE and RFCE need to be explicitly set by
2006 * software when a Copper PHY is used because autonegotiation is managed
2007 * by the PHY rather than the MAC. Software must also configure these
2008 * bits when link is forced on a fiber connection.
2009 */
2010s32 e1000_force_mac_fc(struct e1000_hw *hw)
2011{
2012 u32 ctrl;
2013
2014 /* Get the current configuration of the Device Control Register */
2015 ctrl = er32(CTRL);
2016
2017 /* Because we didn't get link via the internal auto-negotiation
2018 * mechanism (we either forced link or we got link via PHY
2019 * auto-neg), we have to manually enable/disable transmit an
2020 * receive flow control.
2021 *
2022 * The "Case" statement below enables/disable flow control
2023 * according to the "hw->fc" parameter.
2024 *
2025 * The possible values of the "fc" parameter are:
2026 * 0: Flow control is completely disabled
2027 * 1: Rx flow control is enabled (we can receive pause
2028 * frames but not send pause frames).
2029 * 2: Tx flow control is enabled (we can send pause frames
2030 * frames but we do not receive pause frames).
2031 * 3: Both Rx and TX flow control (symmetric) is enabled.
2032 * other: No other values should be possible at this point.
2033 */
2034
2035 switch (hw->fc) {
2036 case E1000_FC_NONE:
2037 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2038 break;
2039 case E1000_FC_RX_PAUSE:
2040 ctrl &= (~E1000_CTRL_TFCE);
2041 ctrl |= E1000_CTRL_RFCE;
2042 break;
2043 case E1000_FC_TX_PAUSE:
2044 ctrl &= (~E1000_CTRL_RFCE);
2045 ctrl |= E1000_CTRL_TFCE;
2046 break;
2047 case E1000_FC_FULL:
2048 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2049 break;
2050 default:
2051 e_dbg("Flow control param set incorrectly\n");
2052 return -E1000_ERR_CONFIG;
2053 }
2054
2055 /* Disable TX Flow Control for 82542 (rev 2.0) */
2056 if (hw->mac_type == e1000_82542_rev2_0)
2057 ctrl &= (~E1000_CTRL_TFCE);
2058
2059 ew32(CTRL, ctrl);
2060 return E1000_SUCCESS;
2061}
2062
2063/**
2064 * e1000_config_fc_after_link_up - configure flow control after autoneg
2065 * @hw: Struct containing variables accessed by shared code
2066 *
2067 * Configures flow control settings after link is established
2068 * Should be called immediately after a valid link has been established.
2069 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2070 * and autonegotiation is enabled, the MAC flow control settings will be set
2071 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2072 * and RFCE bits will be automatically set to the negotiated flow control mode.
2073 */
2074static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2075{
2076 s32 ret_val;
2077 u16 mii_status_reg;
2078 u16 mii_nway_adv_reg;
2079 u16 mii_nway_lp_ability_reg;
2080 u16 speed;
2081 u16 duplex;
2082
2083 /* Check for the case where we have fiber media and auto-neg failed
2084 * so we had to force link. In this case, we need to force the
2085 * configuration of the MAC to match the "fc" parameter.
2086 */
2087 if (((hw->media_type == e1000_media_type_fiber) &&
2088 (hw->autoneg_failed)) ||
2089 ((hw->media_type == e1000_media_type_internal_serdes) &&
2090 (hw->autoneg_failed)) ||
2091 ((hw->media_type == e1000_media_type_copper) &&
2092 (!hw->autoneg))) {
2093 ret_val = e1000_force_mac_fc(hw);
2094 if (ret_val) {
2095 e_dbg("Error forcing flow control settings\n");
2096 return ret_val;
2097 }
2098 }
2099
2100 /* Check for the case where we have copper media and auto-neg is
2101 * enabled. In this case, we need to check and see if Auto-Neg
2102 * has completed, and if so, how the PHY and link partner has
2103 * flow control configured.
2104 */
2105 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2106 /* Read the MII Status Register and check to see if AutoNeg
2107 * has completed. We read this twice because this reg has
2108 * some "sticky" (latched) bits.
2109 */
2110 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2111 if (ret_val)
2112 return ret_val;
2113 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2114 if (ret_val)
2115 return ret_val;
2116
2117 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2118 /* The AutoNeg process has completed, so we now need to
2119 * read both the Auto Negotiation Advertisement Register
2120 * (Address 4) and the Auto_Negotiation Base Page
2121 * Ability Register (Address 5) to determine how flow
2122 * control was negotiated.
2123 */
2124 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2125 &mii_nway_adv_reg);
2126 if (ret_val)
2127 return ret_val;
2128 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2129 &mii_nway_lp_ability_reg);
2130 if (ret_val)
2131 return ret_val;
2132
2133 /* Two bits in the Auto Negotiation Advertisement
2134 * Register (Address 4) and two bits in the Auto
2135 * Negotiation Base Page Ability Register (Address 5)
2136 * determine flow control for both the PHY and the link
2137 * partner. The following table, taken out of the IEEE
2138 * 802.3ab/D6.0 dated March 25, 1999, describes these
2139 * PAUSE resolution bits and how flow control is
2140 * determined based upon these settings.
2141 * NOTE: DC = Don't Care
2142 *
2143 * LOCAL DEVICE | LINK PARTNER
2144 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2145 *-------|---------|-------|---------|------------------
2146 * 0 | 0 | DC | DC | E1000_FC_NONE
2147 * 0 | 1 | 0 | DC | E1000_FC_NONE
2148 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2149 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2150 * 1 | 0 | 0 | DC | E1000_FC_NONE
2151 * 1 | DC | 1 | DC | E1000_FC_FULL
2152 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2153 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2154 *
2155 */
2156 /* Are both PAUSE bits set to 1? If so, this implies
2157 * Symmetric Flow Control is enabled at both ends. The
2158 * ASM_DIR bits are irrelevant per the spec.
2159 *
2160 * For Symmetric Flow Control:
2161 *
2162 * LOCAL DEVICE | LINK PARTNER
2163 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2164 *-------|---------|-------|---------|------------------
2165 * 1 | DC | 1 | DC | E1000_FC_FULL
2166 *
2167 */
2168 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2169 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2170 /* Now we need to check if the user selected Rx
2171 * ONLY of pause frames. In this case, we had
2172 * to advertise FULL flow control because we
2173 * could not advertise Rx ONLY. Hence, we must
2174 * now check to see if we need to turn OFF the
2175 * TRANSMISSION of PAUSE frames.
2176 */
2177 if (hw->original_fc == E1000_FC_FULL) {
2178 hw->fc = E1000_FC_FULL;
2179 e_dbg("Flow Control = FULL.\n");
2180 } else {
2181 hw->fc = E1000_FC_RX_PAUSE;
2182 e_dbg
2183 ("Flow Control = RX PAUSE frames only.\n");
2184 }
2185 }
2186 /* For receiving PAUSE frames ONLY.
2187 *
2188 * LOCAL DEVICE | LINK PARTNER
2189 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2190 *-------|---------|-------|---------|------------------
2191 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2192 *
2193 */
2194 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2195 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2196 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2197 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2198 hw->fc = E1000_FC_TX_PAUSE;
2199 e_dbg
2200 ("Flow Control = TX PAUSE frames only.\n");
2201 }
2202 /* For transmitting PAUSE frames ONLY.
2203 *
2204 * LOCAL DEVICE | LINK PARTNER
2205 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2206 *-------|---------|-------|---------|------------------
2207 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2208 *
2209 */
2210 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2211 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2212 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2213 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2214 hw->fc = E1000_FC_RX_PAUSE;
2215 e_dbg
2216 ("Flow Control = RX PAUSE frames only.\n");
2217 }
2218 /* Per the IEEE spec, at this point flow control should
2219 * be disabled. However, we want to consider that we
2220 * could be connected to a legacy switch that doesn't
2221 * advertise desired flow control, but can be forced on
2222 * the link partner. So if we advertised no flow
2223 * control, that is what we will resolve to. If we
2224 * advertised some kind of receive capability (Rx Pause
2225 * Only or Full Flow Control) and the link partner
2226 * advertised none, we will configure ourselves to
2227 * enable Rx Flow Control only. We can do this safely
2228 * for two reasons: If the link partner really
2229 * didn't want flow control enabled, and we enable Rx,
2230 * no harm done since we won't be receiving any PAUSE
2231 * frames anyway. If the intent on the link partner was
2232 * to have flow control enabled, then by us enabling Rx
2233 * only, we can at least receive pause frames and
2234 * process them. This is a good idea because in most
2235 * cases, since we are predominantly a server NIC, more
2236 * times than not we will be asked to delay transmission
2237 * of packets than asking our link partner to pause
2238 * transmission of frames.
2239 */
2240 else if ((hw->original_fc == E1000_FC_NONE ||
2241 hw->original_fc == E1000_FC_TX_PAUSE) ||
2242 hw->fc_strict_ieee) {
2243 hw->fc = E1000_FC_NONE;
2244 e_dbg("Flow Control = NONE.\n");
2245 } else {
2246 hw->fc = E1000_FC_RX_PAUSE;
2247 e_dbg
2248 ("Flow Control = RX PAUSE frames only.\n");
2249 }
2250
2251 /* Now we need to do one last check... If we auto-
2252 * negotiated to HALF DUPLEX, flow control should not be
2253 * enabled per IEEE 802.3 spec.
2254 */
2255 ret_val =
2256 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2257 if (ret_val) {
2258 e_dbg
2259 ("Error getting link speed and duplex\n");
2260 return ret_val;
2261 }
2262
2263 if (duplex == HALF_DUPLEX)
2264 hw->fc = E1000_FC_NONE;
2265
2266 /* Now we call a subroutine to actually force the MAC
2267 * controller to use the correct flow control settings.
2268 */
2269 ret_val = e1000_force_mac_fc(hw);
2270 if (ret_val) {
2271 e_dbg
2272 ("Error forcing flow control settings\n");
2273 return ret_val;
2274 }
2275 } else {
2276 e_dbg
2277 ("Copper PHY and Auto Neg has not completed.\n");
2278 }
2279 }
2280 return E1000_SUCCESS;
2281}
2282
2283/**
2284 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2285 * @hw: pointer to the HW structure
2286 *
2287 * Checks for link up on the hardware. If link is not up and we have
2288 * a signal, then we need to force link up.
2289 */
2290static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2291{
2292 u32 rxcw;
2293 u32 ctrl;
2294 u32 status;
2295 s32 ret_val = E1000_SUCCESS;
2296
2297 ctrl = er32(CTRL);
2298 status = er32(STATUS);
2299 rxcw = er32(RXCW);
2300
2301 /* If we don't have link (auto-negotiation failed or link partner
2302 * cannot auto-negotiate), and our link partner is not trying to
2303 * auto-negotiate with us (we are receiving idles or data),
2304 * we need to force link up. We also need to give auto-negotiation
2305 * time to complete.
2306 */
2307 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2308 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2309 if (hw->autoneg_failed == 0) {
2310 hw->autoneg_failed = 1;
2311 goto out;
2312 }
2313 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2314
2315 /* Disable auto-negotiation in the TXCW register */
2316 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2317
2318 /* Force link-up and also force full-duplex. */
2319 ctrl = er32(CTRL);
2320 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2321 ew32(CTRL, ctrl);
2322
2323 /* Configure Flow Control after forcing link up. */
2324 ret_val = e1000_config_fc_after_link_up(hw);
2325 if (ret_val) {
2326 e_dbg("Error configuring flow control\n");
2327 goto out;
2328 }
2329 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2330 /* If we are forcing link and we are receiving /C/ ordered
2331 * sets, re-enable auto-negotiation in the TXCW register
2332 * and disable forced link in the Device Control register
2333 * in an attempt to auto-negotiate with our link partner.
2334 */
2335 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2336 ew32(TXCW, hw->txcw);
2337 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2338
2339 hw->serdes_has_link = true;
2340 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2341 /* If we force link for non-auto-negotiation switch, check
2342 * link status based on MAC synchronization for internal
2343 * serdes media type.
2344 */
2345 /* SYNCH bit and IV bit are sticky. */
2346 udelay(10);
2347 rxcw = er32(RXCW);
2348 if (rxcw & E1000_RXCW_SYNCH) {
2349 if (!(rxcw & E1000_RXCW_IV)) {
2350 hw->serdes_has_link = true;
2351 e_dbg("SERDES: Link up - forced.\n");
2352 }
2353 } else {
2354 hw->serdes_has_link = false;
2355 e_dbg("SERDES: Link down - force failed.\n");
2356 }
2357 }
2358
2359 if (E1000_TXCW_ANE & er32(TXCW)) {
2360 status = er32(STATUS);
2361 if (status & E1000_STATUS_LU) {
2362 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2363 udelay(10);
2364 rxcw = er32(RXCW);
2365 if (rxcw & E1000_RXCW_SYNCH) {
2366 if (!(rxcw & E1000_RXCW_IV)) {
2367 hw->serdes_has_link = true;
2368 e_dbg("SERDES: Link up - autoneg "
2369 "completed successfully.\n");
2370 } else {
2371 hw->serdes_has_link = false;
2372 e_dbg("SERDES: Link down - invalid"
2373 "codewords detected in autoneg.\n");
2374 }
2375 } else {
2376 hw->serdes_has_link = false;
2377 e_dbg("SERDES: Link down - no sync.\n");
2378 }
2379 } else {
2380 hw->serdes_has_link = false;
2381 e_dbg("SERDES: Link down - autoneg failed\n");
2382 }
2383 }
2384
2385 out:
2386 return ret_val;
2387}
2388
2389/**
2390 * e1000_check_for_link
2391 * @hw: Struct containing variables accessed by shared code
2392 *
2393 * Checks to see if the link status of the hardware has changed.
2394 * Called by any function that needs to check the link status of the adapter.
2395 */
2396s32 e1000_check_for_link(struct e1000_hw *hw)
2397{
2398 u32 rxcw = 0;
2399 u32 ctrl;
2400 u32 status;
2401 u32 rctl;
2402 u32 icr;
2403 u32 signal = 0;
2404 s32 ret_val;
2405 u16 phy_data;
2406
2407 ctrl = er32(CTRL);
2408 status = er32(STATUS);
2409
2410 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2411 * set when the optics detect a signal. On older adapters, it will be
2412 * cleared when there is a signal. This applies to fiber media only.
2413 */
2414 if ((hw->media_type == e1000_media_type_fiber) ||
2415 (hw->media_type == e1000_media_type_internal_serdes)) {
2416 rxcw = er32(RXCW);
2417
2418 if (hw->media_type == e1000_media_type_fiber) {
2419 signal =
2420 (hw->mac_type >
2421 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2422 if (status & E1000_STATUS_LU)
2423 hw->get_link_status = false;
2424 }
2425 }
2426
2427 /* If we have a copper PHY then we only want to go out to the PHY
2428 * registers to see if Auto-Neg has completed and/or if our link
2429 * status has changed. The get_link_status flag will be set if we
2430 * receive a Link Status Change interrupt or we have Rx Sequence
2431 * Errors.
2432 */
2433 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2434 /* First we want to see if the MII Status Register reports
2435 * link. If so, then we want to get the current speed/duplex
2436 * of the PHY.
2437 * Read the register twice since the link bit is sticky.
2438 */
2439 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2440 if (ret_val)
2441 return ret_val;
2442 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2443 if (ret_val)
2444 return ret_val;
2445
2446 if (phy_data & MII_SR_LINK_STATUS) {
2447 hw->get_link_status = false;
2448 /* Check if there was DownShift, must be checked
2449 * immediately after link-up
2450 */
2451 e1000_check_downshift(hw);
2452
2453 /* If we are on 82544 or 82543 silicon and speed/duplex
2454 * are forced to 10H or 10F, then we will implement the
2455 * polarity reversal workaround. We disable interrupts
2456 * first, and upon returning, place the devices
2457 * interrupt state to its previous value except for the
2458 * link status change interrupt which will
2459 * happen due to the execution of this workaround.
2460 */
2461
2462 if ((hw->mac_type == e1000_82544 ||
2463 hw->mac_type == e1000_82543) &&
2464 (!hw->autoneg) &&
2465 (hw->forced_speed_duplex == e1000_10_full ||
2466 hw->forced_speed_duplex == e1000_10_half)) {
2467 ew32(IMC, 0xffffffff);
2468 ret_val =
2469 e1000_polarity_reversal_workaround(hw);
2470 icr = er32(ICR);
2471 ew32(ICS, (icr & ~E1000_ICS_LSC));
2472 ew32(IMS, IMS_ENABLE_MASK);
2473 }
2474
2475 } else {
2476 /* No link detected */
2477 e1000_config_dsp_after_link_change(hw, false);
2478 return 0;
2479 }
2480
2481 /* If we are forcing speed/duplex, then we simply return since
2482 * we have already determined whether we have link or not.
2483 */
2484 if (!hw->autoneg)
2485 return -E1000_ERR_CONFIG;
2486
2487 /* optimize the dsp settings for the igp phy */
2488 e1000_config_dsp_after_link_change(hw, true);
2489
2490 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2491 * have Si on board that is 82544 or newer, Auto
2492 * Speed Detection takes care of MAC speed/duplex
2493 * configuration. So we only need to configure Collision
2494 * Distance in the MAC. Otherwise, we need to force
2495 * speed/duplex on the MAC to the current PHY speed/duplex
2496 * settings.
2497 */
2498 if ((hw->mac_type >= e1000_82544) &&
2499 (hw->mac_type != e1000_ce4100))
2500 e1000_config_collision_dist(hw);
2501 else {
2502 ret_val = e1000_config_mac_to_phy(hw);
2503 if (ret_val) {
2504 e_dbg
2505 ("Error configuring MAC to PHY settings\n");
2506 return ret_val;
2507 }
2508 }
2509
2510 /* Configure Flow Control now that Auto-Neg has completed.
2511 * First, we need to restore the desired flow control settings
2512 * because we may have had to re-autoneg with a different link
2513 * partner.
2514 */
2515 ret_val = e1000_config_fc_after_link_up(hw);
2516 if (ret_val) {
2517 e_dbg("Error configuring flow control\n");
2518 return ret_val;
2519 }
2520
2521 /* At this point we know that we are on copper and we have
2522 * auto-negotiated link. These are conditions for checking the
2523 * link partner capability register. We use the link speed to
2524 * determine if TBI compatibility needs to be turned on or off.
2525 * If the link is not at gigabit speed, then TBI compatibility
2526 * is not needed. If we are at gigabit speed, we turn on TBI
2527 * compatibility.
2528 */
2529 if (hw->tbi_compatibility_en) {
2530 u16 speed, duplex;
2531
2532 ret_val =
2533 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2534
2535 if (ret_val) {
2536 e_dbg
2537 ("Error getting link speed and duplex\n");
2538 return ret_val;
2539 }
2540 if (speed != SPEED_1000) {
2541 /* If link speed is not set to gigabit speed, we
2542 * do not need to enable TBI compatibility.
2543 */
2544 if (hw->tbi_compatibility_on) {
2545 /* If we previously were in the mode,
2546 * turn it off.
2547 */
2548 rctl = er32(RCTL);
2549 rctl &= ~E1000_RCTL_SBP;
2550 ew32(RCTL, rctl);
2551 hw->tbi_compatibility_on = false;
2552 }
2553 } else {
2554 /* If TBI compatibility is was previously off,
2555 * turn it on. For compatibility with a TBI link
2556 * partner, we will store bad packets. Some
2557 * frames have an additional byte on the end and
2558 * will look like CRC errors to to the hardware.
2559 */
2560 if (!hw->tbi_compatibility_on) {
2561 hw->tbi_compatibility_on = true;
2562 rctl = er32(RCTL);
2563 rctl |= E1000_RCTL_SBP;
2564 ew32(RCTL, rctl);
2565 }
2566 }
2567 }
2568 }
2569
2570 if ((hw->media_type == e1000_media_type_fiber) ||
2571 (hw->media_type == e1000_media_type_internal_serdes))
2572 e1000_check_for_serdes_link_generic(hw);
2573
2574 return E1000_SUCCESS;
2575}
2576
2577/**
2578 * e1000_get_speed_and_duplex
2579 * @hw: Struct containing variables accessed by shared code
2580 * @speed: Speed of the connection
2581 * @duplex: Duplex setting of the connection
2582 *
2583 * Detects the current speed and duplex settings of the hardware.
2584 */
2585s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2586{
2587 u32 status;
2588 s32 ret_val;
2589 u16 phy_data;
2590
2591 if (hw->mac_type >= e1000_82543) {
2592 status = er32(STATUS);
2593 if (status & E1000_STATUS_SPEED_1000) {
2594 *speed = SPEED_1000;
2595 e_dbg("1000 Mbs, ");
2596 } else if (status & E1000_STATUS_SPEED_100) {
2597 *speed = SPEED_100;
2598 e_dbg("100 Mbs, ");
2599 } else {
2600 *speed = SPEED_10;
2601 e_dbg("10 Mbs, ");
2602 }
2603
2604 if (status & E1000_STATUS_FD) {
2605 *duplex = FULL_DUPLEX;
2606 e_dbg("Full Duplex\n");
2607 } else {
2608 *duplex = HALF_DUPLEX;
2609 e_dbg(" Half Duplex\n");
2610 }
2611 } else {
2612 e_dbg("1000 Mbs, Full Duplex\n");
2613 *speed = SPEED_1000;
2614 *duplex = FULL_DUPLEX;
2615 }
2616
2617 /* IGP01 PHY may advertise full duplex operation after speed downgrade
2618 * even if it is operating at half duplex. Here we set the duplex
2619 * settings to match the duplex in the link partner's capabilities.
2620 */
2621 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2622 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2623 if (ret_val)
2624 return ret_val;
2625
2626 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2627 *duplex = HALF_DUPLEX;
2628 else {
2629 ret_val =
2630 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2631 if (ret_val)
2632 return ret_val;
2633 if ((*speed == SPEED_100 &&
2634 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2635 (*speed == SPEED_10 &&
2636 !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2637 *duplex = HALF_DUPLEX;
2638 }
2639 }
2640
2641 return E1000_SUCCESS;
2642}
2643
2644/**
2645 * e1000_wait_autoneg
2646 * @hw: Struct containing variables accessed by shared code
2647 *
2648 * Blocks until autoneg completes or times out (~4.5 seconds)
2649 */
2650static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2651{
2652 s32 ret_val;
2653 u16 i;
2654 u16 phy_data;
2655
2656 e_dbg("Waiting for Auto-Neg to complete.\n");
2657
2658 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2659 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2660 /* Read the MII Status Register and wait for Auto-Neg
2661 * Complete bit to be set.
2662 */
2663 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2664 if (ret_val)
2665 return ret_val;
2666 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2667 if (ret_val)
2668 return ret_val;
2669 if (phy_data & MII_SR_AUTONEG_COMPLETE)
2670 return E1000_SUCCESS;
2671
2672 msleep(100);
2673 }
2674 return E1000_SUCCESS;
2675}
2676
2677/**
2678 * e1000_raise_mdi_clk - Raises the Management Data Clock
2679 * @hw: Struct containing variables accessed by shared code
2680 * @ctrl: Device control register's current value
2681 */
2682static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2683{
2684 /* Raise the clock input to the Management Data Clock (by setting the
2685 * MDC bit), and then delay 10 microseconds.
2686 */
2687 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2688 E1000_WRITE_FLUSH();
2689 udelay(10);
2690}
2691
2692/**
2693 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2694 * @hw: Struct containing variables accessed by shared code
2695 * @ctrl: Device control register's current value
2696 */
2697static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2698{
2699 /* Lower the clock input to the Management Data Clock (by clearing the
2700 * MDC bit), and then delay 10 microseconds.
2701 */
2702 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2703 E1000_WRITE_FLUSH();
2704 udelay(10);
2705}
2706
2707/**
2708 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2709 * @hw: Struct containing variables accessed by shared code
2710 * @data: Data to send out to the PHY
2711 * @count: Number of bits to shift out
2712 *
2713 * Bits are shifted out in MSB to LSB order.
2714 */
2715static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2716{
2717 u32 ctrl;
2718 u32 mask;
2719
2720 /* We need to shift "count" number of bits out to the PHY. So, the value
2721 * in the "data" parameter will be shifted out to the PHY one bit at a
2722 * time. In order to do this, "data" must be broken down into bits.
2723 */
2724 mask = 0x01;
2725 mask <<= (count - 1);
2726
2727 ctrl = er32(CTRL);
2728
2729 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2730 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2731
2732 while (mask) {
2733 /* A "1" is shifted out to the PHY by setting the MDIO bit to
2734 * "1" and then raising and lowering the Management Data Clock.
2735 * A "0" is shifted out to the PHY by setting the MDIO bit to
2736 * "0" and then raising and lowering the clock.
2737 */
2738 if (data & mask)
2739 ctrl |= E1000_CTRL_MDIO;
2740 else
2741 ctrl &= ~E1000_CTRL_MDIO;
2742
2743 ew32(CTRL, ctrl);
2744 E1000_WRITE_FLUSH();
2745
2746 udelay(10);
2747
2748 e1000_raise_mdi_clk(hw, &ctrl);
2749 e1000_lower_mdi_clk(hw, &ctrl);
2750
2751 mask = mask >> 1;
2752 }
2753}
2754
2755/**
2756 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2757 * @hw: Struct containing variables accessed by shared code
2758 *
2759 * Bits are shifted in in MSB to LSB order.
2760 */
2761static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2762{
2763 u32 ctrl;
2764 u16 data = 0;
2765 u8 i;
2766
2767 /* In order to read a register from the PHY, we need to shift in a total
2768 * of 18 bits from the PHY. The first two bit (turnaround) times are
2769 * used to avoid contention on the MDIO pin when a read operation is
2770 * performed. These two bits are ignored by us and thrown away. Bits are
2771 * "shifted in" by raising the input to the Management Data Clock
2772 * (setting the MDC bit), and then reading the value of the MDIO bit.
2773 */
2774 ctrl = er32(CTRL);
2775
2776 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
2777 * input.
2778 */
2779 ctrl &= ~E1000_CTRL_MDIO_DIR;
2780 ctrl &= ~E1000_CTRL_MDIO;
2781
2782 ew32(CTRL, ctrl);
2783 E1000_WRITE_FLUSH();
2784
2785 /* Raise and Lower the clock before reading in the data. This accounts
2786 * for the turnaround bits. The first clock occurred when we clocked out
2787 * the last bit of the Register Address.
2788 */
2789 e1000_raise_mdi_clk(hw, &ctrl);
2790 e1000_lower_mdi_clk(hw, &ctrl);
2791
2792 for (data = 0, i = 0; i < 16; i++) {
2793 data = data << 1;
2794 e1000_raise_mdi_clk(hw, &ctrl);
2795 ctrl = er32(CTRL);
2796 /* Check to see if we shifted in a "1". */
2797 if (ctrl & E1000_CTRL_MDIO)
2798 data |= 1;
2799 e1000_lower_mdi_clk(hw, &ctrl);
2800 }
2801
2802 e1000_raise_mdi_clk(hw, &ctrl);
2803 e1000_lower_mdi_clk(hw, &ctrl);
2804
2805 return data;
2806}
2807
2808/**
2809 * e1000_read_phy_reg - read a phy register
2810 * @hw: Struct containing variables accessed by shared code
2811 * @reg_addr: address of the PHY register to read
2812 * @phy_data: pointer to the value on the PHY register
2813 *
2814 * Reads the value from a PHY register, if the value is on a specific non zero
2815 * page, sets the page first.
2816 */
2817s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2818{
2819 u32 ret_val;
2820 unsigned long flags;
2821
2822 spin_lock_irqsave(&e1000_phy_lock, flags);
2823
2824 if ((hw->phy_type == e1000_phy_igp) &&
2825 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2826 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2827 (u16) reg_addr);
2828 if (ret_val)
2829 goto out;
2830 }
2831
2832 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2833 phy_data);
2834out:
2835 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2836
2837 return ret_val;
2838}
2839
2840static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2841 u16 *phy_data)
2842{
2843 u32 i;
2844 u32 mdic = 0;
2845 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2846
2847 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2848 e_dbg("PHY Address %d is out of range\n", reg_addr);
2849 return -E1000_ERR_PARAM;
2850 }
2851
2852 if (hw->mac_type > e1000_82543) {
2853 /* Set up Op-code, Phy Address, and register address in the MDI
2854 * Control register. The MAC will take care of interfacing with
2855 * the PHY to retrieve the desired data.
2856 */
2857 if (hw->mac_type == e1000_ce4100) {
2858 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2859 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2860 (INTEL_CE_GBE_MDIC_OP_READ) |
2861 (INTEL_CE_GBE_MDIC_GO));
2862
2863 writel(mdic, E1000_MDIO_CMD);
2864
2865 /* Poll the ready bit to see if the MDI read
2866 * completed
2867 */
2868 for (i = 0; i < 64; i++) {
2869 udelay(50);
2870 mdic = readl(E1000_MDIO_CMD);
2871 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2872 break;
2873 }
2874
2875 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2876 e_dbg("MDI Read did not complete\n");
2877 return -E1000_ERR_PHY;
2878 }
2879
2880 mdic = readl(E1000_MDIO_STS);
2881 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2882 e_dbg("MDI Read Error\n");
2883 return -E1000_ERR_PHY;
2884 }
2885 *phy_data = (u16)mdic;
2886 } else {
2887 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2888 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2889 (E1000_MDIC_OP_READ));
2890
2891 ew32(MDIC, mdic);
2892
2893 /* Poll the ready bit to see if the MDI read
2894 * completed
2895 */
2896 for (i = 0; i < 64; i++) {
2897 udelay(50);
2898 mdic = er32(MDIC);
2899 if (mdic & E1000_MDIC_READY)
2900 break;
2901 }
2902 if (!(mdic & E1000_MDIC_READY)) {
2903 e_dbg("MDI Read did not complete\n");
2904 return -E1000_ERR_PHY;
2905 }
2906 if (mdic & E1000_MDIC_ERROR) {
2907 e_dbg("MDI Error\n");
2908 return -E1000_ERR_PHY;
2909 }
2910 *phy_data = (u16)mdic;
2911 }
2912 } else {
2913 /* We must first send a preamble through the MDIO pin to signal
2914 * the beginning of an MII instruction. This is done by sending
2915 * 32 consecutive "1" bits.
2916 */
2917 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2918
2919 /* Now combine the next few fields that are required for a read
2920 * operation. We use this method instead of calling the
2921 * e1000_shift_out_mdi_bits routine five different times. The
2922 * format of a MII read instruction consists of a shift out of
2923 * 14 bits and is defined as follows:
2924 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2925 * followed by a shift in of 18 bits. This first two bits
2926 * shifted in are TurnAround bits used to avoid contention on
2927 * the MDIO pin when a READ operation is performed. These two
2928 * bits are thrown away followed by a shift in of 16 bits which
2929 * contains the desired data.
2930 */
2931 mdic = ((reg_addr) | (phy_addr << 5) |
2932 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2933
2934 e1000_shift_out_mdi_bits(hw, mdic, 14);
2935
2936 /* Now that we've shifted out the read command to the MII, we
2937 * need to "shift in" the 16-bit value (18 total bits) of the
2938 * requested PHY register address.
2939 */
2940 *phy_data = e1000_shift_in_mdi_bits(hw);
2941 }
2942 return E1000_SUCCESS;
2943}
2944
2945/**
2946 * e1000_write_phy_reg - write a phy register
2947 *
2948 * @hw: Struct containing variables accessed by shared code
2949 * @reg_addr: address of the PHY register to write
2950 * @data: data to write to the PHY
2951 *
2952 * Writes a value to a PHY register
2953 */
2954s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2955{
2956 u32 ret_val;
2957 unsigned long flags;
2958
2959 spin_lock_irqsave(&e1000_phy_lock, flags);
2960
2961 if ((hw->phy_type == e1000_phy_igp) &&
2962 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2963 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2964 (u16)reg_addr);
2965 if (ret_val) {
2966 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2967 return ret_val;
2968 }
2969 }
2970
2971 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2972 phy_data);
2973 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2974
2975 return ret_val;
2976}
2977
2978static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2979 u16 phy_data)
2980{
2981 u32 i;
2982 u32 mdic = 0;
2983 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2984
2985 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2986 e_dbg("PHY Address %d is out of range\n", reg_addr);
2987 return -E1000_ERR_PARAM;
2988 }
2989
2990 if (hw->mac_type > e1000_82543) {
2991 /* Set up Op-code, Phy Address, register address, and data
2992 * intended for the PHY register in the MDI Control register.
2993 * The MAC will take care of interfacing with the PHY to send
2994 * the desired data.
2995 */
2996 if (hw->mac_type == e1000_ce4100) {
2997 mdic = (((u32)phy_data) |
2998 (reg_addr << E1000_MDIC_REG_SHIFT) |
2999 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3000 (INTEL_CE_GBE_MDIC_OP_WRITE) |
3001 (INTEL_CE_GBE_MDIC_GO));
3002
3003 writel(mdic, E1000_MDIO_CMD);
3004
3005 /* Poll the ready bit to see if the MDI read
3006 * completed
3007 */
3008 for (i = 0; i < 640; i++) {
3009 udelay(5);
3010 mdic = readl(E1000_MDIO_CMD);
3011 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
3012 break;
3013 }
3014 if (mdic & INTEL_CE_GBE_MDIC_GO) {
3015 e_dbg("MDI Write did not complete\n");
3016 return -E1000_ERR_PHY;
3017 }
3018 } else {
3019 mdic = (((u32)phy_data) |
3020 (reg_addr << E1000_MDIC_REG_SHIFT) |
3021 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3022 (E1000_MDIC_OP_WRITE));
3023
3024 ew32(MDIC, mdic);
3025
3026 /* Poll the ready bit to see if the MDI read
3027 * completed
3028 */
3029 for (i = 0; i < 641; i++) {
3030 udelay(5);
3031 mdic = er32(MDIC);
3032 if (mdic & E1000_MDIC_READY)
3033 break;
3034 }
3035 if (!(mdic & E1000_MDIC_READY)) {
3036 e_dbg("MDI Write did not complete\n");
3037 return -E1000_ERR_PHY;
3038 }
3039 }
3040 } else {
3041 /* We'll need to use the SW defined pins to shift the write
3042 * command out to the PHY. We first send a preamble to the PHY
3043 * to signal the beginning of the MII instruction. This is done
3044 * by sending 32 consecutive "1" bits.
3045 */
3046 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3047
3048 /* Now combine the remaining required fields that will indicate
3049 * a write operation. We use this method instead of calling the
3050 * e1000_shift_out_mdi_bits routine for each field in the
3051 * command. The format of a MII write instruction is as follows:
3052 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>.
3053 */
3054 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3055 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3056 mdic <<= 16;
3057 mdic |= (u32)phy_data;
3058
3059 e1000_shift_out_mdi_bits(hw, mdic, 32);
3060 }
3061
3062 return E1000_SUCCESS;
3063}
3064
3065/**
3066 * e1000_phy_hw_reset - reset the phy, hardware style
3067 * @hw: Struct containing variables accessed by shared code
3068 *
3069 * Returns the PHY to the power-on reset state
3070 */
3071s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3072{
3073 u32 ctrl, ctrl_ext;
3074 u32 led_ctrl;
3075
3076 e_dbg("Resetting Phy...\n");
3077
3078 if (hw->mac_type > e1000_82543) {
3079 /* Read the device control register and assert the
3080 * E1000_CTRL_PHY_RST bit. Then, take it out of reset.
3081 * For e1000 hardware, we delay for 10ms between the assert
3082 * and de-assert.
3083 */
3084 ctrl = er32(CTRL);
3085 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3086 E1000_WRITE_FLUSH();
3087
3088 msleep(10);
3089
3090 ew32(CTRL, ctrl);
3091 E1000_WRITE_FLUSH();
3092
3093 } else {
3094 /* Read the Extended Device Control Register, assert the
3095 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it
3096 * out of reset.
3097 */
3098 ctrl_ext = er32(CTRL_EXT);
3099 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3100 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3101 ew32(CTRL_EXT, ctrl_ext);
3102 E1000_WRITE_FLUSH();
3103 msleep(10);
3104 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3105 ew32(CTRL_EXT, ctrl_ext);
3106 E1000_WRITE_FLUSH();
3107 }
3108 udelay(150);
3109
3110 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3111 /* Configure activity LED after PHY reset */
3112 led_ctrl = er32(LEDCTL);
3113 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3114 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3115 ew32(LEDCTL, led_ctrl);
3116 }
3117
3118 /* Wait for FW to finish PHY configuration. */
3119 return e1000_get_phy_cfg_done(hw);
3120}
3121
3122/**
3123 * e1000_phy_reset - reset the phy to commit settings
3124 * @hw: Struct containing variables accessed by shared code
3125 *
3126 * Resets the PHY
3127 * Sets bit 15 of the MII Control register
3128 */
3129s32 e1000_phy_reset(struct e1000_hw *hw)
3130{
3131 s32 ret_val;
3132 u16 phy_data;
3133
3134 switch (hw->phy_type) {
3135 case e1000_phy_igp:
3136 ret_val = e1000_phy_hw_reset(hw);
3137 if (ret_val)
3138 return ret_val;
3139 break;
3140 default:
3141 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3142 if (ret_val)
3143 return ret_val;
3144
3145 phy_data |= MII_CR_RESET;
3146 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3147 if (ret_val)
3148 return ret_val;
3149
3150 udelay(1);
3151 break;
3152 }
3153
3154 if (hw->phy_type == e1000_phy_igp)
3155 e1000_phy_init_script(hw);
3156
3157 return E1000_SUCCESS;
3158}
3159
3160/**
3161 * e1000_detect_gig_phy - check the phy type
3162 * @hw: Struct containing variables accessed by shared code
3163 *
3164 * Probes the expected PHY address for known PHY IDs
3165 */
3166static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3167{
3168 s32 phy_init_status, ret_val;
3169 u16 phy_id_high, phy_id_low;
3170 bool match = false;
3171
3172 if (hw->phy_id != 0)
3173 return E1000_SUCCESS;
3174
3175 /* Read the PHY ID Registers to identify which PHY is onboard. */
3176 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3177 if (ret_val)
3178 return ret_val;
3179
3180 hw->phy_id = (u32)(phy_id_high << 16);
3181 udelay(20);
3182 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3183 if (ret_val)
3184 return ret_val;
3185
3186 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
3187 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
3188
3189 switch (hw->mac_type) {
3190 case e1000_82543:
3191 if (hw->phy_id == M88E1000_E_PHY_ID)
3192 match = true;
3193 break;
3194 case e1000_82544:
3195 if (hw->phy_id == M88E1000_I_PHY_ID)
3196 match = true;
3197 break;
3198 case e1000_82540:
3199 case e1000_82545:
3200 case e1000_82545_rev_3:
3201 case e1000_82546:
3202 case e1000_82546_rev_3:
3203 if (hw->phy_id == M88E1011_I_PHY_ID)
3204 match = true;
3205 break;
3206 case e1000_ce4100:
3207 if ((hw->phy_id == RTL8211B_PHY_ID) ||
3208 (hw->phy_id == RTL8201N_PHY_ID) ||
3209 (hw->phy_id == M88E1118_E_PHY_ID))
3210 match = true;
3211 break;
3212 case e1000_82541:
3213 case e1000_82541_rev_2:
3214 case e1000_82547:
3215 case e1000_82547_rev_2:
3216 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3217 match = true;
3218 break;
3219 default:
3220 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3221 return -E1000_ERR_CONFIG;
3222 }
3223 phy_init_status = e1000_set_phy_type(hw);
3224
3225 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3226 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3227 return E1000_SUCCESS;
3228 }
3229 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3230 return -E1000_ERR_PHY;
3231}
3232
3233/**
3234 * e1000_phy_reset_dsp - reset DSP
3235 * @hw: Struct containing variables accessed by shared code
3236 *
3237 * Resets the PHY's DSP
3238 */
3239static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3240{
3241 s32 ret_val;
3242
3243 do {
3244 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3245 if (ret_val)
3246 break;
3247 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3248 if (ret_val)
3249 break;
3250 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3251 if (ret_val)
3252 break;
3253 ret_val = E1000_SUCCESS;
3254 } while (0);
3255
3256 return ret_val;
3257}
3258
3259/**
3260 * e1000_phy_igp_get_info - get igp specific registers
3261 * @hw: Struct containing variables accessed by shared code
3262 * @phy_info: PHY information structure
3263 *
3264 * Get PHY information from various PHY registers for igp PHY only.
3265 */
3266static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3267 struct e1000_phy_info *phy_info)
3268{
3269 s32 ret_val;
3270 u16 phy_data, min_length, max_length, average;
3271 e1000_rev_polarity polarity;
3272
3273 /* The downshift status is checked only once, after link is established,
3274 * and it stored in the hw->speed_downgraded parameter.
3275 */
3276 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3277
3278 /* IGP01E1000 does not need to support it. */
3279 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3280
3281 /* IGP01E1000 always correct polarity reversal */
3282 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3283
3284 /* Check polarity status */
3285 ret_val = e1000_check_polarity(hw, &polarity);
3286 if (ret_val)
3287 return ret_val;
3288
3289 phy_info->cable_polarity = polarity;
3290
3291 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3292 if (ret_val)
3293 return ret_val;
3294
3295 phy_info->mdix_mode =
3296 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3297 IGP01E1000_PSSR_MDIX_SHIFT);
3298
3299 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3300 IGP01E1000_PSSR_SPEED_1000MBPS) {
3301 /* Local/Remote Receiver Information are only valid @ 1000
3302 * Mbps
3303 */
3304 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3305 if (ret_val)
3306 return ret_val;
3307
3308 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3309 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3310 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3311 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3312 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3313 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3314
3315 /* Get cable length */
3316 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3317 if (ret_val)
3318 return ret_val;
3319
3320 /* Translate to old method */
3321 average = (max_length + min_length) / 2;
3322
3323 if (average <= e1000_igp_cable_length_50)
3324 phy_info->cable_length = e1000_cable_length_50;
3325 else if (average <= e1000_igp_cable_length_80)
3326 phy_info->cable_length = e1000_cable_length_50_80;
3327 else if (average <= e1000_igp_cable_length_110)
3328 phy_info->cable_length = e1000_cable_length_80_110;
3329 else if (average <= e1000_igp_cable_length_140)
3330 phy_info->cable_length = e1000_cable_length_110_140;
3331 else
3332 phy_info->cable_length = e1000_cable_length_140;
3333 }
3334
3335 return E1000_SUCCESS;
3336}
3337
3338/**
3339 * e1000_phy_m88_get_info - get m88 specific registers
3340 * @hw: Struct containing variables accessed by shared code
3341 * @phy_info: PHY information structure
3342 *
3343 * Get PHY information from various PHY registers for m88 PHY only.
3344 */
3345static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3346 struct e1000_phy_info *phy_info)
3347{
3348 s32 ret_val;
3349 u16 phy_data;
3350 e1000_rev_polarity polarity;
3351
3352 /* The downshift status is checked only once, after link is established,
3353 * and it stored in the hw->speed_downgraded parameter.
3354 */
3355 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3356
3357 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3358 if (ret_val)
3359 return ret_val;
3360
3361 phy_info->extended_10bt_distance =
3362 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3363 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3364 e1000_10bt_ext_dist_enable_lower :
3365 e1000_10bt_ext_dist_enable_normal;
3366
3367 phy_info->polarity_correction =
3368 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3369 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3370 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3371
3372 /* Check polarity status */
3373 ret_val = e1000_check_polarity(hw, &polarity);
3374 if (ret_val)
3375 return ret_val;
3376 phy_info->cable_polarity = polarity;
3377
3378 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3379 if (ret_val)
3380 return ret_val;
3381
3382 phy_info->mdix_mode =
3383 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3384 M88E1000_PSSR_MDIX_SHIFT);
3385
3386 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3387 /* Cable Length Estimation and Local/Remote Receiver Information
3388 * are only valid at 1000 Mbps.
3389 */
3390 phy_info->cable_length =
3391 (e1000_cable_length) ((phy_data &
3392 M88E1000_PSSR_CABLE_LENGTH) >>
3393 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3394
3395 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3396 if (ret_val)
3397 return ret_val;
3398
3399 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3400 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3401 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3402 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3403 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3404 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3405 }
3406
3407 return E1000_SUCCESS;
3408}
3409
3410/**
3411 * e1000_phy_get_info - request phy info
3412 * @hw: Struct containing variables accessed by shared code
3413 * @phy_info: PHY information structure
3414 *
3415 * Get PHY information from various PHY registers
3416 */
3417s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3418{
3419 s32 ret_val;
3420 u16 phy_data;
3421
3422 phy_info->cable_length = e1000_cable_length_undefined;
3423 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3424 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3425 phy_info->downshift = e1000_downshift_undefined;
3426 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3427 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3428 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3429 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3430
3431 if (hw->media_type != e1000_media_type_copper) {
3432 e_dbg("PHY info is only valid for copper media\n");
3433 return -E1000_ERR_CONFIG;
3434 }
3435
3436 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3437 if (ret_val)
3438 return ret_val;
3439
3440 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3441 if (ret_val)
3442 return ret_val;
3443
3444 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3445 e_dbg("PHY info is only valid if link is up\n");
3446 return -E1000_ERR_CONFIG;
3447 }
3448
3449 if (hw->phy_type == e1000_phy_igp)
3450 return e1000_phy_igp_get_info(hw, phy_info);
3451 else if ((hw->phy_type == e1000_phy_8211) ||
3452 (hw->phy_type == e1000_phy_8201))
3453 return E1000_SUCCESS;
3454 else
3455 return e1000_phy_m88_get_info(hw, phy_info);
3456}
3457
3458s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3459{
3460 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3461 e_dbg("Invalid MDI setting detected\n");
3462 hw->mdix = 1;
3463 return -E1000_ERR_CONFIG;
3464 }
3465 return E1000_SUCCESS;
3466}
3467
3468/**
3469 * e1000_init_eeprom_params - initialize sw eeprom vars
3470 * @hw: Struct containing variables accessed by shared code
3471 *
3472 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3473 * is configured.
3474 */
3475s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3476{
3477 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3478 u32 eecd = er32(EECD);
3479 s32 ret_val = E1000_SUCCESS;
3480 u16 eeprom_size;
3481
3482 switch (hw->mac_type) {
3483 case e1000_82542_rev2_0:
3484 case e1000_82542_rev2_1:
3485 case e1000_82543:
3486 case e1000_82544:
3487 eeprom->type = e1000_eeprom_microwire;
3488 eeprom->word_size = 64;
3489 eeprom->opcode_bits = 3;
3490 eeprom->address_bits = 6;
3491 eeprom->delay_usec = 50;
3492 break;
3493 case e1000_82540:
3494 case e1000_82545:
3495 case e1000_82545_rev_3:
3496 case e1000_82546:
3497 case e1000_82546_rev_3:
3498 eeprom->type = e1000_eeprom_microwire;
3499 eeprom->opcode_bits = 3;
3500 eeprom->delay_usec = 50;
3501 if (eecd & E1000_EECD_SIZE) {
3502 eeprom->word_size = 256;
3503 eeprom->address_bits = 8;
3504 } else {
3505 eeprom->word_size = 64;
3506 eeprom->address_bits = 6;
3507 }
3508 break;
3509 case e1000_82541:
3510 case e1000_82541_rev_2:
3511 case e1000_82547:
3512 case e1000_82547_rev_2:
3513 if (eecd & E1000_EECD_TYPE) {
3514 eeprom->type = e1000_eeprom_spi;
3515 eeprom->opcode_bits = 8;
3516 eeprom->delay_usec = 1;
3517 if (eecd & E1000_EECD_ADDR_BITS) {
3518 eeprom->page_size = 32;
3519 eeprom->address_bits = 16;
3520 } else {
3521 eeprom->page_size = 8;
3522 eeprom->address_bits = 8;
3523 }
3524 } else {
3525 eeprom->type = e1000_eeprom_microwire;
3526 eeprom->opcode_bits = 3;
3527 eeprom->delay_usec = 50;
3528 if (eecd & E1000_EECD_ADDR_BITS) {
3529 eeprom->word_size = 256;
3530 eeprom->address_bits = 8;
3531 } else {
3532 eeprom->word_size = 64;
3533 eeprom->address_bits = 6;
3534 }
3535 }
3536 break;
3537 default:
3538 break;
3539 }
3540
3541 if (eeprom->type == e1000_eeprom_spi) {
3542 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes
3543 * 128B to 32KB (incremented by powers of 2).
3544 */
3545 /* Set to default value for initial eeprom read. */
3546 eeprom->word_size = 64;
3547 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3548 if (ret_val)
3549 return ret_val;
3550 eeprom_size =
3551 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3552 /* 256B eeprom size was not supported in earlier hardware, so we
3553 * bump eeprom_size up one to ensure that "1" (which maps to
3554 * 256B) is never the result used in the shifting logic below.
3555 */
3556 if (eeprom_size)
3557 eeprom_size++;
3558
3559 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3560 }
3561 return ret_val;
3562}
3563
3564/**
3565 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3566 * @hw: Struct containing variables accessed by shared code
3567 * @eecd: EECD's current value
3568 */
3569static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3570{
3571 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3572 * wait <delay> microseconds.
3573 */
3574 *eecd = *eecd | E1000_EECD_SK;
3575 ew32(EECD, *eecd);
3576 E1000_WRITE_FLUSH();
3577 udelay(hw->eeprom.delay_usec);
3578}
3579
3580/**
3581 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3582 * @hw: Struct containing variables accessed by shared code
3583 * @eecd: EECD's current value
3584 */
3585static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3586{
3587 /* Lower the clock input to the EEPROM (by clearing the SK bit), and
3588 * then wait 50 microseconds.
3589 */
3590 *eecd = *eecd & ~E1000_EECD_SK;
3591 ew32(EECD, *eecd);
3592 E1000_WRITE_FLUSH();
3593 udelay(hw->eeprom.delay_usec);
3594}
3595
3596/**
3597 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3598 * @hw: Struct containing variables accessed by shared code
3599 * @data: data to send to the EEPROM
3600 * @count: number of bits to shift out
3601 */
3602static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3603{
3604 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3605 u32 eecd;
3606 u32 mask;
3607
3608 /* We need to shift "count" bits out to the EEPROM. So, value in the
3609 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3610 * In order to do this, "data" must be broken down into bits.
3611 */
3612 mask = 0x01 << (count - 1);
3613 eecd = er32(EECD);
3614 if (eeprom->type == e1000_eeprom_microwire)
3615 eecd &= ~E1000_EECD_DO;
3616 else if (eeprom->type == e1000_eeprom_spi)
3617 eecd |= E1000_EECD_DO;
3618
3619 do {
3620 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a
3621 * "1", and then raising and then lowering the clock (the SK bit
3622 * controls the clock input to the EEPROM). A "0" is shifted
3623 * out to the EEPROM by setting "DI" to "0" and then raising and
3624 * then lowering the clock.
3625 */
3626 eecd &= ~E1000_EECD_DI;
3627
3628 if (data & mask)
3629 eecd |= E1000_EECD_DI;
3630
3631 ew32(EECD, eecd);
3632 E1000_WRITE_FLUSH();
3633
3634 udelay(eeprom->delay_usec);
3635
3636 e1000_raise_ee_clk(hw, &eecd);
3637 e1000_lower_ee_clk(hw, &eecd);
3638
3639 mask = mask >> 1;
3640
3641 } while (mask);
3642
3643 /* We leave the "DI" bit set to "0" when we leave this routine. */
3644 eecd &= ~E1000_EECD_DI;
3645 ew32(EECD, eecd);
3646}
3647
3648/**
3649 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3650 * @hw: Struct containing variables accessed by shared code
3651 * @count: number of bits to shift in
3652 */
3653static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3654{
3655 u32 eecd;
3656 u32 i;
3657 u16 data;
3658
3659 /* In order to read a register from the EEPROM, we need to shift 'count'
3660 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3661 * input to the EEPROM (setting the SK bit), and then reading the value
3662 * of the "DO" bit. During this "shifting in" process the "DI" bit
3663 * should always be clear.
3664 */
3665
3666 eecd = er32(EECD);
3667
3668 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3669 data = 0;
3670
3671 for (i = 0; i < count; i++) {
3672 data = data << 1;
3673 e1000_raise_ee_clk(hw, &eecd);
3674
3675 eecd = er32(EECD);
3676
3677 eecd &= ~(E1000_EECD_DI);
3678 if (eecd & E1000_EECD_DO)
3679 data |= 1;
3680
3681 e1000_lower_ee_clk(hw, &eecd);
3682 }
3683
3684 return data;
3685}
3686
3687/**
3688 * e1000_acquire_eeprom - Prepares EEPROM for access
3689 * @hw: Struct containing variables accessed by shared code
3690 *
3691 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3692 * function should be called before issuing a command to the EEPROM.
3693 */
3694static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3695{
3696 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3697 u32 eecd, i = 0;
3698
3699 eecd = er32(EECD);
3700
3701 /* Request EEPROM Access */
3702 if (hw->mac_type > e1000_82544) {
3703 eecd |= E1000_EECD_REQ;
3704 ew32(EECD, eecd);
3705 eecd = er32(EECD);
3706 while ((!(eecd & E1000_EECD_GNT)) &&
3707 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3708 i++;
3709 udelay(5);
3710 eecd = er32(EECD);
3711 }
3712 if (!(eecd & E1000_EECD_GNT)) {
3713 eecd &= ~E1000_EECD_REQ;
3714 ew32(EECD, eecd);
3715 e_dbg("Could not acquire EEPROM grant\n");
3716 return -E1000_ERR_EEPROM;
3717 }
3718 }
3719
3720 /* Setup EEPROM for Read/Write */
3721
3722 if (eeprom->type == e1000_eeprom_microwire) {
3723 /* Clear SK and DI */
3724 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3725 ew32(EECD, eecd);
3726
3727 /* Set CS */
3728 eecd |= E1000_EECD_CS;
3729 ew32(EECD, eecd);
3730 } else if (eeprom->type == e1000_eeprom_spi) {
3731 /* Clear SK and CS */
3732 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3733 ew32(EECD, eecd);
3734 E1000_WRITE_FLUSH();
3735 udelay(1);
3736 }
3737
3738 return E1000_SUCCESS;
3739}
3740
3741/**
3742 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3743 * @hw: Struct containing variables accessed by shared code
3744 */
3745static void e1000_standby_eeprom(struct e1000_hw *hw)
3746{
3747 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3748 u32 eecd;
3749
3750 eecd = er32(EECD);
3751
3752 if (eeprom->type == e1000_eeprom_microwire) {
3753 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3754 ew32(EECD, eecd);
3755 E1000_WRITE_FLUSH();
3756 udelay(eeprom->delay_usec);
3757
3758 /* Clock high */
3759 eecd |= E1000_EECD_SK;
3760 ew32(EECD, eecd);
3761 E1000_WRITE_FLUSH();
3762 udelay(eeprom->delay_usec);
3763
3764 /* Select EEPROM */
3765 eecd |= E1000_EECD_CS;
3766 ew32(EECD, eecd);
3767 E1000_WRITE_FLUSH();
3768 udelay(eeprom->delay_usec);
3769
3770 /* Clock low */
3771 eecd &= ~E1000_EECD_SK;
3772 ew32(EECD, eecd);
3773 E1000_WRITE_FLUSH();
3774 udelay(eeprom->delay_usec);
3775 } else if (eeprom->type == e1000_eeprom_spi) {
3776 /* Toggle CS to flush commands */
3777 eecd |= E1000_EECD_CS;
3778 ew32(EECD, eecd);
3779 E1000_WRITE_FLUSH();
3780 udelay(eeprom->delay_usec);
3781 eecd &= ~E1000_EECD_CS;
3782 ew32(EECD, eecd);
3783 E1000_WRITE_FLUSH();
3784 udelay(eeprom->delay_usec);
3785 }
3786}
3787
3788/**
3789 * e1000_release_eeprom - drop chip select
3790 * @hw: Struct containing variables accessed by shared code
3791 *
3792 * Terminates a command by inverting the EEPROM's chip select pin
3793 */
3794static void e1000_release_eeprom(struct e1000_hw *hw)
3795{
3796 u32 eecd;
3797
3798 eecd = er32(EECD);
3799
3800 if (hw->eeprom.type == e1000_eeprom_spi) {
3801 eecd |= E1000_EECD_CS; /* Pull CS high */
3802 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3803
3804 ew32(EECD, eecd);
3805 E1000_WRITE_FLUSH();
3806
3807 udelay(hw->eeprom.delay_usec);
3808 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3809 /* cleanup eeprom */
3810
3811 /* CS on Microwire is active-high */
3812 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3813
3814 ew32(EECD, eecd);
3815
3816 /* Rising edge of clock */
3817 eecd |= E1000_EECD_SK;
3818 ew32(EECD, eecd);
3819 E1000_WRITE_FLUSH();
3820 udelay(hw->eeprom.delay_usec);
3821
3822 /* Falling edge of clock */
3823 eecd &= ~E1000_EECD_SK;
3824 ew32(EECD, eecd);
3825 E1000_WRITE_FLUSH();
3826 udelay(hw->eeprom.delay_usec);
3827 }
3828
3829 /* Stop requesting EEPROM access */
3830 if (hw->mac_type > e1000_82544) {
3831 eecd &= ~E1000_EECD_REQ;
3832 ew32(EECD, eecd);
3833 }
3834}
3835
3836/**
3837 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3838 * @hw: Struct containing variables accessed by shared code
3839 */
3840static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3841{
3842 u16 retry_count = 0;
3843 u8 spi_stat_reg;
3844
3845 /* Read "Status Register" repeatedly until the LSB is cleared. The
3846 * EEPROM will signal that the command has been completed by clearing
3847 * bit 0 of the internal status register. If it's not cleared within
3848 * 5 milliseconds, then error out.
3849 */
3850 retry_count = 0;
3851 do {
3852 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3853 hw->eeprom.opcode_bits);
3854 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
3855 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3856 break;
3857
3858 udelay(5);
3859 retry_count += 5;
3860
3861 e1000_standby_eeprom(hw);
3862 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3863
3864 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3865 * only 0-5mSec on 5V devices)
3866 */
3867 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3868 e_dbg("SPI EEPROM Status error\n");
3869 return -E1000_ERR_EEPROM;
3870 }
3871
3872 return E1000_SUCCESS;
3873}
3874
3875/**
3876 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3877 * @hw: Struct containing variables accessed by shared code
3878 * @offset: offset of word in the EEPROM to read
3879 * @data: word read from the EEPROM
3880 * @words: number of words to read
3881 */
3882s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3883{
3884 s32 ret;
3885
3886 mutex_lock(&e1000_eeprom_lock);
3887 ret = e1000_do_read_eeprom(hw, offset, words, data);
3888 mutex_unlock(&e1000_eeprom_lock);
3889 return ret;
3890}
3891
3892static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3893 u16 *data)
3894{
3895 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3896 u32 i = 0;
3897
3898 if (hw->mac_type == e1000_ce4100) {
3899 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3900 data);
3901 return E1000_SUCCESS;
3902 }
3903
3904 /* A check for invalid values: offset too large, too many words, and
3905 * not enough words.
3906 */
3907 if ((offset >= eeprom->word_size) ||
3908 (words > eeprom->word_size - offset) ||
3909 (words == 0)) {
3910 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3911 "size = %d\n", offset, eeprom->word_size);
3912 return -E1000_ERR_EEPROM;
3913 }
3914
3915 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3916 * directly. In this case, we need to acquire the EEPROM so that
3917 * FW or other port software does not interrupt.
3918 */
3919 /* Prepare the EEPROM for bit-bang reading */
3920 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3921 return -E1000_ERR_EEPROM;
3922
3923 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3924 * acquired the EEPROM at this point, so any returns should release it
3925 */
3926 if (eeprom->type == e1000_eeprom_spi) {
3927 u16 word_in;
3928 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3929
3930 if (e1000_spi_eeprom_ready(hw)) {
3931 e1000_release_eeprom(hw);
3932 return -E1000_ERR_EEPROM;
3933 }
3934
3935 e1000_standby_eeprom(hw);
3936
3937 /* Some SPI eeproms use the 8th address bit embedded in the
3938 * opcode
3939 */
3940 if ((eeprom->address_bits == 8) && (offset >= 128))
3941 read_opcode |= EEPROM_A8_OPCODE_SPI;
3942
3943 /* Send the READ command (opcode + addr) */
3944 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3945 e1000_shift_out_ee_bits(hw, (u16)(offset * 2),
3946 eeprom->address_bits);
3947
3948 /* Read the data. The address of the eeprom internally
3949 * increments with each byte (spi) being read, saving on the
3950 * overhead of eeprom setup and tear-down. The address counter
3951 * will roll over if reading beyond the size of the eeprom, thus
3952 * allowing the entire memory to be read starting from any
3953 * offset.
3954 */
3955 for (i = 0; i < words; i++) {
3956 word_in = e1000_shift_in_ee_bits(hw, 16);
3957 data[i] = (word_in >> 8) | (word_in << 8);
3958 }
3959 } else if (eeprom->type == e1000_eeprom_microwire) {
3960 for (i = 0; i < words; i++) {
3961 /* Send the READ command (opcode + addr) */
3962 e1000_shift_out_ee_bits(hw,
3963 EEPROM_READ_OPCODE_MICROWIRE,
3964 eeprom->opcode_bits);
3965 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
3966 eeprom->address_bits);
3967
3968 /* Read the data. For microwire, each word requires the
3969 * overhead of eeprom setup and tear-down.
3970 */
3971 data[i] = e1000_shift_in_ee_bits(hw, 16);
3972 e1000_standby_eeprom(hw);
3973 cond_resched();
3974 }
3975 }
3976
3977 /* End this read operation */
3978 e1000_release_eeprom(hw);
3979
3980 return E1000_SUCCESS;
3981}
3982
3983/**
3984 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
3985 * @hw: Struct containing variables accessed by shared code
3986 *
3987 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3988 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3989 * valid.
3990 */
3991s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3992{
3993 u16 checksum = 0;
3994 u16 i, eeprom_data;
3995
3996 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3997 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3998 e_dbg("EEPROM Read Error\n");
3999 return -E1000_ERR_EEPROM;
4000 }
4001 checksum += eeprom_data;
4002 }
4003
4004#ifdef CONFIG_PARISC
4005 /* This is a signature and not a checksum on HP c8000 */
4006 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6))
4007 return E1000_SUCCESS;
4008
4009#endif
4010 if (checksum == (u16)EEPROM_SUM)
4011 return E1000_SUCCESS;
4012 else {
4013 e_dbg("EEPROM Checksum Invalid\n");
4014 return -E1000_ERR_EEPROM;
4015 }
4016}
4017
4018/**
4019 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
4020 * @hw: Struct containing variables accessed by shared code
4021 *
4022 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4023 * Writes the difference to word offset 63 of the EEPROM.
4024 */
4025s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4026{
4027 u16 checksum = 0;
4028 u16 i, eeprom_data;
4029
4030 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4031 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4032 e_dbg("EEPROM Read Error\n");
4033 return -E1000_ERR_EEPROM;
4034 }
4035 checksum += eeprom_data;
4036 }
4037 checksum = (u16)EEPROM_SUM - checksum;
4038 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4039 e_dbg("EEPROM Write Error\n");
4040 return -E1000_ERR_EEPROM;
4041 }
4042 return E1000_SUCCESS;
4043}
4044
4045/**
4046 * e1000_write_eeprom - write words to the different EEPROM types.
4047 * @hw: Struct containing variables accessed by shared code
4048 * @offset: offset within the EEPROM to be written to
4049 * @words: number of words to write
4050 * @data: 16 bit word to be written to the EEPROM
4051 *
4052 * If e1000_update_eeprom_checksum is not called after this function, the
4053 * EEPROM will most likely contain an invalid checksum.
4054 */
4055s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4056{
4057 s32 ret;
4058
4059 mutex_lock(&e1000_eeprom_lock);
4060 ret = e1000_do_write_eeprom(hw, offset, words, data);
4061 mutex_unlock(&e1000_eeprom_lock);
4062 return ret;
4063}
4064
4065static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4066 u16 *data)
4067{
4068 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4069 s32 status = 0;
4070
4071 if (hw->mac_type == e1000_ce4100) {
4072 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4073 data);
4074 return E1000_SUCCESS;
4075 }
4076
4077 /* A check for invalid values: offset too large, too many words, and
4078 * not enough words.
4079 */
4080 if ((offset >= eeprom->word_size) ||
4081 (words > eeprom->word_size - offset) ||
4082 (words == 0)) {
4083 e_dbg("\"words\" parameter out of bounds\n");
4084 return -E1000_ERR_EEPROM;
4085 }
4086
4087 /* Prepare the EEPROM for writing */
4088 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4089 return -E1000_ERR_EEPROM;
4090
4091 if (eeprom->type == e1000_eeprom_microwire) {
4092 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4093 } else {
4094 status = e1000_write_eeprom_spi(hw, offset, words, data);
4095 msleep(10);
4096 }
4097
4098 /* Done with writing */
4099 e1000_release_eeprom(hw);
4100
4101 return status;
4102}
4103
4104/**
4105 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
4106 * @hw: Struct containing variables accessed by shared code
4107 * @offset: offset within the EEPROM to be written to
4108 * @words: number of words to write
4109 * @data: pointer to array of 8 bit words to be written to the EEPROM
4110 */
4111static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4112 u16 *data)
4113{
4114 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4115 u16 widx = 0;
4116
4117 while (widx < words) {
4118 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4119
4120 if (e1000_spi_eeprom_ready(hw))
4121 return -E1000_ERR_EEPROM;
4122
4123 e1000_standby_eeprom(hw);
4124 cond_resched();
4125
4126 /* Send the WRITE ENABLE command (8 bit opcode ) */
4127 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4128 eeprom->opcode_bits);
4129
4130 e1000_standby_eeprom(hw);
4131
4132 /* Some SPI eeproms use the 8th address bit embedded in the
4133 * opcode
4134 */
4135 if ((eeprom->address_bits == 8) && (offset >= 128))
4136 write_opcode |= EEPROM_A8_OPCODE_SPI;
4137
4138 /* Send the Write command (8-bit opcode + addr) */
4139 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4140
4141 e1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2),
4142 eeprom->address_bits);
4143
4144 /* Send the data */
4145
4146 /* Loop to allow for up to whole page write (32 bytes) of
4147 * eeprom
4148 */
4149 while (widx < words) {
4150 u16 word_out = data[widx];
4151
4152 word_out = (word_out >> 8) | (word_out << 8);
4153 e1000_shift_out_ee_bits(hw, word_out, 16);
4154 widx++;
4155
4156 /* Some larger eeprom sizes are capable of a 32-byte
4157 * PAGE WRITE operation, while the smaller eeproms are
4158 * capable of an 8-byte PAGE WRITE operation. Break the
4159 * inner loop to pass new address
4160 */
4161 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4162 e1000_standby_eeprom(hw);
4163 break;
4164 }
4165 }
4166 }
4167
4168 return E1000_SUCCESS;
4169}
4170
4171/**
4172 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4173 * @hw: Struct containing variables accessed by shared code
4174 * @offset: offset within the EEPROM to be written to
4175 * @words: number of words to write
4176 * @data: pointer to array of 8 bit words to be written to the EEPROM
4177 */
4178static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4179 u16 words, u16 *data)
4180{
4181 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4182 u32 eecd;
4183 u16 words_written = 0;
4184 u16 i = 0;
4185
4186 /* Send the write enable command to the EEPROM (3-bit opcode plus
4187 * 6/8-bit dummy address beginning with 11). It's less work to include
4188 * the 11 of the dummy address as part of the opcode than it is to shift
4189 * it over the correct number of bits for the address. This puts the
4190 * EEPROM into write/erase mode.
4191 */
4192 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4193 (u16)(eeprom->opcode_bits + 2));
4194
4195 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4196
4197 /* Prepare the EEPROM */
4198 e1000_standby_eeprom(hw);
4199
4200 while (words_written < words) {
4201 /* Send the Write command (3-bit opcode + addr) */
4202 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4203 eeprom->opcode_bits);
4204
4205 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
4206 eeprom->address_bits);
4207
4208 /* Send the data */
4209 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4210
4211 /* Toggle the CS line. This in effect tells the EEPROM to
4212 * execute the previous command.
4213 */
4214 e1000_standby_eeprom(hw);
4215
4216 /* Read DO repeatedly until it is high (equal to '1'). The
4217 * EEPROM will signal that the command has been completed by
4218 * raising the DO signal. If DO does not go high in 10
4219 * milliseconds, then error out.
4220 */
4221 for (i = 0; i < 200; i++) {
4222 eecd = er32(EECD);
4223 if (eecd & E1000_EECD_DO)
4224 break;
4225 udelay(50);
4226 }
4227 if (i == 200) {
4228 e_dbg("EEPROM Write did not complete\n");
4229 return -E1000_ERR_EEPROM;
4230 }
4231
4232 /* Recover from write */
4233 e1000_standby_eeprom(hw);
4234 cond_resched();
4235
4236 words_written++;
4237 }
4238
4239 /* Send the write disable command to the EEPROM (3-bit opcode plus
4240 * 6/8-bit dummy address beginning with 10). It's less work to include
4241 * the 10 of the dummy address as part of the opcode than it is to shift
4242 * it over the correct number of bits for the address. This takes the
4243 * EEPROM out of write/erase mode.
4244 */
4245 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4246 (u16)(eeprom->opcode_bits + 2));
4247
4248 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4249
4250 return E1000_SUCCESS;
4251}
4252
4253/**
4254 * e1000_read_mac_addr - read the adapters MAC from eeprom
4255 * @hw: Struct containing variables accessed by shared code
4256 *
4257 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4258 * second function of dual function devices
4259 */
4260s32 e1000_read_mac_addr(struct e1000_hw *hw)
4261{
4262 u16 offset;
4263 u16 eeprom_data, i;
4264
4265 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4266 offset = i >> 1;
4267 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4268 e_dbg("EEPROM Read Error\n");
4269 return -E1000_ERR_EEPROM;
4270 }
4271 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
4272 hw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8);
4273 }
4274
4275 switch (hw->mac_type) {
4276 default:
4277 break;
4278 case e1000_82546:
4279 case e1000_82546_rev_3:
4280 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4281 hw->perm_mac_addr[5] ^= 0x01;
4282 break;
4283 }
4284
4285 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4286 hw->mac_addr[i] = hw->perm_mac_addr[i];
4287 return E1000_SUCCESS;
4288}
4289
4290/**
4291 * e1000_init_rx_addrs - Initializes receive address filters.
4292 * @hw: Struct containing variables accessed by shared code
4293 *
4294 * Places the MAC address in receive address register 0 and clears the rest
4295 * of the receive address registers. Clears the multicast table. Assumes
4296 * the receiver is in reset when the routine is called.
4297 */
4298static void e1000_init_rx_addrs(struct e1000_hw *hw)
4299{
4300 u32 i;
4301 u32 rar_num;
4302
4303 /* Setup the receive address. */
4304 e_dbg("Programming MAC Address into RAR[0]\n");
4305
4306 e1000_rar_set(hw, hw->mac_addr, 0);
4307
4308 rar_num = E1000_RAR_ENTRIES;
4309
4310 /* Zero out the other 15 receive addresses. */
4311 e_dbg("Clearing RAR[1-15]\n");
4312 for (i = 1; i < rar_num; i++) {
4313 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4314 E1000_WRITE_FLUSH();
4315 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4316 E1000_WRITE_FLUSH();
4317 }
4318}
4319
4320/**
4321 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4322 * @hw: Struct containing variables accessed by shared code
4323 * @mc_addr: the multicast address to hash
4324 */
4325u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4326{
4327 u32 hash_value = 0;
4328
4329 /* The portion of the address that is used for the hash table is
4330 * determined by the mc_filter_type setting.
4331 */
4332 switch (hw->mc_filter_type) {
4333 /* [0] [1] [2] [3] [4] [5]
4334 * 01 AA 00 12 34 56
4335 * LSB MSB
4336 */
4337 case 0:
4338 /* [47:36] i.e. 0x563 for above example address */
4339 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
4340 break;
4341 case 1:
4342 /* [46:35] i.e. 0xAC6 for above example address */
4343 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
4344 break;
4345 case 2:
4346 /* [45:34] i.e. 0x5D8 for above example address */
4347 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
4348 break;
4349 case 3:
4350 /* [43:32] i.e. 0x634 for above example address */
4351 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
4352 break;
4353 }
4354
4355 hash_value &= 0xFFF;
4356 return hash_value;
4357}
4358
4359/**
4360 * e1000_rar_set - Puts an ethernet address into a receive address register.
4361 * @hw: Struct containing variables accessed by shared code
4362 * @addr: Address to put into receive address register
4363 * @index: Receive address register to write
4364 */
4365void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4366{
4367 u32 rar_low, rar_high;
4368
4369 /* HW expects these in little endian so we reverse the byte order
4370 * from network order (big endian) to little endian
4371 */
4372 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
4373 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
4374 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
4375
4376 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4377 * unit hang.
4378 *
4379 * Description:
4380 * If there are any Rx frames queued up or otherwise present in the HW
4381 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4382 * hang. To work around this issue, we have to disable receives and
4383 * flush out all Rx frames before we enable RSS. To do so, we modify we
4384 * redirect all Rx traffic to manageability and then reset the HW.
4385 * This flushes away Rx frames, and (since the redirections to
4386 * manageability persists across resets) keeps new ones from coming in
4387 * while we work. Then, we clear the Address Valid AV bit for all MAC
4388 * addresses and undo the re-direction to manageability.
4389 * Now, frames are coming in again, but the MAC won't accept them, so
4390 * far so good. We now proceed to initialize RSS (if necessary) and
4391 * configure the Rx unit. Last, we re-enable the AV bits and continue
4392 * on our merry way.
4393 */
4394 switch (hw->mac_type) {
4395 default:
4396 /* Indicate to hardware the Address is Valid. */
4397 rar_high |= E1000_RAH_AV;
4398 break;
4399 }
4400
4401 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4402 E1000_WRITE_FLUSH();
4403 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4404 E1000_WRITE_FLUSH();
4405}
4406
4407/**
4408 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4409 * @hw: Struct containing variables accessed by shared code
4410 * @offset: Offset in VLAN filer table to write
4411 * @value: Value to write into VLAN filter table
4412 */
4413void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4414{
4415 u32 temp;
4416
4417 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4418 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4419 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4420 E1000_WRITE_FLUSH();
4421 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4422 E1000_WRITE_FLUSH();
4423 } else {
4424 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4425 E1000_WRITE_FLUSH();
4426 }
4427}
4428
4429/**
4430 * e1000_clear_vfta - Clears the VLAN filer table
4431 * @hw: Struct containing variables accessed by shared code
4432 */
4433static void e1000_clear_vfta(struct e1000_hw *hw)
4434{
4435 u32 offset;
4436 u32 vfta_value = 0;
4437 u32 vfta_offset = 0;
4438 u32 vfta_bit_in_reg = 0;
4439
4440 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4441 /* If the offset we want to clear is the same offset of the
4442 * manageability VLAN ID, then clear all bits except that of the
4443 * manageability unit
4444 */
4445 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4446 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4447 E1000_WRITE_FLUSH();
4448 }
4449}
4450
4451static s32 e1000_id_led_init(struct e1000_hw *hw)
4452{
4453 u32 ledctl;
4454 const u32 ledctl_mask = 0x000000FF;
4455 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4456 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4457 u16 eeprom_data, i, temp;
4458 const u16 led_mask = 0x0F;
4459
4460 if (hw->mac_type < e1000_82540) {
4461 /* Nothing to do */
4462 return E1000_SUCCESS;
4463 }
4464
4465 ledctl = er32(LEDCTL);
4466 hw->ledctl_default = ledctl;
4467 hw->ledctl_mode1 = hw->ledctl_default;
4468 hw->ledctl_mode2 = hw->ledctl_default;
4469
4470 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4471 e_dbg("EEPROM Read Error\n");
4472 return -E1000_ERR_EEPROM;
4473 }
4474
4475 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4476 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4477 eeprom_data = ID_LED_DEFAULT;
4478 }
4479
4480 for (i = 0; i < 4; i++) {
4481 temp = (eeprom_data >> (i << 2)) & led_mask;
4482 switch (temp) {
4483 case ID_LED_ON1_DEF2:
4484 case ID_LED_ON1_ON2:
4485 case ID_LED_ON1_OFF2:
4486 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4487 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4488 break;
4489 case ID_LED_OFF1_DEF2:
4490 case ID_LED_OFF1_ON2:
4491 case ID_LED_OFF1_OFF2:
4492 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4493 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4494 break;
4495 default:
4496 /* Do nothing */
4497 break;
4498 }
4499 switch (temp) {
4500 case ID_LED_DEF1_ON2:
4501 case ID_LED_ON1_ON2:
4502 case ID_LED_OFF1_ON2:
4503 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4504 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4505 break;
4506 case ID_LED_DEF1_OFF2:
4507 case ID_LED_ON1_OFF2:
4508 case ID_LED_OFF1_OFF2:
4509 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4510 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4511 break;
4512 default:
4513 /* Do nothing */
4514 break;
4515 }
4516 }
4517 return E1000_SUCCESS;
4518}
4519
4520/**
4521 * e1000_setup_led
4522 * @hw: Struct containing variables accessed by shared code
4523 *
4524 * Prepares SW controlable LED for use and saves the current state of the LED.
4525 */
4526s32 e1000_setup_led(struct e1000_hw *hw)
4527{
4528 u32 ledctl;
4529 s32 ret_val = E1000_SUCCESS;
4530
4531 switch (hw->mac_type) {
4532 case e1000_82542_rev2_0:
4533 case e1000_82542_rev2_1:
4534 case e1000_82543:
4535 case e1000_82544:
4536 /* No setup necessary */
4537 break;
4538 case e1000_82541:
4539 case e1000_82547:
4540 case e1000_82541_rev_2:
4541 case e1000_82547_rev_2:
4542 /* Turn off PHY Smart Power Down (if enabled) */
4543 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4544 &hw->phy_spd_default);
4545 if (ret_val)
4546 return ret_val;
4547 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4548 (u16)(hw->phy_spd_default &
4549 ~IGP01E1000_GMII_SPD));
4550 if (ret_val)
4551 return ret_val;
4552 /* Fall Through */
4553 default:
4554 if (hw->media_type == e1000_media_type_fiber) {
4555 ledctl = er32(LEDCTL);
4556 /* Save current LEDCTL settings */
4557 hw->ledctl_default = ledctl;
4558 /* Turn off LED0 */
4559 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4560 E1000_LEDCTL_LED0_BLINK |
4561 E1000_LEDCTL_LED0_MODE_MASK);
4562 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4563 E1000_LEDCTL_LED0_MODE_SHIFT);
4564 ew32(LEDCTL, ledctl);
4565 } else if (hw->media_type == e1000_media_type_copper)
4566 ew32(LEDCTL, hw->ledctl_mode1);
4567 break;
4568 }
4569
4570 return E1000_SUCCESS;
4571}
4572
4573/**
4574 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4575 * @hw: Struct containing variables accessed by shared code
4576 */
4577s32 e1000_cleanup_led(struct e1000_hw *hw)
4578{
4579 s32 ret_val = E1000_SUCCESS;
4580
4581 switch (hw->mac_type) {
4582 case e1000_82542_rev2_0:
4583 case e1000_82542_rev2_1:
4584 case e1000_82543:
4585 case e1000_82544:
4586 /* No cleanup necessary */
4587 break;
4588 case e1000_82541:
4589 case e1000_82547:
4590 case e1000_82541_rev_2:
4591 case e1000_82547_rev_2:
4592 /* Turn on PHY Smart Power Down (if previously enabled) */
4593 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4594 hw->phy_spd_default);
4595 if (ret_val)
4596 return ret_val;
4597 /* Fall Through */
4598 default:
4599 /* Restore LEDCTL settings */
4600 ew32(LEDCTL, hw->ledctl_default);
4601 break;
4602 }
4603
4604 return E1000_SUCCESS;
4605}
4606
4607/**
4608 * e1000_led_on - Turns on the software controllable LED
4609 * @hw: Struct containing variables accessed by shared code
4610 */
4611s32 e1000_led_on(struct e1000_hw *hw)
4612{
4613 u32 ctrl = er32(CTRL);
4614
4615 switch (hw->mac_type) {
4616 case e1000_82542_rev2_0:
4617 case e1000_82542_rev2_1:
4618 case e1000_82543:
4619 /* Set SW Defineable Pin 0 to turn on the LED */
4620 ctrl |= E1000_CTRL_SWDPIN0;
4621 ctrl |= E1000_CTRL_SWDPIO0;
4622 break;
4623 case e1000_82544:
4624 if (hw->media_type == e1000_media_type_fiber) {
4625 /* Set SW Defineable Pin 0 to turn on the LED */
4626 ctrl |= E1000_CTRL_SWDPIN0;
4627 ctrl |= E1000_CTRL_SWDPIO0;
4628 } else {
4629 /* Clear SW Defineable Pin 0 to turn on the LED */
4630 ctrl &= ~E1000_CTRL_SWDPIN0;
4631 ctrl |= E1000_CTRL_SWDPIO0;
4632 }
4633 break;
4634 default:
4635 if (hw->media_type == e1000_media_type_fiber) {
4636 /* Clear SW Defineable Pin 0 to turn on the LED */
4637 ctrl &= ~E1000_CTRL_SWDPIN0;
4638 ctrl |= E1000_CTRL_SWDPIO0;
4639 } else if (hw->media_type == e1000_media_type_copper) {
4640 ew32(LEDCTL, hw->ledctl_mode2);
4641 return E1000_SUCCESS;
4642 }
4643 break;
4644 }
4645
4646 ew32(CTRL, ctrl);
4647
4648 return E1000_SUCCESS;
4649}
4650
4651/**
4652 * e1000_led_off - Turns off the software controllable LED
4653 * @hw: Struct containing variables accessed by shared code
4654 */
4655s32 e1000_led_off(struct e1000_hw *hw)
4656{
4657 u32 ctrl = er32(CTRL);
4658
4659 switch (hw->mac_type) {
4660 case e1000_82542_rev2_0:
4661 case e1000_82542_rev2_1:
4662 case e1000_82543:
4663 /* Clear SW Defineable Pin 0 to turn off the LED */
4664 ctrl &= ~E1000_CTRL_SWDPIN0;
4665 ctrl |= E1000_CTRL_SWDPIO0;
4666 break;
4667 case e1000_82544:
4668 if (hw->media_type == e1000_media_type_fiber) {
4669 /* Clear SW Defineable Pin 0 to turn off the LED */
4670 ctrl &= ~E1000_CTRL_SWDPIN0;
4671 ctrl |= E1000_CTRL_SWDPIO0;
4672 } else {
4673 /* Set SW Defineable Pin 0 to turn off the LED */
4674 ctrl |= E1000_CTRL_SWDPIN0;
4675 ctrl |= E1000_CTRL_SWDPIO0;
4676 }
4677 break;
4678 default:
4679 if (hw->media_type == e1000_media_type_fiber) {
4680 /* Set SW Defineable Pin 0 to turn off the LED */
4681 ctrl |= E1000_CTRL_SWDPIN0;
4682 ctrl |= E1000_CTRL_SWDPIO0;
4683 } else if (hw->media_type == e1000_media_type_copper) {
4684 ew32(LEDCTL, hw->ledctl_mode1);
4685 return E1000_SUCCESS;
4686 }
4687 break;
4688 }
4689
4690 ew32(CTRL, ctrl);
4691
4692 return E1000_SUCCESS;
4693}
4694
4695/**
4696 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4697 * @hw: Struct containing variables accessed by shared code
4698 */
4699static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4700{
4701 volatile u32 temp;
4702
4703 temp = er32(CRCERRS);
4704 temp = er32(SYMERRS);
4705 temp = er32(MPC);
4706 temp = er32(SCC);
4707 temp = er32(ECOL);
4708 temp = er32(MCC);
4709 temp = er32(LATECOL);
4710 temp = er32(COLC);
4711 temp = er32(DC);
4712 temp = er32(SEC);
4713 temp = er32(RLEC);
4714 temp = er32(XONRXC);
4715 temp = er32(XONTXC);
4716 temp = er32(XOFFRXC);
4717 temp = er32(XOFFTXC);
4718 temp = er32(FCRUC);
4719
4720 temp = er32(PRC64);
4721 temp = er32(PRC127);
4722 temp = er32(PRC255);
4723 temp = er32(PRC511);
4724 temp = er32(PRC1023);
4725 temp = er32(PRC1522);
4726
4727 temp = er32(GPRC);
4728 temp = er32(BPRC);
4729 temp = er32(MPRC);
4730 temp = er32(GPTC);
4731 temp = er32(GORCL);
4732 temp = er32(GORCH);
4733 temp = er32(GOTCL);
4734 temp = er32(GOTCH);
4735 temp = er32(RNBC);
4736 temp = er32(RUC);
4737 temp = er32(RFC);
4738 temp = er32(ROC);
4739 temp = er32(RJC);
4740 temp = er32(TORL);
4741 temp = er32(TORH);
4742 temp = er32(TOTL);
4743 temp = er32(TOTH);
4744 temp = er32(TPR);
4745 temp = er32(TPT);
4746
4747 temp = er32(PTC64);
4748 temp = er32(PTC127);
4749 temp = er32(PTC255);
4750 temp = er32(PTC511);
4751 temp = er32(PTC1023);
4752 temp = er32(PTC1522);
4753
4754 temp = er32(MPTC);
4755 temp = er32(BPTC);
4756
4757 if (hw->mac_type < e1000_82543)
4758 return;
4759
4760 temp = er32(ALGNERRC);
4761 temp = er32(RXERRC);
4762 temp = er32(TNCRS);
4763 temp = er32(CEXTERR);
4764 temp = er32(TSCTC);
4765 temp = er32(TSCTFC);
4766
4767 if (hw->mac_type <= e1000_82544)
4768 return;
4769
4770 temp = er32(MGTPRC);
4771 temp = er32(MGTPDC);
4772 temp = er32(MGTPTC);
4773}
4774
4775/**
4776 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4777 * @hw: Struct containing variables accessed by shared code
4778 *
4779 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4780 * hw->ifs_params_forced to true. However, you must initialize hw->
4781 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4782 * before calling this function.
4783 */
4784void e1000_reset_adaptive(struct e1000_hw *hw)
4785{
4786 if (hw->adaptive_ifs) {
4787 if (!hw->ifs_params_forced) {
4788 hw->current_ifs_val = 0;
4789 hw->ifs_min_val = IFS_MIN;
4790 hw->ifs_max_val = IFS_MAX;
4791 hw->ifs_step_size = IFS_STEP;
4792 hw->ifs_ratio = IFS_RATIO;
4793 }
4794 hw->in_ifs_mode = false;
4795 ew32(AIT, 0);
4796 } else {
4797 e_dbg("Not in Adaptive IFS mode!\n");
4798 }
4799}
4800
4801/**
4802 * e1000_update_adaptive - update adaptive IFS
4803 * @hw: Struct containing variables accessed by shared code
4804 * @tx_packets: Number of transmits since last callback
4805 * @total_collisions: Number of collisions since last callback
4806 *
4807 * Called during the callback/watchdog routine to update IFS value based on
4808 * the ratio of transmits to collisions.
4809 */
4810void e1000_update_adaptive(struct e1000_hw *hw)
4811{
4812 if (hw->adaptive_ifs) {
4813 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4814 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4815 hw->in_ifs_mode = true;
4816 if (hw->current_ifs_val < hw->ifs_max_val) {
4817 if (hw->current_ifs_val == 0)
4818 hw->current_ifs_val =
4819 hw->ifs_min_val;
4820 else
4821 hw->current_ifs_val +=
4822 hw->ifs_step_size;
4823 ew32(AIT, hw->current_ifs_val);
4824 }
4825 }
4826 } else {
4827 if (hw->in_ifs_mode &&
4828 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4829 hw->current_ifs_val = 0;
4830 hw->in_ifs_mode = false;
4831 ew32(AIT, 0);
4832 }
4833 }
4834 } else {
4835 e_dbg("Not in Adaptive IFS mode!\n");
4836 }
4837}
4838
4839/**
4840 * e1000_get_bus_info
4841 * @hw: Struct containing variables accessed by shared code
4842 *
4843 * Gets the current PCI bus type, speed, and width of the hardware
4844 */
4845void e1000_get_bus_info(struct e1000_hw *hw)
4846{
4847 u32 status;
4848
4849 switch (hw->mac_type) {
4850 case e1000_82542_rev2_0:
4851 case e1000_82542_rev2_1:
4852 hw->bus_type = e1000_bus_type_pci;
4853 hw->bus_speed = e1000_bus_speed_unknown;
4854 hw->bus_width = e1000_bus_width_unknown;
4855 break;
4856 default:
4857 status = er32(STATUS);
4858 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4859 e1000_bus_type_pcix : e1000_bus_type_pci;
4860
4861 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4862 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4863 e1000_bus_speed_66 : e1000_bus_speed_120;
4864 } else if (hw->bus_type == e1000_bus_type_pci) {
4865 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4866 e1000_bus_speed_66 : e1000_bus_speed_33;
4867 } else {
4868 switch (status & E1000_STATUS_PCIX_SPEED) {
4869 case E1000_STATUS_PCIX_SPEED_66:
4870 hw->bus_speed = e1000_bus_speed_66;
4871 break;
4872 case E1000_STATUS_PCIX_SPEED_100:
4873 hw->bus_speed = e1000_bus_speed_100;
4874 break;
4875 case E1000_STATUS_PCIX_SPEED_133:
4876 hw->bus_speed = e1000_bus_speed_133;
4877 break;
4878 default:
4879 hw->bus_speed = e1000_bus_speed_reserved;
4880 break;
4881 }
4882 }
4883 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4884 e1000_bus_width_64 : e1000_bus_width_32;
4885 break;
4886 }
4887}
4888
4889/**
4890 * e1000_write_reg_io
4891 * @hw: Struct containing variables accessed by shared code
4892 * @offset: offset to write to
4893 * @value: value to write
4894 *
4895 * Writes a value to one of the devices registers using port I/O (as opposed to
4896 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4897 */
4898static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
4899{
4900 unsigned long io_addr = hw->io_base;
4901 unsigned long io_data = hw->io_base + 4;
4902
4903 e1000_io_write(hw, io_addr, offset);
4904 e1000_io_write(hw, io_data, value);
4905}
4906
4907/**
4908 * e1000_get_cable_length - Estimates the cable length.
4909 * @hw: Struct containing variables accessed by shared code
4910 * @min_length: The estimated minimum length
4911 * @max_length: The estimated maximum length
4912 *
4913 * returns: - E1000_ERR_XXX
4914 * E1000_SUCCESS
4915 *
4916 * This function always returns a ranged length (minimum & maximum).
4917 * So for M88 phy's, this function interprets the one value returned from the
4918 * register to the minimum and maximum range.
4919 * For IGP phy's, the function calculates the range by the AGC registers.
4920 */
4921static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4922 u16 *max_length)
4923{
4924 s32 ret_val;
4925 u16 agc_value = 0;
4926 u16 i, phy_data;
4927 u16 cable_length;
4928
4929 *min_length = *max_length = 0;
4930
4931 /* Use old method for Phy older than IGP */
4932 if (hw->phy_type == e1000_phy_m88) {
4933 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4934 &phy_data);
4935 if (ret_val)
4936 return ret_val;
4937 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4938 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4939
4940 /* Convert the enum value to ranged values */
4941 switch (cable_length) {
4942 case e1000_cable_length_50:
4943 *min_length = 0;
4944 *max_length = e1000_igp_cable_length_50;
4945 break;
4946 case e1000_cable_length_50_80:
4947 *min_length = e1000_igp_cable_length_50;
4948 *max_length = e1000_igp_cable_length_80;
4949 break;
4950 case e1000_cable_length_80_110:
4951 *min_length = e1000_igp_cable_length_80;
4952 *max_length = e1000_igp_cable_length_110;
4953 break;
4954 case e1000_cable_length_110_140:
4955 *min_length = e1000_igp_cable_length_110;
4956 *max_length = e1000_igp_cable_length_140;
4957 break;
4958 case e1000_cable_length_140:
4959 *min_length = e1000_igp_cable_length_140;
4960 *max_length = e1000_igp_cable_length_170;
4961 break;
4962 default:
4963 return -E1000_ERR_PHY;
4964 }
4965 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4966 u16 cur_agc_value;
4967 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4968 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
4969 IGP01E1000_PHY_AGC_A,
4970 IGP01E1000_PHY_AGC_B,
4971 IGP01E1000_PHY_AGC_C,
4972 IGP01E1000_PHY_AGC_D
4973 };
4974 /* Read the AGC registers for all channels */
4975 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4976 ret_val =
4977 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4978 if (ret_val)
4979 return ret_val;
4980
4981 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4982
4983 /* Value bound check. */
4984 if ((cur_agc_value >=
4985 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4986 (cur_agc_value == 0))
4987 return -E1000_ERR_PHY;
4988
4989 agc_value += cur_agc_value;
4990
4991 /* Update minimal AGC value. */
4992 if (min_agc_value > cur_agc_value)
4993 min_agc_value = cur_agc_value;
4994 }
4995
4996 /* Remove the minimal AGC result for length < 50m */
4997 if (agc_value <
4998 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4999 agc_value -= min_agc_value;
5000
5001 /* Get the average length of the remaining 3 channels */
5002 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
5003 } else {
5004 /* Get the average length of all the 4 channels. */
5005 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
5006 }
5007
5008 /* Set the range of the calculated length. */
5009 *min_length = ((e1000_igp_cable_length_table[agc_value] -
5010 IGP01E1000_AGC_RANGE) > 0) ?
5011 (e1000_igp_cable_length_table[agc_value] -
5012 IGP01E1000_AGC_RANGE) : 0;
5013 *max_length = e1000_igp_cable_length_table[agc_value] +
5014 IGP01E1000_AGC_RANGE;
5015 }
5016
5017 return E1000_SUCCESS;
5018}
5019
5020/**
5021 * e1000_check_polarity - Check the cable polarity
5022 * @hw: Struct containing variables accessed by shared code
5023 * @polarity: output parameter : 0 - Polarity is not reversed
5024 * 1 - Polarity is reversed.
5025 *
5026 * returns: - E1000_ERR_XXX
5027 * E1000_SUCCESS
5028 *
5029 * For phy's older than IGP, this function simply reads the polarity bit in the
5030 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5031 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5032 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5033 * IGP01E1000_PHY_PCS_INIT_REG.
5034 */
5035static s32 e1000_check_polarity(struct e1000_hw *hw,
5036 e1000_rev_polarity *polarity)
5037{
5038 s32 ret_val;
5039 u16 phy_data;
5040
5041 if (hw->phy_type == e1000_phy_m88) {
5042 /* return the Polarity bit in the Status register. */
5043 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5044 &phy_data);
5045 if (ret_val)
5046 return ret_val;
5047 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5048 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5049 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5050
5051 } else if (hw->phy_type == e1000_phy_igp) {
5052 /* Read the Status register to check the speed */
5053 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5054 &phy_data);
5055 if (ret_val)
5056 return ret_val;
5057
5058 /* If speed is 1000 Mbps, must read the
5059 * IGP01E1000_PHY_PCS_INIT_REG to find the polarity status
5060 */
5061 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5062 IGP01E1000_PSSR_SPEED_1000MBPS) {
5063 /* Read the GIG initialization PCS register (0x00B4) */
5064 ret_val =
5065 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5066 &phy_data);
5067 if (ret_val)
5068 return ret_val;
5069
5070 /* Check the polarity bits */
5071 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5072 e1000_rev_polarity_reversed :
5073 e1000_rev_polarity_normal;
5074 } else {
5075 /* For 10 Mbps, read the polarity bit in the status
5076 * register. (for 100 Mbps this bit is always 0)
5077 */
5078 *polarity =
5079 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5080 e1000_rev_polarity_reversed :
5081 e1000_rev_polarity_normal;
5082 }
5083 }
5084 return E1000_SUCCESS;
5085}
5086
5087/**
5088 * e1000_check_downshift - Check if Downshift occurred
5089 * @hw: Struct containing variables accessed by shared code
5090 * @downshift: output parameter : 0 - No Downshift occurred.
5091 * 1 - Downshift occurred.
5092 *
5093 * returns: - E1000_ERR_XXX
5094 * E1000_SUCCESS
5095 *
5096 * For phy's older than IGP, this function reads the Downshift bit in the Phy
5097 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5098 * Link Health register. In IGP this bit is latched high, so the driver must
5099 * read it immediately after link is established.
5100 */
5101static s32 e1000_check_downshift(struct e1000_hw *hw)
5102{
5103 s32 ret_val;
5104 u16 phy_data;
5105
5106 if (hw->phy_type == e1000_phy_igp) {
5107 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5108 &phy_data);
5109 if (ret_val)
5110 return ret_val;
5111
5112 hw->speed_downgraded =
5113 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5114 } else if (hw->phy_type == e1000_phy_m88) {
5115 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5116 &phy_data);
5117 if (ret_val)
5118 return ret_val;
5119
5120 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5121 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5122 }
5123
5124 return E1000_SUCCESS;
5125}
5126
5127static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5128 IGP01E1000_PHY_AGC_PARAM_A,
5129 IGP01E1000_PHY_AGC_PARAM_B,
5130 IGP01E1000_PHY_AGC_PARAM_C,
5131 IGP01E1000_PHY_AGC_PARAM_D
5132};
5133
5134static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)
5135{
5136 u16 min_length, max_length;
5137 u16 phy_data, i;
5138 s32 ret_val;
5139
5140 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
5141 if (ret_val)
5142 return ret_val;
5143
5144 if (hw->dsp_config_state != e1000_dsp_config_enabled)
5145 return 0;
5146
5147 if (min_length >= e1000_igp_cable_length_50) {
5148 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5149 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
5150 &phy_data);
5151 if (ret_val)
5152 return ret_val;
5153
5154 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5155
5156 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
5157 phy_data);
5158 if (ret_val)
5159 return ret_val;
5160 }
5161 hw->dsp_config_state = e1000_dsp_config_activated;
5162 } else {
5163 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5164 u32 idle_errs = 0;
5165
5166 /* clear previous idle error counts */
5167 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
5168 if (ret_val)
5169 return ret_val;
5170
5171 for (i = 0; i < ffe_idle_err_timeout; i++) {
5172 udelay(1000);
5173 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5174 &phy_data);
5175 if (ret_val)
5176 return ret_val;
5177
5178 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5179 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5180 hw->ffe_config_state = e1000_ffe_config_active;
5181
5182 ret_val = e1000_write_phy_reg(hw,
5183 IGP01E1000_PHY_DSP_FFE,
5184 IGP01E1000_PHY_DSP_FFE_CM_CP);
5185 if (ret_val)
5186 return ret_val;
5187 break;
5188 }
5189
5190 if (idle_errs)
5191 ffe_idle_err_timeout =
5192 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5193 }
5194 }
5195
5196 return 0;
5197}
5198
5199/**
5200 * e1000_config_dsp_after_link_change
5201 * @hw: Struct containing variables accessed by shared code
5202 * @link_up: was link up at the time this was called
5203 *
5204 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5205 * E1000_SUCCESS at any other case.
5206 *
5207 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5208 * gigabit link is achieved to improve link quality.
5209 */
5210
5211static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5212{
5213 s32 ret_val;
5214 u16 phy_data, phy_saved_data, speed, duplex, i;
5215
5216 if (hw->phy_type != e1000_phy_igp)
5217 return E1000_SUCCESS;
5218
5219 if (link_up) {
5220 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5221 if (ret_val) {
5222 e_dbg("Error getting link speed and duplex\n");
5223 return ret_val;
5224 }
5225
5226 if (speed == SPEED_1000) {
5227 ret_val = e1000_1000Mb_check_cable_length(hw);
5228 if (ret_val)
5229 return ret_val;
5230 }
5231 } else {
5232 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5233 /* Save off the current value of register 0x2F5B to be
5234 * restored at the end of the routines.
5235 */
5236 ret_val =
5237 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5238
5239 if (ret_val)
5240 return ret_val;
5241
5242 /* Disable the PHY transmitter */
5243 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5244
5245 if (ret_val)
5246 return ret_val;
5247
5248 msleep(20);
5249
5250 ret_val = e1000_write_phy_reg(hw, 0x0000,
5251 IGP01E1000_IEEE_FORCE_GIGA);
5252 if (ret_val)
5253 return ret_val;
5254 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5255 ret_val =
5256 e1000_read_phy_reg(hw, dsp_reg_array[i],
5257 &phy_data);
5258 if (ret_val)
5259 return ret_val;
5260
5261 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5262 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5263
5264 ret_val =
5265 e1000_write_phy_reg(hw, dsp_reg_array[i],
5266 phy_data);
5267 if (ret_val)
5268 return ret_val;
5269 }
5270
5271 ret_val = e1000_write_phy_reg(hw, 0x0000,
5272 IGP01E1000_IEEE_RESTART_AUTONEG);
5273 if (ret_val)
5274 return ret_val;
5275
5276 msleep(20);
5277
5278 /* Now enable the transmitter */
5279 ret_val =
5280 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5281
5282 if (ret_val)
5283 return ret_val;
5284
5285 hw->dsp_config_state = e1000_dsp_config_enabled;
5286 }
5287
5288 if (hw->ffe_config_state == e1000_ffe_config_active) {
5289 /* Save off the current value of register 0x2F5B to be
5290 * restored at the end of the routines.
5291 */
5292 ret_val =
5293 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5294
5295 if (ret_val)
5296 return ret_val;
5297
5298 /* Disable the PHY transmitter */
5299 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5300
5301 if (ret_val)
5302 return ret_val;
5303
5304 msleep(20);
5305
5306 ret_val = e1000_write_phy_reg(hw, 0x0000,
5307 IGP01E1000_IEEE_FORCE_GIGA);
5308 if (ret_val)
5309 return ret_val;
5310 ret_val =
5311 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5312 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5313 if (ret_val)
5314 return ret_val;
5315
5316 ret_val = e1000_write_phy_reg(hw, 0x0000,
5317 IGP01E1000_IEEE_RESTART_AUTONEG);
5318 if (ret_val)
5319 return ret_val;
5320
5321 msleep(20);
5322
5323 /* Now enable the transmitter */
5324 ret_val =
5325 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5326
5327 if (ret_val)
5328 return ret_val;
5329
5330 hw->ffe_config_state = e1000_ffe_config_enabled;
5331 }
5332 }
5333 return E1000_SUCCESS;
5334}
5335
5336/**
5337 * e1000_set_phy_mode - Set PHY to class A mode
5338 * @hw: Struct containing variables accessed by shared code
5339 *
5340 * Assumes the following operations will follow to enable the new class mode.
5341 * 1. Do a PHY soft reset
5342 * 2. Restart auto-negotiation or force link.
5343 */
5344static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5345{
5346 s32 ret_val;
5347 u16 eeprom_data;
5348
5349 if ((hw->mac_type == e1000_82545_rev_3) &&
5350 (hw->media_type == e1000_media_type_copper)) {
5351 ret_val =
5352 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5353 &eeprom_data);
5354 if (ret_val)
5355 return ret_val;
5356
5357 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5358 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5359 ret_val =
5360 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5361 0x000B);
5362 if (ret_val)
5363 return ret_val;
5364 ret_val =
5365 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5366 0x8104);
5367 if (ret_val)
5368 return ret_val;
5369
5370 hw->phy_reset_disable = false;
5371 }
5372 }
5373
5374 return E1000_SUCCESS;
5375}
5376
5377/**
5378 * e1000_set_d3_lplu_state - set d3 link power state
5379 * @hw: Struct containing variables accessed by shared code
5380 * @active: true to enable lplu false to disable lplu.
5381 *
5382 * This function sets the lplu state according to the active flag. When
5383 * activating lplu this function also disables smart speed and vise versa.
5384 * lplu will not be activated unless the device autonegotiation advertisement
5385 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5386 *
5387 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5388 * E1000_SUCCESS at any other case.
5389 */
5390static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5391{
5392 s32 ret_val;
5393 u16 phy_data;
5394
5395 if (hw->phy_type != e1000_phy_igp)
5396 return E1000_SUCCESS;
5397
5398 /* During driver activity LPLU should not be used or it will attain link
5399 * from the lowest speeds starting from 10Mbps. The capability is used
5400 * for Dx transitions and states
5401 */
5402 if (hw->mac_type == e1000_82541_rev_2 ||
5403 hw->mac_type == e1000_82547_rev_2) {
5404 ret_val =
5405 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5406 if (ret_val)
5407 return ret_val;
5408 }
5409
5410 if (!active) {
5411 if (hw->mac_type == e1000_82541_rev_2 ||
5412 hw->mac_type == e1000_82547_rev_2) {
5413 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5414 ret_val =
5415 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5416 phy_data);
5417 if (ret_val)
5418 return ret_val;
5419 }
5420
5421 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
5422 * during Dx states where the power conservation is most
5423 * important. During driver activity we should enable
5424 * SmartSpeed, so performance is maintained.
5425 */
5426 if (hw->smart_speed == e1000_smart_speed_on) {
5427 ret_val =
5428 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5429 &phy_data);
5430 if (ret_val)
5431 return ret_val;
5432
5433 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5434 ret_val =
5435 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5436 phy_data);
5437 if (ret_val)
5438 return ret_val;
5439 } else if (hw->smart_speed == e1000_smart_speed_off) {
5440 ret_val =
5441 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5442 &phy_data);
5443 if (ret_val)
5444 return ret_val;
5445
5446 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5447 ret_val =
5448 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5449 phy_data);
5450 if (ret_val)
5451 return ret_val;
5452 }
5453 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5454 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
5455 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5456 if (hw->mac_type == e1000_82541_rev_2 ||
5457 hw->mac_type == e1000_82547_rev_2) {
5458 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5459 ret_val =
5460 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5461 phy_data);
5462 if (ret_val)
5463 return ret_val;
5464 }
5465
5466 /* When LPLU is enabled we should disable SmartSpeed */
5467 ret_val =
5468 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5469 &phy_data);
5470 if (ret_val)
5471 return ret_val;
5472
5473 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5474 ret_val =
5475 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5476 phy_data);
5477 if (ret_val)
5478 return ret_val;
5479 }
5480 return E1000_SUCCESS;
5481}
5482
5483/**
5484 * e1000_set_vco_speed
5485 * @hw: Struct containing variables accessed by shared code
5486 *
5487 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5488 */
5489static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5490{
5491 s32 ret_val;
5492 u16 default_page = 0;
5493 u16 phy_data;
5494
5495 switch (hw->mac_type) {
5496 case e1000_82545_rev_3:
5497 case e1000_82546_rev_3:
5498 break;
5499 default:
5500 return E1000_SUCCESS;
5501 }
5502
5503 /* Set PHY register 30, page 5, bit 8 to 0 */
5504
5505 ret_val =
5506 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5507 if (ret_val)
5508 return ret_val;
5509
5510 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5511 if (ret_val)
5512 return ret_val;
5513
5514 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5515 if (ret_val)
5516 return ret_val;
5517
5518 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5519 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5520 if (ret_val)
5521 return ret_val;
5522
5523 /* Set PHY register 30, page 4, bit 11 to 1 */
5524
5525 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5526 if (ret_val)
5527 return ret_val;
5528
5529 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5530 if (ret_val)
5531 return ret_val;
5532
5533 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5534 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5535 if (ret_val)
5536 return ret_val;
5537
5538 ret_val =
5539 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5540 if (ret_val)
5541 return ret_val;
5542
5543 return E1000_SUCCESS;
5544}
5545
5546/**
5547 * e1000_enable_mng_pass_thru - check for bmc pass through
5548 * @hw: Struct containing variables accessed by shared code
5549 *
5550 * Verifies the hardware needs to allow ARPs to be processed by the host
5551 * returns: - true/false
5552 */
5553u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5554{
5555 u32 manc;
5556
5557 if (hw->asf_firmware_present) {
5558 manc = er32(MANC);
5559
5560 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5561 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5562 return false;
5563 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5564 return true;
5565 }
5566 return false;
5567}
5568
5569static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5570{
5571 s32 ret_val;
5572 u16 mii_status_reg;
5573 u16 i;
5574
5575 /* Polarity reversal workaround for forced 10F/10H links. */
5576
5577 /* Disable the transmitter on the PHY */
5578
5579 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5580 if (ret_val)
5581 return ret_val;
5582 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5583 if (ret_val)
5584 return ret_val;
5585
5586 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5587 if (ret_val)
5588 return ret_val;
5589
5590 /* This loop will early-out if the NO link condition has been met. */
5591 for (i = PHY_FORCE_TIME; i > 0; i--) {
5592 /* Read the MII Status Register and wait for Link Status bit
5593 * to be clear.
5594 */
5595
5596 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5597 if (ret_val)
5598 return ret_val;
5599
5600 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5601 if (ret_val)
5602 return ret_val;
5603
5604 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5605 break;
5606 msleep(100);
5607 }
5608
5609 /* Recommended delay time after link has been lost */
5610 msleep(1000);
5611
5612 /* Now we will re-enable th transmitter on the PHY */
5613
5614 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5615 if (ret_val)
5616 return ret_val;
5617 msleep(50);
5618 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5619 if (ret_val)
5620 return ret_val;
5621 msleep(50);
5622 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5623 if (ret_val)
5624 return ret_val;
5625 msleep(50);
5626 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5627 if (ret_val)
5628 return ret_val;
5629
5630 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5631 if (ret_val)
5632 return ret_val;
5633
5634 /* This loop will early-out if the link condition has been met. */
5635 for (i = PHY_FORCE_TIME; i > 0; i--) {
5636 /* Read the MII Status Register and wait for Link Status bit
5637 * to be set.
5638 */
5639
5640 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5641 if (ret_val)
5642 return ret_val;
5643
5644 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5645 if (ret_val)
5646 return ret_val;
5647
5648 if (mii_status_reg & MII_SR_LINK_STATUS)
5649 break;
5650 msleep(100);
5651 }
5652 return E1000_SUCCESS;
5653}
5654
5655/**
5656 * e1000_get_auto_rd_done
5657 * @hw: Struct containing variables accessed by shared code
5658 *
5659 * Check for EEPROM Auto Read bit done.
5660 * returns: - E1000_ERR_RESET if fail to reset MAC
5661 * E1000_SUCCESS at any other case.
5662 */
5663static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5664{
5665 msleep(5);
5666 return E1000_SUCCESS;
5667}
5668
5669/**
5670 * e1000_get_phy_cfg_done
5671 * @hw: Struct containing variables accessed by shared code
5672 *
5673 * Checks if the PHY configuration is done
5674 * returns: - E1000_ERR_RESET if fail to reset MAC
5675 * E1000_SUCCESS at any other case.
5676 */
5677static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5678{
5679 msleep(10);
5680 return E1000_SUCCESS;
5681}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2006 Intel Corporation. */
3
4/* e1000_hw.c
5 * Shared functions for accessing and configuring the MAC
6 */
7
8#include "e1000.h"
9
10static s32 e1000_check_downshift(struct e1000_hw *hw);
11static s32 e1000_check_polarity(struct e1000_hw *hw,
12 e1000_rev_polarity *polarity);
13static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
14static void e1000_clear_vfta(struct e1000_hw *hw);
15static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
16 bool link_up);
17static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
18static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
19static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
20static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
21 u16 *max_length);
22static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
23static s32 e1000_id_led_init(struct e1000_hw *hw);
24static void e1000_init_rx_addrs(struct e1000_hw *hw);
25static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
26 struct e1000_phy_info *phy_info);
27static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
28 struct e1000_phy_info *phy_info);
29static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
30static s32 e1000_wait_autoneg(struct e1000_hw *hw);
31static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
32static s32 e1000_set_phy_type(struct e1000_hw *hw);
33static void e1000_phy_init_script(struct e1000_hw *hw);
34static s32 e1000_setup_copper_link(struct e1000_hw *hw);
35static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
36static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
37static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
38static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
39static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
40static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
41static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
42static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
43static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
44static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
45 u16 words, u16 *data);
46static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
47 u16 words, u16 *data);
48static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
49static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
50static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
51static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
52static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
53 u16 phy_data);
54static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
55 u16 *phy_data);
56static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
57static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
58static void e1000_release_eeprom(struct e1000_hw *hw);
59static void e1000_standby_eeprom(struct e1000_hw *hw);
60static s32 e1000_set_vco_speed(struct e1000_hw *hw);
61static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
62static s32 e1000_set_phy_mode(struct e1000_hw *hw);
63static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
64 u16 *data);
65static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
66 u16 *data);
67
68/* IGP cable length table */
69static const
70u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
71 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
72 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
73 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
74 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
75 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
76 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
77 100,
78 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
79 110, 110,
80 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
81 120, 120
82};
83
84static DEFINE_MUTEX(e1000_eeprom_lock);
85static DEFINE_SPINLOCK(e1000_phy_lock);
86
87/**
88 * e1000_set_phy_type - Set the phy type member in the hw struct.
89 * @hw: Struct containing variables accessed by shared code
90 */
91static s32 e1000_set_phy_type(struct e1000_hw *hw)
92{
93 if (hw->mac_type == e1000_undefined)
94 return -E1000_ERR_PHY_TYPE;
95
96 switch (hw->phy_id) {
97 case M88E1000_E_PHY_ID:
98 case M88E1000_I_PHY_ID:
99 case M88E1011_I_PHY_ID:
100 case M88E1111_I_PHY_ID:
101 case M88E1118_E_PHY_ID:
102 hw->phy_type = e1000_phy_m88;
103 break;
104 case IGP01E1000_I_PHY_ID:
105 if (hw->mac_type == e1000_82541 ||
106 hw->mac_type == e1000_82541_rev_2 ||
107 hw->mac_type == e1000_82547 ||
108 hw->mac_type == e1000_82547_rev_2)
109 hw->phy_type = e1000_phy_igp;
110 break;
111 case RTL8211B_PHY_ID:
112 hw->phy_type = e1000_phy_8211;
113 break;
114 case RTL8201N_PHY_ID:
115 hw->phy_type = e1000_phy_8201;
116 break;
117 default:
118 /* Should never have loaded on this device */
119 hw->phy_type = e1000_phy_undefined;
120 return -E1000_ERR_PHY_TYPE;
121 }
122
123 return E1000_SUCCESS;
124}
125
126/**
127 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
128 * @hw: Struct containing variables accessed by shared code
129 */
130static void e1000_phy_init_script(struct e1000_hw *hw)
131{
132 u16 phy_saved_data;
133
134 if (hw->phy_init_script) {
135 msleep(20);
136
137 /* Save off the current value of register 0x2F5B to be restored
138 * at the end of this routine.
139 */
140 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
141
142 /* Disabled the PHY transmitter */
143 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
144 msleep(20);
145
146 e1000_write_phy_reg(hw, 0x0000, 0x0140);
147 msleep(5);
148
149 switch (hw->mac_type) {
150 case e1000_82541:
151 case e1000_82547:
152 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
153 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
154 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
155 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
156 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
157 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
158 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
159 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
160 e1000_write_phy_reg(hw, 0x2010, 0x0008);
161 break;
162
163 case e1000_82541_rev_2:
164 case e1000_82547_rev_2:
165 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
166 break;
167 default:
168 break;
169 }
170
171 e1000_write_phy_reg(hw, 0x0000, 0x3300);
172 msleep(20);
173
174 /* Now enable the transmitter */
175 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
176
177 if (hw->mac_type == e1000_82547) {
178 u16 fused, fine, coarse;
179
180 /* Move to analog registers page */
181 e1000_read_phy_reg(hw,
182 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
183 &fused);
184
185 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
186 e1000_read_phy_reg(hw,
187 IGP01E1000_ANALOG_FUSE_STATUS,
188 &fused);
189
190 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
191 coarse =
192 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
193
194 if (coarse >
195 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
196 coarse -=
197 IGP01E1000_ANALOG_FUSE_COARSE_10;
198 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
199 } else if (coarse ==
200 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
201 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
202
203 fused =
204 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
205 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
206 (coarse &
207 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
208
209 e1000_write_phy_reg(hw,
210 IGP01E1000_ANALOG_FUSE_CONTROL,
211 fused);
212 e1000_write_phy_reg(hw,
213 IGP01E1000_ANALOG_FUSE_BYPASS,
214 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
215 }
216 }
217 }
218}
219
220/**
221 * e1000_set_mac_type - Set the mac type member in the hw struct.
222 * @hw: Struct containing variables accessed by shared code
223 */
224s32 e1000_set_mac_type(struct e1000_hw *hw)
225{
226 switch (hw->device_id) {
227 case E1000_DEV_ID_82542:
228 switch (hw->revision_id) {
229 case E1000_82542_2_0_REV_ID:
230 hw->mac_type = e1000_82542_rev2_0;
231 break;
232 case E1000_82542_2_1_REV_ID:
233 hw->mac_type = e1000_82542_rev2_1;
234 break;
235 default:
236 /* Invalid 82542 revision ID */
237 return -E1000_ERR_MAC_TYPE;
238 }
239 break;
240 case E1000_DEV_ID_82543GC_FIBER:
241 case E1000_DEV_ID_82543GC_COPPER:
242 hw->mac_type = e1000_82543;
243 break;
244 case E1000_DEV_ID_82544EI_COPPER:
245 case E1000_DEV_ID_82544EI_FIBER:
246 case E1000_DEV_ID_82544GC_COPPER:
247 case E1000_DEV_ID_82544GC_LOM:
248 hw->mac_type = e1000_82544;
249 break;
250 case E1000_DEV_ID_82540EM:
251 case E1000_DEV_ID_82540EM_LOM:
252 case E1000_DEV_ID_82540EP:
253 case E1000_DEV_ID_82540EP_LOM:
254 case E1000_DEV_ID_82540EP_LP:
255 hw->mac_type = e1000_82540;
256 break;
257 case E1000_DEV_ID_82545EM_COPPER:
258 case E1000_DEV_ID_82545EM_FIBER:
259 hw->mac_type = e1000_82545;
260 break;
261 case E1000_DEV_ID_82545GM_COPPER:
262 case E1000_DEV_ID_82545GM_FIBER:
263 case E1000_DEV_ID_82545GM_SERDES:
264 hw->mac_type = e1000_82545_rev_3;
265 break;
266 case E1000_DEV_ID_82546EB_COPPER:
267 case E1000_DEV_ID_82546EB_FIBER:
268 case E1000_DEV_ID_82546EB_QUAD_COPPER:
269 hw->mac_type = e1000_82546;
270 break;
271 case E1000_DEV_ID_82546GB_COPPER:
272 case E1000_DEV_ID_82546GB_FIBER:
273 case E1000_DEV_ID_82546GB_SERDES:
274 case E1000_DEV_ID_82546GB_PCIE:
275 case E1000_DEV_ID_82546GB_QUAD_COPPER:
276 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
277 hw->mac_type = e1000_82546_rev_3;
278 break;
279 case E1000_DEV_ID_82541EI:
280 case E1000_DEV_ID_82541EI_MOBILE:
281 case E1000_DEV_ID_82541ER_LOM:
282 hw->mac_type = e1000_82541;
283 break;
284 case E1000_DEV_ID_82541ER:
285 case E1000_DEV_ID_82541GI:
286 case E1000_DEV_ID_82541GI_LF:
287 case E1000_DEV_ID_82541GI_MOBILE:
288 hw->mac_type = e1000_82541_rev_2;
289 break;
290 case E1000_DEV_ID_82547EI:
291 case E1000_DEV_ID_82547EI_MOBILE:
292 hw->mac_type = e1000_82547;
293 break;
294 case E1000_DEV_ID_82547GI:
295 hw->mac_type = e1000_82547_rev_2;
296 break;
297 case E1000_DEV_ID_INTEL_CE4100_GBE:
298 hw->mac_type = e1000_ce4100;
299 break;
300 default:
301 /* Should never have loaded on this device */
302 return -E1000_ERR_MAC_TYPE;
303 }
304
305 switch (hw->mac_type) {
306 case e1000_82541:
307 case e1000_82547:
308 case e1000_82541_rev_2:
309 case e1000_82547_rev_2:
310 hw->asf_firmware_present = true;
311 break;
312 default:
313 break;
314 }
315
316 /* The 82543 chip does not count tx_carrier_errors properly in
317 * FD mode
318 */
319 if (hw->mac_type == e1000_82543)
320 hw->bad_tx_carr_stats_fd = true;
321
322 if (hw->mac_type > e1000_82544)
323 hw->has_smbus = true;
324
325 return E1000_SUCCESS;
326}
327
328/**
329 * e1000_set_media_type - Set media type and TBI compatibility.
330 * @hw: Struct containing variables accessed by shared code
331 */
332void e1000_set_media_type(struct e1000_hw *hw)
333{
334 u32 status;
335
336 if (hw->mac_type != e1000_82543) {
337 /* tbi_compatibility is only valid on 82543 */
338 hw->tbi_compatibility_en = false;
339 }
340
341 switch (hw->device_id) {
342 case E1000_DEV_ID_82545GM_SERDES:
343 case E1000_DEV_ID_82546GB_SERDES:
344 hw->media_type = e1000_media_type_internal_serdes;
345 break;
346 default:
347 switch (hw->mac_type) {
348 case e1000_82542_rev2_0:
349 case e1000_82542_rev2_1:
350 hw->media_type = e1000_media_type_fiber;
351 break;
352 case e1000_ce4100:
353 hw->media_type = e1000_media_type_copper;
354 break;
355 default:
356 status = er32(STATUS);
357 if (status & E1000_STATUS_TBIMODE) {
358 hw->media_type = e1000_media_type_fiber;
359 /* tbi_compatibility not valid on fiber */
360 hw->tbi_compatibility_en = false;
361 } else {
362 hw->media_type = e1000_media_type_copper;
363 }
364 break;
365 }
366 }
367}
368
369/**
370 * e1000_reset_hw - reset the hardware completely
371 * @hw: Struct containing variables accessed by shared code
372 *
373 * Reset the transmit and receive units; mask and clear all interrupts.
374 */
375s32 e1000_reset_hw(struct e1000_hw *hw)
376{
377 u32 ctrl;
378 u32 ctrl_ext;
379 u32 manc;
380 u32 led_ctrl;
381 s32 ret_val;
382
383 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
384 if (hw->mac_type == e1000_82542_rev2_0) {
385 e_dbg("Disabling MWI on 82542 rev 2.0\n");
386 e1000_pci_clear_mwi(hw);
387 }
388
389 /* Clear interrupt mask to stop board from generating interrupts */
390 e_dbg("Masking off all interrupts\n");
391 ew32(IMC, 0xffffffff);
392
393 /* Disable the Transmit and Receive units. Then delay to allow
394 * any pending transactions to complete before we hit the MAC with
395 * the global reset.
396 */
397 ew32(RCTL, 0);
398 ew32(TCTL, E1000_TCTL_PSP);
399 E1000_WRITE_FLUSH();
400
401 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
402 hw->tbi_compatibility_on = false;
403
404 /* Delay to allow any outstanding PCI transactions to complete before
405 * resetting the device
406 */
407 msleep(10);
408
409 ctrl = er32(CTRL);
410
411 /* Must reset the PHY before resetting the MAC */
412 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
413 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
414 E1000_WRITE_FLUSH();
415 msleep(5);
416 }
417
418 /* Issue a global reset to the MAC. This will reset the chip's
419 * transmit, receive, DMA, and link units. It will not effect
420 * the current PCI configuration. The global reset bit is self-
421 * clearing, and should clear within a microsecond.
422 */
423 e_dbg("Issuing a global reset to MAC\n");
424
425 switch (hw->mac_type) {
426 case e1000_82544:
427 case e1000_82540:
428 case e1000_82545:
429 case e1000_82546:
430 case e1000_82541:
431 case e1000_82541_rev_2:
432 /* These controllers can't ack the 64-bit write when issuing the
433 * reset, so use IO-mapping as a workaround to issue the reset
434 */
435 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
436 break;
437 case e1000_82545_rev_3:
438 case e1000_82546_rev_3:
439 /* Reset is performed on a shadow of the control register */
440 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
441 break;
442 case e1000_ce4100:
443 default:
444 ew32(CTRL, (ctrl | E1000_CTRL_RST));
445 break;
446 }
447
448 /* After MAC reset, force reload of EEPROM to restore power-on settings
449 * to device. Later controllers reload the EEPROM automatically, so
450 * just wait for reload to complete.
451 */
452 switch (hw->mac_type) {
453 case e1000_82542_rev2_0:
454 case e1000_82542_rev2_1:
455 case e1000_82543:
456 case e1000_82544:
457 /* Wait for reset to complete */
458 udelay(10);
459 ctrl_ext = er32(CTRL_EXT);
460 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
461 ew32(CTRL_EXT, ctrl_ext);
462 E1000_WRITE_FLUSH();
463 /* Wait for EEPROM reload */
464 msleep(2);
465 break;
466 case e1000_82541:
467 case e1000_82541_rev_2:
468 case e1000_82547:
469 case e1000_82547_rev_2:
470 /* Wait for EEPROM reload */
471 msleep(20);
472 break;
473 default:
474 /* Auto read done will delay 5ms or poll based on mac type */
475 ret_val = e1000_get_auto_rd_done(hw);
476 if (ret_val)
477 return ret_val;
478 break;
479 }
480
481 /* Disable HW ARPs on ASF enabled adapters */
482 if (hw->mac_type >= e1000_82540) {
483 manc = er32(MANC);
484 manc &= ~(E1000_MANC_ARP_EN);
485 ew32(MANC, manc);
486 }
487
488 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
489 e1000_phy_init_script(hw);
490
491 /* Configure activity LED after PHY reset */
492 led_ctrl = er32(LEDCTL);
493 led_ctrl &= IGP_ACTIVITY_LED_MASK;
494 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
495 ew32(LEDCTL, led_ctrl);
496 }
497
498 /* Clear interrupt mask to stop board from generating interrupts */
499 e_dbg("Masking off all interrupts\n");
500 ew32(IMC, 0xffffffff);
501
502 /* Clear any pending interrupt events. */
503 er32(ICR);
504
505 /* If MWI was previously enabled, reenable it. */
506 if (hw->mac_type == e1000_82542_rev2_0) {
507 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
508 e1000_pci_set_mwi(hw);
509 }
510
511 return E1000_SUCCESS;
512}
513
514/**
515 * e1000_init_hw - Performs basic configuration of the adapter.
516 * @hw: Struct containing variables accessed by shared code
517 *
518 * Assumes that the controller has previously been reset and is in a
519 * post-reset uninitialized state. Initializes the receive address registers,
520 * multicast table, and VLAN filter table. Calls routines to setup link
521 * configuration and flow control settings. Clears all on-chip counters. Leaves
522 * the transmit and receive units disabled and uninitialized.
523 */
524s32 e1000_init_hw(struct e1000_hw *hw)
525{
526 u32 ctrl;
527 u32 i;
528 s32 ret_val;
529 u32 mta_size;
530 u32 ctrl_ext;
531
532 /* Initialize Identification LED */
533 ret_val = e1000_id_led_init(hw);
534 if (ret_val) {
535 e_dbg("Error Initializing Identification LED\n");
536 return ret_val;
537 }
538
539 /* Set the media type and TBI compatibility */
540 e1000_set_media_type(hw);
541
542 /* Disabling VLAN filtering. */
543 e_dbg("Initializing the IEEE VLAN\n");
544 if (hw->mac_type < e1000_82545_rev_3)
545 ew32(VET, 0);
546 e1000_clear_vfta(hw);
547
548 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
549 if (hw->mac_type == e1000_82542_rev2_0) {
550 e_dbg("Disabling MWI on 82542 rev 2.0\n");
551 e1000_pci_clear_mwi(hw);
552 ew32(RCTL, E1000_RCTL_RST);
553 E1000_WRITE_FLUSH();
554 msleep(5);
555 }
556
557 /* Setup the receive address. This involves initializing all of the
558 * Receive Address Registers (RARs 0 - 15).
559 */
560 e1000_init_rx_addrs(hw);
561
562 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
563 if (hw->mac_type == e1000_82542_rev2_0) {
564 ew32(RCTL, 0);
565 E1000_WRITE_FLUSH();
566 msleep(1);
567 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
568 e1000_pci_set_mwi(hw);
569 }
570
571 /* Zero out the Multicast HASH table */
572 e_dbg("Zeroing the MTA\n");
573 mta_size = E1000_MC_TBL_SIZE;
574 for (i = 0; i < mta_size; i++) {
575 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
576 /* use write flush to prevent Memory Write Block (MWB) from
577 * occurring when accessing our register space
578 */
579 E1000_WRITE_FLUSH();
580 }
581
582 /* Set the PCI priority bit correctly in the CTRL register. This
583 * determines if the adapter gives priority to receives, or if it
584 * gives equal priority to transmits and receives. Valid only on
585 * 82542 and 82543 silicon.
586 */
587 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
588 ctrl = er32(CTRL);
589 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
590 }
591
592 switch (hw->mac_type) {
593 case e1000_82545_rev_3:
594 case e1000_82546_rev_3:
595 break;
596 default:
597 /* Workaround for PCI-X problem when BIOS sets MMRBC
598 * incorrectly.
599 */
600 if (hw->bus_type == e1000_bus_type_pcix &&
601 e1000_pcix_get_mmrbc(hw) > 2048)
602 e1000_pcix_set_mmrbc(hw, 2048);
603 break;
604 }
605
606 /* Call a subroutine to configure the link and setup flow control. */
607 ret_val = e1000_setup_link(hw);
608
609 /* Set the transmit descriptor write-back policy */
610 if (hw->mac_type > e1000_82544) {
611 ctrl = er32(TXDCTL);
612 ctrl =
613 (ctrl & ~E1000_TXDCTL_WTHRESH) |
614 E1000_TXDCTL_FULL_TX_DESC_WB;
615 ew32(TXDCTL, ctrl);
616 }
617
618 /* Clear all of the statistics registers (clear on read). It is
619 * important that we do this after we have tried to establish link
620 * because the symbol error count will increment wildly if there
621 * is no link.
622 */
623 e1000_clear_hw_cntrs(hw);
624
625 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
626 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
627 ctrl_ext = er32(CTRL_EXT);
628 /* Relaxed ordering must be disabled to avoid a parity
629 * error crash in a PCI slot.
630 */
631 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
632 ew32(CTRL_EXT, ctrl_ext);
633 }
634
635 return ret_val;
636}
637
638/**
639 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
640 * @hw: Struct containing variables accessed by shared code.
641 */
642static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
643{
644 u16 eeprom_data;
645 s32 ret_val;
646
647 if (hw->media_type != e1000_media_type_internal_serdes)
648 return E1000_SUCCESS;
649
650 switch (hw->mac_type) {
651 case e1000_82545_rev_3:
652 case e1000_82546_rev_3:
653 break;
654 default:
655 return E1000_SUCCESS;
656 }
657
658 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
659 &eeprom_data);
660 if (ret_val)
661 return ret_val;
662
663 if (eeprom_data != EEPROM_RESERVED_WORD) {
664 /* Adjust SERDES output amplitude only. */
665 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
666 ret_val =
667 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
668 if (ret_val)
669 return ret_val;
670 }
671
672 return E1000_SUCCESS;
673}
674
675/**
676 * e1000_setup_link - Configures flow control and link settings.
677 * @hw: Struct containing variables accessed by shared code
678 *
679 * Determines which flow control settings to use. Calls the appropriate media-
680 * specific link configuration function. Configures the flow control settings.
681 * Assuming the adapter has a valid link partner, a valid link should be
682 * established. Assumes the hardware has previously been reset and the
683 * transmitter and receiver are not enabled.
684 */
685s32 e1000_setup_link(struct e1000_hw *hw)
686{
687 u32 ctrl_ext;
688 s32 ret_val;
689 u16 eeprom_data;
690
691 /* Read and store word 0x0F of the EEPROM. This word contains bits
692 * that determine the hardware's default PAUSE (flow control) mode,
693 * a bit that determines whether the HW defaults to enabling or
694 * disabling auto-negotiation, and the direction of the
695 * SW defined pins. If there is no SW over-ride of the flow
696 * control setting, then the variable hw->fc will
697 * be initialized based on a value in the EEPROM.
698 */
699 if (hw->fc == E1000_FC_DEFAULT) {
700 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
701 1, &eeprom_data);
702 if (ret_val) {
703 e_dbg("EEPROM Read Error\n");
704 return -E1000_ERR_EEPROM;
705 }
706 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
707 hw->fc = E1000_FC_NONE;
708 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
709 EEPROM_WORD0F_ASM_DIR)
710 hw->fc = E1000_FC_TX_PAUSE;
711 else
712 hw->fc = E1000_FC_FULL;
713 }
714
715 /* We want to save off the original Flow Control configuration just
716 * in case we get disconnected and then reconnected into a different
717 * hub or switch with different Flow Control capabilities.
718 */
719 if (hw->mac_type == e1000_82542_rev2_0)
720 hw->fc &= (~E1000_FC_TX_PAUSE);
721
722 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
723 hw->fc &= (~E1000_FC_RX_PAUSE);
724
725 hw->original_fc = hw->fc;
726
727 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
728
729 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
730 * polarity value for the SW controlled pins, and setup the
731 * Extended Device Control reg with that info.
732 * This is needed because one of the SW controlled pins is used for
733 * signal detection. So this should be done before e1000_setup_pcs_link()
734 * or e1000_phy_setup() is called.
735 */
736 if (hw->mac_type == e1000_82543) {
737 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
738 1, &eeprom_data);
739 if (ret_val) {
740 e_dbg("EEPROM Read Error\n");
741 return -E1000_ERR_EEPROM;
742 }
743 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
744 SWDPIO__EXT_SHIFT);
745 ew32(CTRL_EXT, ctrl_ext);
746 }
747
748 /* Call the necessary subroutine to configure the link. */
749 ret_val = (hw->media_type == e1000_media_type_copper) ?
750 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
751
752 /* Initialize the flow control address, type, and PAUSE timer
753 * registers to their default values. This is done even if flow
754 * control is disabled, because it does not hurt anything to
755 * initialize these registers.
756 */
757 e_dbg("Initializing the Flow Control address, type and timer regs\n");
758
759 ew32(FCT, FLOW_CONTROL_TYPE);
760 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
761 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
762
763 ew32(FCTTV, hw->fc_pause_time);
764
765 /* Set the flow control receive threshold registers. Normally,
766 * these registers will be set to a default threshold that may be
767 * adjusted later by the driver's runtime code. However, if the
768 * ability to transmit pause frames in not enabled, then these
769 * registers will be set to 0.
770 */
771 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
772 ew32(FCRTL, 0);
773 ew32(FCRTH, 0);
774 } else {
775 /* We need to set up the Receive Threshold high and low water
776 * marks as well as (optionally) enabling the transmission of
777 * XON frames.
778 */
779 if (hw->fc_send_xon) {
780 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
781 ew32(FCRTH, hw->fc_high_water);
782 } else {
783 ew32(FCRTL, hw->fc_low_water);
784 ew32(FCRTH, hw->fc_high_water);
785 }
786 }
787 return ret_val;
788}
789
790/**
791 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
792 * @hw: Struct containing variables accessed by shared code
793 *
794 * Manipulates Physical Coding Sublayer functions in order to configure
795 * link. Assumes the hardware has been previously reset and the transmitter
796 * and receiver are not enabled.
797 */
798static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
799{
800 u32 ctrl;
801 u32 status;
802 u32 txcw = 0;
803 u32 i;
804 u32 signal = 0;
805 s32 ret_val;
806
807 /* On adapters with a MAC newer than 82544, SWDP 1 will be
808 * set when the optics detect a signal. On older adapters, it will be
809 * cleared when there is a signal. This applies to fiber media only.
810 * If we're on serdes media, adjust the output amplitude to value
811 * set in the EEPROM.
812 */
813 ctrl = er32(CTRL);
814 if (hw->media_type == e1000_media_type_fiber)
815 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
816
817 ret_val = e1000_adjust_serdes_amplitude(hw);
818 if (ret_val)
819 return ret_val;
820
821 /* Take the link out of reset */
822 ctrl &= ~(E1000_CTRL_LRST);
823
824 /* Adjust VCO speed to improve BER performance */
825 ret_val = e1000_set_vco_speed(hw);
826 if (ret_val)
827 return ret_val;
828
829 e1000_config_collision_dist(hw);
830
831 /* Check for a software override of the flow control settings, and setup
832 * the device accordingly. If auto-negotiation is enabled, then
833 * software will have to set the "PAUSE" bits to the correct value in
834 * the Tranmsit Config Word Register (TXCW) and re-start
835 * auto-negotiation. However, if auto-negotiation is disabled, then
836 * software will have to manually configure the two flow control enable
837 * bits in the CTRL register.
838 *
839 * The possible values of the "fc" parameter are:
840 * 0: Flow control is completely disabled
841 * 1: Rx flow control is enabled (we can receive pause frames, but
842 * not send pause frames).
843 * 2: Tx flow control is enabled (we can send pause frames but we do
844 * not support receiving pause frames).
845 * 3: Both Rx and TX flow control (symmetric) are enabled.
846 */
847 switch (hw->fc) {
848 case E1000_FC_NONE:
849 /* Flow ctrl is completely disabled by a software over-ride */
850 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
851 break;
852 case E1000_FC_RX_PAUSE:
853 /* Rx Flow control is enabled and Tx Flow control is disabled by
854 * a software over-ride. Since there really isn't a way to
855 * advertise that we are capable of Rx Pause ONLY, we will
856 * advertise that we support both symmetric and asymmetric Rx
857 * PAUSE. Later, we will disable the adapter's ability to send
858 * PAUSE frames.
859 */
860 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
861 break;
862 case E1000_FC_TX_PAUSE:
863 /* Tx Flow control is enabled, and Rx Flow control is disabled,
864 * by a software over-ride.
865 */
866 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
867 break;
868 case E1000_FC_FULL:
869 /* Flow control (both Rx and Tx) is enabled by a software
870 * over-ride.
871 */
872 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
873 break;
874 default:
875 e_dbg("Flow control param set incorrectly\n");
876 return -E1000_ERR_CONFIG;
877 }
878
879 /* Since auto-negotiation is enabled, take the link out of reset (the
880 * link will be in reset, because we previously reset the chip). This
881 * will restart auto-negotiation. If auto-negotiation is successful
882 * then the link-up status bit will be set and the flow control enable
883 * bits (RFCE and TFCE) will be set according to their negotiated value.
884 */
885 e_dbg("Auto-negotiation enabled\n");
886
887 ew32(TXCW, txcw);
888 ew32(CTRL, ctrl);
889 E1000_WRITE_FLUSH();
890
891 hw->txcw = txcw;
892 msleep(1);
893
894 /* If we have a signal (the cable is plugged in) then poll for a
895 * "Link-Up" indication in the Device Status Register. Time-out if a
896 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should
897 * complete in less than 500 milliseconds even if the other end is doing
898 * it in SW). For internal serdes, we just assume a signal is present,
899 * then poll.
900 */
901 if (hw->media_type == e1000_media_type_internal_serdes ||
902 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
903 e_dbg("Looking for Link\n");
904 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
905 msleep(10);
906 status = er32(STATUS);
907 if (status & E1000_STATUS_LU)
908 break;
909 }
910 if (i == (LINK_UP_TIMEOUT / 10)) {
911 e_dbg("Never got a valid link from auto-neg!!!\n");
912 hw->autoneg_failed = 1;
913 /* AutoNeg failed to achieve a link, so we'll call
914 * e1000_check_for_link. This routine will force the
915 * link up if we detect a signal. This will allow us to
916 * communicate with non-autonegotiating link partners.
917 */
918 ret_val = e1000_check_for_link(hw);
919 if (ret_val) {
920 e_dbg("Error while checking for link\n");
921 return ret_val;
922 }
923 hw->autoneg_failed = 0;
924 } else {
925 hw->autoneg_failed = 0;
926 e_dbg("Valid Link Found\n");
927 }
928 } else {
929 e_dbg("No Signal Detected\n");
930 }
931 return E1000_SUCCESS;
932}
933
934/**
935 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
936 * @hw: Struct containing variables accessed by shared code
937 *
938 * Commits changes to PHY configuration by calling e1000_phy_reset().
939 */
940static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
941{
942 s32 ret_val;
943
944 /* SW reset the PHY so all changes take effect */
945 ret_val = e1000_phy_reset(hw);
946 if (ret_val) {
947 e_dbg("Error Resetting the PHY\n");
948 return ret_val;
949 }
950
951 return E1000_SUCCESS;
952}
953
954static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
955{
956 s32 ret_val;
957 u32 ctrl_aux;
958
959 switch (hw->phy_type) {
960 case e1000_phy_8211:
961 ret_val = e1000_copper_link_rtl_setup(hw);
962 if (ret_val) {
963 e_dbg("e1000_copper_link_rtl_setup failed!\n");
964 return ret_val;
965 }
966 break;
967 case e1000_phy_8201:
968 /* Set RMII mode */
969 ctrl_aux = er32(CTL_AUX);
970 ctrl_aux |= E1000_CTL_AUX_RMII;
971 ew32(CTL_AUX, ctrl_aux);
972 E1000_WRITE_FLUSH();
973
974 /* Disable the J/K bits required for receive */
975 ctrl_aux = er32(CTL_AUX);
976 ctrl_aux |= 0x4;
977 ctrl_aux &= ~0x2;
978 ew32(CTL_AUX, ctrl_aux);
979 E1000_WRITE_FLUSH();
980 ret_val = e1000_copper_link_rtl_setup(hw);
981
982 if (ret_val) {
983 e_dbg("e1000_copper_link_rtl_setup failed!\n");
984 return ret_val;
985 }
986 break;
987 default:
988 e_dbg("Error Resetting the PHY\n");
989 return E1000_ERR_PHY_TYPE;
990 }
991
992 return E1000_SUCCESS;
993}
994
995/**
996 * e1000_copper_link_preconfig - early configuration for copper
997 * @hw: Struct containing variables accessed by shared code
998 *
999 * Make sure we have a valid PHY and change PHY mode before link setup.
1000 */
1001static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1002{
1003 u32 ctrl;
1004 s32 ret_val;
1005 u16 phy_data;
1006
1007 ctrl = er32(CTRL);
1008 /* With 82543, we need to force speed and duplex on the MAC equal to
1009 * what the PHY speed and duplex configuration is. In addition, we need
1010 * to perform a hardware reset on the PHY to take it out of reset.
1011 */
1012 if (hw->mac_type > e1000_82543) {
1013 ctrl |= E1000_CTRL_SLU;
1014 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1015 ew32(CTRL, ctrl);
1016 } else {
1017 ctrl |=
1018 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1019 ew32(CTRL, ctrl);
1020 ret_val = e1000_phy_hw_reset(hw);
1021 if (ret_val)
1022 return ret_val;
1023 }
1024
1025 /* Make sure we have a valid PHY */
1026 ret_val = e1000_detect_gig_phy(hw);
1027 if (ret_val) {
1028 e_dbg("Error, did not detect valid phy.\n");
1029 return ret_val;
1030 }
1031 e_dbg("Phy ID = %x\n", hw->phy_id);
1032
1033 /* Set PHY to class A mode (if necessary) */
1034 ret_val = e1000_set_phy_mode(hw);
1035 if (ret_val)
1036 return ret_val;
1037
1038 if ((hw->mac_type == e1000_82545_rev_3) ||
1039 (hw->mac_type == e1000_82546_rev_3)) {
1040 ret_val =
1041 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1042 phy_data |= 0x00000008;
1043 ret_val =
1044 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1045 }
1046
1047 if (hw->mac_type <= e1000_82543 ||
1048 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1049 hw->mac_type == e1000_82541_rev_2 ||
1050 hw->mac_type == e1000_82547_rev_2)
1051 hw->phy_reset_disable = false;
1052
1053 return E1000_SUCCESS;
1054}
1055
1056/**
1057 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1058 * @hw: Struct containing variables accessed by shared code
1059 */
1060static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1061{
1062 u32 led_ctrl;
1063 s32 ret_val;
1064 u16 phy_data;
1065
1066 if (hw->phy_reset_disable)
1067 return E1000_SUCCESS;
1068
1069 ret_val = e1000_phy_reset(hw);
1070 if (ret_val) {
1071 e_dbg("Error Resetting the PHY\n");
1072 return ret_val;
1073 }
1074
1075 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1076 msleep(15);
1077 /* Configure activity LED after PHY reset */
1078 led_ctrl = er32(LEDCTL);
1079 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1080 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1081 ew32(LEDCTL, led_ctrl);
1082
1083 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1084 if (hw->phy_type == e1000_phy_igp) {
1085 /* disable lplu d3 during driver init */
1086 ret_val = e1000_set_d3_lplu_state(hw, false);
1087 if (ret_val) {
1088 e_dbg("Error Disabling LPLU D3\n");
1089 return ret_val;
1090 }
1091 }
1092
1093 /* Configure mdi-mdix settings */
1094 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1095 if (ret_val)
1096 return ret_val;
1097
1098 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1099 hw->dsp_config_state = e1000_dsp_config_disabled;
1100 /* Force MDI for earlier revs of the IGP PHY */
1101 phy_data &=
1102 ~(IGP01E1000_PSCR_AUTO_MDIX |
1103 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1104 hw->mdix = 1;
1105
1106 } else {
1107 hw->dsp_config_state = e1000_dsp_config_enabled;
1108 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1109
1110 switch (hw->mdix) {
1111 case 1:
1112 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1113 break;
1114 case 2:
1115 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1116 break;
1117 case 0:
1118 default:
1119 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1120 break;
1121 }
1122 }
1123 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1124 if (ret_val)
1125 return ret_val;
1126
1127 /* set auto-master slave resolution settings */
1128 if (hw->autoneg) {
1129 e1000_ms_type phy_ms_setting = hw->master_slave;
1130
1131 if (hw->ffe_config_state == e1000_ffe_config_active)
1132 hw->ffe_config_state = e1000_ffe_config_enabled;
1133
1134 if (hw->dsp_config_state == e1000_dsp_config_activated)
1135 hw->dsp_config_state = e1000_dsp_config_enabled;
1136
1137 /* when autonegotiation advertisement is only 1000Mbps then we
1138 * should disable SmartSpeed and enable Auto MasterSlave
1139 * resolution as hardware default.
1140 */
1141 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1142 /* Disable SmartSpeed */
1143 ret_val =
1144 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1145 &phy_data);
1146 if (ret_val)
1147 return ret_val;
1148 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1149 ret_val =
1150 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1151 phy_data);
1152 if (ret_val)
1153 return ret_val;
1154 /* Set auto Master/Slave resolution process */
1155 ret_val =
1156 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1157 if (ret_val)
1158 return ret_val;
1159 phy_data &= ~CR_1000T_MS_ENABLE;
1160 ret_val =
1161 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1162 if (ret_val)
1163 return ret_val;
1164 }
1165
1166 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1167 if (ret_val)
1168 return ret_val;
1169
1170 /* load defaults for future use */
1171 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1172 ((phy_data & CR_1000T_MS_VALUE) ?
1173 e1000_ms_force_master :
1174 e1000_ms_force_slave) : e1000_ms_auto;
1175
1176 switch (phy_ms_setting) {
1177 case e1000_ms_force_master:
1178 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1179 break;
1180 case e1000_ms_force_slave:
1181 phy_data |= CR_1000T_MS_ENABLE;
1182 phy_data &= ~(CR_1000T_MS_VALUE);
1183 break;
1184 case e1000_ms_auto:
1185 phy_data &= ~CR_1000T_MS_ENABLE;
1186 break;
1187 default:
1188 break;
1189 }
1190 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1191 if (ret_val)
1192 return ret_val;
1193 }
1194
1195 return E1000_SUCCESS;
1196}
1197
1198/**
1199 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1200 * @hw: Struct containing variables accessed by shared code
1201 */
1202static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1203{
1204 s32 ret_val;
1205 u16 phy_data;
1206
1207 if (hw->phy_reset_disable)
1208 return E1000_SUCCESS;
1209
1210 /* Enable CRS on TX. This must be set for half-duplex operation. */
1211 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1212 if (ret_val)
1213 return ret_val;
1214
1215 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1216
1217 /* Options:
1218 * MDI/MDI-X = 0 (default)
1219 * 0 - Auto for all speeds
1220 * 1 - MDI mode
1221 * 2 - MDI-X mode
1222 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1223 */
1224 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1225
1226 switch (hw->mdix) {
1227 case 1:
1228 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1229 break;
1230 case 2:
1231 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1232 break;
1233 case 3:
1234 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1235 break;
1236 case 0:
1237 default:
1238 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1239 break;
1240 }
1241
1242 /* Options:
1243 * disable_polarity_correction = 0 (default)
1244 * Automatic Correction for Reversed Cable Polarity
1245 * 0 - Disabled
1246 * 1 - Enabled
1247 */
1248 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1249 if (hw->disable_polarity_correction == 1)
1250 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1251 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1252 if (ret_val)
1253 return ret_val;
1254
1255 if (hw->phy_revision < M88E1011_I_REV_4) {
1256 /* Force TX_CLK in the Extended PHY Specific Control Register
1257 * to 25MHz clock.
1258 */
1259 ret_val =
1260 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1261 &phy_data);
1262 if (ret_val)
1263 return ret_val;
1264
1265 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1266
1267 if ((hw->phy_revision == E1000_REVISION_2) &&
1268 (hw->phy_id == M88E1111_I_PHY_ID)) {
1269 /* Vidalia Phy, set the downshift counter to 5x */
1270 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1271 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1272 ret_val = e1000_write_phy_reg(hw,
1273 M88E1000_EXT_PHY_SPEC_CTRL,
1274 phy_data);
1275 if (ret_val)
1276 return ret_val;
1277 } else {
1278 /* Configure Master and Slave downshift values */
1279 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1280 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1281 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1282 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1283 ret_val = e1000_write_phy_reg(hw,
1284 M88E1000_EXT_PHY_SPEC_CTRL,
1285 phy_data);
1286 if (ret_val)
1287 return ret_val;
1288 }
1289 }
1290
1291 /* SW Reset the PHY so all changes take effect */
1292 ret_val = e1000_phy_reset(hw);
1293 if (ret_val) {
1294 e_dbg("Error Resetting the PHY\n");
1295 return ret_val;
1296 }
1297
1298 return E1000_SUCCESS;
1299}
1300
1301/**
1302 * e1000_copper_link_autoneg - setup auto-neg
1303 * @hw: Struct containing variables accessed by shared code
1304 *
1305 * Setup auto-negotiation and flow control advertisements,
1306 * and then perform auto-negotiation.
1307 */
1308static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1309{
1310 s32 ret_val;
1311 u16 phy_data;
1312
1313 /* Perform some bounds checking on the hw->autoneg_advertised
1314 * parameter. If this variable is zero, then set it to the default.
1315 */
1316 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1317
1318 /* If autoneg_advertised is zero, we assume it was not defaulted
1319 * by the calling code so we set to advertise full capability.
1320 */
1321 if (hw->autoneg_advertised == 0)
1322 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1323
1324 /* IFE/RTL8201N PHY only supports 10/100 */
1325 if (hw->phy_type == e1000_phy_8201)
1326 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1327
1328 e_dbg("Reconfiguring auto-neg advertisement params\n");
1329 ret_val = e1000_phy_setup_autoneg(hw);
1330 if (ret_val) {
1331 e_dbg("Error Setting up Auto-Negotiation\n");
1332 return ret_val;
1333 }
1334 e_dbg("Restarting Auto-Neg\n");
1335
1336 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1337 * the Auto Neg Restart bit in the PHY control register.
1338 */
1339 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1340 if (ret_val)
1341 return ret_val;
1342
1343 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1344 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1345 if (ret_val)
1346 return ret_val;
1347
1348 /* Does the user want to wait for Auto-Neg to complete here, or
1349 * check at a later time (for example, callback routine).
1350 */
1351 if (hw->wait_autoneg_complete) {
1352 ret_val = e1000_wait_autoneg(hw);
1353 if (ret_val) {
1354 e_dbg
1355 ("Error while waiting for autoneg to complete\n");
1356 return ret_val;
1357 }
1358 }
1359
1360 hw->get_link_status = true;
1361
1362 return E1000_SUCCESS;
1363}
1364
1365/**
1366 * e1000_copper_link_postconfig - post link setup
1367 * @hw: Struct containing variables accessed by shared code
1368 *
1369 * Config the MAC and the PHY after link is up.
1370 * 1) Set up the MAC to the current PHY speed/duplex
1371 * if we are on 82543. If we
1372 * are on newer silicon, we only need to configure
1373 * collision distance in the Transmit Control Register.
1374 * 2) Set up flow control on the MAC to that established with
1375 * the link partner.
1376 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1377 */
1378static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1379{
1380 s32 ret_val;
1381
1382 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1383 e1000_config_collision_dist(hw);
1384 } else {
1385 ret_val = e1000_config_mac_to_phy(hw);
1386 if (ret_val) {
1387 e_dbg("Error configuring MAC to PHY settings\n");
1388 return ret_val;
1389 }
1390 }
1391 ret_val = e1000_config_fc_after_link_up(hw);
1392 if (ret_val) {
1393 e_dbg("Error Configuring Flow Control\n");
1394 return ret_val;
1395 }
1396
1397 /* Config DSP to improve Giga link quality */
1398 if (hw->phy_type == e1000_phy_igp) {
1399 ret_val = e1000_config_dsp_after_link_change(hw, true);
1400 if (ret_val) {
1401 e_dbg("Error Configuring DSP after link up\n");
1402 return ret_val;
1403 }
1404 }
1405
1406 return E1000_SUCCESS;
1407}
1408
1409/**
1410 * e1000_setup_copper_link - phy/speed/duplex setting
1411 * @hw: Struct containing variables accessed by shared code
1412 *
1413 * Detects which PHY is present and sets up the speed and duplex
1414 */
1415static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1416{
1417 s32 ret_val;
1418 u16 i;
1419 u16 phy_data;
1420
1421 /* Check if it is a valid PHY and set PHY mode if necessary. */
1422 ret_val = e1000_copper_link_preconfig(hw);
1423 if (ret_val)
1424 return ret_val;
1425
1426 if (hw->phy_type == e1000_phy_igp) {
1427 ret_val = e1000_copper_link_igp_setup(hw);
1428 if (ret_val)
1429 return ret_val;
1430 } else if (hw->phy_type == e1000_phy_m88) {
1431 ret_val = e1000_copper_link_mgp_setup(hw);
1432 if (ret_val)
1433 return ret_val;
1434 } else {
1435 ret_val = gbe_dhg_phy_setup(hw);
1436 if (ret_val) {
1437 e_dbg("gbe_dhg_phy_setup failed!\n");
1438 return ret_val;
1439 }
1440 }
1441
1442 if (hw->autoneg) {
1443 /* Setup autoneg and flow control advertisement
1444 * and perform autonegotiation
1445 */
1446 ret_val = e1000_copper_link_autoneg(hw);
1447 if (ret_val)
1448 return ret_val;
1449 } else {
1450 /* PHY will be set to 10H, 10F, 100H,or 100F
1451 * depending on value from forced_speed_duplex.
1452 */
1453 e_dbg("Forcing speed and duplex\n");
1454 ret_val = e1000_phy_force_speed_duplex(hw);
1455 if (ret_val) {
1456 e_dbg("Error Forcing Speed and Duplex\n");
1457 return ret_val;
1458 }
1459 }
1460
1461 /* Check link status. Wait up to 100 microseconds for link to become
1462 * valid.
1463 */
1464 for (i = 0; i < 10; i++) {
1465 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1466 if (ret_val)
1467 return ret_val;
1468 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1469 if (ret_val)
1470 return ret_val;
1471
1472 if (phy_data & MII_SR_LINK_STATUS) {
1473 /* Config the MAC and PHY after link is up */
1474 ret_val = e1000_copper_link_postconfig(hw);
1475 if (ret_val)
1476 return ret_val;
1477
1478 e_dbg("Valid link established!!!\n");
1479 return E1000_SUCCESS;
1480 }
1481 udelay(10);
1482 }
1483
1484 e_dbg("Unable to establish link!!!\n");
1485 return E1000_SUCCESS;
1486}
1487
1488/**
1489 * e1000_phy_setup_autoneg - phy settings
1490 * @hw: Struct containing variables accessed by shared code
1491 *
1492 * Configures PHY autoneg and flow control advertisement settings
1493 */
1494s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1495{
1496 s32 ret_val;
1497 u16 mii_autoneg_adv_reg;
1498 u16 mii_1000t_ctrl_reg;
1499
1500 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1501 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1502 if (ret_val)
1503 return ret_val;
1504
1505 /* Read the MII 1000Base-T Control Register (Address 9). */
1506 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1507 if (ret_val)
1508 return ret_val;
1509 else if (hw->phy_type == e1000_phy_8201)
1510 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1511
1512 /* Need to parse both autoneg_advertised and fc and set up
1513 * the appropriate PHY registers. First we will parse for
1514 * autoneg_advertised software override. Since we can advertise
1515 * a plethora of combinations, we need to check each bit
1516 * individually.
1517 */
1518
1519 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1520 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1521 * the 1000Base-T Control Register (Address 9).
1522 */
1523 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1524 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1525
1526 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1527
1528 /* Do we want to advertise 10 Mb Half Duplex? */
1529 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1530 e_dbg("Advertise 10mb Half duplex\n");
1531 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1532 }
1533
1534 /* Do we want to advertise 10 Mb Full Duplex? */
1535 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1536 e_dbg("Advertise 10mb Full duplex\n");
1537 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1538 }
1539
1540 /* Do we want to advertise 100 Mb Half Duplex? */
1541 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1542 e_dbg("Advertise 100mb Half duplex\n");
1543 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1544 }
1545
1546 /* Do we want to advertise 100 Mb Full Duplex? */
1547 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1548 e_dbg("Advertise 100mb Full duplex\n");
1549 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1550 }
1551
1552 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1553 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1554 e_dbg
1555 ("Advertise 1000mb Half duplex requested, request denied!\n");
1556 }
1557
1558 /* Do we want to advertise 1000 Mb Full Duplex? */
1559 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1560 e_dbg("Advertise 1000mb Full duplex\n");
1561 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1562 }
1563
1564 /* Check for a software override of the flow control settings, and
1565 * setup the PHY advertisement registers accordingly. If
1566 * auto-negotiation is enabled, then software will have to set the
1567 * "PAUSE" bits to the correct value in the Auto-Negotiation
1568 * Advertisement Register (PHY_AUTONEG_ADV) and re-start
1569 * auto-negotiation.
1570 *
1571 * The possible values of the "fc" parameter are:
1572 * 0: Flow control is completely disabled
1573 * 1: Rx flow control is enabled (we can receive pause frames
1574 * but not send pause frames).
1575 * 2: Tx flow control is enabled (we can send pause frames
1576 * but we do not support receiving pause frames).
1577 * 3: Both Rx and TX flow control (symmetric) are enabled.
1578 * other: No software override. The flow control configuration
1579 * in the EEPROM is used.
1580 */
1581 switch (hw->fc) {
1582 case E1000_FC_NONE: /* 0 */
1583 /* Flow control (RX & TX) is completely disabled by a
1584 * software over-ride.
1585 */
1586 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1587 break;
1588 case E1000_FC_RX_PAUSE: /* 1 */
1589 /* RX Flow control is enabled, and TX Flow control is
1590 * disabled, by a software over-ride.
1591 */
1592 /* Since there really isn't a way to advertise that we are
1593 * capable of RX Pause ONLY, we will advertise that we
1594 * support both symmetric and asymmetric RX PAUSE. Later
1595 * (in e1000_config_fc_after_link_up) we will disable the
1596 * hw's ability to send PAUSE frames.
1597 */
1598 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1599 break;
1600 case E1000_FC_TX_PAUSE: /* 2 */
1601 /* TX Flow control is enabled, and RX Flow control is
1602 * disabled, by a software over-ride.
1603 */
1604 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1605 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1606 break;
1607 case E1000_FC_FULL: /* 3 */
1608 /* Flow control (both RX and TX) is enabled by a software
1609 * over-ride.
1610 */
1611 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1612 break;
1613 default:
1614 e_dbg("Flow control param set incorrectly\n");
1615 return -E1000_ERR_CONFIG;
1616 }
1617
1618 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1619 if (ret_val)
1620 return ret_val;
1621
1622 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1623
1624 if (hw->phy_type == e1000_phy_8201) {
1625 mii_1000t_ctrl_reg = 0;
1626 } else {
1627 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1628 mii_1000t_ctrl_reg);
1629 if (ret_val)
1630 return ret_val;
1631 }
1632
1633 return E1000_SUCCESS;
1634}
1635
1636/**
1637 * e1000_phy_force_speed_duplex - force link settings
1638 * @hw: Struct containing variables accessed by shared code
1639 *
1640 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1641 */
1642static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1643{
1644 u32 ctrl;
1645 s32 ret_val;
1646 u16 mii_ctrl_reg;
1647 u16 mii_status_reg;
1648 u16 phy_data;
1649 u16 i;
1650
1651 /* Turn off Flow control if we are forcing speed and duplex. */
1652 hw->fc = E1000_FC_NONE;
1653
1654 e_dbg("hw->fc = %d\n", hw->fc);
1655
1656 /* Read the Device Control Register. */
1657 ctrl = er32(CTRL);
1658
1659 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1660 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1661 ctrl &= ~(DEVICE_SPEED_MASK);
1662
1663 /* Clear the Auto Speed Detect Enable bit. */
1664 ctrl &= ~E1000_CTRL_ASDE;
1665
1666 /* Read the MII Control Register. */
1667 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1668 if (ret_val)
1669 return ret_val;
1670
1671 /* We need to disable autoneg in order to force link and duplex. */
1672
1673 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1674
1675 /* Are we forcing Full or Half Duplex? */
1676 if (hw->forced_speed_duplex == e1000_100_full ||
1677 hw->forced_speed_duplex == e1000_10_full) {
1678 /* We want to force full duplex so we SET the full duplex bits
1679 * in the Device and MII Control Registers.
1680 */
1681 ctrl |= E1000_CTRL_FD;
1682 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1683 e_dbg("Full Duplex\n");
1684 } else {
1685 /* We want to force half duplex so we CLEAR the full duplex bits
1686 * in the Device and MII Control Registers.
1687 */
1688 ctrl &= ~E1000_CTRL_FD;
1689 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1690 e_dbg("Half Duplex\n");
1691 }
1692
1693 /* Are we forcing 100Mbps??? */
1694 if (hw->forced_speed_duplex == e1000_100_full ||
1695 hw->forced_speed_duplex == e1000_100_half) {
1696 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1697 ctrl |= E1000_CTRL_SPD_100;
1698 mii_ctrl_reg |= MII_CR_SPEED_100;
1699 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1700 e_dbg("Forcing 100mb ");
1701 } else {
1702 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1703 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1704 mii_ctrl_reg |= MII_CR_SPEED_10;
1705 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1706 e_dbg("Forcing 10mb ");
1707 }
1708
1709 e1000_config_collision_dist(hw);
1710
1711 /* Write the configured values back to the Device Control Reg. */
1712 ew32(CTRL, ctrl);
1713
1714 if (hw->phy_type == e1000_phy_m88) {
1715 ret_val =
1716 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1717 if (ret_val)
1718 return ret_val;
1719
1720 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires
1721 * MDI forced whenever speed are duplex are forced.
1722 */
1723 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1724 ret_val =
1725 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1726 if (ret_val)
1727 return ret_val;
1728
1729 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1730
1731 /* Need to reset the PHY or these changes will be ignored */
1732 mii_ctrl_reg |= MII_CR_RESET;
1733
1734 /* Disable MDI-X support for 10/100 */
1735 } else {
1736 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1737 * forced whenever speed or duplex are forced.
1738 */
1739 ret_val =
1740 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1741 if (ret_val)
1742 return ret_val;
1743
1744 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1745 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1746
1747 ret_val =
1748 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1749 if (ret_val)
1750 return ret_val;
1751 }
1752
1753 /* Write back the modified PHY MII control register. */
1754 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1755 if (ret_val)
1756 return ret_val;
1757
1758 udelay(1);
1759
1760 /* The wait_autoneg_complete flag may be a little misleading here.
1761 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1762 * But we do want to delay for a period while forcing only so we
1763 * don't generate false No Link messages. So we will wait here
1764 * only if the user has set wait_autoneg_complete to 1, which is
1765 * the default.
1766 */
1767 if (hw->wait_autoneg_complete) {
1768 /* We will wait for autoneg to complete. */
1769 e_dbg("Waiting for forced speed/duplex link.\n");
1770 mii_status_reg = 0;
1771
1772 /* Wait for autoneg to complete or 4.5 seconds to expire */
1773 for (i = PHY_FORCE_TIME; i > 0; i--) {
1774 /* Read the MII Status Register and wait for Auto-Neg
1775 * Complete bit to be set.
1776 */
1777 ret_val =
1778 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1779 if (ret_val)
1780 return ret_val;
1781
1782 ret_val =
1783 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1784 if (ret_val)
1785 return ret_val;
1786
1787 if (mii_status_reg & MII_SR_LINK_STATUS)
1788 break;
1789 msleep(100);
1790 }
1791 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1792 /* We didn't get link. Reset the DSP and wait again
1793 * for link.
1794 */
1795 ret_val = e1000_phy_reset_dsp(hw);
1796 if (ret_val) {
1797 e_dbg("Error Resetting PHY DSP\n");
1798 return ret_val;
1799 }
1800 }
1801 /* This loop will early-out if the link condition has been
1802 * met
1803 */
1804 for (i = PHY_FORCE_TIME; i > 0; i--) {
1805 if (mii_status_reg & MII_SR_LINK_STATUS)
1806 break;
1807 msleep(100);
1808 /* Read the MII Status Register and wait for Auto-Neg
1809 * Complete bit to be set.
1810 */
1811 ret_val =
1812 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1813 if (ret_val)
1814 return ret_val;
1815
1816 ret_val =
1817 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1818 if (ret_val)
1819 return ret_val;
1820 }
1821 }
1822
1823 if (hw->phy_type == e1000_phy_m88) {
1824 /* Because we reset the PHY above, we need to re-force TX_CLK in
1825 * the Extended PHY Specific Control Register to 25MHz clock.
1826 * This value defaults back to a 2.5MHz clock when the PHY is
1827 * reset.
1828 */
1829 ret_val =
1830 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1831 &phy_data);
1832 if (ret_val)
1833 return ret_val;
1834
1835 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1836 ret_val =
1837 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1838 phy_data);
1839 if (ret_val)
1840 return ret_val;
1841
1842 /* In addition, because of the s/w reset above, we need to
1843 * enable CRS on Tx. This must be set for both full and half
1844 * duplex operation.
1845 */
1846 ret_val =
1847 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1848 if (ret_val)
1849 return ret_val;
1850
1851 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1852 ret_val =
1853 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1854 if (ret_val)
1855 return ret_val;
1856
1857 if ((hw->mac_type == e1000_82544 ||
1858 hw->mac_type == e1000_82543) &&
1859 (!hw->autoneg) &&
1860 (hw->forced_speed_duplex == e1000_10_full ||
1861 hw->forced_speed_duplex == e1000_10_half)) {
1862 ret_val = e1000_polarity_reversal_workaround(hw);
1863 if (ret_val)
1864 return ret_val;
1865 }
1866 }
1867 return E1000_SUCCESS;
1868}
1869
1870/**
1871 * e1000_config_collision_dist - set collision distance register
1872 * @hw: Struct containing variables accessed by shared code
1873 *
1874 * Sets the collision distance in the Transmit Control register.
1875 * Link should have been established previously. Reads the speed and duplex
1876 * information from the Device Status register.
1877 */
1878void e1000_config_collision_dist(struct e1000_hw *hw)
1879{
1880 u32 tctl, coll_dist;
1881
1882 if (hw->mac_type < e1000_82543)
1883 coll_dist = E1000_COLLISION_DISTANCE_82542;
1884 else
1885 coll_dist = E1000_COLLISION_DISTANCE;
1886
1887 tctl = er32(TCTL);
1888
1889 tctl &= ~E1000_TCTL_COLD;
1890 tctl |= coll_dist << E1000_COLD_SHIFT;
1891
1892 ew32(TCTL, tctl);
1893 E1000_WRITE_FLUSH();
1894}
1895
1896/**
1897 * e1000_config_mac_to_phy - sync phy and mac settings
1898 * @hw: Struct containing variables accessed by shared code
1899 *
1900 * Sets MAC speed and duplex settings to reflect the those in the PHY
1901 * The contents of the PHY register containing the needed information need to
1902 * be passed in.
1903 */
1904static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1905{
1906 u32 ctrl;
1907 s32 ret_val;
1908 u16 phy_data;
1909
1910 /* 82544 or newer MAC, Auto Speed Detection takes care of
1911 * MAC speed/duplex configuration.
1912 */
1913 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1914 return E1000_SUCCESS;
1915
1916 /* Read the Device Control Register and set the bits to Force Speed
1917 * and Duplex.
1918 */
1919 ctrl = er32(CTRL);
1920 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1921 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1922
1923 switch (hw->phy_type) {
1924 case e1000_phy_8201:
1925 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1926 if (ret_val)
1927 return ret_val;
1928
1929 if (phy_data & RTL_PHY_CTRL_FD)
1930 ctrl |= E1000_CTRL_FD;
1931 else
1932 ctrl &= ~E1000_CTRL_FD;
1933
1934 if (phy_data & RTL_PHY_CTRL_SPD_100)
1935 ctrl |= E1000_CTRL_SPD_100;
1936 else
1937 ctrl |= E1000_CTRL_SPD_10;
1938
1939 e1000_config_collision_dist(hw);
1940 break;
1941 default:
1942 /* Set up duplex in the Device Control and Transmit Control
1943 * registers depending on negotiated values.
1944 */
1945 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1946 &phy_data);
1947 if (ret_val)
1948 return ret_val;
1949
1950 if (phy_data & M88E1000_PSSR_DPLX)
1951 ctrl |= E1000_CTRL_FD;
1952 else
1953 ctrl &= ~E1000_CTRL_FD;
1954
1955 e1000_config_collision_dist(hw);
1956
1957 /* Set up speed in the Device Control register depending on
1958 * negotiated values.
1959 */
1960 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1961 ctrl |= E1000_CTRL_SPD_1000;
1962 else if ((phy_data & M88E1000_PSSR_SPEED) ==
1963 M88E1000_PSSR_100MBS)
1964 ctrl |= E1000_CTRL_SPD_100;
1965 }
1966
1967 /* Write the configured values back to the Device Control Reg. */
1968 ew32(CTRL, ctrl);
1969 return E1000_SUCCESS;
1970}
1971
1972/**
1973 * e1000_force_mac_fc - force flow control settings
1974 * @hw: Struct containing variables accessed by shared code
1975 *
1976 * Forces the MAC's flow control settings.
1977 * Sets the TFCE and RFCE bits in the device control register to reflect
1978 * the adapter settings. TFCE and RFCE need to be explicitly set by
1979 * software when a Copper PHY is used because autonegotiation is managed
1980 * by the PHY rather than the MAC. Software must also configure these
1981 * bits when link is forced on a fiber connection.
1982 */
1983s32 e1000_force_mac_fc(struct e1000_hw *hw)
1984{
1985 u32 ctrl;
1986
1987 /* Get the current configuration of the Device Control Register */
1988 ctrl = er32(CTRL);
1989
1990 /* Because we didn't get link via the internal auto-negotiation
1991 * mechanism (we either forced link or we got link via PHY
1992 * auto-neg), we have to manually enable/disable transmit an
1993 * receive flow control.
1994 *
1995 * The "Case" statement below enables/disable flow control
1996 * according to the "hw->fc" parameter.
1997 *
1998 * The possible values of the "fc" parameter are:
1999 * 0: Flow control is completely disabled
2000 * 1: Rx flow control is enabled (we can receive pause
2001 * frames but not send pause frames).
2002 * 2: Tx flow control is enabled (we can send pause frames
2003 * frames but we do not receive pause frames).
2004 * 3: Both Rx and TX flow control (symmetric) is enabled.
2005 * other: No other values should be possible at this point.
2006 */
2007
2008 switch (hw->fc) {
2009 case E1000_FC_NONE:
2010 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2011 break;
2012 case E1000_FC_RX_PAUSE:
2013 ctrl &= (~E1000_CTRL_TFCE);
2014 ctrl |= E1000_CTRL_RFCE;
2015 break;
2016 case E1000_FC_TX_PAUSE:
2017 ctrl &= (~E1000_CTRL_RFCE);
2018 ctrl |= E1000_CTRL_TFCE;
2019 break;
2020 case E1000_FC_FULL:
2021 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2022 break;
2023 default:
2024 e_dbg("Flow control param set incorrectly\n");
2025 return -E1000_ERR_CONFIG;
2026 }
2027
2028 /* Disable TX Flow Control for 82542 (rev 2.0) */
2029 if (hw->mac_type == e1000_82542_rev2_0)
2030 ctrl &= (~E1000_CTRL_TFCE);
2031
2032 ew32(CTRL, ctrl);
2033 return E1000_SUCCESS;
2034}
2035
2036/**
2037 * e1000_config_fc_after_link_up - configure flow control after autoneg
2038 * @hw: Struct containing variables accessed by shared code
2039 *
2040 * Configures flow control settings after link is established
2041 * Should be called immediately after a valid link has been established.
2042 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2043 * and autonegotiation is enabled, the MAC flow control settings will be set
2044 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2045 * and RFCE bits will be automatically set to the negotiated flow control mode.
2046 */
2047static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2048{
2049 s32 ret_val;
2050 u16 mii_status_reg;
2051 u16 mii_nway_adv_reg;
2052 u16 mii_nway_lp_ability_reg;
2053 u16 speed;
2054 u16 duplex;
2055
2056 /* Check for the case where we have fiber media and auto-neg failed
2057 * so we had to force link. In this case, we need to force the
2058 * configuration of the MAC to match the "fc" parameter.
2059 */
2060 if (((hw->media_type == e1000_media_type_fiber) &&
2061 (hw->autoneg_failed)) ||
2062 ((hw->media_type == e1000_media_type_internal_serdes) &&
2063 (hw->autoneg_failed)) ||
2064 ((hw->media_type == e1000_media_type_copper) &&
2065 (!hw->autoneg))) {
2066 ret_val = e1000_force_mac_fc(hw);
2067 if (ret_val) {
2068 e_dbg("Error forcing flow control settings\n");
2069 return ret_val;
2070 }
2071 }
2072
2073 /* Check for the case where we have copper media and auto-neg is
2074 * enabled. In this case, we need to check and see if Auto-Neg
2075 * has completed, and if so, how the PHY and link partner has
2076 * flow control configured.
2077 */
2078 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2079 /* Read the MII Status Register and check to see if AutoNeg
2080 * has completed. We read this twice because this reg has
2081 * some "sticky" (latched) bits.
2082 */
2083 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2084 if (ret_val)
2085 return ret_val;
2086 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2087 if (ret_val)
2088 return ret_val;
2089
2090 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2091 /* The AutoNeg process has completed, so we now need to
2092 * read both the Auto Negotiation Advertisement Register
2093 * (Address 4) and the Auto_Negotiation Base Page
2094 * Ability Register (Address 5) to determine how flow
2095 * control was negotiated.
2096 */
2097 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2098 &mii_nway_adv_reg);
2099 if (ret_val)
2100 return ret_val;
2101 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2102 &mii_nway_lp_ability_reg);
2103 if (ret_val)
2104 return ret_val;
2105
2106 /* Two bits in the Auto Negotiation Advertisement
2107 * Register (Address 4) and two bits in the Auto
2108 * Negotiation Base Page Ability Register (Address 5)
2109 * determine flow control for both the PHY and the link
2110 * partner. The following table, taken out of the IEEE
2111 * 802.3ab/D6.0 dated March 25, 1999, describes these
2112 * PAUSE resolution bits and how flow control is
2113 * determined based upon these settings.
2114 * NOTE: DC = Don't Care
2115 *
2116 * LOCAL DEVICE | LINK PARTNER
2117 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2118 *-------|---------|-------|---------|------------------
2119 * 0 | 0 | DC | DC | E1000_FC_NONE
2120 * 0 | 1 | 0 | DC | E1000_FC_NONE
2121 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2122 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2123 * 1 | 0 | 0 | DC | E1000_FC_NONE
2124 * 1 | DC | 1 | DC | E1000_FC_FULL
2125 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2126 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2127 *
2128 */
2129 /* Are both PAUSE bits set to 1? If so, this implies
2130 * Symmetric Flow Control is enabled at both ends. The
2131 * ASM_DIR bits are irrelevant per the spec.
2132 *
2133 * For Symmetric Flow Control:
2134 *
2135 * LOCAL DEVICE | LINK PARTNER
2136 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2137 *-------|---------|-------|---------|------------------
2138 * 1 | DC | 1 | DC | E1000_FC_FULL
2139 *
2140 */
2141 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2142 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2143 /* Now we need to check if the user selected Rx
2144 * ONLY of pause frames. In this case, we had
2145 * to advertise FULL flow control because we
2146 * could not advertise Rx ONLY. Hence, we must
2147 * now check to see if we need to turn OFF the
2148 * TRANSMISSION of PAUSE frames.
2149 */
2150 if (hw->original_fc == E1000_FC_FULL) {
2151 hw->fc = E1000_FC_FULL;
2152 e_dbg("Flow Control = FULL.\n");
2153 } else {
2154 hw->fc = E1000_FC_RX_PAUSE;
2155 e_dbg
2156 ("Flow Control = RX PAUSE frames only.\n");
2157 }
2158 }
2159 /* For receiving PAUSE frames ONLY.
2160 *
2161 * LOCAL DEVICE | LINK PARTNER
2162 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2163 *-------|---------|-------|---------|------------------
2164 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2165 *
2166 */
2167 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2168 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2169 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2170 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2171 hw->fc = E1000_FC_TX_PAUSE;
2172 e_dbg
2173 ("Flow Control = TX PAUSE frames only.\n");
2174 }
2175 /* For transmitting PAUSE frames ONLY.
2176 *
2177 * LOCAL DEVICE | LINK PARTNER
2178 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2179 *-------|---------|-------|---------|------------------
2180 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2181 *
2182 */
2183 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2184 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2185 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2186 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2187 hw->fc = E1000_FC_RX_PAUSE;
2188 e_dbg
2189 ("Flow Control = RX PAUSE frames only.\n");
2190 }
2191 /* Per the IEEE spec, at this point flow control should
2192 * be disabled. However, we want to consider that we
2193 * could be connected to a legacy switch that doesn't
2194 * advertise desired flow control, but can be forced on
2195 * the link partner. So if we advertised no flow
2196 * control, that is what we will resolve to. If we
2197 * advertised some kind of receive capability (Rx Pause
2198 * Only or Full Flow Control) and the link partner
2199 * advertised none, we will configure ourselves to
2200 * enable Rx Flow Control only. We can do this safely
2201 * for two reasons: If the link partner really
2202 * didn't want flow control enabled, and we enable Rx,
2203 * no harm done since we won't be receiving any PAUSE
2204 * frames anyway. If the intent on the link partner was
2205 * to have flow control enabled, then by us enabling Rx
2206 * only, we can at least receive pause frames and
2207 * process them. This is a good idea because in most
2208 * cases, since we are predominantly a server NIC, more
2209 * times than not we will be asked to delay transmission
2210 * of packets than asking our link partner to pause
2211 * transmission of frames.
2212 */
2213 else if ((hw->original_fc == E1000_FC_NONE ||
2214 hw->original_fc == E1000_FC_TX_PAUSE) ||
2215 hw->fc_strict_ieee) {
2216 hw->fc = E1000_FC_NONE;
2217 e_dbg("Flow Control = NONE.\n");
2218 } else {
2219 hw->fc = E1000_FC_RX_PAUSE;
2220 e_dbg
2221 ("Flow Control = RX PAUSE frames only.\n");
2222 }
2223
2224 /* Now we need to do one last check... If we auto-
2225 * negotiated to HALF DUPLEX, flow control should not be
2226 * enabled per IEEE 802.3 spec.
2227 */
2228 ret_val =
2229 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2230 if (ret_val) {
2231 e_dbg
2232 ("Error getting link speed and duplex\n");
2233 return ret_val;
2234 }
2235
2236 if (duplex == HALF_DUPLEX)
2237 hw->fc = E1000_FC_NONE;
2238
2239 /* Now we call a subroutine to actually force the MAC
2240 * controller to use the correct flow control settings.
2241 */
2242 ret_val = e1000_force_mac_fc(hw);
2243 if (ret_val) {
2244 e_dbg
2245 ("Error forcing flow control settings\n");
2246 return ret_val;
2247 }
2248 } else {
2249 e_dbg
2250 ("Copper PHY and Auto Neg has not completed.\n");
2251 }
2252 }
2253 return E1000_SUCCESS;
2254}
2255
2256/**
2257 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2258 * @hw: pointer to the HW structure
2259 *
2260 * Checks for link up on the hardware. If link is not up and we have
2261 * a signal, then we need to force link up.
2262 */
2263static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2264{
2265 u32 rxcw;
2266 u32 ctrl;
2267 u32 status;
2268 s32 ret_val = E1000_SUCCESS;
2269
2270 ctrl = er32(CTRL);
2271 status = er32(STATUS);
2272 rxcw = er32(RXCW);
2273
2274 /* If we don't have link (auto-negotiation failed or link partner
2275 * cannot auto-negotiate), and our link partner is not trying to
2276 * auto-negotiate with us (we are receiving idles or data),
2277 * we need to force link up. We also need to give auto-negotiation
2278 * time to complete.
2279 */
2280 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2281 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2282 if (hw->autoneg_failed == 0) {
2283 hw->autoneg_failed = 1;
2284 goto out;
2285 }
2286 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2287
2288 /* Disable auto-negotiation in the TXCW register */
2289 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2290
2291 /* Force link-up and also force full-duplex. */
2292 ctrl = er32(CTRL);
2293 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2294 ew32(CTRL, ctrl);
2295
2296 /* Configure Flow Control after forcing link up. */
2297 ret_val = e1000_config_fc_after_link_up(hw);
2298 if (ret_val) {
2299 e_dbg("Error configuring flow control\n");
2300 goto out;
2301 }
2302 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2303 /* If we are forcing link and we are receiving /C/ ordered
2304 * sets, re-enable auto-negotiation in the TXCW register
2305 * and disable forced link in the Device Control register
2306 * in an attempt to auto-negotiate with our link partner.
2307 */
2308 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2309 ew32(TXCW, hw->txcw);
2310 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2311
2312 hw->serdes_has_link = true;
2313 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2314 /* If we force link for non-auto-negotiation switch, check
2315 * link status based on MAC synchronization for internal
2316 * serdes media type.
2317 */
2318 /* SYNCH bit and IV bit are sticky. */
2319 udelay(10);
2320 rxcw = er32(RXCW);
2321 if (rxcw & E1000_RXCW_SYNCH) {
2322 if (!(rxcw & E1000_RXCW_IV)) {
2323 hw->serdes_has_link = true;
2324 e_dbg("SERDES: Link up - forced.\n");
2325 }
2326 } else {
2327 hw->serdes_has_link = false;
2328 e_dbg("SERDES: Link down - force failed.\n");
2329 }
2330 }
2331
2332 if (E1000_TXCW_ANE & er32(TXCW)) {
2333 status = er32(STATUS);
2334 if (status & E1000_STATUS_LU) {
2335 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2336 udelay(10);
2337 rxcw = er32(RXCW);
2338 if (rxcw & E1000_RXCW_SYNCH) {
2339 if (!(rxcw & E1000_RXCW_IV)) {
2340 hw->serdes_has_link = true;
2341 e_dbg("SERDES: Link up - autoneg "
2342 "completed successfully.\n");
2343 } else {
2344 hw->serdes_has_link = false;
2345 e_dbg("SERDES: Link down - invalid"
2346 "codewords detected in autoneg.\n");
2347 }
2348 } else {
2349 hw->serdes_has_link = false;
2350 e_dbg("SERDES: Link down - no sync.\n");
2351 }
2352 } else {
2353 hw->serdes_has_link = false;
2354 e_dbg("SERDES: Link down - autoneg failed\n");
2355 }
2356 }
2357
2358 out:
2359 return ret_val;
2360}
2361
2362/**
2363 * e1000_check_for_link
2364 * @hw: Struct containing variables accessed by shared code
2365 *
2366 * Checks to see if the link status of the hardware has changed.
2367 * Called by any function that needs to check the link status of the adapter.
2368 */
2369s32 e1000_check_for_link(struct e1000_hw *hw)
2370{
2371 u32 status;
2372 u32 rctl;
2373 u32 icr;
2374 s32 ret_val;
2375 u16 phy_data;
2376
2377 er32(CTRL);
2378 status = er32(STATUS);
2379
2380 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2381 * set when the optics detect a signal. On older adapters, it will be
2382 * cleared when there is a signal. This applies to fiber media only.
2383 */
2384 if ((hw->media_type == e1000_media_type_fiber) ||
2385 (hw->media_type == e1000_media_type_internal_serdes)) {
2386 er32(RXCW);
2387
2388 if (hw->media_type == e1000_media_type_fiber) {
2389 if (status & E1000_STATUS_LU)
2390 hw->get_link_status = false;
2391 }
2392 }
2393
2394 /* If we have a copper PHY then we only want to go out to the PHY
2395 * registers to see if Auto-Neg has completed and/or if our link
2396 * status has changed. The get_link_status flag will be set if we
2397 * receive a Link Status Change interrupt or we have Rx Sequence
2398 * Errors.
2399 */
2400 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2401 /* First we want to see if the MII Status Register reports
2402 * link. If so, then we want to get the current speed/duplex
2403 * of the PHY.
2404 * Read the register twice since the link bit is sticky.
2405 */
2406 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2407 if (ret_val)
2408 return ret_val;
2409 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2410 if (ret_val)
2411 return ret_val;
2412
2413 if (phy_data & MII_SR_LINK_STATUS) {
2414 hw->get_link_status = false;
2415 /* Check if there was DownShift, must be checked
2416 * immediately after link-up
2417 */
2418 e1000_check_downshift(hw);
2419
2420 /* If we are on 82544 or 82543 silicon and speed/duplex
2421 * are forced to 10H or 10F, then we will implement the
2422 * polarity reversal workaround. We disable interrupts
2423 * first, and upon returning, place the devices
2424 * interrupt state to its previous value except for the
2425 * link status change interrupt which will
2426 * happen due to the execution of this workaround.
2427 */
2428
2429 if ((hw->mac_type == e1000_82544 ||
2430 hw->mac_type == e1000_82543) &&
2431 (!hw->autoneg) &&
2432 (hw->forced_speed_duplex == e1000_10_full ||
2433 hw->forced_speed_duplex == e1000_10_half)) {
2434 ew32(IMC, 0xffffffff);
2435 ret_val =
2436 e1000_polarity_reversal_workaround(hw);
2437 icr = er32(ICR);
2438 ew32(ICS, (icr & ~E1000_ICS_LSC));
2439 ew32(IMS, IMS_ENABLE_MASK);
2440 }
2441
2442 } else {
2443 /* No link detected */
2444 e1000_config_dsp_after_link_change(hw, false);
2445 return 0;
2446 }
2447
2448 /* If we are forcing speed/duplex, then we simply return since
2449 * we have already determined whether we have link or not.
2450 */
2451 if (!hw->autoneg)
2452 return -E1000_ERR_CONFIG;
2453
2454 /* optimize the dsp settings for the igp phy */
2455 e1000_config_dsp_after_link_change(hw, true);
2456
2457 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2458 * have Si on board that is 82544 or newer, Auto
2459 * Speed Detection takes care of MAC speed/duplex
2460 * configuration. So we only need to configure Collision
2461 * Distance in the MAC. Otherwise, we need to force
2462 * speed/duplex on the MAC to the current PHY speed/duplex
2463 * settings.
2464 */
2465 if ((hw->mac_type >= e1000_82544) &&
2466 (hw->mac_type != e1000_ce4100))
2467 e1000_config_collision_dist(hw);
2468 else {
2469 ret_val = e1000_config_mac_to_phy(hw);
2470 if (ret_val) {
2471 e_dbg
2472 ("Error configuring MAC to PHY settings\n");
2473 return ret_val;
2474 }
2475 }
2476
2477 /* Configure Flow Control now that Auto-Neg has completed.
2478 * First, we need to restore the desired flow control settings
2479 * because we may have had to re-autoneg with a different link
2480 * partner.
2481 */
2482 ret_val = e1000_config_fc_after_link_up(hw);
2483 if (ret_val) {
2484 e_dbg("Error configuring flow control\n");
2485 return ret_val;
2486 }
2487
2488 /* At this point we know that we are on copper and we have
2489 * auto-negotiated link. These are conditions for checking the
2490 * link partner capability register. We use the link speed to
2491 * determine if TBI compatibility needs to be turned on or off.
2492 * If the link is not at gigabit speed, then TBI compatibility
2493 * is not needed. If we are at gigabit speed, we turn on TBI
2494 * compatibility.
2495 */
2496 if (hw->tbi_compatibility_en) {
2497 u16 speed, duplex;
2498
2499 ret_val =
2500 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2501
2502 if (ret_val) {
2503 e_dbg
2504 ("Error getting link speed and duplex\n");
2505 return ret_val;
2506 }
2507 if (speed != SPEED_1000) {
2508 /* If link speed is not set to gigabit speed, we
2509 * do not need to enable TBI compatibility.
2510 */
2511 if (hw->tbi_compatibility_on) {
2512 /* If we previously were in the mode,
2513 * turn it off.
2514 */
2515 rctl = er32(RCTL);
2516 rctl &= ~E1000_RCTL_SBP;
2517 ew32(RCTL, rctl);
2518 hw->tbi_compatibility_on = false;
2519 }
2520 } else {
2521 /* If TBI compatibility is was previously off,
2522 * turn it on. For compatibility with a TBI link
2523 * partner, we will store bad packets. Some
2524 * frames have an additional byte on the end and
2525 * will look like CRC errors to the hardware.
2526 */
2527 if (!hw->tbi_compatibility_on) {
2528 hw->tbi_compatibility_on = true;
2529 rctl = er32(RCTL);
2530 rctl |= E1000_RCTL_SBP;
2531 ew32(RCTL, rctl);
2532 }
2533 }
2534 }
2535 }
2536
2537 if ((hw->media_type == e1000_media_type_fiber) ||
2538 (hw->media_type == e1000_media_type_internal_serdes))
2539 e1000_check_for_serdes_link_generic(hw);
2540
2541 return E1000_SUCCESS;
2542}
2543
2544/**
2545 * e1000_get_speed_and_duplex
2546 * @hw: Struct containing variables accessed by shared code
2547 * @speed: Speed of the connection
2548 * @duplex: Duplex setting of the connection
2549 *
2550 * Detects the current speed and duplex settings of the hardware.
2551 */
2552s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2553{
2554 u32 status;
2555 s32 ret_val;
2556 u16 phy_data;
2557
2558 if (hw->mac_type >= e1000_82543) {
2559 status = er32(STATUS);
2560 if (status & E1000_STATUS_SPEED_1000) {
2561 *speed = SPEED_1000;
2562 e_dbg("1000 Mbs, ");
2563 } else if (status & E1000_STATUS_SPEED_100) {
2564 *speed = SPEED_100;
2565 e_dbg("100 Mbs, ");
2566 } else {
2567 *speed = SPEED_10;
2568 e_dbg("10 Mbs, ");
2569 }
2570
2571 if (status & E1000_STATUS_FD) {
2572 *duplex = FULL_DUPLEX;
2573 e_dbg("Full Duplex\n");
2574 } else {
2575 *duplex = HALF_DUPLEX;
2576 e_dbg(" Half Duplex\n");
2577 }
2578 } else {
2579 e_dbg("1000 Mbs, Full Duplex\n");
2580 *speed = SPEED_1000;
2581 *duplex = FULL_DUPLEX;
2582 }
2583
2584 /* IGP01 PHY may advertise full duplex operation after speed downgrade
2585 * even if it is operating at half duplex. Here we set the duplex
2586 * settings to match the duplex in the link partner's capabilities.
2587 */
2588 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2589 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2590 if (ret_val)
2591 return ret_val;
2592
2593 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2594 *duplex = HALF_DUPLEX;
2595 else {
2596 ret_val =
2597 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2598 if (ret_val)
2599 return ret_val;
2600 if ((*speed == SPEED_100 &&
2601 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2602 (*speed == SPEED_10 &&
2603 !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2604 *duplex = HALF_DUPLEX;
2605 }
2606 }
2607
2608 return E1000_SUCCESS;
2609}
2610
2611/**
2612 * e1000_wait_autoneg
2613 * @hw: Struct containing variables accessed by shared code
2614 *
2615 * Blocks until autoneg completes or times out (~4.5 seconds)
2616 */
2617static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2618{
2619 s32 ret_val;
2620 u16 i;
2621 u16 phy_data;
2622
2623 e_dbg("Waiting for Auto-Neg to complete.\n");
2624
2625 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2626 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2627 /* Read the MII Status Register and wait for Auto-Neg
2628 * Complete bit to be set.
2629 */
2630 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2631 if (ret_val)
2632 return ret_val;
2633 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2634 if (ret_val)
2635 return ret_val;
2636 if (phy_data & MII_SR_AUTONEG_COMPLETE)
2637 return E1000_SUCCESS;
2638
2639 msleep(100);
2640 }
2641 return E1000_SUCCESS;
2642}
2643
2644/**
2645 * e1000_raise_mdi_clk - Raises the Management Data Clock
2646 * @hw: Struct containing variables accessed by shared code
2647 * @ctrl: Device control register's current value
2648 */
2649static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2650{
2651 /* Raise the clock input to the Management Data Clock (by setting the
2652 * MDC bit), and then delay 10 microseconds.
2653 */
2654 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2655 E1000_WRITE_FLUSH();
2656 udelay(10);
2657}
2658
2659/**
2660 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2661 * @hw: Struct containing variables accessed by shared code
2662 * @ctrl: Device control register's current value
2663 */
2664static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2665{
2666 /* Lower the clock input to the Management Data Clock (by clearing the
2667 * MDC bit), and then delay 10 microseconds.
2668 */
2669 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2670 E1000_WRITE_FLUSH();
2671 udelay(10);
2672}
2673
2674/**
2675 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2676 * @hw: Struct containing variables accessed by shared code
2677 * @data: Data to send out to the PHY
2678 * @count: Number of bits to shift out
2679 *
2680 * Bits are shifted out in MSB to LSB order.
2681 */
2682static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2683{
2684 u32 ctrl;
2685 u32 mask;
2686
2687 /* We need to shift "count" number of bits out to the PHY. So, the value
2688 * in the "data" parameter will be shifted out to the PHY one bit at a
2689 * time. In order to do this, "data" must be broken down into bits.
2690 */
2691 mask = 0x01;
2692 mask <<= (count - 1);
2693
2694 ctrl = er32(CTRL);
2695
2696 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2697 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2698
2699 while (mask) {
2700 /* A "1" is shifted out to the PHY by setting the MDIO bit to
2701 * "1" and then raising and lowering the Management Data Clock.
2702 * A "0" is shifted out to the PHY by setting the MDIO bit to
2703 * "0" and then raising and lowering the clock.
2704 */
2705 if (data & mask)
2706 ctrl |= E1000_CTRL_MDIO;
2707 else
2708 ctrl &= ~E1000_CTRL_MDIO;
2709
2710 ew32(CTRL, ctrl);
2711 E1000_WRITE_FLUSH();
2712
2713 udelay(10);
2714
2715 e1000_raise_mdi_clk(hw, &ctrl);
2716 e1000_lower_mdi_clk(hw, &ctrl);
2717
2718 mask = mask >> 1;
2719 }
2720}
2721
2722/**
2723 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2724 * @hw: Struct containing variables accessed by shared code
2725 *
2726 * Bits are shifted in MSB to LSB order.
2727 */
2728static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2729{
2730 u32 ctrl;
2731 u16 data = 0;
2732 u8 i;
2733
2734 /* In order to read a register from the PHY, we need to shift in a total
2735 * of 18 bits from the PHY. The first two bit (turnaround) times are
2736 * used to avoid contention on the MDIO pin when a read operation is
2737 * performed. These two bits are ignored by us and thrown away. Bits are
2738 * "shifted in" by raising the input to the Management Data Clock
2739 * (setting the MDC bit), and then reading the value of the MDIO bit.
2740 */
2741 ctrl = er32(CTRL);
2742
2743 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
2744 * input.
2745 */
2746 ctrl &= ~E1000_CTRL_MDIO_DIR;
2747 ctrl &= ~E1000_CTRL_MDIO;
2748
2749 ew32(CTRL, ctrl);
2750 E1000_WRITE_FLUSH();
2751
2752 /* Raise and Lower the clock before reading in the data. This accounts
2753 * for the turnaround bits. The first clock occurred when we clocked out
2754 * the last bit of the Register Address.
2755 */
2756 e1000_raise_mdi_clk(hw, &ctrl);
2757 e1000_lower_mdi_clk(hw, &ctrl);
2758
2759 for (data = 0, i = 0; i < 16; i++) {
2760 data = data << 1;
2761 e1000_raise_mdi_clk(hw, &ctrl);
2762 ctrl = er32(CTRL);
2763 /* Check to see if we shifted in a "1". */
2764 if (ctrl & E1000_CTRL_MDIO)
2765 data |= 1;
2766 e1000_lower_mdi_clk(hw, &ctrl);
2767 }
2768
2769 e1000_raise_mdi_clk(hw, &ctrl);
2770 e1000_lower_mdi_clk(hw, &ctrl);
2771
2772 return data;
2773}
2774
2775/**
2776 * e1000_read_phy_reg - read a phy register
2777 * @hw: Struct containing variables accessed by shared code
2778 * @reg_addr: address of the PHY register to read
2779 * @phy_data: pointer to the value on the PHY register
2780 *
2781 * Reads the value from a PHY register, if the value is on a specific non zero
2782 * page, sets the page first.
2783 */
2784s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2785{
2786 u32 ret_val;
2787 unsigned long flags;
2788
2789 spin_lock_irqsave(&e1000_phy_lock, flags);
2790
2791 if ((hw->phy_type == e1000_phy_igp) &&
2792 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2793 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2794 (u16) reg_addr);
2795 if (ret_val)
2796 goto out;
2797 }
2798
2799 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2800 phy_data);
2801out:
2802 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2803
2804 return ret_val;
2805}
2806
2807static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2808 u16 *phy_data)
2809{
2810 u32 i;
2811 u32 mdic = 0;
2812 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2813
2814 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2815 e_dbg("PHY Address %d is out of range\n", reg_addr);
2816 return -E1000_ERR_PARAM;
2817 }
2818
2819 if (hw->mac_type > e1000_82543) {
2820 /* Set up Op-code, Phy Address, and register address in the MDI
2821 * Control register. The MAC will take care of interfacing with
2822 * the PHY to retrieve the desired data.
2823 */
2824 if (hw->mac_type == e1000_ce4100) {
2825 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2826 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2827 (INTEL_CE_GBE_MDIC_OP_READ) |
2828 (INTEL_CE_GBE_MDIC_GO));
2829
2830 writel(mdic, E1000_MDIO_CMD);
2831
2832 /* Poll the ready bit to see if the MDI read
2833 * completed
2834 */
2835 for (i = 0; i < 64; i++) {
2836 udelay(50);
2837 mdic = readl(E1000_MDIO_CMD);
2838 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2839 break;
2840 }
2841
2842 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2843 e_dbg("MDI Read did not complete\n");
2844 return -E1000_ERR_PHY;
2845 }
2846
2847 mdic = readl(E1000_MDIO_STS);
2848 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2849 e_dbg("MDI Read Error\n");
2850 return -E1000_ERR_PHY;
2851 }
2852 *phy_data = (u16)mdic;
2853 } else {
2854 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2855 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2856 (E1000_MDIC_OP_READ));
2857
2858 ew32(MDIC, mdic);
2859
2860 /* Poll the ready bit to see if the MDI read
2861 * completed
2862 */
2863 for (i = 0; i < 64; i++) {
2864 udelay(50);
2865 mdic = er32(MDIC);
2866 if (mdic & E1000_MDIC_READY)
2867 break;
2868 }
2869 if (!(mdic & E1000_MDIC_READY)) {
2870 e_dbg("MDI Read did not complete\n");
2871 return -E1000_ERR_PHY;
2872 }
2873 if (mdic & E1000_MDIC_ERROR) {
2874 e_dbg("MDI Error\n");
2875 return -E1000_ERR_PHY;
2876 }
2877 *phy_data = (u16)mdic;
2878 }
2879 } else {
2880 /* We must first send a preamble through the MDIO pin to signal
2881 * the beginning of an MII instruction. This is done by sending
2882 * 32 consecutive "1" bits.
2883 */
2884 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2885
2886 /* Now combine the next few fields that are required for a read
2887 * operation. We use this method instead of calling the
2888 * e1000_shift_out_mdi_bits routine five different times. The
2889 * format of a MII read instruction consists of a shift out of
2890 * 14 bits and is defined as follows:
2891 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2892 * followed by a shift in of 18 bits. This first two bits
2893 * shifted in are TurnAround bits used to avoid contention on
2894 * the MDIO pin when a READ operation is performed. These two
2895 * bits are thrown away followed by a shift in of 16 bits which
2896 * contains the desired data.
2897 */
2898 mdic = ((reg_addr) | (phy_addr << 5) |
2899 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2900
2901 e1000_shift_out_mdi_bits(hw, mdic, 14);
2902
2903 /* Now that we've shifted out the read command to the MII, we
2904 * need to "shift in" the 16-bit value (18 total bits) of the
2905 * requested PHY register address.
2906 */
2907 *phy_data = e1000_shift_in_mdi_bits(hw);
2908 }
2909 return E1000_SUCCESS;
2910}
2911
2912/**
2913 * e1000_write_phy_reg - write a phy register
2914 *
2915 * @hw: Struct containing variables accessed by shared code
2916 * @reg_addr: address of the PHY register to write
2917 * @phy_data: data to write to the PHY
2918 *
2919 * Writes a value to a PHY register
2920 */
2921s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2922{
2923 u32 ret_val;
2924 unsigned long flags;
2925
2926 spin_lock_irqsave(&e1000_phy_lock, flags);
2927
2928 if ((hw->phy_type == e1000_phy_igp) &&
2929 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2930 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2931 (u16)reg_addr);
2932 if (ret_val) {
2933 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2934 return ret_val;
2935 }
2936 }
2937
2938 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2939 phy_data);
2940 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2941
2942 return ret_val;
2943}
2944
2945static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2946 u16 phy_data)
2947{
2948 u32 i;
2949 u32 mdic = 0;
2950 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2951
2952 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2953 e_dbg("PHY Address %d is out of range\n", reg_addr);
2954 return -E1000_ERR_PARAM;
2955 }
2956
2957 if (hw->mac_type > e1000_82543) {
2958 /* Set up Op-code, Phy Address, register address, and data
2959 * intended for the PHY register in the MDI Control register.
2960 * The MAC will take care of interfacing with the PHY to send
2961 * the desired data.
2962 */
2963 if (hw->mac_type == e1000_ce4100) {
2964 mdic = (((u32)phy_data) |
2965 (reg_addr << E1000_MDIC_REG_SHIFT) |
2966 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2967 (INTEL_CE_GBE_MDIC_OP_WRITE) |
2968 (INTEL_CE_GBE_MDIC_GO));
2969
2970 writel(mdic, E1000_MDIO_CMD);
2971
2972 /* Poll the ready bit to see if the MDI read
2973 * completed
2974 */
2975 for (i = 0; i < 640; i++) {
2976 udelay(5);
2977 mdic = readl(E1000_MDIO_CMD);
2978 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2979 break;
2980 }
2981 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2982 e_dbg("MDI Write did not complete\n");
2983 return -E1000_ERR_PHY;
2984 }
2985 } else {
2986 mdic = (((u32)phy_data) |
2987 (reg_addr << E1000_MDIC_REG_SHIFT) |
2988 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2989 (E1000_MDIC_OP_WRITE));
2990
2991 ew32(MDIC, mdic);
2992
2993 /* Poll the ready bit to see if the MDI read
2994 * completed
2995 */
2996 for (i = 0; i < 641; i++) {
2997 udelay(5);
2998 mdic = er32(MDIC);
2999 if (mdic & E1000_MDIC_READY)
3000 break;
3001 }
3002 if (!(mdic & E1000_MDIC_READY)) {
3003 e_dbg("MDI Write did not complete\n");
3004 return -E1000_ERR_PHY;
3005 }
3006 }
3007 } else {
3008 /* We'll need to use the SW defined pins to shift the write
3009 * command out to the PHY. We first send a preamble to the PHY
3010 * to signal the beginning of the MII instruction. This is done
3011 * by sending 32 consecutive "1" bits.
3012 */
3013 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3014
3015 /* Now combine the remaining required fields that will indicate
3016 * a write operation. We use this method instead of calling the
3017 * e1000_shift_out_mdi_bits routine for each field in the
3018 * command. The format of a MII write instruction is as follows:
3019 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>.
3020 */
3021 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3022 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3023 mdic <<= 16;
3024 mdic |= (u32)phy_data;
3025
3026 e1000_shift_out_mdi_bits(hw, mdic, 32);
3027 }
3028
3029 return E1000_SUCCESS;
3030}
3031
3032/**
3033 * e1000_phy_hw_reset - reset the phy, hardware style
3034 * @hw: Struct containing variables accessed by shared code
3035 *
3036 * Returns the PHY to the power-on reset state
3037 */
3038s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3039{
3040 u32 ctrl, ctrl_ext;
3041 u32 led_ctrl;
3042
3043 e_dbg("Resetting Phy...\n");
3044
3045 if (hw->mac_type > e1000_82543) {
3046 /* Read the device control register and assert the
3047 * E1000_CTRL_PHY_RST bit. Then, take it out of reset.
3048 * For e1000 hardware, we delay for 10ms between the assert
3049 * and de-assert.
3050 */
3051 ctrl = er32(CTRL);
3052 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3053 E1000_WRITE_FLUSH();
3054
3055 msleep(10);
3056
3057 ew32(CTRL, ctrl);
3058 E1000_WRITE_FLUSH();
3059
3060 } else {
3061 /* Read the Extended Device Control Register, assert the
3062 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it
3063 * out of reset.
3064 */
3065 ctrl_ext = er32(CTRL_EXT);
3066 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3067 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3068 ew32(CTRL_EXT, ctrl_ext);
3069 E1000_WRITE_FLUSH();
3070 msleep(10);
3071 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3072 ew32(CTRL_EXT, ctrl_ext);
3073 E1000_WRITE_FLUSH();
3074 }
3075 udelay(150);
3076
3077 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3078 /* Configure activity LED after PHY reset */
3079 led_ctrl = er32(LEDCTL);
3080 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3081 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3082 ew32(LEDCTL, led_ctrl);
3083 }
3084
3085 /* Wait for FW to finish PHY configuration. */
3086 return e1000_get_phy_cfg_done(hw);
3087}
3088
3089/**
3090 * e1000_phy_reset - reset the phy to commit settings
3091 * @hw: Struct containing variables accessed by shared code
3092 *
3093 * Resets the PHY
3094 * Sets bit 15 of the MII Control register
3095 */
3096s32 e1000_phy_reset(struct e1000_hw *hw)
3097{
3098 s32 ret_val;
3099 u16 phy_data;
3100
3101 switch (hw->phy_type) {
3102 case e1000_phy_igp:
3103 ret_val = e1000_phy_hw_reset(hw);
3104 if (ret_val)
3105 return ret_val;
3106 break;
3107 default:
3108 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3109 if (ret_val)
3110 return ret_val;
3111
3112 phy_data |= MII_CR_RESET;
3113 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3114 if (ret_val)
3115 return ret_val;
3116
3117 udelay(1);
3118 break;
3119 }
3120
3121 if (hw->phy_type == e1000_phy_igp)
3122 e1000_phy_init_script(hw);
3123
3124 return E1000_SUCCESS;
3125}
3126
3127/**
3128 * e1000_detect_gig_phy - check the phy type
3129 * @hw: Struct containing variables accessed by shared code
3130 *
3131 * Probes the expected PHY address for known PHY IDs
3132 */
3133static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3134{
3135 s32 phy_init_status, ret_val;
3136 u16 phy_id_high, phy_id_low;
3137 bool match = false;
3138
3139 if (hw->phy_id != 0)
3140 return E1000_SUCCESS;
3141
3142 /* Read the PHY ID Registers to identify which PHY is onboard. */
3143 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3144 if (ret_val)
3145 return ret_val;
3146
3147 hw->phy_id = (u32)(phy_id_high << 16);
3148 udelay(20);
3149 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3150 if (ret_val)
3151 return ret_val;
3152
3153 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
3154 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
3155
3156 switch (hw->mac_type) {
3157 case e1000_82543:
3158 if (hw->phy_id == M88E1000_E_PHY_ID)
3159 match = true;
3160 break;
3161 case e1000_82544:
3162 if (hw->phy_id == M88E1000_I_PHY_ID)
3163 match = true;
3164 break;
3165 case e1000_82540:
3166 case e1000_82545:
3167 case e1000_82545_rev_3:
3168 case e1000_82546:
3169 case e1000_82546_rev_3:
3170 if (hw->phy_id == M88E1011_I_PHY_ID)
3171 match = true;
3172 break;
3173 case e1000_ce4100:
3174 if ((hw->phy_id == RTL8211B_PHY_ID) ||
3175 (hw->phy_id == RTL8201N_PHY_ID) ||
3176 (hw->phy_id == M88E1118_E_PHY_ID))
3177 match = true;
3178 break;
3179 case e1000_82541:
3180 case e1000_82541_rev_2:
3181 case e1000_82547:
3182 case e1000_82547_rev_2:
3183 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3184 match = true;
3185 break;
3186 default:
3187 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3188 return -E1000_ERR_CONFIG;
3189 }
3190 phy_init_status = e1000_set_phy_type(hw);
3191
3192 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3193 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3194 return E1000_SUCCESS;
3195 }
3196 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3197 return -E1000_ERR_PHY;
3198}
3199
3200/**
3201 * e1000_phy_reset_dsp - reset DSP
3202 * @hw: Struct containing variables accessed by shared code
3203 *
3204 * Resets the PHY's DSP
3205 */
3206static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3207{
3208 s32 ret_val;
3209
3210 do {
3211 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3212 if (ret_val)
3213 break;
3214 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3215 if (ret_val)
3216 break;
3217 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3218 if (ret_val)
3219 break;
3220 ret_val = E1000_SUCCESS;
3221 } while (0);
3222
3223 return ret_val;
3224}
3225
3226/**
3227 * e1000_phy_igp_get_info - get igp specific registers
3228 * @hw: Struct containing variables accessed by shared code
3229 * @phy_info: PHY information structure
3230 *
3231 * Get PHY information from various PHY registers for igp PHY only.
3232 */
3233static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3234 struct e1000_phy_info *phy_info)
3235{
3236 s32 ret_val;
3237 u16 phy_data, min_length, max_length, average;
3238 e1000_rev_polarity polarity;
3239
3240 /* The downshift status is checked only once, after link is established,
3241 * and it stored in the hw->speed_downgraded parameter.
3242 */
3243 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3244
3245 /* IGP01E1000 does not need to support it. */
3246 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3247
3248 /* IGP01E1000 always correct polarity reversal */
3249 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3250
3251 /* Check polarity status */
3252 ret_val = e1000_check_polarity(hw, &polarity);
3253 if (ret_val)
3254 return ret_val;
3255
3256 phy_info->cable_polarity = polarity;
3257
3258 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3259 if (ret_val)
3260 return ret_val;
3261
3262 phy_info->mdix_mode =
3263 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3264 IGP01E1000_PSSR_MDIX_SHIFT);
3265
3266 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3267 IGP01E1000_PSSR_SPEED_1000MBPS) {
3268 /* Local/Remote Receiver Information are only valid @ 1000
3269 * Mbps
3270 */
3271 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3272 if (ret_val)
3273 return ret_val;
3274
3275 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3276 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3277 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3278 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3279 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3280 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3281
3282 /* Get cable length */
3283 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3284 if (ret_val)
3285 return ret_val;
3286
3287 /* Translate to old method */
3288 average = (max_length + min_length) / 2;
3289
3290 if (average <= e1000_igp_cable_length_50)
3291 phy_info->cable_length = e1000_cable_length_50;
3292 else if (average <= e1000_igp_cable_length_80)
3293 phy_info->cable_length = e1000_cable_length_50_80;
3294 else if (average <= e1000_igp_cable_length_110)
3295 phy_info->cable_length = e1000_cable_length_80_110;
3296 else if (average <= e1000_igp_cable_length_140)
3297 phy_info->cable_length = e1000_cable_length_110_140;
3298 else
3299 phy_info->cable_length = e1000_cable_length_140;
3300 }
3301
3302 return E1000_SUCCESS;
3303}
3304
3305/**
3306 * e1000_phy_m88_get_info - get m88 specific registers
3307 * @hw: Struct containing variables accessed by shared code
3308 * @phy_info: PHY information structure
3309 *
3310 * Get PHY information from various PHY registers for m88 PHY only.
3311 */
3312static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3313 struct e1000_phy_info *phy_info)
3314{
3315 s32 ret_val;
3316 u16 phy_data;
3317 e1000_rev_polarity polarity;
3318
3319 /* The downshift status is checked only once, after link is established,
3320 * and it stored in the hw->speed_downgraded parameter.
3321 */
3322 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3323
3324 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3325 if (ret_val)
3326 return ret_val;
3327
3328 phy_info->extended_10bt_distance =
3329 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3330 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3331 e1000_10bt_ext_dist_enable_lower :
3332 e1000_10bt_ext_dist_enable_normal;
3333
3334 phy_info->polarity_correction =
3335 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3336 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3337 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3338
3339 /* Check polarity status */
3340 ret_val = e1000_check_polarity(hw, &polarity);
3341 if (ret_val)
3342 return ret_val;
3343 phy_info->cable_polarity = polarity;
3344
3345 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3346 if (ret_val)
3347 return ret_val;
3348
3349 phy_info->mdix_mode =
3350 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3351 M88E1000_PSSR_MDIX_SHIFT);
3352
3353 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3354 /* Cable Length Estimation and Local/Remote Receiver Information
3355 * are only valid at 1000 Mbps.
3356 */
3357 phy_info->cable_length =
3358 (e1000_cable_length) ((phy_data &
3359 M88E1000_PSSR_CABLE_LENGTH) >>
3360 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3361
3362 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3363 if (ret_val)
3364 return ret_val;
3365
3366 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3367 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3368 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3369 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3370 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3371 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3372 }
3373
3374 return E1000_SUCCESS;
3375}
3376
3377/**
3378 * e1000_phy_get_info - request phy info
3379 * @hw: Struct containing variables accessed by shared code
3380 * @phy_info: PHY information structure
3381 *
3382 * Get PHY information from various PHY registers
3383 */
3384s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3385{
3386 s32 ret_val;
3387 u16 phy_data;
3388
3389 phy_info->cable_length = e1000_cable_length_undefined;
3390 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3391 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3392 phy_info->downshift = e1000_downshift_undefined;
3393 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3394 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3395 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3396 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3397
3398 if (hw->media_type != e1000_media_type_copper) {
3399 e_dbg("PHY info is only valid for copper media\n");
3400 return -E1000_ERR_CONFIG;
3401 }
3402
3403 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3404 if (ret_val)
3405 return ret_val;
3406
3407 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3408 if (ret_val)
3409 return ret_val;
3410
3411 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3412 e_dbg("PHY info is only valid if link is up\n");
3413 return -E1000_ERR_CONFIG;
3414 }
3415
3416 if (hw->phy_type == e1000_phy_igp)
3417 return e1000_phy_igp_get_info(hw, phy_info);
3418 else if ((hw->phy_type == e1000_phy_8211) ||
3419 (hw->phy_type == e1000_phy_8201))
3420 return E1000_SUCCESS;
3421 else
3422 return e1000_phy_m88_get_info(hw, phy_info);
3423}
3424
3425s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3426{
3427 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3428 e_dbg("Invalid MDI setting detected\n");
3429 hw->mdix = 1;
3430 return -E1000_ERR_CONFIG;
3431 }
3432 return E1000_SUCCESS;
3433}
3434
3435/**
3436 * e1000_init_eeprom_params - initialize sw eeprom vars
3437 * @hw: Struct containing variables accessed by shared code
3438 *
3439 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3440 * is configured.
3441 */
3442s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3443{
3444 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3445 u32 eecd = er32(EECD);
3446 s32 ret_val = E1000_SUCCESS;
3447 u16 eeprom_size;
3448
3449 switch (hw->mac_type) {
3450 case e1000_82542_rev2_0:
3451 case e1000_82542_rev2_1:
3452 case e1000_82543:
3453 case e1000_82544:
3454 eeprom->type = e1000_eeprom_microwire;
3455 eeprom->word_size = 64;
3456 eeprom->opcode_bits = 3;
3457 eeprom->address_bits = 6;
3458 eeprom->delay_usec = 50;
3459 break;
3460 case e1000_82540:
3461 case e1000_82545:
3462 case e1000_82545_rev_3:
3463 case e1000_82546:
3464 case e1000_82546_rev_3:
3465 eeprom->type = e1000_eeprom_microwire;
3466 eeprom->opcode_bits = 3;
3467 eeprom->delay_usec = 50;
3468 if (eecd & E1000_EECD_SIZE) {
3469 eeprom->word_size = 256;
3470 eeprom->address_bits = 8;
3471 } else {
3472 eeprom->word_size = 64;
3473 eeprom->address_bits = 6;
3474 }
3475 break;
3476 case e1000_82541:
3477 case e1000_82541_rev_2:
3478 case e1000_82547:
3479 case e1000_82547_rev_2:
3480 if (eecd & E1000_EECD_TYPE) {
3481 eeprom->type = e1000_eeprom_spi;
3482 eeprom->opcode_bits = 8;
3483 eeprom->delay_usec = 1;
3484 if (eecd & E1000_EECD_ADDR_BITS) {
3485 eeprom->page_size = 32;
3486 eeprom->address_bits = 16;
3487 } else {
3488 eeprom->page_size = 8;
3489 eeprom->address_bits = 8;
3490 }
3491 } else {
3492 eeprom->type = e1000_eeprom_microwire;
3493 eeprom->opcode_bits = 3;
3494 eeprom->delay_usec = 50;
3495 if (eecd & E1000_EECD_ADDR_BITS) {
3496 eeprom->word_size = 256;
3497 eeprom->address_bits = 8;
3498 } else {
3499 eeprom->word_size = 64;
3500 eeprom->address_bits = 6;
3501 }
3502 }
3503 break;
3504 default:
3505 break;
3506 }
3507
3508 if (eeprom->type == e1000_eeprom_spi) {
3509 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes
3510 * 128B to 32KB (incremented by powers of 2).
3511 */
3512 /* Set to default value for initial eeprom read. */
3513 eeprom->word_size = 64;
3514 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3515 if (ret_val)
3516 return ret_val;
3517 eeprom_size =
3518 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3519 /* 256B eeprom size was not supported in earlier hardware, so we
3520 * bump eeprom_size up one to ensure that "1" (which maps to
3521 * 256B) is never the result used in the shifting logic below.
3522 */
3523 if (eeprom_size)
3524 eeprom_size++;
3525
3526 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3527 }
3528 return ret_val;
3529}
3530
3531/**
3532 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3533 * @hw: Struct containing variables accessed by shared code
3534 * @eecd: EECD's current value
3535 */
3536static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3537{
3538 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3539 * wait <delay> microseconds.
3540 */
3541 *eecd = *eecd | E1000_EECD_SK;
3542 ew32(EECD, *eecd);
3543 E1000_WRITE_FLUSH();
3544 udelay(hw->eeprom.delay_usec);
3545}
3546
3547/**
3548 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3549 * @hw: Struct containing variables accessed by shared code
3550 * @eecd: EECD's current value
3551 */
3552static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3553{
3554 /* Lower the clock input to the EEPROM (by clearing the SK bit), and
3555 * then wait 50 microseconds.
3556 */
3557 *eecd = *eecd & ~E1000_EECD_SK;
3558 ew32(EECD, *eecd);
3559 E1000_WRITE_FLUSH();
3560 udelay(hw->eeprom.delay_usec);
3561}
3562
3563/**
3564 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3565 * @hw: Struct containing variables accessed by shared code
3566 * @data: data to send to the EEPROM
3567 * @count: number of bits to shift out
3568 */
3569static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3570{
3571 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3572 u32 eecd;
3573 u32 mask;
3574
3575 /* We need to shift "count" bits out to the EEPROM. So, value in the
3576 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3577 * In order to do this, "data" must be broken down into bits.
3578 */
3579 mask = 0x01 << (count - 1);
3580 eecd = er32(EECD);
3581 if (eeprom->type == e1000_eeprom_microwire)
3582 eecd &= ~E1000_EECD_DO;
3583 else if (eeprom->type == e1000_eeprom_spi)
3584 eecd |= E1000_EECD_DO;
3585
3586 do {
3587 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a
3588 * "1", and then raising and then lowering the clock (the SK bit
3589 * controls the clock input to the EEPROM). A "0" is shifted
3590 * out to the EEPROM by setting "DI" to "0" and then raising and
3591 * then lowering the clock.
3592 */
3593 eecd &= ~E1000_EECD_DI;
3594
3595 if (data & mask)
3596 eecd |= E1000_EECD_DI;
3597
3598 ew32(EECD, eecd);
3599 E1000_WRITE_FLUSH();
3600
3601 udelay(eeprom->delay_usec);
3602
3603 e1000_raise_ee_clk(hw, &eecd);
3604 e1000_lower_ee_clk(hw, &eecd);
3605
3606 mask = mask >> 1;
3607
3608 } while (mask);
3609
3610 /* We leave the "DI" bit set to "0" when we leave this routine. */
3611 eecd &= ~E1000_EECD_DI;
3612 ew32(EECD, eecd);
3613}
3614
3615/**
3616 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3617 * @hw: Struct containing variables accessed by shared code
3618 * @count: number of bits to shift in
3619 */
3620static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3621{
3622 u32 eecd;
3623 u32 i;
3624 u16 data;
3625
3626 /* In order to read a register from the EEPROM, we need to shift 'count'
3627 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3628 * input to the EEPROM (setting the SK bit), and then reading the value
3629 * of the "DO" bit. During this "shifting in" process the "DI" bit
3630 * should always be clear.
3631 */
3632
3633 eecd = er32(EECD);
3634
3635 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3636 data = 0;
3637
3638 for (i = 0; i < count; i++) {
3639 data = data << 1;
3640 e1000_raise_ee_clk(hw, &eecd);
3641
3642 eecd = er32(EECD);
3643
3644 eecd &= ~(E1000_EECD_DI);
3645 if (eecd & E1000_EECD_DO)
3646 data |= 1;
3647
3648 e1000_lower_ee_clk(hw, &eecd);
3649 }
3650
3651 return data;
3652}
3653
3654/**
3655 * e1000_acquire_eeprom - Prepares EEPROM for access
3656 * @hw: Struct containing variables accessed by shared code
3657 *
3658 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3659 * function should be called before issuing a command to the EEPROM.
3660 */
3661static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3662{
3663 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3664 u32 eecd, i = 0;
3665
3666 eecd = er32(EECD);
3667
3668 /* Request EEPROM Access */
3669 if (hw->mac_type > e1000_82544) {
3670 eecd |= E1000_EECD_REQ;
3671 ew32(EECD, eecd);
3672 eecd = er32(EECD);
3673 while ((!(eecd & E1000_EECD_GNT)) &&
3674 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3675 i++;
3676 udelay(5);
3677 eecd = er32(EECD);
3678 }
3679 if (!(eecd & E1000_EECD_GNT)) {
3680 eecd &= ~E1000_EECD_REQ;
3681 ew32(EECD, eecd);
3682 e_dbg("Could not acquire EEPROM grant\n");
3683 return -E1000_ERR_EEPROM;
3684 }
3685 }
3686
3687 /* Setup EEPROM for Read/Write */
3688
3689 if (eeprom->type == e1000_eeprom_microwire) {
3690 /* Clear SK and DI */
3691 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3692 ew32(EECD, eecd);
3693
3694 /* Set CS */
3695 eecd |= E1000_EECD_CS;
3696 ew32(EECD, eecd);
3697 } else if (eeprom->type == e1000_eeprom_spi) {
3698 /* Clear SK and CS */
3699 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3700 ew32(EECD, eecd);
3701 E1000_WRITE_FLUSH();
3702 udelay(1);
3703 }
3704
3705 return E1000_SUCCESS;
3706}
3707
3708/**
3709 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3710 * @hw: Struct containing variables accessed by shared code
3711 */
3712static void e1000_standby_eeprom(struct e1000_hw *hw)
3713{
3714 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3715 u32 eecd;
3716
3717 eecd = er32(EECD);
3718
3719 if (eeprom->type == e1000_eeprom_microwire) {
3720 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3721 ew32(EECD, eecd);
3722 E1000_WRITE_FLUSH();
3723 udelay(eeprom->delay_usec);
3724
3725 /* Clock high */
3726 eecd |= E1000_EECD_SK;
3727 ew32(EECD, eecd);
3728 E1000_WRITE_FLUSH();
3729 udelay(eeprom->delay_usec);
3730
3731 /* Select EEPROM */
3732 eecd |= E1000_EECD_CS;
3733 ew32(EECD, eecd);
3734 E1000_WRITE_FLUSH();
3735 udelay(eeprom->delay_usec);
3736
3737 /* Clock low */
3738 eecd &= ~E1000_EECD_SK;
3739 ew32(EECD, eecd);
3740 E1000_WRITE_FLUSH();
3741 udelay(eeprom->delay_usec);
3742 } else if (eeprom->type == e1000_eeprom_spi) {
3743 /* Toggle CS to flush commands */
3744 eecd |= E1000_EECD_CS;
3745 ew32(EECD, eecd);
3746 E1000_WRITE_FLUSH();
3747 udelay(eeprom->delay_usec);
3748 eecd &= ~E1000_EECD_CS;
3749 ew32(EECD, eecd);
3750 E1000_WRITE_FLUSH();
3751 udelay(eeprom->delay_usec);
3752 }
3753}
3754
3755/**
3756 * e1000_release_eeprom - drop chip select
3757 * @hw: Struct containing variables accessed by shared code
3758 *
3759 * Terminates a command by inverting the EEPROM's chip select pin
3760 */
3761static void e1000_release_eeprom(struct e1000_hw *hw)
3762{
3763 u32 eecd;
3764
3765 eecd = er32(EECD);
3766
3767 if (hw->eeprom.type == e1000_eeprom_spi) {
3768 eecd |= E1000_EECD_CS; /* Pull CS high */
3769 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3770
3771 ew32(EECD, eecd);
3772 E1000_WRITE_FLUSH();
3773
3774 udelay(hw->eeprom.delay_usec);
3775 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3776 /* cleanup eeprom */
3777
3778 /* CS on Microwire is active-high */
3779 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3780
3781 ew32(EECD, eecd);
3782
3783 /* Rising edge of clock */
3784 eecd |= E1000_EECD_SK;
3785 ew32(EECD, eecd);
3786 E1000_WRITE_FLUSH();
3787 udelay(hw->eeprom.delay_usec);
3788
3789 /* Falling edge of clock */
3790 eecd &= ~E1000_EECD_SK;
3791 ew32(EECD, eecd);
3792 E1000_WRITE_FLUSH();
3793 udelay(hw->eeprom.delay_usec);
3794 }
3795
3796 /* Stop requesting EEPROM access */
3797 if (hw->mac_type > e1000_82544) {
3798 eecd &= ~E1000_EECD_REQ;
3799 ew32(EECD, eecd);
3800 }
3801}
3802
3803/**
3804 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3805 * @hw: Struct containing variables accessed by shared code
3806 */
3807static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3808{
3809 u16 retry_count = 0;
3810 u8 spi_stat_reg;
3811
3812 /* Read "Status Register" repeatedly until the LSB is cleared. The
3813 * EEPROM will signal that the command has been completed by clearing
3814 * bit 0 of the internal status register. If it's not cleared within
3815 * 5 milliseconds, then error out.
3816 */
3817 retry_count = 0;
3818 do {
3819 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3820 hw->eeprom.opcode_bits);
3821 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
3822 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3823 break;
3824
3825 udelay(5);
3826 retry_count += 5;
3827
3828 e1000_standby_eeprom(hw);
3829 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3830
3831 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3832 * only 0-5mSec on 5V devices)
3833 */
3834 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3835 e_dbg("SPI EEPROM Status error\n");
3836 return -E1000_ERR_EEPROM;
3837 }
3838
3839 return E1000_SUCCESS;
3840}
3841
3842/**
3843 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3844 * @hw: Struct containing variables accessed by shared code
3845 * @offset: offset of word in the EEPROM to read
3846 * @data: word read from the EEPROM
3847 * @words: number of words to read
3848 */
3849s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3850{
3851 s32 ret;
3852
3853 mutex_lock(&e1000_eeprom_lock);
3854 ret = e1000_do_read_eeprom(hw, offset, words, data);
3855 mutex_unlock(&e1000_eeprom_lock);
3856 return ret;
3857}
3858
3859static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3860 u16 *data)
3861{
3862 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3863 u32 i = 0;
3864
3865 if (hw->mac_type == e1000_ce4100) {
3866 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3867 data);
3868 return E1000_SUCCESS;
3869 }
3870
3871 /* A check for invalid values: offset too large, too many words, and
3872 * not enough words.
3873 */
3874 if ((offset >= eeprom->word_size) ||
3875 (words > eeprom->word_size - offset) ||
3876 (words == 0)) {
3877 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3878 "size = %d\n", offset, eeprom->word_size);
3879 return -E1000_ERR_EEPROM;
3880 }
3881
3882 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3883 * directly. In this case, we need to acquire the EEPROM so that
3884 * FW or other port software does not interrupt.
3885 */
3886 /* Prepare the EEPROM for bit-bang reading */
3887 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3888 return -E1000_ERR_EEPROM;
3889
3890 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3891 * acquired the EEPROM at this point, so any returns should release it
3892 */
3893 if (eeprom->type == e1000_eeprom_spi) {
3894 u16 word_in;
3895 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3896
3897 if (e1000_spi_eeprom_ready(hw)) {
3898 e1000_release_eeprom(hw);
3899 return -E1000_ERR_EEPROM;
3900 }
3901
3902 e1000_standby_eeprom(hw);
3903
3904 /* Some SPI eeproms use the 8th address bit embedded in the
3905 * opcode
3906 */
3907 if ((eeprom->address_bits == 8) && (offset >= 128))
3908 read_opcode |= EEPROM_A8_OPCODE_SPI;
3909
3910 /* Send the READ command (opcode + addr) */
3911 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3912 e1000_shift_out_ee_bits(hw, (u16)(offset * 2),
3913 eeprom->address_bits);
3914
3915 /* Read the data. The address of the eeprom internally
3916 * increments with each byte (spi) being read, saving on the
3917 * overhead of eeprom setup and tear-down. The address counter
3918 * will roll over if reading beyond the size of the eeprom, thus
3919 * allowing the entire memory to be read starting from any
3920 * offset.
3921 */
3922 for (i = 0; i < words; i++) {
3923 word_in = e1000_shift_in_ee_bits(hw, 16);
3924 data[i] = (word_in >> 8) | (word_in << 8);
3925 }
3926 } else if (eeprom->type == e1000_eeprom_microwire) {
3927 for (i = 0; i < words; i++) {
3928 /* Send the READ command (opcode + addr) */
3929 e1000_shift_out_ee_bits(hw,
3930 EEPROM_READ_OPCODE_MICROWIRE,
3931 eeprom->opcode_bits);
3932 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
3933 eeprom->address_bits);
3934
3935 /* Read the data. For microwire, each word requires the
3936 * overhead of eeprom setup and tear-down.
3937 */
3938 data[i] = e1000_shift_in_ee_bits(hw, 16);
3939 e1000_standby_eeprom(hw);
3940 cond_resched();
3941 }
3942 }
3943
3944 /* End this read operation */
3945 e1000_release_eeprom(hw);
3946
3947 return E1000_SUCCESS;
3948}
3949
3950/**
3951 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
3952 * @hw: Struct containing variables accessed by shared code
3953 *
3954 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3955 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3956 * valid.
3957 */
3958s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3959{
3960 u16 checksum = 0;
3961 u16 i, eeprom_data;
3962
3963 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3964 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3965 e_dbg("EEPROM Read Error\n");
3966 return -E1000_ERR_EEPROM;
3967 }
3968 checksum += eeprom_data;
3969 }
3970
3971#ifdef CONFIG_PARISC
3972 /* This is a signature and not a checksum on HP c8000 */
3973 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6))
3974 return E1000_SUCCESS;
3975
3976#endif
3977 if (checksum == (u16)EEPROM_SUM)
3978 return E1000_SUCCESS;
3979 else {
3980 e_dbg("EEPROM Checksum Invalid\n");
3981 return -E1000_ERR_EEPROM;
3982 }
3983}
3984
3985/**
3986 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
3987 * @hw: Struct containing variables accessed by shared code
3988 *
3989 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3990 * Writes the difference to word offset 63 of the EEPROM.
3991 */
3992s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
3993{
3994 u16 checksum = 0;
3995 u16 i, eeprom_data;
3996
3997 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3998 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3999 e_dbg("EEPROM Read Error\n");
4000 return -E1000_ERR_EEPROM;
4001 }
4002 checksum += eeprom_data;
4003 }
4004 checksum = (u16)EEPROM_SUM - checksum;
4005 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4006 e_dbg("EEPROM Write Error\n");
4007 return -E1000_ERR_EEPROM;
4008 }
4009 return E1000_SUCCESS;
4010}
4011
4012/**
4013 * e1000_write_eeprom - write words to the different EEPROM types.
4014 * @hw: Struct containing variables accessed by shared code
4015 * @offset: offset within the EEPROM to be written to
4016 * @words: number of words to write
4017 * @data: 16 bit word to be written to the EEPROM
4018 *
4019 * If e1000_update_eeprom_checksum is not called after this function, the
4020 * EEPROM will most likely contain an invalid checksum.
4021 */
4022s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4023{
4024 s32 ret;
4025
4026 mutex_lock(&e1000_eeprom_lock);
4027 ret = e1000_do_write_eeprom(hw, offset, words, data);
4028 mutex_unlock(&e1000_eeprom_lock);
4029 return ret;
4030}
4031
4032static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4033 u16 *data)
4034{
4035 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4036 s32 status = 0;
4037
4038 if (hw->mac_type == e1000_ce4100) {
4039 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4040 data);
4041 return E1000_SUCCESS;
4042 }
4043
4044 /* A check for invalid values: offset too large, too many words, and
4045 * not enough words.
4046 */
4047 if ((offset >= eeprom->word_size) ||
4048 (words > eeprom->word_size - offset) ||
4049 (words == 0)) {
4050 e_dbg("\"words\" parameter out of bounds\n");
4051 return -E1000_ERR_EEPROM;
4052 }
4053
4054 /* Prepare the EEPROM for writing */
4055 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4056 return -E1000_ERR_EEPROM;
4057
4058 if (eeprom->type == e1000_eeprom_microwire) {
4059 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4060 } else {
4061 status = e1000_write_eeprom_spi(hw, offset, words, data);
4062 msleep(10);
4063 }
4064
4065 /* Done with writing */
4066 e1000_release_eeprom(hw);
4067
4068 return status;
4069}
4070
4071/**
4072 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
4073 * @hw: Struct containing variables accessed by shared code
4074 * @offset: offset within the EEPROM to be written to
4075 * @words: number of words to write
4076 * @data: pointer to array of 8 bit words to be written to the EEPROM
4077 */
4078static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4079 u16 *data)
4080{
4081 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4082 u16 widx = 0;
4083
4084 while (widx < words) {
4085 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4086
4087 if (e1000_spi_eeprom_ready(hw))
4088 return -E1000_ERR_EEPROM;
4089
4090 e1000_standby_eeprom(hw);
4091 cond_resched();
4092
4093 /* Send the WRITE ENABLE command (8 bit opcode ) */
4094 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4095 eeprom->opcode_bits);
4096
4097 e1000_standby_eeprom(hw);
4098
4099 /* Some SPI eeproms use the 8th address bit embedded in the
4100 * opcode
4101 */
4102 if ((eeprom->address_bits == 8) && (offset >= 128))
4103 write_opcode |= EEPROM_A8_OPCODE_SPI;
4104
4105 /* Send the Write command (8-bit opcode + addr) */
4106 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4107
4108 e1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2),
4109 eeprom->address_bits);
4110
4111 /* Send the data */
4112
4113 /* Loop to allow for up to whole page write (32 bytes) of
4114 * eeprom
4115 */
4116 while (widx < words) {
4117 u16 word_out = data[widx];
4118
4119 word_out = (word_out >> 8) | (word_out << 8);
4120 e1000_shift_out_ee_bits(hw, word_out, 16);
4121 widx++;
4122
4123 /* Some larger eeprom sizes are capable of a 32-byte
4124 * PAGE WRITE operation, while the smaller eeproms are
4125 * capable of an 8-byte PAGE WRITE operation. Break the
4126 * inner loop to pass new address
4127 */
4128 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4129 e1000_standby_eeprom(hw);
4130 break;
4131 }
4132 }
4133 }
4134
4135 return E1000_SUCCESS;
4136}
4137
4138/**
4139 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4140 * @hw: Struct containing variables accessed by shared code
4141 * @offset: offset within the EEPROM to be written to
4142 * @words: number of words to write
4143 * @data: pointer to array of 8 bit words to be written to the EEPROM
4144 */
4145static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4146 u16 words, u16 *data)
4147{
4148 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4149 u32 eecd;
4150 u16 words_written = 0;
4151 u16 i = 0;
4152
4153 /* Send the write enable command to the EEPROM (3-bit opcode plus
4154 * 6/8-bit dummy address beginning with 11). It's less work to include
4155 * the 11 of the dummy address as part of the opcode than it is to shift
4156 * it over the correct number of bits for the address. This puts the
4157 * EEPROM into write/erase mode.
4158 */
4159 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4160 (u16)(eeprom->opcode_bits + 2));
4161
4162 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4163
4164 /* Prepare the EEPROM */
4165 e1000_standby_eeprom(hw);
4166
4167 while (words_written < words) {
4168 /* Send the Write command (3-bit opcode + addr) */
4169 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4170 eeprom->opcode_bits);
4171
4172 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
4173 eeprom->address_bits);
4174
4175 /* Send the data */
4176 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4177
4178 /* Toggle the CS line. This in effect tells the EEPROM to
4179 * execute the previous command.
4180 */
4181 e1000_standby_eeprom(hw);
4182
4183 /* Read DO repeatedly until it is high (equal to '1'). The
4184 * EEPROM will signal that the command has been completed by
4185 * raising the DO signal. If DO does not go high in 10
4186 * milliseconds, then error out.
4187 */
4188 for (i = 0; i < 200; i++) {
4189 eecd = er32(EECD);
4190 if (eecd & E1000_EECD_DO)
4191 break;
4192 udelay(50);
4193 }
4194 if (i == 200) {
4195 e_dbg("EEPROM Write did not complete\n");
4196 return -E1000_ERR_EEPROM;
4197 }
4198
4199 /* Recover from write */
4200 e1000_standby_eeprom(hw);
4201 cond_resched();
4202
4203 words_written++;
4204 }
4205
4206 /* Send the write disable command to the EEPROM (3-bit opcode plus
4207 * 6/8-bit dummy address beginning with 10). It's less work to include
4208 * the 10 of the dummy address as part of the opcode than it is to shift
4209 * it over the correct number of bits for the address. This takes the
4210 * EEPROM out of write/erase mode.
4211 */
4212 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4213 (u16)(eeprom->opcode_bits + 2));
4214
4215 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4216
4217 return E1000_SUCCESS;
4218}
4219
4220/**
4221 * e1000_read_mac_addr - read the adapters MAC from eeprom
4222 * @hw: Struct containing variables accessed by shared code
4223 *
4224 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4225 * second function of dual function devices
4226 */
4227s32 e1000_read_mac_addr(struct e1000_hw *hw)
4228{
4229 u16 offset;
4230 u16 eeprom_data, i;
4231
4232 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4233 offset = i >> 1;
4234 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4235 e_dbg("EEPROM Read Error\n");
4236 return -E1000_ERR_EEPROM;
4237 }
4238 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
4239 hw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8);
4240 }
4241
4242 switch (hw->mac_type) {
4243 default:
4244 break;
4245 case e1000_82546:
4246 case e1000_82546_rev_3:
4247 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4248 hw->perm_mac_addr[5] ^= 0x01;
4249 break;
4250 }
4251
4252 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4253 hw->mac_addr[i] = hw->perm_mac_addr[i];
4254 return E1000_SUCCESS;
4255}
4256
4257/**
4258 * e1000_init_rx_addrs - Initializes receive address filters.
4259 * @hw: Struct containing variables accessed by shared code
4260 *
4261 * Places the MAC address in receive address register 0 and clears the rest
4262 * of the receive address registers. Clears the multicast table. Assumes
4263 * the receiver is in reset when the routine is called.
4264 */
4265static void e1000_init_rx_addrs(struct e1000_hw *hw)
4266{
4267 u32 i;
4268 u32 rar_num;
4269
4270 /* Setup the receive address. */
4271 e_dbg("Programming MAC Address into RAR[0]\n");
4272
4273 e1000_rar_set(hw, hw->mac_addr, 0);
4274
4275 rar_num = E1000_RAR_ENTRIES;
4276
4277 /* Zero out the following 14 receive addresses. RAR[15] is for
4278 * manageability
4279 */
4280 e_dbg("Clearing RAR[1-14]\n");
4281 for (i = 1; i < rar_num; i++) {
4282 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4283 E1000_WRITE_FLUSH();
4284 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4285 E1000_WRITE_FLUSH();
4286 }
4287}
4288
4289/**
4290 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4291 * @hw: Struct containing variables accessed by shared code
4292 * @mc_addr: the multicast address to hash
4293 */
4294u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4295{
4296 u32 hash_value = 0;
4297
4298 /* The portion of the address that is used for the hash table is
4299 * determined by the mc_filter_type setting.
4300 */
4301 switch (hw->mc_filter_type) {
4302 /* [0] [1] [2] [3] [4] [5]
4303 * 01 AA 00 12 34 56
4304 * LSB MSB
4305 */
4306 case 0:
4307 /* [47:36] i.e. 0x563 for above example address */
4308 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
4309 break;
4310 case 1:
4311 /* [46:35] i.e. 0xAC6 for above example address */
4312 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
4313 break;
4314 case 2:
4315 /* [45:34] i.e. 0x5D8 for above example address */
4316 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
4317 break;
4318 case 3:
4319 /* [43:32] i.e. 0x634 for above example address */
4320 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
4321 break;
4322 }
4323
4324 hash_value &= 0xFFF;
4325 return hash_value;
4326}
4327
4328/**
4329 * e1000_rar_set - Puts an ethernet address into a receive address register.
4330 * @hw: Struct containing variables accessed by shared code
4331 * @addr: Address to put into receive address register
4332 * @index: Receive address register to write
4333 */
4334void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4335{
4336 u32 rar_low, rar_high;
4337
4338 /* HW expects these in little endian so we reverse the byte order
4339 * from network order (big endian) to little endian
4340 */
4341 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
4342 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
4343 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
4344
4345 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4346 * unit hang.
4347 *
4348 * Description:
4349 * If there are any Rx frames queued up or otherwise present in the HW
4350 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4351 * hang. To work around this issue, we have to disable receives and
4352 * flush out all Rx frames before we enable RSS. To do so, we modify we
4353 * redirect all Rx traffic to manageability and then reset the HW.
4354 * This flushes away Rx frames, and (since the redirections to
4355 * manageability persists across resets) keeps new ones from coming in
4356 * while we work. Then, we clear the Address Valid AV bit for all MAC
4357 * addresses and undo the re-direction to manageability.
4358 * Now, frames are coming in again, but the MAC won't accept them, so
4359 * far so good. We now proceed to initialize RSS (if necessary) and
4360 * configure the Rx unit. Last, we re-enable the AV bits and continue
4361 * on our merry way.
4362 */
4363 switch (hw->mac_type) {
4364 default:
4365 /* Indicate to hardware the Address is Valid. */
4366 rar_high |= E1000_RAH_AV;
4367 break;
4368 }
4369
4370 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4371 E1000_WRITE_FLUSH();
4372 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4373 E1000_WRITE_FLUSH();
4374}
4375
4376/**
4377 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4378 * @hw: Struct containing variables accessed by shared code
4379 * @offset: Offset in VLAN filer table to write
4380 * @value: Value to write into VLAN filter table
4381 */
4382void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4383{
4384 u32 temp;
4385
4386 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4387 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4388 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4389 E1000_WRITE_FLUSH();
4390 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4391 E1000_WRITE_FLUSH();
4392 } else {
4393 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4394 E1000_WRITE_FLUSH();
4395 }
4396}
4397
4398/**
4399 * e1000_clear_vfta - Clears the VLAN filer table
4400 * @hw: Struct containing variables accessed by shared code
4401 */
4402static void e1000_clear_vfta(struct e1000_hw *hw)
4403{
4404 u32 offset;
4405
4406 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4407 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
4408 E1000_WRITE_FLUSH();
4409 }
4410}
4411
4412static s32 e1000_id_led_init(struct e1000_hw *hw)
4413{
4414 u32 ledctl;
4415 const u32 ledctl_mask = 0x000000FF;
4416 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4417 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4418 u16 eeprom_data, i, temp;
4419 const u16 led_mask = 0x0F;
4420
4421 if (hw->mac_type < e1000_82540) {
4422 /* Nothing to do */
4423 return E1000_SUCCESS;
4424 }
4425
4426 ledctl = er32(LEDCTL);
4427 hw->ledctl_default = ledctl;
4428 hw->ledctl_mode1 = hw->ledctl_default;
4429 hw->ledctl_mode2 = hw->ledctl_default;
4430
4431 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4432 e_dbg("EEPROM Read Error\n");
4433 return -E1000_ERR_EEPROM;
4434 }
4435
4436 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4437 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4438 eeprom_data = ID_LED_DEFAULT;
4439 }
4440
4441 for (i = 0; i < 4; i++) {
4442 temp = (eeprom_data >> (i << 2)) & led_mask;
4443 switch (temp) {
4444 case ID_LED_ON1_DEF2:
4445 case ID_LED_ON1_ON2:
4446 case ID_LED_ON1_OFF2:
4447 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4448 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4449 break;
4450 case ID_LED_OFF1_DEF2:
4451 case ID_LED_OFF1_ON2:
4452 case ID_LED_OFF1_OFF2:
4453 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4454 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4455 break;
4456 default:
4457 /* Do nothing */
4458 break;
4459 }
4460 switch (temp) {
4461 case ID_LED_DEF1_ON2:
4462 case ID_LED_ON1_ON2:
4463 case ID_LED_OFF1_ON2:
4464 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4465 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4466 break;
4467 case ID_LED_DEF1_OFF2:
4468 case ID_LED_ON1_OFF2:
4469 case ID_LED_OFF1_OFF2:
4470 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4471 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4472 break;
4473 default:
4474 /* Do nothing */
4475 break;
4476 }
4477 }
4478 return E1000_SUCCESS;
4479}
4480
4481/**
4482 * e1000_setup_led
4483 * @hw: Struct containing variables accessed by shared code
4484 *
4485 * Prepares SW controlable LED for use and saves the current state of the LED.
4486 */
4487s32 e1000_setup_led(struct e1000_hw *hw)
4488{
4489 u32 ledctl;
4490 s32 ret_val = E1000_SUCCESS;
4491
4492 switch (hw->mac_type) {
4493 case e1000_82542_rev2_0:
4494 case e1000_82542_rev2_1:
4495 case e1000_82543:
4496 case e1000_82544:
4497 /* No setup necessary */
4498 break;
4499 case e1000_82541:
4500 case e1000_82547:
4501 case e1000_82541_rev_2:
4502 case e1000_82547_rev_2:
4503 /* Turn off PHY Smart Power Down (if enabled) */
4504 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4505 &hw->phy_spd_default);
4506 if (ret_val)
4507 return ret_val;
4508 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4509 (u16)(hw->phy_spd_default &
4510 ~IGP01E1000_GMII_SPD));
4511 if (ret_val)
4512 return ret_val;
4513 fallthrough;
4514 default:
4515 if (hw->media_type == e1000_media_type_fiber) {
4516 ledctl = er32(LEDCTL);
4517 /* Save current LEDCTL settings */
4518 hw->ledctl_default = ledctl;
4519 /* Turn off LED0 */
4520 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4521 E1000_LEDCTL_LED0_BLINK |
4522 E1000_LEDCTL_LED0_MODE_MASK);
4523 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4524 E1000_LEDCTL_LED0_MODE_SHIFT);
4525 ew32(LEDCTL, ledctl);
4526 } else if (hw->media_type == e1000_media_type_copper)
4527 ew32(LEDCTL, hw->ledctl_mode1);
4528 break;
4529 }
4530
4531 return E1000_SUCCESS;
4532}
4533
4534/**
4535 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4536 * @hw: Struct containing variables accessed by shared code
4537 */
4538s32 e1000_cleanup_led(struct e1000_hw *hw)
4539{
4540 s32 ret_val = E1000_SUCCESS;
4541
4542 switch (hw->mac_type) {
4543 case e1000_82542_rev2_0:
4544 case e1000_82542_rev2_1:
4545 case e1000_82543:
4546 case e1000_82544:
4547 /* No cleanup necessary */
4548 break;
4549 case e1000_82541:
4550 case e1000_82547:
4551 case e1000_82541_rev_2:
4552 case e1000_82547_rev_2:
4553 /* Turn on PHY Smart Power Down (if previously enabled) */
4554 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4555 hw->phy_spd_default);
4556 if (ret_val)
4557 return ret_val;
4558 fallthrough;
4559 default:
4560 /* Restore LEDCTL settings */
4561 ew32(LEDCTL, hw->ledctl_default);
4562 break;
4563 }
4564
4565 return E1000_SUCCESS;
4566}
4567
4568/**
4569 * e1000_led_on - Turns on the software controllable LED
4570 * @hw: Struct containing variables accessed by shared code
4571 */
4572s32 e1000_led_on(struct e1000_hw *hw)
4573{
4574 u32 ctrl = er32(CTRL);
4575
4576 switch (hw->mac_type) {
4577 case e1000_82542_rev2_0:
4578 case e1000_82542_rev2_1:
4579 case e1000_82543:
4580 /* Set SW Defineable Pin 0 to turn on the LED */
4581 ctrl |= E1000_CTRL_SWDPIN0;
4582 ctrl |= E1000_CTRL_SWDPIO0;
4583 break;
4584 case e1000_82544:
4585 if (hw->media_type == e1000_media_type_fiber) {
4586 /* Set SW Defineable Pin 0 to turn on the LED */
4587 ctrl |= E1000_CTRL_SWDPIN0;
4588 ctrl |= E1000_CTRL_SWDPIO0;
4589 } else {
4590 /* Clear SW Defineable Pin 0 to turn on the LED */
4591 ctrl &= ~E1000_CTRL_SWDPIN0;
4592 ctrl |= E1000_CTRL_SWDPIO0;
4593 }
4594 break;
4595 default:
4596 if (hw->media_type == e1000_media_type_fiber) {
4597 /* Clear SW Defineable Pin 0 to turn on the LED */
4598 ctrl &= ~E1000_CTRL_SWDPIN0;
4599 ctrl |= E1000_CTRL_SWDPIO0;
4600 } else if (hw->media_type == e1000_media_type_copper) {
4601 ew32(LEDCTL, hw->ledctl_mode2);
4602 return E1000_SUCCESS;
4603 }
4604 break;
4605 }
4606
4607 ew32(CTRL, ctrl);
4608
4609 return E1000_SUCCESS;
4610}
4611
4612/**
4613 * e1000_led_off - Turns off the software controllable LED
4614 * @hw: Struct containing variables accessed by shared code
4615 */
4616s32 e1000_led_off(struct e1000_hw *hw)
4617{
4618 u32 ctrl = er32(CTRL);
4619
4620 switch (hw->mac_type) {
4621 case e1000_82542_rev2_0:
4622 case e1000_82542_rev2_1:
4623 case e1000_82543:
4624 /* Clear SW Defineable Pin 0 to turn off the LED */
4625 ctrl &= ~E1000_CTRL_SWDPIN0;
4626 ctrl |= E1000_CTRL_SWDPIO0;
4627 break;
4628 case e1000_82544:
4629 if (hw->media_type == e1000_media_type_fiber) {
4630 /* Clear SW Defineable Pin 0 to turn off the LED */
4631 ctrl &= ~E1000_CTRL_SWDPIN0;
4632 ctrl |= E1000_CTRL_SWDPIO0;
4633 } else {
4634 /* Set SW Defineable Pin 0 to turn off the LED */
4635 ctrl |= E1000_CTRL_SWDPIN0;
4636 ctrl |= E1000_CTRL_SWDPIO0;
4637 }
4638 break;
4639 default:
4640 if (hw->media_type == e1000_media_type_fiber) {
4641 /* Set SW Defineable Pin 0 to turn off the LED */
4642 ctrl |= E1000_CTRL_SWDPIN0;
4643 ctrl |= E1000_CTRL_SWDPIO0;
4644 } else if (hw->media_type == e1000_media_type_copper) {
4645 ew32(LEDCTL, hw->ledctl_mode1);
4646 return E1000_SUCCESS;
4647 }
4648 break;
4649 }
4650
4651 ew32(CTRL, ctrl);
4652
4653 return E1000_SUCCESS;
4654}
4655
4656/**
4657 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4658 * @hw: Struct containing variables accessed by shared code
4659 */
4660static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4661{
4662 er32(CRCERRS);
4663 er32(SYMERRS);
4664 er32(MPC);
4665 er32(SCC);
4666 er32(ECOL);
4667 er32(MCC);
4668 er32(LATECOL);
4669 er32(COLC);
4670 er32(DC);
4671 er32(SEC);
4672 er32(RLEC);
4673 er32(XONRXC);
4674 er32(XONTXC);
4675 er32(XOFFRXC);
4676 er32(XOFFTXC);
4677 er32(FCRUC);
4678
4679 er32(PRC64);
4680 er32(PRC127);
4681 er32(PRC255);
4682 er32(PRC511);
4683 er32(PRC1023);
4684 er32(PRC1522);
4685
4686 er32(GPRC);
4687 er32(BPRC);
4688 er32(MPRC);
4689 er32(GPTC);
4690 er32(GORCL);
4691 er32(GORCH);
4692 er32(GOTCL);
4693 er32(GOTCH);
4694 er32(RNBC);
4695 er32(RUC);
4696 er32(RFC);
4697 er32(ROC);
4698 er32(RJC);
4699 er32(TORL);
4700 er32(TORH);
4701 er32(TOTL);
4702 er32(TOTH);
4703 er32(TPR);
4704 er32(TPT);
4705
4706 er32(PTC64);
4707 er32(PTC127);
4708 er32(PTC255);
4709 er32(PTC511);
4710 er32(PTC1023);
4711 er32(PTC1522);
4712
4713 er32(MPTC);
4714 er32(BPTC);
4715
4716 if (hw->mac_type < e1000_82543)
4717 return;
4718
4719 er32(ALGNERRC);
4720 er32(RXERRC);
4721 er32(TNCRS);
4722 er32(CEXTERR);
4723 er32(TSCTC);
4724 er32(TSCTFC);
4725
4726 if (hw->mac_type <= e1000_82544)
4727 return;
4728
4729 er32(MGTPRC);
4730 er32(MGTPDC);
4731 er32(MGTPTC);
4732}
4733
4734/**
4735 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4736 * @hw: Struct containing variables accessed by shared code
4737 *
4738 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4739 * hw->ifs_params_forced to true. However, you must initialize hw->
4740 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4741 * before calling this function.
4742 */
4743void e1000_reset_adaptive(struct e1000_hw *hw)
4744{
4745 if (hw->adaptive_ifs) {
4746 if (!hw->ifs_params_forced) {
4747 hw->current_ifs_val = 0;
4748 hw->ifs_min_val = IFS_MIN;
4749 hw->ifs_max_val = IFS_MAX;
4750 hw->ifs_step_size = IFS_STEP;
4751 hw->ifs_ratio = IFS_RATIO;
4752 }
4753 hw->in_ifs_mode = false;
4754 ew32(AIT, 0);
4755 } else {
4756 e_dbg("Not in Adaptive IFS mode!\n");
4757 }
4758}
4759
4760/**
4761 * e1000_update_adaptive - update adaptive IFS
4762 * @hw: Struct containing variables accessed by shared code
4763 *
4764 * Called during the callback/watchdog routine to update IFS value based on
4765 * the ratio of transmits to collisions.
4766 */
4767void e1000_update_adaptive(struct e1000_hw *hw)
4768{
4769 if (hw->adaptive_ifs) {
4770 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4771 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4772 hw->in_ifs_mode = true;
4773 if (hw->current_ifs_val < hw->ifs_max_val) {
4774 if (hw->current_ifs_val == 0)
4775 hw->current_ifs_val =
4776 hw->ifs_min_val;
4777 else
4778 hw->current_ifs_val +=
4779 hw->ifs_step_size;
4780 ew32(AIT, hw->current_ifs_val);
4781 }
4782 }
4783 } else {
4784 if (hw->in_ifs_mode &&
4785 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4786 hw->current_ifs_val = 0;
4787 hw->in_ifs_mode = false;
4788 ew32(AIT, 0);
4789 }
4790 }
4791 } else {
4792 e_dbg("Not in Adaptive IFS mode!\n");
4793 }
4794}
4795
4796/**
4797 * e1000_get_bus_info
4798 * @hw: Struct containing variables accessed by shared code
4799 *
4800 * Gets the current PCI bus type, speed, and width of the hardware
4801 */
4802void e1000_get_bus_info(struct e1000_hw *hw)
4803{
4804 u32 status;
4805
4806 switch (hw->mac_type) {
4807 case e1000_82542_rev2_0:
4808 case e1000_82542_rev2_1:
4809 hw->bus_type = e1000_bus_type_pci;
4810 hw->bus_speed = e1000_bus_speed_unknown;
4811 hw->bus_width = e1000_bus_width_unknown;
4812 break;
4813 default:
4814 status = er32(STATUS);
4815 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4816 e1000_bus_type_pcix : e1000_bus_type_pci;
4817
4818 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4819 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4820 e1000_bus_speed_66 : e1000_bus_speed_120;
4821 } else if (hw->bus_type == e1000_bus_type_pci) {
4822 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4823 e1000_bus_speed_66 : e1000_bus_speed_33;
4824 } else {
4825 switch (status & E1000_STATUS_PCIX_SPEED) {
4826 case E1000_STATUS_PCIX_SPEED_66:
4827 hw->bus_speed = e1000_bus_speed_66;
4828 break;
4829 case E1000_STATUS_PCIX_SPEED_100:
4830 hw->bus_speed = e1000_bus_speed_100;
4831 break;
4832 case E1000_STATUS_PCIX_SPEED_133:
4833 hw->bus_speed = e1000_bus_speed_133;
4834 break;
4835 default:
4836 hw->bus_speed = e1000_bus_speed_reserved;
4837 break;
4838 }
4839 }
4840 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4841 e1000_bus_width_64 : e1000_bus_width_32;
4842 break;
4843 }
4844}
4845
4846/**
4847 * e1000_write_reg_io
4848 * @hw: Struct containing variables accessed by shared code
4849 * @offset: offset to write to
4850 * @value: value to write
4851 *
4852 * Writes a value to one of the devices registers using port I/O (as opposed to
4853 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4854 */
4855static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
4856{
4857 unsigned long io_addr = hw->io_base;
4858 unsigned long io_data = hw->io_base + 4;
4859
4860 e1000_io_write(hw, io_addr, offset);
4861 e1000_io_write(hw, io_data, value);
4862}
4863
4864/**
4865 * e1000_get_cable_length - Estimates the cable length.
4866 * @hw: Struct containing variables accessed by shared code
4867 * @min_length: The estimated minimum length
4868 * @max_length: The estimated maximum length
4869 *
4870 * returns: - E1000_ERR_XXX
4871 * E1000_SUCCESS
4872 *
4873 * This function always returns a ranged length (minimum & maximum).
4874 * So for M88 phy's, this function interprets the one value returned from the
4875 * register to the minimum and maximum range.
4876 * For IGP phy's, the function calculates the range by the AGC registers.
4877 */
4878static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4879 u16 *max_length)
4880{
4881 s32 ret_val;
4882 u16 agc_value = 0;
4883 u16 i, phy_data;
4884 u16 cable_length;
4885
4886 *min_length = *max_length = 0;
4887
4888 /* Use old method for Phy older than IGP */
4889 if (hw->phy_type == e1000_phy_m88) {
4890 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4891 &phy_data);
4892 if (ret_val)
4893 return ret_val;
4894 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4895 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4896
4897 /* Convert the enum value to ranged values */
4898 switch (cable_length) {
4899 case e1000_cable_length_50:
4900 *min_length = 0;
4901 *max_length = e1000_igp_cable_length_50;
4902 break;
4903 case e1000_cable_length_50_80:
4904 *min_length = e1000_igp_cable_length_50;
4905 *max_length = e1000_igp_cable_length_80;
4906 break;
4907 case e1000_cable_length_80_110:
4908 *min_length = e1000_igp_cable_length_80;
4909 *max_length = e1000_igp_cable_length_110;
4910 break;
4911 case e1000_cable_length_110_140:
4912 *min_length = e1000_igp_cable_length_110;
4913 *max_length = e1000_igp_cable_length_140;
4914 break;
4915 case e1000_cable_length_140:
4916 *min_length = e1000_igp_cable_length_140;
4917 *max_length = e1000_igp_cable_length_170;
4918 break;
4919 default:
4920 return -E1000_ERR_PHY;
4921 }
4922 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4923 u16 cur_agc_value;
4924 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4925 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
4926 IGP01E1000_PHY_AGC_A,
4927 IGP01E1000_PHY_AGC_B,
4928 IGP01E1000_PHY_AGC_C,
4929 IGP01E1000_PHY_AGC_D
4930 };
4931 /* Read the AGC registers for all channels */
4932 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4933 ret_val =
4934 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4935 if (ret_val)
4936 return ret_val;
4937
4938 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4939
4940 /* Value bound check. */
4941 if ((cur_agc_value >=
4942 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4943 (cur_agc_value == 0))
4944 return -E1000_ERR_PHY;
4945
4946 agc_value += cur_agc_value;
4947
4948 /* Update minimal AGC value. */
4949 if (min_agc_value > cur_agc_value)
4950 min_agc_value = cur_agc_value;
4951 }
4952
4953 /* Remove the minimal AGC result for length < 50m */
4954 if (agc_value <
4955 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4956 agc_value -= min_agc_value;
4957
4958 /* Get the average length of the remaining 3 channels */
4959 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4960 } else {
4961 /* Get the average length of all the 4 channels. */
4962 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4963 }
4964
4965 /* Set the range of the calculated length. */
4966 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4967 IGP01E1000_AGC_RANGE) > 0) ?
4968 (e1000_igp_cable_length_table[agc_value] -
4969 IGP01E1000_AGC_RANGE) : 0;
4970 *max_length = e1000_igp_cable_length_table[agc_value] +
4971 IGP01E1000_AGC_RANGE;
4972 }
4973
4974 return E1000_SUCCESS;
4975}
4976
4977/**
4978 * e1000_check_polarity - Check the cable polarity
4979 * @hw: Struct containing variables accessed by shared code
4980 * @polarity: output parameter : 0 - Polarity is not reversed
4981 * 1 - Polarity is reversed.
4982 *
4983 * returns: - E1000_ERR_XXX
4984 * E1000_SUCCESS
4985 *
4986 * For phy's older than IGP, this function simply reads the polarity bit in the
4987 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4988 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4989 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4990 * IGP01E1000_PHY_PCS_INIT_REG.
4991 */
4992static s32 e1000_check_polarity(struct e1000_hw *hw,
4993 e1000_rev_polarity *polarity)
4994{
4995 s32 ret_val;
4996 u16 phy_data;
4997
4998 if (hw->phy_type == e1000_phy_m88) {
4999 /* return the Polarity bit in the Status register. */
5000 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5001 &phy_data);
5002 if (ret_val)
5003 return ret_val;
5004 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5005 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5006 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5007
5008 } else if (hw->phy_type == e1000_phy_igp) {
5009 /* Read the Status register to check the speed */
5010 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5011 &phy_data);
5012 if (ret_val)
5013 return ret_val;
5014
5015 /* If speed is 1000 Mbps, must read the
5016 * IGP01E1000_PHY_PCS_INIT_REG to find the polarity status
5017 */
5018 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5019 IGP01E1000_PSSR_SPEED_1000MBPS) {
5020 /* Read the GIG initialization PCS register (0x00B4) */
5021 ret_val =
5022 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5023 &phy_data);
5024 if (ret_val)
5025 return ret_val;
5026
5027 /* Check the polarity bits */
5028 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5029 e1000_rev_polarity_reversed :
5030 e1000_rev_polarity_normal;
5031 } else {
5032 /* For 10 Mbps, read the polarity bit in the status
5033 * register. (for 100 Mbps this bit is always 0)
5034 */
5035 *polarity =
5036 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5037 e1000_rev_polarity_reversed :
5038 e1000_rev_polarity_normal;
5039 }
5040 }
5041 return E1000_SUCCESS;
5042}
5043
5044/**
5045 * e1000_check_downshift - Check if Downshift occurred
5046 * @hw: Struct containing variables accessed by shared code
5047 *
5048 * returns: - E1000_ERR_XXX
5049 * E1000_SUCCESS
5050 *
5051 * For phy's older than IGP, this function reads the Downshift bit in the Phy
5052 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5053 * Link Health register. In IGP this bit is latched high, so the driver must
5054 * read it immediately after link is established.
5055 */
5056static s32 e1000_check_downshift(struct e1000_hw *hw)
5057{
5058 s32 ret_val;
5059 u16 phy_data;
5060
5061 if (hw->phy_type == e1000_phy_igp) {
5062 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5063 &phy_data);
5064 if (ret_val)
5065 return ret_val;
5066
5067 hw->speed_downgraded =
5068 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5069 } else if (hw->phy_type == e1000_phy_m88) {
5070 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5071 &phy_data);
5072 if (ret_val)
5073 return ret_val;
5074
5075 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5076 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5077 }
5078
5079 return E1000_SUCCESS;
5080}
5081
5082static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5083 IGP01E1000_PHY_AGC_PARAM_A,
5084 IGP01E1000_PHY_AGC_PARAM_B,
5085 IGP01E1000_PHY_AGC_PARAM_C,
5086 IGP01E1000_PHY_AGC_PARAM_D
5087};
5088
5089static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)
5090{
5091 u16 min_length, max_length;
5092 u16 phy_data, i;
5093 s32 ret_val;
5094
5095 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
5096 if (ret_val)
5097 return ret_val;
5098
5099 if (hw->dsp_config_state != e1000_dsp_config_enabled)
5100 return 0;
5101
5102 if (min_length >= e1000_igp_cable_length_50) {
5103 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5104 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
5105 &phy_data);
5106 if (ret_val)
5107 return ret_val;
5108
5109 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5110
5111 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
5112 phy_data);
5113 if (ret_val)
5114 return ret_val;
5115 }
5116 hw->dsp_config_state = e1000_dsp_config_activated;
5117 } else {
5118 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5119 u32 idle_errs = 0;
5120
5121 /* clear previous idle error counts */
5122 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
5123 if (ret_val)
5124 return ret_val;
5125
5126 for (i = 0; i < ffe_idle_err_timeout; i++) {
5127 udelay(1000);
5128 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5129 &phy_data);
5130 if (ret_val)
5131 return ret_val;
5132
5133 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5134 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5135 hw->ffe_config_state = e1000_ffe_config_active;
5136
5137 ret_val = e1000_write_phy_reg(hw,
5138 IGP01E1000_PHY_DSP_FFE,
5139 IGP01E1000_PHY_DSP_FFE_CM_CP);
5140 if (ret_val)
5141 return ret_val;
5142 break;
5143 }
5144
5145 if (idle_errs)
5146 ffe_idle_err_timeout =
5147 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5148 }
5149 }
5150
5151 return 0;
5152}
5153
5154/**
5155 * e1000_config_dsp_after_link_change
5156 * @hw: Struct containing variables accessed by shared code
5157 * @link_up: was link up at the time this was called
5158 *
5159 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5160 * E1000_SUCCESS at any other case.
5161 *
5162 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5163 * gigabit link is achieved to improve link quality.
5164 */
5165
5166static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5167{
5168 s32 ret_val;
5169 u16 phy_data, phy_saved_data, speed, duplex, i;
5170
5171 if (hw->phy_type != e1000_phy_igp)
5172 return E1000_SUCCESS;
5173
5174 if (link_up) {
5175 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5176 if (ret_val) {
5177 e_dbg("Error getting link speed and duplex\n");
5178 return ret_val;
5179 }
5180
5181 if (speed == SPEED_1000) {
5182 ret_val = e1000_1000Mb_check_cable_length(hw);
5183 if (ret_val)
5184 return ret_val;
5185 }
5186 } else {
5187 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5188 /* Save off the current value of register 0x2F5B to be
5189 * restored at the end of the routines.
5190 */
5191 ret_val =
5192 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5193
5194 if (ret_val)
5195 return ret_val;
5196
5197 /* Disable the PHY transmitter */
5198 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5199
5200 if (ret_val)
5201 return ret_val;
5202
5203 msleep(20);
5204
5205 ret_val = e1000_write_phy_reg(hw, 0x0000,
5206 IGP01E1000_IEEE_FORCE_GIGA);
5207 if (ret_val)
5208 return ret_val;
5209 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5210 ret_val =
5211 e1000_read_phy_reg(hw, dsp_reg_array[i],
5212 &phy_data);
5213 if (ret_val)
5214 return ret_val;
5215
5216 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5217 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5218
5219 ret_val =
5220 e1000_write_phy_reg(hw, dsp_reg_array[i],
5221 phy_data);
5222 if (ret_val)
5223 return ret_val;
5224 }
5225
5226 ret_val = e1000_write_phy_reg(hw, 0x0000,
5227 IGP01E1000_IEEE_RESTART_AUTONEG);
5228 if (ret_val)
5229 return ret_val;
5230
5231 msleep(20);
5232
5233 /* Now enable the transmitter */
5234 ret_val =
5235 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5236
5237 if (ret_val)
5238 return ret_val;
5239
5240 hw->dsp_config_state = e1000_dsp_config_enabled;
5241 }
5242
5243 if (hw->ffe_config_state == e1000_ffe_config_active) {
5244 /* Save off the current value of register 0x2F5B to be
5245 * restored at the end of the routines.
5246 */
5247 ret_val =
5248 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5249
5250 if (ret_val)
5251 return ret_val;
5252
5253 /* Disable the PHY transmitter */
5254 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5255
5256 if (ret_val)
5257 return ret_val;
5258
5259 msleep(20);
5260
5261 ret_val = e1000_write_phy_reg(hw, 0x0000,
5262 IGP01E1000_IEEE_FORCE_GIGA);
5263 if (ret_val)
5264 return ret_val;
5265 ret_val =
5266 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5267 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5268 if (ret_val)
5269 return ret_val;
5270
5271 ret_val = e1000_write_phy_reg(hw, 0x0000,
5272 IGP01E1000_IEEE_RESTART_AUTONEG);
5273 if (ret_val)
5274 return ret_val;
5275
5276 msleep(20);
5277
5278 /* Now enable the transmitter */
5279 ret_val =
5280 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5281
5282 if (ret_val)
5283 return ret_val;
5284
5285 hw->ffe_config_state = e1000_ffe_config_enabled;
5286 }
5287 }
5288 return E1000_SUCCESS;
5289}
5290
5291/**
5292 * e1000_set_phy_mode - Set PHY to class A mode
5293 * @hw: Struct containing variables accessed by shared code
5294 *
5295 * Assumes the following operations will follow to enable the new class mode.
5296 * 1. Do a PHY soft reset
5297 * 2. Restart auto-negotiation or force link.
5298 */
5299static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5300{
5301 s32 ret_val;
5302 u16 eeprom_data;
5303
5304 if ((hw->mac_type == e1000_82545_rev_3) &&
5305 (hw->media_type == e1000_media_type_copper)) {
5306 ret_val =
5307 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5308 &eeprom_data);
5309 if (ret_val)
5310 return ret_val;
5311
5312 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5313 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5314 ret_val =
5315 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5316 0x000B);
5317 if (ret_val)
5318 return ret_val;
5319 ret_val =
5320 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5321 0x8104);
5322 if (ret_val)
5323 return ret_val;
5324
5325 hw->phy_reset_disable = false;
5326 }
5327 }
5328
5329 return E1000_SUCCESS;
5330}
5331
5332/**
5333 * e1000_set_d3_lplu_state - set d3 link power state
5334 * @hw: Struct containing variables accessed by shared code
5335 * @active: true to enable lplu false to disable lplu.
5336 *
5337 * This function sets the lplu state according to the active flag. When
5338 * activating lplu this function also disables smart speed and vise versa.
5339 * lplu will not be activated unless the device autonegotiation advertisement
5340 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5341 *
5342 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5343 * E1000_SUCCESS at any other case.
5344 */
5345static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5346{
5347 s32 ret_val;
5348 u16 phy_data;
5349
5350 if (hw->phy_type != e1000_phy_igp)
5351 return E1000_SUCCESS;
5352
5353 /* During driver activity LPLU should not be used or it will attain link
5354 * from the lowest speeds starting from 10Mbps. The capability is used
5355 * for Dx transitions and states
5356 */
5357 if (hw->mac_type == e1000_82541_rev_2 ||
5358 hw->mac_type == e1000_82547_rev_2) {
5359 ret_val =
5360 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5361 if (ret_val)
5362 return ret_val;
5363 }
5364
5365 if (!active) {
5366 if (hw->mac_type == e1000_82541_rev_2 ||
5367 hw->mac_type == e1000_82547_rev_2) {
5368 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5369 ret_val =
5370 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5371 phy_data);
5372 if (ret_val)
5373 return ret_val;
5374 }
5375
5376 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
5377 * during Dx states where the power conservation is most
5378 * important. During driver activity we should enable
5379 * SmartSpeed, so performance is maintained.
5380 */
5381 if (hw->smart_speed == e1000_smart_speed_on) {
5382 ret_val =
5383 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5384 &phy_data);
5385 if (ret_val)
5386 return ret_val;
5387
5388 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5389 ret_val =
5390 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5391 phy_data);
5392 if (ret_val)
5393 return ret_val;
5394 } else if (hw->smart_speed == e1000_smart_speed_off) {
5395 ret_val =
5396 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5397 &phy_data);
5398 if (ret_val)
5399 return ret_val;
5400
5401 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5402 ret_val =
5403 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5404 phy_data);
5405 if (ret_val)
5406 return ret_val;
5407 }
5408 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5409 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
5410 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5411 if (hw->mac_type == e1000_82541_rev_2 ||
5412 hw->mac_type == e1000_82547_rev_2) {
5413 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5414 ret_val =
5415 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5416 phy_data);
5417 if (ret_val)
5418 return ret_val;
5419 }
5420
5421 /* When LPLU is enabled we should disable SmartSpeed */
5422 ret_val =
5423 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5424 &phy_data);
5425 if (ret_val)
5426 return ret_val;
5427
5428 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5429 ret_val =
5430 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5431 phy_data);
5432 if (ret_val)
5433 return ret_val;
5434 }
5435 return E1000_SUCCESS;
5436}
5437
5438/**
5439 * e1000_set_vco_speed
5440 * @hw: Struct containing variables accessed by shared code
5441 *
5442 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5443 */
5444static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5445{
5446 s32 ret_val;
5447 u16 default_page = 0;
5448 u16 phy_data;
5449
5450 switch (hw->mac_type) {
5451 case e1000_82545_rev_3:
5452 case e1000_82546_rev_3:
5453 break;
5454 default:
5455 return E1000_SUCCESS;
5456 }
5457
5458 /* Set PHY register 30, page 5, bit 8 to 0 */
5459
5460 ret_val =
5461 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5462 if (ret_val)
5463 return ret_val;
5464
5465 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5466 if (ret_val)
5467 return ret_val;
5468
5469 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5470 if (ret_val)
5471 return ret_val;
5472
5473 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5474 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5475 if (ret_val)
5476 return ret_val;
5477
5478 /* Set PHY register 30, page 4, bit 11 to 1 */
5479
5480 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5481 if (ret_val)
5482 return ret_val;
5483
5484 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5485 if (ret_val)
5486 return ret_val;
5487
5488 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5489 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5490 if (ret_val)
5491 return ret_val;
5492
5493 ret_val =
5494 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5495 if (ret_val)
5496 return ret_val;
5497
5498 return E1000_SUCCESS;
5499}
5500
5501/**
5502 * e1000_enable_mng_pass_thru - check for bmc pass through
5503 * @hw: Struct containing variables accessed by shared code
5504 *
5505 * Verifies the hardware needs to allow ARPs to be processed by the host
5506 * returns: - true/false
5507 */
5508u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5509{
5510 u32 manc;
5511
5512 if (hw->asf_firmware_present) {
5513 manc = er32(MANC);
5514
5515 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5516 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5517 return false;
5518 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5519 return true;
5520 }
5521 return false;
5522}
5523
5524static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5525{
5526 s32 ret_val;
5527 u16 mii_status_reg;
5528 u16 i;
5529
5530 /* Polarity reversal workaround for forced 10F/10H links. */
5531
5532 /* Disable the transmitter on the PHY */
5533
5534 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5535 if (ret_val)
5536 return ret_val;
5537 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5538 if (ret_val)
5539 return ret_val;
5540
5541 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5542 if (ret_val)
5543 return ret_val;
5544
5545 /* This loop will early-out if the NO link condition has been met. */
5546 for (i = PHY_FORCE_TIME; i > 0; i--) {
5547 /* Read the MII Status Register and wait for Link Status bit
5548 * to be clear.
5549 */
5550
5551 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5552 if (ret_val)
5553 return ret_val;
5554
5555 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5556 if (ret_val)
5557 return ret_val;
5558
5559 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5560 break;
5561 msleep(100);
5562 }
5563
5564 /* Recommended delay time after link has been lost */
5565 msleep(1000);
5566
5567 /* Now we will re-enable th transmitter on the PHY */
5568
5569 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5570 if (ret_val)
5571 return ret_val;
5572 msleep(50);
5573 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5574 if (ret_val)
5575 return ret_val;
5576 msleep(50);
5577 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5578 if (ret_val)
5579 return ret_val;
5580 msleep(50);
5581 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5582 if (ret_val)
5583 return ret_val;
5584
5585 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5586 if (ret_val)
5587 return ret_val;
5588
5589 /* This loop will early-out if the link condition has been met. */
5590 for (i = PHY_FORCE_TIME; i > 0; i--) {
5591 /* Read the MII Status Register and wait for Link Status bit
5592 * to be set.
5593 */
5594
5595 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5596 if (ret_val)
5597 return ret_val;
5598
5599 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5600 if (ret_val)
5601 return ret_val;
5602
5603 if (mii_status_reg & MII_SR_LINK_STATUS)
5604 break;
5605 msleep(100);
5606 }
5607 return E1000_SUCCESS;
5608}
5609
5610/**
5611 * e1000_get_auto_rd_done
5612 * @hw: Struct containing variables accessed by shared code
5613 *
5614 * Check for EEPROM Auto Read bit done.
5615 * returns: - E1000_ERR_RESET if fail to reset MAC
5616 * E1000_SUCCESS at any other case.
5617 */
5618static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5619{
5620 msleep(5);
5621 return E1000_SUCCESS;
5622}
5623
5624/**
5625 * e1000_get_phy_cfg_done
5626 * @hw: Struct containing variables accessed by shared code
5627 *
5628 * Checks if the PHY configuration is done
5629 * returns: - E1000_ERR_RESET if fail to reset MAC
5630 * E1000_SUCCESS at any other case.
5631 */
5632static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5633{
5634 msleep(10);
5635 return E1000_SUCCESS;
5636}