1/*
   2 * GPMC support functions
   3 *
   4 * Copyright (C) 2005-2006 Nokia Corporation
   5 *
   6 * Author: Juha Yrjola
   7 *
   8 * Copyright (C) 2009 Texas Instruments
   9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License version 2 as
  13 * published by the Free Software Foundation.
  14 */
  15#include <linux/irq.h>
  16#include <linux/kernel.h>
  17#include <linux/init.h>
  18#include <linux/err.h>
  19#include <linux/clk.h>
  20#include <linux/ioport.h>
  21#include <linux/spinlock.h>
  22#include <linux/io.h>
  23#include <linux/module.h>
 
 
  24#include <linux/interrupt.h>
 
  25#include <linux/platform_device.h>
  26#include <linux/of.h>
  27#include <linux/of_address.h>
  28#include <linux/of_mtd.h>
  29#include <linux/of_device.h>
  30#include <linux/of_platform.h>
  31#include <linux/omap-gpmc.h>
  32#include <linux/mtd/nand.h>
  33#include <linux/pm_runtime.h>
 
  34
  35#include <linux/platform_data/mtd-nand-omap2.h>
  36#include <linux/platform_data/mtd-onenand-omap2.h>
  37
  38#include <asm/mach-types.h>
  39
  40#define	DEVICE_NAME		"omap-gpmc"
  41
  42/* GPMC register offsets */
  43#define GPMC_REVISION		0x00
  44#define GPMC_SYSCONFIG		0x10
  45#define GPMC_SYSSTATUS		0x14
  46#define GPMC_IRQSTATUS		0x18
  47#define GPMC_IRQENABLE		0x1c
  48#define GPMC_TIMEOUT_CONTROL	0x40
  49#define GPMC_ERR_ADDRESS	0x44
  50#define GPMC_ERR_TYPE		0x48
  51#define GPMC_CONFIG		0x50
  52#define GPMC_STATUS		0x54
  53#define GPMC_PREFETCH_CONFIG1	0x1e0
  54#define GPMC_PREFETCH_CONFIG2	0x1e4
  55#define GPMC_PREFETCH_CONTROL	0x1ec
  56#define GPMC_PREFETCH_STATUS	0x1f0
  57#define GPMC_ECC_CONFIG		0x1f4
  58#define GPMC_ECC_CONTROL	0x1f8
  59#define GPMC_ECC_SIZE_CONFIG	0x1fc
  60#define GPMC_ECC1_RESULT        0x200
  61#define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  62#define	GPMC_ECC_BCH_RESULT_1	0x244	/* not available on OMAP2 */
  63#define	GPMC_ECC_BCH_RESULT_2	0x248	/* not available on OMAP2 */
  64#define	GPMC_ECC_BCH_RESULT_3	0x24c	/* not available on OMAP2 */
  65#define	GPMC_ECC_BCH_RESULT_4	0x300	/* not available on OMAP2 */
  66#define	GPMC_ECC_BCH_RESULT_5	0x304	/* not available on OMAP2 */
  67#define	GPMC_ECC_BCH_RESULT_6	0x308	/* not available on OMAP2 */
  68
  69/* GPMC ECC control settings */
  70#define GPMC_ECC_CTRL_ECCCLEAR		0x100
  71#define GPMC_ECC_CTRL_ECCDISABLE	0x000
  72#define GPMC_ECC_CTRL_ECCREG1		0x001
  73#define GPMC_ECC_CTRL_ECCREG2		0x002
  74#define GPMC_ECC_CTRL_ECCREG3		0x003
  75#define GPMC_ECC_CTRL_ECCREG4		0x004
  76#define GPMC_ECC_CTRL_ECCREG5		0x005
  77#define GPMC_ECC_CTRL_ECCREG6		0x006
  78#define GPMC_ECC_CTRL_ECCREG7		0x007
  79#define GPMC_ECC_CTRL_ECCREG8		0x008
  80#define GPMC_ECC_CTRL_ECCREG9		0x009
  81
  82#define GPMC_CONFIG_LIMITEDADDRESS		BIT(1)
  83
 
 
  84#define	GPMC_CONFIG2_CSEXTRADELAY		BIT(7)
  85#define	GPMC_CONFIG3_ADVEXTRADELAY		BIT(7)
  86#define	GPMC_CONFIG4_OEEXTRADELAY		BIT(7)
  87#define	GPMC_CONFIG4_WEEXTRADELAY		BIT(23)
  88#define	GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN	BIT(6)
  89#define	GPMC_CONFIG6_CYCLE2CYCLESAMECSEN	BIT(7)
  90
  91#define GPMC_CS0_OFFSET		0x60
  92#define GPMC_CS_SIZE		0x30
  93#define	GPMC_BCH_SIZE		0x10
  94
 
 
 
 
 
 
 
 
  95#define GPMC_MEM_END		0x3FFFFFFF
  96
  97#define GPMC_CHUNK_SHIFT	24		/* 16 MB */
  98#define GPMC_SECTION_SHIFT	28		/* 128 MB */
  99
 100#define CS_NUM_SHIFT		24
 101#define ENABLE_PREFETCH		(0x1 << 7)
 102#define DMA_MPU_MODE		2
 103
 104#define	GPMC_REVISION_MAJOR(l)		((l >> 4) & 0xf)
 105#define	GPMC_REVISION_MINOR(l)		(l & 0xf)
 106
 107#define	GPMC_HAS_WR_ACCESS		0x1
 108#define	GPMC_HAS_WR_DATA_MUX_BUS	0x2
 109#define	GPMC_HAS_MUX_AAD		0x4
 110
 111#define GPMC_NR_WAITPINS		4
 112
 113#define GPMC_CS_CONFIG1		0x00
 114#define GPMC_CS_CONFIG2		0x04
 115#define GPMC_CS_CONFIG3		0x08
 116#define GPMC_CS_CONFIG4		0x0c
 117#define GPMC_CS_CONFIG5		0x10
 118#define GPMC_CS_CONFIG6		0x14
 119#define GPMC_CS_CONFIG7		0x18
 120#define GPMC_CS_NAND_COMMAND	0x1c
 121#define GPMC_CS_NAND_ADDRESS	0x20
 122#define GPMC_CS_NAND_DATA	0x24
 123
 124/* Control Commands */
 125#define GPMC_CONFIG_RDY_BSY	0x00000001
 126#define GPMC_CONFIG_DEV_SIZE	0x00000002
 127#define GPMC_CONFIG_DEV_TYPE	0x00000003
 128#define GPMC_SET_IRQ_STATUS	0x00000004
 129
 130#define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 131#define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 132#define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 133#define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 134#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 135#define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 136#define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 137#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 138/** CLKACTIVATIONTIME Max Ticks */
 139#define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 140#define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 141/** ATTACHEDDEVICEPAGELENGTH Max Value */
 142#define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 143#define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 144#define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 145#define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 146/** WAITMONITORINGTIME Max Ticks */
 147#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 148#define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 149#define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 150#define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 151/** DEVICESIZE Max Value */
 152#define GPMC_CONFIG1_DEVICESIZE_MAX     1
 153#define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 154#define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 155#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 156#define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 157#define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 158#define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 159#define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 160#define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 161#define GPMC_CONFIG7_CSVALID		(1 << 6)
 162
 163#define GPMC_CONFIG7_BASEADDRESS_MASK	0x3f
 164#define GPMC_CONFIG7_CSVALID_MASK	BIT(6)
 165#define GPMC_CONFIG7_MASKADDRESS_OFFSET	8
 166#define GPMC_CONFIG7_MASKADDRESS_MASK	(0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 167/* All CONFIG7 bits except reserved bits */
 168#define GPMC_CONFIG7_MASK		(GPMC_CONFIG7_BASEADDRESS_MASK | \
 169					 GPMC_CONFIG7_CSVALID_MASK |     \
 170					 GPMC_CONFIG7_MASKADDRESS_MASK)
 171
 172#define GPMC_DEVICETYPE_NOR		0
 173#define GPMC_DEVICETYPE_NAND		2
 174#define GPMC_CONFIG_WRITEPROTECT	0x00000010
 175#define WR_RD_PIN_MONITORING		0x00600000
 176
 177#define GPMC_ENABLE_IRQ		0x0000000d
 178
 179/* ECC commands */
 180#define GPMC_ECC_READ		0 /* Reset Hardware ECC for read */
 181#define GPMC_ECC_WRITE		1 /* Reset Hardware ECC for write */
 182#define GPMC_ECC_READSYN	2 /* Reset before syndrom is read back */
 183
 184/* XXX: Only NAND irq has been considered,currently these are the only ones used
 185 */
 186#define	GPMC_NR_IRQ		2
 187
 188enum gpmc_clk_domain {
 189	GPMC_CD_FCLK,
 190	GPMC_CD_CLK
 191};
 192
 193struct gpmc_cs_data {
 194	const char *name;
 195
 196#define GPMC_CS_RESERVED	(1 << 0)
 197	u32 flags;
 198
 199	struct resource mem;
 200};
 201
 202struct gpmc_client_irq	{
 203	unsigned		irq;
 204	u32			bitmask;
 205};
 206
 207/* Structure to save gpmc cs context */
 208struct gpmc_cs_config {
 209	u32 config1;
 210	u32 config2;
 211	u32 config3;
 212	u32 config4;
 213	u32 config5;
 214	u32 config6;
 215	u32 config7;
 216	int is_valid;
 217};
 218
 219/*
 220 * Structure to save/restore gpmc context
 221 * to support core off on OMAP3
 222 */
 223struct omap3_gpmc_regs {
 224	u32 sysconfig;
 225	u32 irqenable;
 226	u32 timeout_ctrl;
 227	u32 config;
 228	u32 prefetch_config1;
 229	u32 prefetch_config2;
 230	u32 prefetch_control;
 231	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 232};
 233
 234static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 235static struct irq_chip gpmc_irq_chip;
 236static int gpmc_irq_start;
 
 
 
 
 
 
 237
 238static struct resource	gpmc_mem_root;
 239static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 240static DEFINE_SPINLOCK(gpmc_mem_lock);
 241/* Define chip-selects as reserved by default until probe completes */
 242static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 243static unsigned int gpmc_nr_waitpins;
 244static struct device *gpmc_dev;
 245static int gpmc_irq;
 246static resource_size_t phys_base, mem_size;
 247static unsigned gpmc_capability;
 248static void __iomem *gpmc_base;
 249
 250static struct clk *gpmc_l3_clk;
 251
 252static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 253
 254static void gpmc_write_reg(int idx, u32 val)
 255{
 256	writel_relaxed(val, gpmc_base + idx);
 257}
 258
 259static u32 gpmc_read_reg(int idx)
 260{
 261	return readl_relaxed(gpmc_base + idx);
 262}
 263
 264void gpmc_cs_write_reg(int cs, int idx, u32 val)
 265{
 266	void __iomem *reg_addr;
 267
 268	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 269	writel_relaxed(val, reg_addr);
 270}
 271
 272static u32 gpmc_cs_read_reg(int cs, int idx)
 273{
 274	void __iomem *reg_addr;
 275
 276	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 277	return readl_relaxed(reg_addr);
 278}
 279
 280/* TODO: Add support for gpmc_fck to clock framework and use it */
 281static unsigned long gpmc_get_fclk_period(void)
 282{
 283	unsigned long rate = clk_get_rate(gpmc_l3_clk);
 284
 285	rate /= 1000;
 286	rate = 1000000000 / rate;	/* In picoseconds */
 287
 288	return rate;
 289}
 290
 291/**
 292 * gpmc_get_clk_period - get period of selected clock domain in ps
 293 * @cs Chip Select Region.
 294 * @cd Clock Domain.
 295 *
 296 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 297 * prior to calling this function with GPMC_CD_CLK.
 298 */
 299static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 300{
 301
 302	unsigned long tick_ps = gpmc_get_fclk_period();
 303	u32 l;
 304	int div;
 305
 306	switch (cd) {
 307	case GPMC_CD_CLK:
 308		/* get current clk divider */
 309		l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 310		div = (l & 0x03) + 1;
 311		/* get GPMC_CLK period */
 312		tick_ps *= div;
 313		break;
 314	case GPMC_CD_FCLK:
 315		/* FALL-THROUGH */
 316	default:
 317		break;
 318	}
 319
 320	return tick_ps;
 321
 322}
 323
 324static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 325					 enum gpmc_clk_domain cd)
 326{
 327	unsigned long tick_ps;
 328
 329	/* Calculate in picosecs to yield more exact results */
 330	tick_ps = gpmc_get_clk_period(cs, cd);
 331
 332	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 333}
 334
 335static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 336{
 337	return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 338}
 339
 340static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 341{
 342	unsigned long tick_ps;
 343
 344	/* Calculate in picosecs to yield more exact results */
 345	tick_ps = gpmc_get_fclk_period();
 346
 347	return (time_ps + tick_ps - 1) / tick_ps;
 348}
 349
 350unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
 351				  enum gpmc_clk_domain cd)
 352{
 353	return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 354}
 355
 356unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 357{
 358	return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 359}
 360
 361static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 362{
 363	return ticks * gpmc_get_fclk_period();
 364}
 365
 366static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 367{
 368	unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 369
 370	return ticks * gpmc_get_fclk_period();
 371}
 372
 373static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 374{
 375	u32 l;
 376
 377	l = gpmc_cs_read_reg(cs, reg);
 378	if (value)
 379		l |= mask;
 380	else
 381		l &= ~mask;
 382	gpmc_cs_write_reg(cs, reg, l);
 383}
 384
 385static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 386{
 387	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 388			   GPMC_CONFIG1_TIME_PARA_GRAN,
 389			   p->time_para_granularity);
 390	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 391			   GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 392	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 393			   GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 394	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 395			   GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 396	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 397			   GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 398	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 399			   GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 400			   p->cycle2cyclesamecsen);
 401	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 402			   GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 403			   p->cycle2cyclediffcsen);
 404}
 405
 406#ifdef CONFIG_OMAP_GPMC_DEBUG
 407/**
 408 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 409 * @cs:      Chip Select Region
 410 * @reg:     GPMC_CS_CONFIGn register offset.
 411 * @st_bit:  Start Bit
 412 * @end_bit: End Bit. Must be >= @st_bit.
 413 * @ma:x     Maximum parameter value (before optional @shift).
 414 *           If 0, maximum is as high as @st_bit and @end_bit allow.
 415 * @name:    DTS node name, w/o "gpmc,"
 416 * @cd:      Clock Domain of timing parameter.
 417 * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 418 * @raw:     Raw Format Option.
 419 *           raw format:  gpmc,name = <value>
 420 *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 421 *           Where x ns -- y ns result in the same tick value.
 422 *           When @max is exceeded, "invalid" is printed inside comment.
 423 * @noval:   Parameter values equal to 0 are not printed.
 424 * @return:  Specified timing parameter (after optional @shift).
 425 *
 426 */
 427static int get_gpmc_timing_reg(
 428	/* timing specifiers */
 429	int cs, int reg, int st_bit, int end_bit, int max,
 430	const char *name, const enum gpmc_clk_domain cd,
 431	/* value transform */
 432	int shift,
 433	/* format specifiers */
 434	bool raw, bool noval)
 435{
 436	u32 l;
 437	int nr_bits;
 438	int mask;
 439	bool invalid;
 440
 441	l = gpmc_cs_read_reg(cs, reg);
 442	nr_bits = end_bit - st_bit + 1;
 443	mask = (1 << nr_bits) - 1;
 444	l = (l >> st_bit) & mask;
 445	if (!max)
 446		max = mask;
 447	invalid = l > max;
 448	if (shift)
 449		l = (shift << l);
 450	if (noval && (l == 0))
 451		return 0;
 452	if (!raw) {
 453		/* DTS tick format for timings in ns */
 454		unsigned int time_ns;
 455		unsigned int time_ns_min = 0;
 456
 457		if (l)
 458			time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 459		time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 460		pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
 461			name, time_ns, time_ns_min, time_ns, l,
 462			invalid ? "; invalid " : " ");
 463	} else {
 464		/* raw format */
 465		pr_info("gpmc,%s = <%u>%s\n", name, l,
 466			invalid ? " /* invalid */" : "");
 467	}
 468
 469	return l;
 470}
 471
 472#define GPMC_PRINT_CONFIG(cs, config) \
 473	pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 474		gpmc_cs_read_reg(cs, config))
 475#define GPMC_GET_RAW(reg, st, end, field) \
 476	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 477#define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 478	get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 479#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 480	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 481#define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 482	get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 483#define GPMC_GET_TICKS(reg, st, end, field) \
 484	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 485#define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 486	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 487#define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 488	get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 489
 490static void gpmc_show_regs(int cs, const char *desc)
 491{
 492	pr_info("gpmc cs%i %s:\n", cs, desc);
 493	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 494	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 495	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 496	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 497	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 498	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 499}
 500
 501/*
 502 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 503 * see commit c9fb809.
 504 */
 505static void gpmc_cs_show_timings(int cs, const char *desc)
 506{
 507	gpmc_show_regs(cs, desc);
 508
 509	pr_info("gpmc cs%i access configuration:\n", cs);
 510	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 511	GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 512	GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
 513			 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 514	GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 515	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 516	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 517	GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 518			       GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 519			       "burst-length");
 520	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 521	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 522	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 523	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 524	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 525
 526	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 527
 528	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 529
 530	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 531	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 532
 533	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 534	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 535
 536	pr_info("gpmc cs%i timings configuration:\n", cs);
 537	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 538	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 539	GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 540
 541	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 542	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 543	GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 544	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 545		GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 546		GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 547				"adv-aad-mux-rd-off-ns");
 548		GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 549				"adv-aad-mux-wr-off-ns");
 550	}
 551
 552	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 553	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 554	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 555		GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 556		GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 557	}
 558	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 559	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 560
 561	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 562	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 563	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 564
 565	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 566
 567	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 568	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 569
 570	GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 571			      GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 572			      "wait-monitoring-ns", GPMC_CD_CLK);
 573	GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 574			      GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 575			      "clk-activation-ns", GPMC_CD_FCLK);
 576
 577	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 578	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 579}
 580#else
 581static inline void gpmc_cs_show_timings(int cs, const char *desc)
 582{
 583}
 584#endif
 585
 586/**
 587 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 588 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 589 * prior to calling this function with @cd equal to GPMC_CD_CLK.
 590 *
 591 * @cs:      Chip Select Region.
 592 * @reg:     GPMC_CS_CONFIGn register offset.
 593 * @st_bit:  Start Bit
 594 * @end_bit: End Bit. Must be >= @st_bit.
 595 * @max:     Maximum parameter value.
 596 *           If 0, maximum is as high as @st_bit and @end_bit allow.
 597 * @time:    Timing parameter in ns.
 598 * @cd:      Timing parameter clock domain.
 599 * @name:    Timing parameter name.
 600 * @return:  0 on success, -1 on error.
 601 */
 602static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 603			       int time, enum gpmc_clk_domain cd, const char *name)
 604{
 605	u32 l;
 606	int ticks, mask, nr_bits;
 607
 608	if (time == 0)
 609		ticks = 0;
 610	else
 611		ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 612	nr_bits = end_bit - st_bit + 1;
 613	mask = (1 << nr_bits) - 1;
 614
 615	if (!max)
 616		max = mask;
 617
 618	if (ticks > max) {
 619		pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 620		       __func__, cs, name, time, ticks, max);
 621
 622		return -1;
 623	}
 624
 625	l = gpmc_cs_read_reg(cs, reg);
 626#ifdef CONFIG_OMAP_GPMC_DEBUG
 627	pr_info(
 628		"GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 629	       cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 630			(l >> st_bit) & mask, time);
 631#endif
 632	l &= ~(mask << st_bit);
 633	l |= ticks << st_bit;
 634	gpmc_cs_write_reg(cs, reg, l);
 635
 636	return 0;
 637}
 638
 639#define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 640	if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 641	    t->field, (cd), #field) < 0)                       \
 642		return -1
 643
 644#define GPMC_SET_ONE(reg, st, end, field) \
 645	GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 646
 647/**
 648 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 649 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 650 * read  --> don't sample bus too early
 651 * write --> data is longer on bus
 652 *
 653 * Formula:
 654 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 655 *                    / waitmonitoring_ticks)
 656 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 657 * div <= 0 check.
 658 *
 659 * @wait_monitoring: WAITMONITORINGTIME in ns.
 660 * @return:          -1 on failure to scale, else proper divider > 0.
 661 */
 662static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 663{
 664
 665	int div = gpmc_ns_to_ticks(wait_monitoring);
 666
 667	div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 668	div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 669
 670	if (div > 4)
 671		return -1;
 672	if (div <= 0)
 673		div = 1;
 674
 675	return div;
 676
 677}
 678
 679/**
 680 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 681 * @sync_clk: GPMC_CLK period in ps.
 682 * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 683 *            Else, returns -1.
 684 */
 685int gpmc_calc_divider(unsigned int sync_clk)
 686{
 687	int div = gpmc_ps_to_ticks(sync_clk);
 688
 689	if (div > 4)
 690		return -1;
 691	if (div <= 0)
 692		div = 1;
 693
 694	return div;
 695}
 696
 697/**
 698 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 699 * @cs:     Chip Select Region.
 700 * @t:      GPMC timing parameters.
 701 * @s:      GPMC timing settings.
 702 * @return: 0 on success, -1 on error.
 703 */
 704int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 705			const struct gpmc_settings *s)
 706{
 707	int div;
 708	u32 l;
 709
 710	div = gpmc_calc_divider(t->sync_clk);
 711	if (div < 0)
 712		return div;
 713
 714	/*
 715	 * See if we need to change the divider for waitmonitoringtime.
 716	 *
 717	 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 718	 * pure asynchronous accesses, i.e. both read and write asynchronous.
 719	 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 720	 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 721	 *
 722	 * This statement must not change div to scale async WAITMONITORINGTIME
 723	 * to protect mixed synchronous and asynchronous accesses.
 724	 *
 725	 * We raise an error later if WAITMONITORINGTIME does not fit.
 726	 */
 727	if (!s->sync_read && !s->sync_write &&
 728	    (s->wait_on_read || s->wait_on_write)
 729	   ) {
 730
 731		div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 732		if (div < 0) {
 733			pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 734			       __func__,
 735			       t->wait_monitoring
 736			       );
 737			return -1;
 738		}
 739	}
 740
 741	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 742	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 743	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 744
 745	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 746	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 747	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 748	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 749		GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
 750		GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
 751		GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
 752	}
 
 
 
 
 
 
 753
 754	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 755	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 756	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 757		GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
 758		GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 759	}
 760	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 761	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 762
 763	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 764	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 765	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 766
 767	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 768
 769	GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 770	GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 771
 772	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 773		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 774	if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 775		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 776
 777	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 778	l &= ~0x03;
 779	l |= (div - 1);
 780	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 781
 782	GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 783			    GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 784			    wait_monitoring, GPMC_CD_CLK);
 785	GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 786			    GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 787			    clk_activation, GPMC_CD_FCLK);
 
 
 
 
 
 788
 789#ifdef CONFIG_OMAP_GPMC_DEBUG
 790	pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 791			cs, (div * gpmc_get_fclk_period()) / 1000, div);
 792#endif
 793
 794	gpmc_cs_bool_timings(cs, &t->bool_timings);
 795	gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 796
 797	return 0;
 798}
 799
 800static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 801{
 802	u32 l;
 803	u32 mask;
 804
 805	/*
 806	 * Ensure that base address is aligned on a
 807	 * boundary equal to or greater than size.
 808	 */
 809	if (base & (size - 1))
 810		return -EINVAL;
 811
 812	base >>= GPMC_CHUNK_SHIFT;
 813	mask = (1 << GPMC_SECTION_SHIFT) - size;
 814	mask >>= GPMC_CHUNK_SHIFT;
 815	mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 816
 817	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 818	l &= ~GPMC_CONFIG7_MASK;
 819	l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 820	l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 821	l |= GPMC_CONFIG7_CSVALID;
 822	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 823
 824	return 0;
 825}
 826
 827static void gpmc_cs_enable_mem(int cs)
 828{
 829	u32 l;
 830
 831	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 832	l |= GPMC_CONFIG7_CSVALID;
 833	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 834}
 835
 836static void gpmc_cs_disable_mem(int cs)
 837{
 838	u32 l;
 839
 840	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 841	l &= ~GPMC_CONFIG7_CSVALID;
 842	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 843}
 844
 845static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 846{
 847	u32 l;
 848	u32 mask;
 849
 850	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 851	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 852	mask = (l >> 8) & 0x0f;
 853	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 854}
 855
 856static int gpmc_cs_mem_enabled(int cs)
 857{
 858	u32 l;
 859
 860	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 861	return l & GPMC_CONFIG7_CSVALID;
 862}
 863
 864static void gpmc_cs_set_reserved(int cs, int reserved)
 865{
 866	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 867
 868	gpmc->flags |= GPMC_CS_RESERVED;
 869}
 870
 871static bool gpmc_cs_reserved(int cs)
 872{
 873	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 874
 875	return gpmc->flags & GPMC_CS_RESERVED;
 876}
 877
 878static void gpmc_cs_set_name(int cs, const char *name)
 879{
 880	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 881
 882	gpmc->name = name;
 883}
 884
 885static const char *gpmc_cs_get_name(int cs)
 886{
 887	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 888
 889	return gpmc->name;
 890}
 891
 892static unsigned long gpmc_mem_align(unsigned long size)
 893{
 894	int order;
 895
 896	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 897	order = GPMC_CHUNK_SHIFT - 1;
 898	do {
 899		size >>= 1;
 900		order++;
 901	} while (size);
 902	size = 1 << order;
 903	return size;
 904}
 905
 906static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 907{
 908	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 909	struct resource *res = &gpmc->mem;
 910	int r;
 911
 912	size = gpmc_mem_align(size);
 913	spin_lock(&gpmc_mem_lock);
 914	res->start = base;
 915	res->end = base + size - 1;
 916	r = request_resource(&gpmc_mem_root, res);
 917	spin_unlock(&gpmc_mem_lock);
 918
 919	return r;
 920}
 921
 922static int gpmc_cs_delete_mem(int cs)
 923{
 924	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 925	struct resource *res = &gpmc->mem;
 926	int r;
 927
 928	spin_lock(&gpmc_mem_lock);
 929	r = release_resource(res);
 930	res->start = 0;
 931	res->end = 0;
 932	spin_unlock(&gpmc_mem_lock);
 933
 934	return r;
 935}
 936
 937/**
 938 * gpmc_cs_remap - remaps a chip-select physical base address
 939 * @cs:		chip-select to remap
 940 * @base:	physical base address to re-map chip-select to
 941 *
 942 * Re-maps a chip-select to a new physical base address specified by
 943 * "base". Returns 0 on success and appropriate negative error code
 944 * on failure.
 945 */
 946static int gpmc_cs_remap(int cs, u32 base)
 947{
 948	int ret;
 949	u32 old_base, size;
 950
 951	if (cs > gpmc_cs_num) {
 952		pr_err("%s: requested chip-select is disabled\n", __func__);
 953		return -ENODEV;
 954	}
 955
 956	/*
 957	 * Make sure we ignore any device offsets from the GPMC partition
 958	 * allocated for the chip select and that the new base confirms
 959	 * to the GPMC 16MB minimum granularity.
 960	 */ 
 961	base &= ~(SZ_16M - 1);
 962
 963	gpmc_cs_get_memconf(cs, &old_base, &size);
 964	if (base == old_base)
 965		return 0;
 966
 967	ret = gpmc_cs_delete_mem(cs);
 968	if (ret < 0)
 969		return ret;
 970
 971	ret = gpmc_cs_insert_mem(cs, base, size);
 972	if (ret < 0)
 973		return ret;
 974
 975	ret = gpmc_cs_set_memconf(cs, base, size);
 976
 977	return ret;
 978}
 979
 980int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 981{
 982	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 983	struct resource *res = &gpmc->mem;
 984	int r = -1;
 985
 986	if (cs > gpmc_cs_num) {
 987		pr_err("%s: requested chip-select is disabled\n", __func__);
 988		return -ENODEV;
 989	}
 990	size = gpmc_mem_align(size);
 991	if (size > (1 << GPMC_SECTION_SHIFT))
 992		return -ENOMEM;
 993
 994	spin_lock(&gpmc_mem_lock);
 995	if (gpmc_cs_reserved(cs)) {
 996		r = -EBUSY;
 997		goto out;
 998	}
 999	if (gpmc_cs_mem_enabled(cs))
1000		r = adjust_resource(res, res->start & ~(size - 1), size);
1001	if (r < 0)
1002		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1003				      size, NULL, NULL);
1004	if (r < 0)
1005		goto out;
1006
1007	/* Disable CS while changing base address and size mask */
1008	gpmc_cs_disable_mem(cs);
1009
1010	r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1011	if (r < 0) {
1012		release_resource(res);
1013		goto out;
1014	}
1015
1016	/* Enable CS */
1017	gpmc_cs_enable_mem(cs);
1018	*base = res->start;
1019	gpmc_cs_set_reserved(cs, 1);
1020out:
1021	spin_unlock(&gpmc_mem_lock);
1022	return r;
1023}
1024EXPORT_SYMBOL(gpmc_cs_request);
1025
1026void gpmc_cs_free(int cs)
1027{
1028	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1029	struct resource *res = &gpmc->mem;
1030
1031	spin_lock(&gpmc_mem_lock);
1032	if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1033		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1034		BUG();
1035		spin_unlock(&gpmc_mem_lock);
1036		return;
1037	}
 
 
 
1038	gpmc_cs_disable_mem(cs);
1039	if (res->flags)
1040		release_resource(res);
1041	gpmc_cs_set_reserved(cs, 0);
1042	spin_unlock(&gpmc_mem_lock);
1043}
1044EXPORT_SYMBOL(gpmc_cs_free);
1045
1046/**
1047 * gpmc_configure - write request to configure gpmc
1048 * @cmd: command type
1049 * @wval: value to write
1050 * @return status of the operation
1051 */
1052int gpmc_configure(int cmd, int wval)
1053{
1054	u32 regval;
1055
1056	switch (cmd) {
1057	case GPMC_ENABLE_IRQ:
1058		gpmc_write_reg(GPMC_IRQENABLE, wval);
1059		break;
1060
1061	case GPMC_SET_IRQ_STATUS:
1062		gpmc_write_reg(GPMC_IRQSTATUS, wval);
1063		break;
1064
1065	case GPMC_CONFIG_WP:
1066		regval = gpmc_read_reg(GPMC_CONFIG);
1067		if (wval)
1068			regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1069		else
1070			regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1071		gpmc_write_reg(GPMC_CONFIG, regval);
1072		break;
1073
1074	default:
1075		pr_err("%s: command not supported\n", __func__);
1076		return -EINVAL;
1077	}
1078
1079	return 0;
1080}
1081EXPORT_SYMBOL(gpmc_configure);
1082
1083void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1084{
1085	int i;
1086
1087	reg->gpmc_status = gpmc_base + GPMC_STATUS;
 
 
1088	reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1089				GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1090	reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1091				GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1092	reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1093				GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1094	reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1095	reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1096	reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1097	reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1098	reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1099	reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1100	reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1101	reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1102
1103	for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1104		reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1105					   GPMC_BCH_SIZE * i;
1106		reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1107					   GPMC_BCH_SIZE * i;
1108		reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1109					   GPMC_BCH_SIZE * i;
1110		reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1111					   GPMC_BCH_SIZE * i;
1112		reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1113					   i * GPMC_BCH_SIZE;
1114		reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1115					   i * GPMC_BCH_SIZE;
1116		reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1117					   i * GPMC_BCH_SIZE;
1118	}
 
 
1119}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1120
1121int gpmc_get_client_irq(unsigned irq_config)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1122{
1123	int i;
 
 
 
 
1124
1125	if (hweight32(irq_config) > 1)
 
 
 
 
1126		return 0;
1127
1128	for (i = 0; i < GPMC_NR_IRQ; i++)
1129		if (gpmc_client_irq[i].bitmask & irq_config)
1130			return gpmc_client_irq[i].irq;
1131
1132	return 0;
 
 
 
 
1133}
 
1134
1135static int gpmc_irq_endis(unsigned irq, bool endis)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1136{
1137	int i;
1138	u32 regval;
1139
1140	for (i = 0; i < GPMC_NR_IRQ; i++)
1141		if (irq == gpmc_client_irq[i].irq) {
1142			regval = gpmc_read_reg(GPMC_IRQENABLE);
1143			if (endis)
1144				regval |= gpmc_client_irq[i].bitmask;
1145			else
1146				regval &= ~gpmc_client_irq[i].bitmask;
1147			gpmc_write_reg(GPMC_IRQENABLE, regval);
1148			break;
1149		}
1150
1151	return 0;
1152}
1153
1154static void gpmc_irq_disable(struct irq_data *p)
1155{
1156	gpmc_irq_endis(p->irq, false);
1157}
1158
1159static void gpmc_irq_enable(struct irq_data *p)
1160{
1161	gpmc_irq_endis(p->irq, true);
1162}
1163
1164static void gpmc_irq_noop(struct irq_data *data) { }
 
 
 
1165
1166static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 
 
 
1167
1168static int gpmc_setup_irq(void)
1169{
1170	int i;
1171	u32 regval;
1172
1173	if (!gpmc_irq)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1174		return -EINVAL;
1175
1176	gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
1177	if (gpmc_irq_start < 0) {
1178		pr_err("irq_alloc_descs failed\n");
1179		return gpmc_irq_start;
1180	}
1181
1182	gpmc_irq_chip.name = "gpmc";
1183	gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
1184	gpmc_irq_chip.irq_enable = gpmc_irq_enable;
1185	gpmc_irq_chip.irq_disable = gpmc_irq_disable;
1186	gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
1187	gpmc_irq_chip.irq_ack = gpmc_irq_noop;
1188	gpmc_irq_chip.irq_mask = gpmc_irq_noop;
1189	gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
1190
1191	gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
1192	gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
1193
1194	for (i = 0; i < GPMC_NR_IRQ; i++) {
1195		gpmc_client_irq[i].irq = gpmc_irq_start + i;
1196		irq_set_chip_and_handler(gpmc_client_irq[i].irq,
1197					&gpmc_irq_chip, handle_simple_irq);
1198		irq_modify_status(gpmc_client_irq[i].irq, IRQ_NOREQUEST,
1199				  IRQ_NOAUTOEN);
1200	}
1201
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1202	/* Disable interrupts */
1203	gpmc_write_reg(GPMC_IRQENABLE, 0);
1204
1205	/* clear interrupts */
1206	regval = gpmc_read_reg(GPMC_IRQSTATUS);
1207	gpmc_write_reg(GPMC_IRQSTATUS, regval);
1208
1209	return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1210}
1211
1212static int gpmc_free_irq(void)
1213{
1214	int i;
1215
1216	if (gpmc_irq)
1217		free_irq(gpmc_irq, NULL);
1218
1219	for (i = 0; i < GPMC_NR_IRQ; i++) {
1220		irq_set_handler(gpmc_client_irq[i].irq, NULL);
1221		irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
1222	}
1223
1224	irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
 
1225
1226	return 0;
1227}
1228
1229static void gpmc_mem_exit(void)
1230{
1231	int cs;
1232
1233	for (cs = 0; cs < gpmc_cs_num; cs++) {
1234		if (!gpmc_cs_mem_enabled(cs))
1235			continue;
1236		gpmc_cs_delete_mem(cs);
1237	}
1238
1239}
1240
1241static void gpmc_mem_init(void)
1242{
1243	int cs;
1244
1245	/*
1246	 * The first 1MB of GPMC address space is typically mapped to
1247	 * the internal ROM. Never allocate the first page, to
1248	 * facilitate bug detection; even if we didn't boot from ROM.
1249	 */
1250	gpmc_mem_root.start = SZ_1M;
1251	gpmc_mem_root.end = GPMC_MEM_END;
1252
1253	/* Reserve all regions that has been set up by bootloader */
1254	for (cs = 0; cs < gpmc_cs_num; cs++) {
1255		u32 base, size;
1256
1257		if (!gpmc_cs_mem_enabled(cs))
1258			continue;
1259		gpmc_cs_get_memconf(cs, &base, &size);
1260		if (gpmc_cs_insert_mem(cs, base, size)) {
1261			pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1262				__func__, cs, base, base + size);
1263			gpmc_cs_disable_mem(cs);
1264		}
1265	}
1266}
1267
1268static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1269{
1270	u32 temp;
1271	int div;
1272
1273	div = gpmc_calc_divider(sync_clk);
1274	temp = gpmc_ps_to_ticks(time_ps);
1275	temp = (temp + div - 1) / div;
1276	return gpmc_ticks_to_ps(temp * div);
1277}
1278
1279/* XXX: can the cycles be avoided ? */
1280static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1281				       struct gpmc_device_timings *dev_t,
1282				       bool mux)
1283{
1284	u32 temp;
1285
1286	/* adv_rd_off */
1287	temp = dev_t->t_avdp_r;
1288	/* XXX: mux check required ? */
1289	if (mux) {
1290		/* XXX: t_avdp not to be required for sync, only added for tusb
1291		 * this indirectly necessitates requirement of t_avdp_r and
1292		 * t_avdp_w instead of having a single t_avdp
1293		 */
1294		temp = max_t(u32, temp,	gpmc_t->clk_activation + dev_t->t_avdh);
1295		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1296	}
1297	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1298
1299	/* oe_on */
1300	temp = dev_t->t_oeasu; /* XXX: remove this ? */
1301	if (mux) {
1302		temp = max_t(u32, temp,	gpmc_t->clk_activation + dev_t->t_ach);
1303		temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1304				gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1305	}
1306	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1307
1308	/* access */
1309	/* XXX: any scope for improvement ?, by combining oe_on
1310	 * and clk_activation, need to check whether
1311	 * access = clk_activation + round to sync clk ?
1312	 */
1313	temp = max_t(u32, dev_t->t_iaa,	dev_t->cyc_iaa * gpmc_t->sync_clk);
1314	temp += gpmc_t->clk_activation;
1315	if (dev_t->cyc_oe)
1316		temp = max_t(u32, temp, gpmc_t->oe_on +
1317				gpmc_ticks_to_ps(dev_t->cyc_oe));
1318	gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1319
1320	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1321	gpmc_t->cs_rd_off = gpmc_t->oe_off;
1322
1323	/* rd_cycle */
1324	temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1325	temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1326							gpmc_t->access;
1327	/* XXX: barter t_ce_rdyz with t_cez_r ? */
1328	if (dev_t->t_ce_rdyz)
1329		temp = max_t(u32, temp,	gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1330	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1331
1332	return 0;
1333}
1334
1335static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1336					struct gpmc_device_timings *dev_t,
1337					bool mux)
1338{
1339	u32 temp;
1340
1341	/* adv_wr_off */
1342	temp = dev_t->t_avdp_w;
1343	if (mux) {
1344		temp = max_t(u32, temp,
1345			gpmc_t->clk_activation + dev_t->t_avdh);
1346		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1347	}
1348	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1349
1350	/* wr_data_mux_bus */
1351	temp = max_t(u32, dev_t->t_weasu,
1352			gpmc_t->clk_activation + dev_t->t_rdyo);
1353	/* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1354	 * and in that case remember to handle we_on properly
1355	 */
1356	if (mux) {
1357		temp = max_t(u32, temp,
1358			gpmc_t->adv_wr_off + dev_t->t_aavdh);
1359		temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1360				gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1361	}
1362	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1363
1364	/* we_on */
1365	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1366		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1367	else
1368		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1369
1370	/* wr_access */
1371	/* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1372	gpmc_t->wr_access = gpmc_t->access;
1373
1374	/* we_off */
1375	temp = gpmc_t->we_on + dev_t->t_wpl;
1376	temp = max_t(u32, temp,
1377			gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1378	temp = max_t(u32, temp,
1379		gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1380	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1381
1382	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1383							dev_t->t_wph);
1384
1385	/* wr_cycle */
1386	temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1387	temp += gpmc_t->wr_access;
1388	/* XXX: barter t_ce_rdyz with t_cez_w ? */
1389	if (dev_t->t_ce_rdyz)
1390		temp = max_t(u32, temp,
1391				 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1392	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1393
1394	return 0;
1395}
1396
1397static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1398					struct gpmc_device_timings *dev_t,
1399					bool mux)
1400{
1401	u32 temp;
1402
1403	/* adv_rd_off */
1404	temp = dev_t->t_avdp_r;
1405	if (mux)
1406		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1407	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1408
1409	/* oe_on */
1410	temp = dev_t->t_oeasu;
1411	if (mux)
1412		temp = max_t(u32, temp,
1413			gpmc_t->adv_rd_off + dev_t->t_aavdh);
1414	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1415
1416	/* access */
1417	temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1418				gpmc_t->oe_on + dev_t->t_oe);
1419	temp = max_t(u32, temp,
1420				gpmc_t->cs_on + dev_t->t_ce);
1421	temp = max_t(u32, temp,
1422				gpmc_t->adv_on + dev_t->t_aa);
1423	gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1424
1425	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1426	gpmc_t->cs_rd_off = gpmc_t->oe_off;
1427
1428	/* rd_cycle */
1429	temp = max_t(u32, dev_t->t_rd_cycle,
1430			gpmc_t->cs_rd_off + dev_t->t_cez_r);
1431	temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1432	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1433
1434	return 0;
1435}
1436
1437static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1438					 struct gpmc_device_timings *dev_t,
1439					 bool mux)
1440{
1441	u32 temp;
1442
1443	/* adv_wr_off */
1444	temp = dev_t->t_avdp_w;
1445	if (mux)
1446		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1447	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1448
1449	/* wr_data_mux_bus */
1450	temp = dev_t->t_weasu;
1451	if (mux) {
1452		temp = max_t(u32, temp,	gpmc_t->adv_wr_off + dev_t->t_aavdh);
1453		temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1454				gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1455	}
1456	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1457
1458	/* we_on */
1459	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1460		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1461	else
1462		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1463
1464	/* we_off */
1465	temp = gpmc_t->we_on + dev_t->t_wpl;
1466	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1467
1468	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1469							dev_t->t_wph);
1470
1471	/* wr_cycle */
1472	temp = max_t(u32, dev_t->t_wr_cycle,
1473				gpmc_t->cs_wr_off + dev_t->t_cez_w);
1474	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1475
1476	return 0;
1477}
1478
1479static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1480			struct gpmc_device_timings *dev_t)
1481{
1482	u32 temp;
1483
1484	gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1485						gpmc_get_fclk_period();
1486
1487	gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1488					dev_t->t_bacc,
1489					gpmc_t->sync_clk);
1490
1491	temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1492	gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1493
1494	if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1495		return 0;
1496
1497	if (dev_t->ce_xdelay)
1498		gpmc_t->bool_timings.cs_extra_delay = true;
1499	if (dev_t->avd_xdelay)
1500		gpmc_t->bool_timings.adv_extra_delay = true;
1501	if (dev_t->oe_xdelay)
1502		gpmc_t->bool_timings.oe_extra_delay = true;
1503	if (dev_t->we_xdelay)
1504		gpmc_t->bool_timings.we_extra_delay = true;
1505
1506	return 0;
1507}
1508
1509static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1510				    struct gpmc_device_timings *dev_t,
1511				    bool sync)
1512{
1513	u32 temp;
1514
1515	/* cs_on */
1516	gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1517
1518	/* adv_on */
1519	temp = dev_t->t_avdasu;
1520	if (dev_t->t_ce_avd)
1521		temp = max_t(u32, temp,
1522				gpmc_t->cs_on + dev_t->t_ce_avd);
1523	gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1524
1525	if (sync)
1526		gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1527
1528	return 0;
1529}
1530
1531/* TODO: remove this function once all peripherals are confirmed to
 
1532 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1533 * has to be modified to handle timings in ps instead of ns
1534*/
1535static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1536{
1537	t->cs_on /= 1000;
1538	t->cs_rd_off /= 1000;
1539	t->cs_wr_off /= 1000;
1540	t->adv_on /= 1000;
1541	t->adv_rd_off /= 1000;
1542	t->adv_wr_off /= 1000;
1543	t->we_on /= 1000;
1544	t->we_off /= 1000;
1545	t->oe_on /= 1000;
1546	t->oe_off /= 1000;
1547	t->page_burst_access /= 1000;
1548	t->access /= 1000;
1549	t->rd_cycle /= 1000;
1550	t->wr_cycle /= 1000;
1551	t->bus_turnaround /= 1000;
1552	t->cycle2cycle_delay /= 1000;
1553	t->wait_monitoring /= 1000;
1554	t->clk_activation /= 1000;
1555	t->wr_access /= 1000;
1556	t->wr_data_mux_bus /= 1000;
1557}
1558
1559int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1560		      struct gpmc_settings *gpmc_s,
1561		      struct gpmc_device_timings *dev_t)
1562{
1563	bool mux = false, sync = false;
1564
1565	if (gpmc_s) {
1566		mux = gpmc_s->mux_add_data ? true : false;
1567		sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1568	}
1569
1570	memset(gpmc_t, 0, sizeof(*gpmc_t));
1571
1572	gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1573
1574	if (gpmc_s && gpmc_s->sync_read)
1575		gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1576	else
1577		gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1578
1579	if (gpmc_s && gpmc_s->sync_write)
1580		gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1581	else
1582		gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1583
1584	/* TODO: remove, see function definition */
1585	gpmc_convert_ps_to_ns(gpmc_t);
1586
1587	return 0;
1588}
1589
1590/**
1591 * gpmc_cs_program_settings - programs non-timing related settings
1592 * @cs:		GPMC chip-select to program
1593 * @p:		pointer to GPMC settings structure
1594 *
1595 * Programs non-timing related settings for a GPMC chip-select, such as
1596 * bus-width, burst configuration, etc. Function should be called once
1597 * for each chip-select that is being used and must be called before
1598 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1599 * register will be initialised to zero by this function. Returns 0 on
1600 * success and appropriate negative error code on failure.
1601 */
1602int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1603{
1604	u32 config1;
1605
1606	if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1607		pr_err("%s: invalid width %d!", __func__, p->device_width);
1608		return -EINVAL;
1609	}
1610
1611	/* Address-data multiplexing not supported for NAND devices */
1612	if (p->device_nand && p->mux_add_data) {
1613		pr_err("%s: invalid configuration!\n", __func__);
1614		return -EINVAL;
1615	}
1616
1617	if ((p->mux_add_data > GPMC_MUX_AD) ||
1618	    ((p->mux_add_data == GPMC_MUX_AAD) &&
1619	     !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1620		pr_err("%s: invalid multiplex configuration!\n", __func__);
1621		return -EINVAL;
1622	}
1623
1624	/* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1625	if (p->burst_read || p->burst_write) {
1626		switch (p->burst_len) {
1627		case GPMC_BURST_4:
1628		case GPMC_BURST_8:
1629		case GPMC_BURST_16:
1630			break;
1631		default:
1632			pr_err("%s: invalid page/burst-length (%d)\n",
1633			       __func__, p->burst_len);
1634			return -EINVAL;
1635		}
1636	}
1637
1638	if (p->wait_pin > gpmc_nr_waitpins) {
1639		pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1640		return -EINVAL;
1641	}
1642
1643	config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1644
1645	if (p->sync_read)
1646		config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1647	if (p->sync_write)
1648		config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1649	if (p->wait_on_read)
1650		config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1651	if (p->wait_on_write)
1652		config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1653	if (p->wait_on_read || p->wait_on_write)
1654		config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1655	if (p->device_nand)
1656		config1	|= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1657	if (p->mux_add_data)
1658		config1	|= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1659	if (p->burst_read)
1660		config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1661	if (p->burst_write)
1662		config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1663	if (p->burst_read || p->burst_write) {
1664		config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1665		config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1666	}
1667
1668	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1669
1670	return 0;
1671}
1672
1673#ifdef CONFIG_OF
1674static const struct of_device_id gpmc_dt_ids[] = {
1675	{ .compatible = "ti,omap2420-gpmc" },
1676	{ .compatible = "ti,omap2430-gpmc" },
1677	{ .compatible = "ti,omap3430-gpmc" },	/* omap3430 & omap3630 */
1678	{ .compatible = "ti,omap4430-gpmc" },	/* omap4430 & omap4460 & omap543x */
1679	{ .compatible = "ti,am3352-gpmc" },	/* am335x devices */
1680	{ }
1681};
1682MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1683
1684/**
1685 * gpmc_read_settings_dt - read gpmc settings from device-tree
1686 * @np:		pointer to device-tree node for a gpmc child device
1687 * @p:		pointer to gpmc settings structure
1688 *
1689 * Reads the GPMC settings for a GPMC child device from device-tree and
1690 * stores them in the GPMC settings structure passed. The GPMC settings
1691 * structure is initialised to zero by this function and so any
1692 * previously stored settings will be cleared.
1693 */
1694void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1695{
1696	memset(p, 0, sizeof(struct gpmc_settings));
1697
1698	p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1699	p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1700	of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1701	of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1702
1703	if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1704		p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1705		p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1706		p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1707		if (!p->burst_read && !p->burst_write)
1708			pr_warn("%s: page/burst-length set but not used!\n",
1709				__func__);
1710	}
1711
1712	if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1713		p->wait_on_read = of_property_read_bool(np,
1714							"gpmc,wait-on-read");
1715		p->wait_on_write = of_property_read_bool(np,
1716							 "gpmc,wait-on-write");
1717		if (!p->wait_on_read && !p->wait_on_write)
1718			pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1719				 __func__);
1720	}
1721}
1722
1723static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1724						struct gpmc_timings *gpmc_t)
1725{
1726	struct gpmc_bool_timings *p;
1727
1728	if (!np || !gpmc_t)
1729		return;
1730
1731	memset(gpmc_t, 0, sizeof(*gpmc_t));
1732
1733	/* minimum clock period for syncronous mode */
1734	of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1735
1736	/* chip select timtings */
1737	of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1738	of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1739	of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1740
1741	/* ADV signal timings */
1742	of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1743	of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1744	of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1745	of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1746			     &gpmc_t->adv_aad_mux_on);
1747	of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1748			     &gpmc_t->adv_aad_mux_rd_off);
1749	of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1750			     &gpmc_t->adv_aad_mux_wr_off);
1751
1752	/* WE signal timings */
1753	of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1754	of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1755
1756	/* OE signal timings */
1757	of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1758	of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1759	of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1760			     &gpmc_t->oe_aad_mux_on);
1761	of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1762			     &gpmc_t->oe_aad_mux_off);
1763
1764	/* access and cycle timings */
1765	of_property_read_u32(np, "gpmc,page-burst-access-ns",
1766			     &gpmc_t->page_burst_access);
1767	of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1768	of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1769	of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1770	of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1771			     &gpmc_t->bus_turnaround);
1772	of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1773			     &gpmc_t->cycle2cycle_delay);
1774	of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1775			     &gpmc_t->wait_monitoring);
1776	of_property_read_u32(np, "gpmc,clk-activation-ns",
1777			     &gpmc_t->clk_activation);
1778
1779	/* only applicable to OMAP3+ */
1780	of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1781	of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1782			     &gpmc_t->wr_data_mux_bus);
1783
1784	/* bool timing parameters */
1785	p = &gpmc_t->bool_timings;
1786
1787	p->cycle2cyclediffcsen =
1788		of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1789	p->cycle2cyclesamecsen =
1790		of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1791	p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1792	p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1793	p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1794	p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1795	p->time_para_granularity =
1796		of_property_read_bool(np, "gpmc,time-para-granularity");
1797}
1798
1799#if IS_ENABLED(CONFIG_MTD_NAND)
1800
1801static const char * const nand_xfer_types[] = {
1802	[NAND_OMAP_PREFETCH_POLLED]		= "prefetch-polled",
1803	[NAND_OMAP_POLLED]			= "polled",
1804	[NAND_OMAP_PREFETCH_DMA]		= "prefetch-dma",
1805	[NAND_OMAP_PREFETCH_IRQ]		= "prefetch-irq",
1806};
1807
1808static int gpmc_probe_nand_child(struct platform_device *pdev,
1809				 struct device_node *child)
1810{
1811	u32 val;
1812	const char *s;
1813	struct gpmc_timings gpmc_t;
1814	struct omap_nand_platform_data *gpmc_nand_data;
1815
1816	if (of_property_read_u32(child, "reg", &val) < 0) {
1817		dev_err(&pdev->dev, "%s has no 'reg' property\n",
1818			child->full_name);
1819		return -ENODEV;
1820	}
1821
1822	gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1823				      GFP_KERNEL);
1824	if (!gpmc_nand_data)
1825		return -ENOMEM;
1826
1827	gpmc_nand_data->cs = val;
1828	gpmc_nand_data->of_node = child;
1829
1830	/* Detect availability of ELM module */
1831	gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1832	if (gpmc_nand_data->elm_of_node == NULL)
1833		gpmc_nand_data->elm_of_node =
1834					of_parse_phandle(child, "elm_id", 0);
1835
1836	/* select ecc-scheme for NAND */
1837	if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1838		pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1839		return -ENODEV;
1840	}
1841
1842	if (!strcmp(s, "sw"))
1843		gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1844	else if (!strcmp(s, "ham1") ||
1845		 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1846		gpmc_nand_data->ecc_opt =
1847				OMAP_ECC_HAM1_CODE_HW;
1848	else if (!strcmp(s, "bch4"))
1849		if (gpmc_nand_data->elm_of_node)
1850			gpmc_nand_data->ecc_opt =
1851				OMAP_ECC_BCH4_CODE_HW;
1852		else
1853			gpmc_nand_data->ecc_opt =
1854				OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1855	else if (!strcmp(s, "bch8"))
1856		if (gpmc_nand_data->elm_of_node)
1857			gpmc_nand_data->ecc_opt =
1858				OMAP_ECC_BCH8_CODE_HW;
1859		else
1860			gpmc_nand_data->ecc_opt =
1861				OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1862	else if (!strcmp(s, "bch16"))
1863		if (gpmc_nand_data->elm_of_node)
1864			gpmc_nand_data->ecc_opt =
1865				OMAP_ECC_BCH16_CODE_HW;
1866		else
1867			pr_err("%s: BCH16 requires ELM support\n", __func__);
1868	else
1869		pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1870
1871	/* select data transfer mode for NAND controller */
1872	if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1873		for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1874			if (!strcasecmp(s, nand_xfer_types[val])) {
1875				gpmc_nand_data->xfer_type = val;
1876				break;
1877			}
1878
1879	gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1880
1881	val = of_get_nand_bus_width(child);
1882	if (val == 16)
1883		gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1884
1885	gpmc_read_timings_dt(child, &gpmc_t);
1886	gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1887
1888	return 0;
1889}
1890#else
1891static int gpmc_probe_nand_child(struct platform_device *pdev,
1892				 struct device_node *child)
1893{
1894	return 0;
1895}
1896#endif
1897
1898#if IS_ENABLED(CONFIG_MTD_ONENAND)
1899static int gpmc_probe_onenand_child(struct platform_device *pdev,
1900				 struct device_node *child)
1901{
1902	u32 val;
1903	struct omap_onenand_platform_data *gpmc_onenand_data;
1904
1905	if (of_property_read_u32(child, "reg", &val) < 0) {
1906		dev_err(&pdev->dev, "%s has no 'reg' property\n",
1907			child->full_name);
1908		return -ENODEV;
1909	}
1910
1911	gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1912					 GFP_KERNEL);
1913	if (!gpmc_onenand_data)
1914		return -ENOMEM;
1915
1916	gpmc_onenand_data->cs = val;
1917	gpmc_onenand_data->of_node = child;
1918	gpmc_onenand_data->dma_channel = -1;
1919
1920	if (!of_property_read_u32(child, "dma-channel", &val))
1921		gpmc_onenand_data->dma_channel = val;
1922
1923	gpmc_onenand_init(gpmc_onenand_data);
1924
1925	return 0;
1926}
1927#else
1928static int gpmc_probe_onenand_child(struct platform_device *pdev,
1929				    struct device_node *child)
1930{
1931	return 0;
1932}
1933#endif
1934
1935/**
1936 * gpmc_probe_generic_child - configures the gpmc for a child device
1937 * @pdev:	pointer to gpmc platform device
1938 * @child:	pointer to device-tree node for child device
1939 *
1940 * Allocates and configures a GPMC chip-select for a child device.
1941 * Returns 0 on success and appropriate negative error code on failure.
1942 */
1943static int gpmc_probe_generic_child(struct platform_device *pdev,
1944				struct device_node *child)
1945{
1946	struct gpmc_settings gpmc_s;
1947	struct gpmc_timings gpmc_t;
1948	struct resource res;
1949	unsigned long base;
1950	const char *name;
1951	int ret, cs;
1952	u32 val;
 
 
1953
1954	if (of_property_read_u32(child, "reg", &cs) < 0) {
1955		dev_err(&pdev->dev, "%s has no 'reg' property\n",
1956			child->full_name);
1957		return -ENODEV;
1958	}
1959
1960	if (of_address_to_resource(child, 0, &res) < 0) {
1961		dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1962			child->full_name);
1963		return -ENODEV;
1964	}
1965
1966	/*
1967	 * Check if we have multiple instances of the same device
1968	 * on a single chip select. If so, use the already initialized
1969	 * timings.
1970	 */
1971	name = gpmc_cs_get_name(cs);
1972	if (name && child->name && of_node_cmp(child->name, name) == 0)
1973			goto no_timings;
1974
1975	ret = gpmc_cs_request(cs, resource_size(&res), &base);
1976	if (ret < 0) {
1977		dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1978		return ret;
1979	}
1980	gpmc_cs_set_name(cs, child->name);
1981
1982	gpmc_read_settings_dt(child, &gpmc_s);
1983	gpmc_read_timings_dt(child, &gpmc_t);
1984
1985	/*
1986	 * For some GPMC devices we still need to rely on the bootloader
1987	 * timings because the devices can be connected via FPGA.
1988	 * REVISIT: Add timing support from slls644g.pdf.
1989	 */
1990	if (!gpmc_t.cs_rd_off) {
1991		WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1992			cs);
1993		gpmc_cs_show_timings(cs,
1994				     "please add GPMC bootloader timings to .dts");
1995		goto no_timings;
1996	}
1997
1998	/* CS must be disabled while making changes to gpmc configuration */
1999	gpmc_cs_disable_mem(cs);
2000
2001	/*
2002	 * FIXME: gpmc_cs_request() will map the CS to an arbitary
2003	 * location in the gpmc address space. When booting with
2004	 * device-tree we want the NOR flash to be mapped to the
2005	 * location specified in the device-tree blob. So remap the
2006	 * CS to this location. Once DT migration is complete should
2007	 * just make gpmc_cs_request() map a specific address.
2008	 */
2009	ret = gpmc_cs_remap(cs, res.start);
2010	if (ret < 0) {
2011		dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2012			cs, &res.start);
 
 
 
 
 
 
 
 
 
2013		goto err;
2014	}
2015
2016	ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
2017	if (ret < 0)
2018		goto err;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2019
2020	gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
 
2021	ret = gpmc_cs_program_settings(cs, &gpmc_s);
2022	if (ret < 0)
2023		goto err;
2024
2025	ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2026	if (ret) {
2027		dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2028			child->name);
2029		goto err;
2030	}
2031
2032	/* Clear limited address i.e. enable A26-A11 */
2033	val = gpmc_read_reg(GPMC_CONFIG);
2034	val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2035	gpmc_write_reg(GPMC_CONFIG, val);
2036
2037	/* Enable CS region */
2038	gpmc_cs_enable_mem(cs);
2039
2040no_timings:
2041
2042	/* create platform device, NULL on error or when disabled */
2043	if (!of_platform_device_create(child, NULL, &pdev->dev))
2044		goto err_child_fail;
2045
2046	/* is child a common bus? */
2047	if (of_match_node(of_default_bus_match_table, child))
2048		/* create children and other common bus children */
2049		if (of_platform_populate(child, of_default_bus_match_table,
2050					 NULL, &pdev->dev))
2051			goto err_child_fail;
2052
2053	return 0;
2054
2055err_child_fail:
2056
2057	dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2058	ret = -ENODEV;
2059
 
 
2060err:
2061	gpmc_cs_free(cs);
2062
2063	return ret;
2064}
2065
2066static int gpmc_probe_dt(struct platform_device *pdev)
2067{
2068	int ret;
2069	struct device_node *child;
2070	const struct of_device_id *of_id =
2071		of_match_device(gpmc_dt_ids, &pdev->dev);
2072
2073	if (!of_id)
2074		return 0;
2075
2076	ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2077				   &gpmc_cs_num);
2078	if (ret < 0) {
2079		pr_err("%s: number of chip-selects not defined\n", __func__);
2080		return ret;
2081	} else if (gpmc_cs_num < 1) {
2082		pr_err("%s: all chip-selects are disabled\n", __func__);
2083		return -EINVAL;
2084	} else if (gpmc_cs_num > GPMC_CS_NUM) {
2085		pr_err("%s: number of supported chip-selects cannot be > %d\n",
2086					 __func__, GPMC_CS_NUM);
2087		return -EINVAL;
2088	}
2089
2090	ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2091				   &gpmc_nr_waitpins);
2092	if (ret < 0) {
2093		pr_err("%s: number of wait pins not found!\n", __func__);
2094		return ret;
2095	}
2096
2097	for_each_available_child_of_node(pdev->dev.of_node, child) {
 
2098
2099		if (!child->name)
2100			continue;
 
 
2101
2102		if (of_node_cmp(child->name, "nand") == 0)
2103			ret = gpmc_probe_nand_child(pdev, child);
2104		else if (of_node_cmp(child->name, "onenand") == 0)
2105			ret = gpmc_probe_onenand_child(pdev, child);
2106		else
2107			ret = gpmc_probe_generic_child(pdev, child);
2108	}
2109
2110	return 0;
2111}
2112#else
 
 
 
 
2113static int gpmc_probe_dt(struct platform_device *pdev)
2114{
2115	return 0;
2116}
2117#endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2118
2119static int gpmc_probe(struct platform_device *pdev)
2120{
2121	int rc;
2122	u32 l;
2123	struct resource *res;
 
 
 
 
 
 
 
 
2124
2125	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2126	if (res == NULL)
2127		return -ENOENT;
2128
2129	phys_base = res->start;
2130	mem_size = resource_size(res);
2131
2132	gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2133	if (IS_ERR(gpmc_base))
2134		return PTR_ERR(gpmc_base);
2135
2136	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2137	if (res == NULL)
2138		dev_warn(&pdev->dev, "Failed to get resource: irq\n");
2139	else
2140		gpmc_irq = res->start;
 
 
2141
2142	gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2143	if (IS_ERR(gpmc_l3_clk)) {
2144		dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2145		gpmc_irq = 0;
2146		return PTR_ERR(gpmc_l3_clk);
2147	}
2148
2149	if (!clk_get_rate(gpmc_l3_clk)) {
2150		dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2151		return -EINVAL;
2152	}
2153
 
 
 
 
 
 
 
 
 
2154	pm_runtime_enable(&pdev->dev);
2155	pm_runtime_get_sync(&pdev->dev);
2156
2157	gpmc_dev = &pdev->dev;
2158
2159	l = gpmc_read_reg(GPMC_REVISION);
2160
2161	/*
2162	 * FIXME: Once device-tree migration is complete the below flags
2163	 * should be populated based upon the device-tree compatible
2164	 * string. For now just use the IP revision. OMAP3+ devices have
2165	 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2166	 * devices support the addr-addr-data multiplex protocol.
2167	 *
2168	 * GPMC IP revisions:
2169	 * - OMAP24xx			= 2.0
2170	 * - OMAP3xxx			= 5.0
2171	 * - OMAP44xx/54xx/AM335x	= 6.0
2172	 */
2173	if (GPMC_REVISION_MAJOR(l) > 0x4)
2174		gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2175	if (GPMC_REVISION_MAJOR(l) > 0x5)
2176		gpmc_capability |= GPMC_HAS_MUX_AAD;
2177	dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2178		 GPMC_REVISION_MINOR(l));
2179
2180	gpmc_mem_init();
 
 
 
2181
2182	if (gpmc_setup_irq() < 0)
2183		dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
2184
2185	if (!pdev->dev.of_node) {
2186		gpmc_cs_num	 = GPMC_CS_NUM;
2187		gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2188	}
2189
2190	rc = gpmc_probe_dt(pdev);
2191	if (rc < 0) {
2192		pm_runtime_put_sync(&pdev->dev);
2193		dev_err(gpmc_dev, "failed to probe DT parameters\n");
2194		return rc;
2195	}
2196
2197	return 0;
 
 
 
 
 
 
 
2198}
2199
2200static int gpmc_remove(struct platform_device *pdev)
2201{
2202	gpmc_free_irq();
 
 
2203	gpmc_mem_exit();
2204	pm_runtime_put_sync(&pdev->dev);
2205	pm_runtime_disable(&pdev->dev);
2206	gpmc_dev = NULL;
2207	return 0;
2208}
2209
2210#ifdef CONFIG_PM_SLEEP
2211static int gpmc_suspend(struct device *dev)
2212{
2213	omap3_gpmc_save_context();
2214	pm_runtime_put_sync(dev);
2215	return 0;
2216}
2217
2218static int gpmc_resume(struct device *dev)
2219{
2220	pm_runtime_get_sync(dev);
2221	omap3_gpmc_restore_context();
2222	return 0;
2223}
2224#endif
2225
2226static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2227
2228static struct platform_driver gpmc_driver = {
2229	.probe		= gpmc_probe,
2230	.remove		= gpmc_remove,
2231	.driver		= {
2232		.name	= DEVICE_NAME,
2233		.of_match_table = of_match_ptr(gpmc_dt_ids),
2234		.pm	= &gpmc_pm_ops,
2235	},
2236};
2237
2238static __init int gpmc_init(void)
2239{
2240	return platform_driver_register(&gpmc_driver);
2241}
2242
2243static __exit void gpmc_exit(void)
2244{
2245	platform_driver_unregister(&gpmc_driver);
2246
2247}
2248
2249postcore_initcall(gpmc_init);
2250module_exit(gpmc_exit);
2251
2252static irqreturn_t gpmc_handle_irq(int irq, void *dev)
2253{
2254	int i;
2255	u32 regval;
2256
2257	regval = gpmc_read_reg(GPMC_IRQSTATUS);
2258
2259	if (!regval)
2260		return IRQ_NONE;
2261
2262	for (i = 0; i < GPMC_NR_IRQ; i++)
2263		if (regval & gpmc_client_irq[i].bitmask)
2264			generic_handle_irq(gpmc_client_irq[i].irq);
2265
2266	gpmc_write_reg(GPMC_IRQSTATUS, regval);
2267
2268	return IRQ_HANDLED;
2269}
2270
2271static struct omap3_gpmc_regs gpmc_context;
2272
2273void omap3_gpmc_save_context(void)
2274{
2275	int i;
2276
2277	if (!gpmc_base)
2278		return;
2279
2280	gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2281	gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2282	gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2283	gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2284	gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2285	gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2286	gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2287	for (i = 0; i < gpmc_cs_num; i++) {
2288		gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2289		if (gpmc_context.cs_context[i].is_valid) {
2290			gpmc_context.cs_context[i].config1 =
2291				gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2292			gpmc_context.cs_context[i].config2 =
2293				gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2294			gpmc_context.cs_context[i].config3 =
2295				gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2296			gpmc_context.cs_context[i].config4 =
2297				gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2298			gpmc_context.cs_context[i].config5 =
2299				gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2300			gpmc_context.cs_context[i].config6 =
2301				gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2302			gpmc_context.cs_context[i].config7 =
2303				gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2304		}
2305	}
2306}
2307
2308void omap3_gpmc_restore_context(void)
2309{
2310	int i;
2311
2312	if (!gpmc_base)
2313		return;
2314
2315	gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2316	gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2317	gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2318	gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2319	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2320	gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2321	gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2322	for (i = 0; i < gpmc_cs_num; i++) {
2323		if (gpmc_context.cs_context[i].is_valid) {
2324			gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2325				gpmc_context.cs_context[i].config1);
2326			gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2327				gpmc_context.cs_context[i].config2);
2328			gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2329				gpmc_context.cs_context[i].config3);
2330			gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2331				gpmc_context.cs_context[i].config4);
2332			gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2333				gpmc_context.cs_context[i].config5);
2334			gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2335				gpmc_context.cs_context[i].config6);
2336			gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2337				gpmc_context.cs_context[i].config7);
2338		}
2339	}
2340}