1/*
  2 * \file ati_pcigart.c
  3 * ATI PCI GART support
  4 *
  5 * \author Gareth Hughes <gareth@valinux.com>
  6 */
  7
  8/*
  9 * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
 10 *
 11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 12 * All Rights Reserved.
 13 *
 14 * Permission is hereby granted, free of charge, to any person obtaining a
 15 * copy of this software and associated documentation files (the "Software"),
 16 * to deal in the Software without restriction, including without limitation
 17 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 18 * and/or sell copies of the Software, and to permit persons to whom the
 19 * Software is furnished to do so, subject to the following conditions:
 20 *
 21 * The above copyright notice and this permission notice (including the next
 22 * paragraph) shall be included in all copies or substantial portions of the
 23 * Software.
 24 *
 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 28 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 31 * DEALINGS IN THE SOFTWARE.
 32 */
 33
 34#include <linux/export.h>
 35#include <linux/pci.h>
 36
 37#include <drm/drm_device.h>
 38#include <drm/drm_legacy.h>
 39#include <drm/drm_print.h>
 40
 41#include "ati_pcigart.h"
 42
 43# define ATI_PCIGART_PAGE_SIZE		4096	/**< PCI GART page size */
 44
 45static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
 46				       struct drm_ati_pcigart_info *gart_info)
 47{
 48	drm_dma_handle_t *dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL);
 49
 50	if (!dmah)
 51		return -ENOMEM;
 52
 53	dmah->size = gart_info->table_size;
 54	dmah->vaddr = dma_alloc_coherent(dev->dev,
 55					 dmah->size,
 56					 &dmah->busaddr,
 57					 GFP_KERNEL);
 58
 59	if (!dmah->vaddr) {
 60		kfree(dmah);
 61		return -ENOMEM;
 62	}
 63
 64	gart_info->table_handle = dmah;
 65	return 0;
 66}
 67
 68static void drm_ati_free_pcigart_table(struct drm_device *dev,
 69				       struct drm_ati_pcigart_info *gart_info)
 70{
 71	drm_dma_handle_t *dmah = gart_info->table_handle;
 72
 73	dma_free_coherent(dev->dev, dmah->size, dmah->vaddr, dmah->busaddr);
 74	kfree(dmah);
 75
 76	gart_info->table_handle = NULL;
 77}
 78
 79int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 80{
 81	struct drm_sg_mem *entry = dev->sg;
 82	struct pci_dev *pdev = to_pci_dev(dev->dev);
 83	unsigned long pages;
 84	int i;
 85	int max_pages;
 86
 87	/* we need to support large memory configurations */
 88	if (!entry) {
 89		DRM_ERROR("no scatter/gather memory!\n");
 90		return 0;
 91	}
 92
 93	if (gart_info->bus_addr) {
 94
 95		max_pages = (gart_info->table_size / sizeof(u32));
 96		pages = (entry->pages <= max_pages)
 97		  ? entry->pages : max_pages;
 98
 99		for (i = 0; i < pages; i++) {
100			if (!entry->busaddr[i])
101				break;
102			pci_unmap_page(pdev, entry->busaddr[i], PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
103		}
104
105		if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
106			gart_info->bus_addr = 0;
107	}
108
109	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
110	    gart_info->table_handle) {
111		drm_ati_free_pcigart_table(dev, gart_info);
112	}
113
114	return 1;
115}
116
117int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
118{
119	struct drm_local_map *map = &gart_info->mapping;
120	struct drm_sg_mem *entry = dev->sg;
121	struct pci_dev *pdev = to_pci_dev(dev->dev);
122	void *address = NULL;
123	unsigned long pages;
124	u32 *pci_gart = NULL, page_base, gart_idx;
125	dma_addr_t bus_address = 0;
126	int i, j, ret = -ENOMEM;
127	int max_ati_pages, max_real_pages;
128
129	if (!entry) {
130		DRM_ERROR("no scatter/gather memory!\n");
131		goto done;
132	}
133
134	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
135		DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
136
137		if (pci_set_dma_mask(pdev, gart_info->table_mask)) {
138			DRM_ERROR("fail to set dma mask to 0x%Lx\n",
139				  (unsigned long long)gart_info->table_mask);
140			ret = -EFAULT;
141			goto done;
142		}
143
144		ret = drm_ati_alloc_pcigart_table(dev, gart_info);
145		if (ret) {
146			DRM_ERROR("cannot allocate PCI GART page!\n");
147			goto done;
148		}
149
150		pci_gart = gart_info->table_handle->vaddr;
151		address = gart_info->table_handle->vaddr;
152		bus_address = gart_info->table_handle->busaddr;
153	} else {
154		address = gart_info->addr;
155		bus_address = gart_info->bus_addr;
156		DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
157			  (unsigned long long)bus_address,
158			  (unsigned long)address);
159	}
160
161
162	max_ati_pages = (gart_info->table_size / sizeof(u32));
163	max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
164	pages = (entry->pages <= max_real_pages)
165	    ? entry->pages : max_real_pages;
166
167	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
168		memset(pci_gart, 0, max_ati_pages * sizeof(u32));
169	} else {
170		memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u32));
171	}
172
173	gart_idx = 0;
174	for (i = 0; i < pages; i++) {
175		/* we need to support large memory configurations */
176		entry->busaddr[i] = pci_map_page(pdev, entry->pagelist[i],
177						 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
178		if (pci_dma_mapping_error(pdev, entry->busaddr[i])) {
179			DRM_ERROR("unable to map PCIGART pages!\n");
180			drm_ati_pcigart_cleanup(dev, gart_info);
181			address = NULL;
182			bus_address = 0;
183			ret = -ENOMEM;
184			goto done;
185		}
186		page_base = (u32) entry->busaddr[i];
187
188		for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
189			u32 offset;
190			u32 val;
191
192			switch(gart_info->gart_reg_if) {
193			case DRM_ATI_GART_IGP:
194				val = page_base | 0xc;
195				break;
196			case DRM_ATI_GART_PCIE:
197				val = (page_base >> 8) | 0xc;
198				break;
199			default:
200			case DRM_ATI_GART_PCI:
201				val = page_base;
202				break;
203			}
204			if (gart_info->gart_table_location ==
205			    DRM_ATI_GART_MAIN) {
206				pci_gart[gart_idx] = cpu_to_le32(val);
207			} else {
208				offset = gart_idx * sizeof(u32);
209				writel(val, (void __iomem *)map->handle + offset);
210			}
211			gart_idx++;
212			page_base += ATI_PCIGART_PAGE_SIZE;
213		}
214	}
215	ret = 0;
216
217#if defined(__i386__) || defined(__x86_64__)
218	wbinvd();
219#else
220	mb();
221#endif
222
223      done:
224	gart_info->addr = address;
225	gart_info->bus_addr = bus_address;
226	return ret;
227}